1 ADDER - 4 BIT ALL-NAND-GATE BINARY ADDER 2 3*** SUBCIRCUIT DEFINITIONS 4.SUBCKT NAND in1 in2 out VDD 5* NODES: INPUT(2), OUTPUT, VCC 6M1 out in2 Vdd Vdd p1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p 7M2 net.1 in2 0 0 n1 W=3u L=0.35u pd=9u ad=9p ps=9u as=9p 8M3 out in1 Vdd Vdd p1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p 9M4 out in1 net.1 0 n1 W=3u L=0.35u pd=9u ad=9p ps=9u as=9p 10.ENDS NAND 11 12.SUBCKT ONEBIT 1 2 3 4 5 6 13* NODES: INPUT(2), CARRY-IN, OUTPUT, CARRY-OUT, VCC 14X1 1 2 7 6 NAND 15X2 1 7 8 6 NAND 16X3 2 7 9 6 NAND 17X4 8 9 10 6 NAND 18X5 3 10 11 6 NAND 19X6 3 11 12 6 NAND 20X7 10 11 13 6 NAND 21X8 12 13 4 6 NAND 22X9 11 7 5 6 NAND 23.ENDS ONEBIT 24 25.SUBCKT TWOBIT 1 2 3 4 5 6 7 8 9 26* NODES: INPUT - BIT0(2) / BIT1(2), OUTPUT - BIT0 / BIT1, 27* CARRY-IN, CARRY-OUT, VCC 28X1 1 2 7 5 10 9 ONEBIT 29X2 3 4 10 6 8 9 ONEBIT 30.ENDS TWOBIT 31 32.SUBCKT FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 33* NODES: INPUT - BIT0(2) / BIT1(2) / BIT2(2) / BIT3(2), 34* OUTPUT - BIT0 / BIT1 / BIT2 / BIT3, CARRY-IN, CARRY-OUT, VCC 35X1 1 2 3 4 9 10 13 16 15 TWOBIT 36X2 5 6 7 8 11 12 16 14 15 TWOBIT 37.ENDS FOURBIT 38 39*** POWER 40VCC 99 0 DC 3.3V 41 42*** ALL INPUTS 43VIN1A 1 0 DC 0 PULSE(0 3 0 5NS 5NS 20NS 50NS) 44VIN1B 2 0 DC 0 PULSE(0 3 0 5NS 5NS 30NS 100NS) 45VIN2A 3 0 DC 0 PULSE(0 3 0 5NS 5NS 50NS 200NS) 46VIN2B 4 0 DC 0 PULSE(0 3 0 5NS 5NS 90NS 400NS) 47VIN3A 5 0 DC 0 PULSE(0 3 0 5NS 5NS 170NS 800NS) 48VIN3B 6 0 DC 0 PULSE(0 3 0 5NS 5NS 330NS 1600NS) 49VIN4A 7 0 DC 0 PULSE(0 3 0 5NS 5NS 650NS 3200NS) 50VIN4B 8 0 DC 0 PULSE(0 3 0 5NS 5NS 1290NS 6400NS) 51 52*** DEFINE NOMINAL CIRCUIT 53X1 1 2 3 4 5 6 7 8 9 10 11 12 0 13 99 FOURBIT 54 55.option noinit acct 56.TRAN 500p 6400NS 57* save inputs 58* .save V(1) V(2) V(3) V(4) V(5) V(6) V(7) V(8) 59 60* use BSIM3 model with default parameters 61.model n1 nmos level=49 version=3.3.0 62.model p1 pmos level=49 version=3.3.0 63*.include ./Modelcards/modelcard32.nmos 64*.include ./Modelcards/modelcard32.pmos 65 66.END 67