1entity issue371 is 2end issue371; 3 4architecture behav of issue371 is 5 signal clock : bit; 6 signal chip_select_sig : bit; 7 signal address_sig : bit_vector(2 downto 0); 8 signal write_sig : bit; 9 signal host_data_bus_sig : bit_vector(7 downto 0); 10 11 function rising_edge(signal x : bit) return boolean is 12 begin 13 return x = '1' and x'last_value = '0'; 14 end function; 15 16 procedure wait_for_ticks (num_clock_cycles : in integer) is 17 begin 18 for i in 1 to num_clock_cycles loop 19 wait until rising_edge(clock); 20 end loop; 21 end procedure wait_for_ticks; 22 23 procedure host_write (addr: in bit_vector; 24 byte : in bit_vector; 25 signal clock : in bit; 26 signal chip_select : out bit; 27 signal address : out bit_vector; 28 signal write : out bit; 29 signal host_data_bus : out bit_vector; 30 invert_cs_etc : in bit 31 ) is 32 begin 33 wait until rising_edge(clock); 34 write <= '1' xor invert_cs_etc; 35 chip_select <= '1' xor invert_cs_etc; 36 address <= addr; 37 host_data_bus <= byte; 38 wait_for_ticks(1); 39 40 write <= '0' xor invert_cs_etc; 41 chip_select <= '0' xor invert_cs_etc; 42 for i in address'LOW to address'HIGH loop 43 address(i) <= '0'; 44 end loop; 45 for i in host_data_bus'LOW to host_data_bus'HIGH loop 46 host_data_bus(i) <= '0'; 47 end loop; 48 wait until rising_edge(clock); 49 end procedure host_write; 50 51begin 52 53 process 54 begin 55 for i in 0 to 10 loop 56 clock <= '0'; 57 wait for 1 us; 58 clock <= '1'; 59 wait for 1 us; 60 end loop; 61 wait; 62 end process; 63 64 process 65 begin 66 host_write("001", X"aa", clock, chip_select_sig, address_sig, write_sig, host_data_bus_sig, '0'); 67 for i in address_sig'LOW to address_sig'HIGH loop 68 assert address_sig(i) = '0'; 69 end loop; 70 for i in host_data_bus_sig'LOW to host_data_bus_sig'HIGH loop 71 assert host_data_bus_sig(i) = '0'; 72 end loop; 73 wait; 74 end process; 75end behav; 76