1entity issue116 is 2end issue116; 3 4architecture behav of issue116 is 5 6 signal intstat : BIT_VECTOR (7 DOWNTO 0); 7 ALIAS INT_int : BIT is intstat(7); 8 9begin 10 11 INT_int <= '1' when (intstat(6 downto 0) and "1111111") /= "0000000"; 12 --intstat(7) <= '1' when (intstat(6 downto 0) and "1111111") /= "0000000"; 13 14 process 15 begin 16 assert intstat(7) = '0'; 17 intstat(6 downto 0) <= "0000001"; 18 wait for 1 ns; 19 assert INT_int = '1'; 20 intstat(6 downto 0) <= "0000000"; 21 wait for 1 ns; 22 assert INT_int = '1'; 23 wait; 24 end process; 25end behav; 26