1module mux #(.Dsz(1), .Diz(1)) ($${NUMIN:I%, }S, Z);
2   input ${IZ_RANGE} $${NUMIN:, :I%};
3   input ${S_RANGE} S;
4   output ${IZ_RANGE} Z;
5   reg 	  ${IZ_RANGE} Z;
6
7   always
8     begin
9	case (S)
10$${NUMIN:\n:	  ${S_BITS}'d%: Z <= #Dsz ${invZ} I%;}
11	  default: Z <= #Dsz ${invZ} ${IZ_BITS}'hx;
12	endcase // case(S)
13	@(S or $${NUMIN: or :I%});
14     end
15
16endmodule // mux
17