1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2005 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Inputs 9 clk 10 ); 11 12 input clk; 13 14 reg [9:0] index; 15 wire [7:0] index0 = index[7:0] + 8'h0; 16 wire [7:0] index1 = index[7:0] + 8'h1; 17 wire [7:0] index2 = index[7:0] + 8'h2; 18 wire [7:0] index3 = index[7:0] + 8'h3; 19 wire [7:0] index4 = index[7:0] + 8'h4; 20 wire [7:0] index5 = index[7:0] + 8'h5; 21 wire [7:0] index6 = index[7:0] + 8'h6; 22 wire [7:0] index7 = index[7:0] + 8'h7; 23 24 /*AUTOWIRE*/ 25 // Beginning of automatic wires (for undeclared instantiated-module outputs) 26 wire [9:0] outa0; // From s0 of t_case_huge_sub.v 27 wire [9:0] outa1; // From s1 of t_case_huge_sub.v 28 wire [9:0] outa2; // From s2 of t_case_huge_sub.v 29 wire [9:0] outa3; // From s3 of t_case_huge_sub.v 30 wire [9:0] outa4; // From s4 of t_case_huge_sub.v 31 wire [9:0] outa5; // From s5 of t_case_huge_sub.v 32 wire [9:0] outa6; // From s6 of t_case_huge_sub.v 33 wire [9:0] outa7; // From s7 of t_case_huge_sub.v 34 wire [1:0] outb0; // From s0 of t_case_huge_sub.v 35 wire [1:0] outb1; // From s1 of t_case_huge_sub.v 36 wire [1:0] outb2; // From s2 of t_case_huge_sub.v 37 wire [1:0] outb3; // From s3 of t_case_huge_sub.v 38 wire [1:0] outb4; // From s4 of t_case_huge_sub.v 39 wire [1:0] outb5; // From s5 of t_case_huge_sub.v 40 wire [1:0] outb6; // From s6 of t_case_huge_sub.v 41 wire [1:0] outb7; // From s7 of t_case_huge_sub.v 42 wire outc0; // From s0 of t_case_huge_sub.v 43 wire outc1; // From s1 of t_case_huge_sub.v 44 wire outc2; // From s2 of t_case_huge_sub.v 45 wire outc3; // From s3 of t_case_huge_sub.v 46 wire outc4; // From s4 of t_case_huge_sub.v 47 wire outc5; // From s5 of t_case_huge_sub.v 48 wire outc6; // From s6 of t_case_huge_sub.v 49 wire outc7; // From s7 of t_case_huge_sub.v 50 wire [9:0] outq; // From q of t_case_huge_sub4.v 51 wire [3:0] outr; // From sub3 of t_case_huge_sub3.v 52 wire [9:0] outsmall; // From sub2 of t_case_huge_sub2.v 53 // End of automatics 54 55 t_case_huge_sub2 sub2 ( 56 // Outputs 57 .outa (outsmall[9:0]), 58 /*AUTOINST*/ 59 // Inputs 60 .index (index[9:0])); 61 62 t_case_huge_sub3 sub3 (/*AUTOINST*/ 63 // Outputs 64 .outr (outr[3:0]), 65 // Inputs 66 .clk (clk), 67 .index (index[9:0])); 68 69 /* t_case_huge_sub AUTO_TEMPLATE ( 70 .outa (outa@[]), 71 .outb (outb@[]), 72 .outc (outc@[]), 73 .index (index@[])); 74 */ 75 76 t_case_huge_sub s0 (/*AUTOINST*/ 77 // Outputs 78 .outa (outa0[9:0]), // Templated 79 .outb (outb0[1:0]), // Templated 80 .outc (outc0), // Templated 81 // Inputs 82 .index (index0[7:0])); // Templated 83 t_case_huge_sub s1 (/*AUTOINST*/ 84 // Outputs 85 .outa (outa1[9:0]), // Templated 86 .outb (outb1[1:0]), // Templated 87 .outc (outc1), // Templated 88 // Inputs 89 .index (index1[7:0])); // Templated 90 t_case_huge_sub s2 (/*AUTOINST*/ 91 // Outputs 92 .outa (outa2[9:0]), // Templated 93 .outb (outb2[1:0]), // Templated 94 .outc (outc2), // Templated 95 // Inputs 96 .index (index2[7:0])); // Templated 97 t_case_huge_sub s3 (/*AUTOINST*/ 98 // Outputs 99 .outa (outa3[9:0]), // Templated 100 .outb (outb3[1:0]), // Templated 101 .outc (outc3), // Templated 102 // Inputs 103 .index (index3[7:0])); // Templated 104 t_case_huge_sub s4 (/*AUTOINST*/ 105 // Outputs 106 .outa (outa4[9:0]), // Templated 107 .outb (outb4[1:0]), // Templated 108 .outc (outc4), // Templated 109 // Inputs 110 .index (index4[7:0])); // Templated 111 t_case_huge_sub s5 (/*AUTOINST*/ 112 // Outputs 113 .outa (outa5[9:0]), // Templated 114 .outb (outb5[1:0]), // Templated 115 .outc (outc5), // Templated 116 // Inputs 117 .index (index5[7:0])); // Templated 118 t_case_huge_sub s6 (/*AUTOINST*/ 119 // Outputs 120 .outa (outa6[9:0]), // Templated 121 .outb (outb6[1:0]), // Templated 122 .outc (outc6), // Templated 123 // Inputs 124 .index (index6[7:0])); // Templated 125 t_case_huge_sub s7 (/*AUTOINST*/ 126 // Outputs 127 .outa (outa7[9:0]), // Templated 128 .outb (outb7[1:0]), // Templated 129 .outc (outc7), // Templated 130 // Inputs 131 .index (index7[7:0])); // Templated 132 133 t_case_huge_sub4 q (/*AUTOINST*/ 134 // Outputs 135 .outq (outq[9:0]), 136 // Inputs 137 .index (index[7:0])); 138 139 140 integer cyc; initial cyc=1; 141 initial index = 10'h0; 142 143 always @ (posedge clk) begin 144 if (cyc!=0) begin 145 cyc <= cyc + 1; 146 //$write("%x: %x\n",cyc,outr); 147 //$write("%x: %x %x %x %x\n", cyc, outa1,outb1,outc1,index1); 148 if (cyc==1) begin 149 index <= 10'h236; 150 end 151 if (cyc==2) begin 152 index <= 10'h022; 153 if (outsmall != 10'h282) $stop; 154 if (outr != 4'b0) $stop; 155 if ({outa0,outb0,outc0}!={10'h282,2'd3,1'b0}) $stop; 156 if ({outa1,outb1,outc1}!={10'h21c,2'd3,1'b1}) $stop; 157 if ({outa2,outb2,outc2}!={10'h148,2'd0,1'b1}) $stop; 158 if ({outa3,outb3,outc3}!={10'h3c0,2'd2,1'b0}) $stop; 159 if ({outa4,outb4,outc4}!={10'h176,2'd1,1'b1}) $stop; 160 if ({outa5,outb5,outc5}!={10'h3fc,2'd2,1'b1}) $stop; 161 if ({outa6,outb6,outc6}!={10'h295,2'd3,1'b1}) $stop; 162 if ({outa7,outb7,outc7}!={10'h113,2'd2,1'b1}) $stop; 163 if (outq != 10'h001) $stop; 164 end 165 if (cyc==3) begin 166 index <= 10'h165; 167 if (outsmall != 10'h191) $stop; 168 if (outr != 4'h5) $stop; 169 if ({outa1,outb1,outc1}!={10'h379,2'd1,1'b0}) $stop; 170 if ({outa2,outb2,outc2}!={10'h073,2'd0,1'b0}) $stop; 171 if ({outa3,outb3,outc3}!={10'h2fd,2'd3,1'b1}) $stop; 172 if ({outa4,outb4,outc4}!={10'h2e0,2'd3,1'b1}) $stop; 173 if ({outa5,outb5,outc5}!={10'h337,2'd1,1'b1}) $stop; 174 if ({outa6,outb6,outc6}!={10'h2c7,2'd3,1'b1}) $stop; 175 if ({outa7,outb7,outc7}!={10'h19e,2'd3,1'b0}) $stop; 176 if (outq != 10'h001) $stop; 177 end 178 if (cyc==4) begin 179 index <= 10'h201; 180 if (outsmall != 10'h268) $stop; 181 if (outr != 4'h2) $stop; 182 if ({outa1,outb1,outc1}!={10'h111,2'd1,1'b0}) $stop; 183 if ({outa2,outb2,outc2}!={10'h1f9,2'd0,1'b0}) $stop; 184 if ({outa3,outb3,outc3}!={10'h232,2'd0,1'b1}) $stop; 185 if ({outa4,outb4,outc4}!={10'h255,2'd3,1'b0}) $stop; 186 if ({outa5,outb5,outc5}!={10'h34c,2'd1,1'b1}) $stop; 187 if ({outa6,outb6,outc6}!={10'h049,2'd1,1'b1}) $stop; 188 if ({outa7,outb7,outc7}!={10'h197,2'd3,1'b0}) $stop; 189 if (outq != 10'h001) $stop; 190 end 191 if (cyc==5) begin 192 index <= 10'h3ff; 193 if (outr != 4'hd) $stop; 194 if (outq != 10'h001) $stop; 195 end 196 if (cyc==6) begin 197 index <= 10'h0; 198 if (outr != 4'hd) $stop; 199 if (outq != 10'h114) $stop; 200 end 201 if (cyc==7) begin 202 if (outr != 4'h4) $stop; 203 end 204 if (cyc==9) begin 205 $write("*-* All Finished *-*\n"); 206 $finish; 207 end 208 end 209 end 210endmodule 211