1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2020 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7class ClsNoArg;
8   const int imembera;  // Ok for new() to assign to a const
9   function new();
10      imembera = 5;
11   endfunction : new
12endclass
13
14class ClsArg;
15   int imembera;
16   function new(int i);
17      imembera = i + 1;
18   endfunction
19   function int geta;
20      return imembera;
21   endfunction
22   static function ClsArg create6;
23      ClsArg obj;
24      obj = new(6 - 1);
25      return obj;
26   endfunction
27endclass
28
29class Cls2Arg;
30   int imembera;
31   int imemberb;
32   function new(int i, int j);
33      imembera = i + 1;
34      imemberb = j + 2;
35   endfunction
36
37   function Cls2Arg clone();
38      Cls2Arg ret;
39      ret = new(imembera, imemberb);
40      return ret;
41   endfunction
42endclass
43
44module t (/*AUTOARG*/);
45   initial begin
46      ClsNoArg c1;
47      ClsArg   c2;
48      Cls2Arg  c3;
49      Cls2Arg  c4;
50
51      c1 = new;
52      if (c1.imembera != 5) $stop;
53
54      c2 = new(3 - 1);
55      if (c2.imembera != 3) $stop;
56      if (c2.geta() != 3) $stop;
57
58      c2 = ClsArg::create6();
59      if (c2.imembera != 6) $stop;
60      if (c2.geta() != 6) $stop;
61
62      c3 = new(4, 5);
63      if (c3.imembera != 5) $stop;
64      if (c3.imemberb != 7) $stop;
65
66      c4 = c3.clone();
67      if (c4.imembera != 6) $stop;
68      if (c4.imemberb != 9) $stop;
69
70      $write("*-* All Finished *-*\n");
71      $finish;
72   end
73endmodule
74