1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2020 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Inputs 9 clk 10 ); 11 input clk; 12 13 //TODO sub #(.WIDTH(1)) w1; 14 //TODO sub #(.WIDTH(2)) w2; 15 //TODO sub #(.WIDTH(3)) w3; 16 //TODO sub #(.WIDTH(4)) w4; 17 sub #(.WIDTH(5)) w5; 18 19 always @ (posedge clk) begin 20 $write("*-* All Finished *-*\n"); 21 $finish; 22 end 23endmodule 24 25module sub (); 26 parameter WIDTH=5; // WIDTH >= 5 fails. WIDTH <= 4 passes 27 28 typedef struct packed { 29 logic [WIDTH-1:0] data; 30 } [15:0] w_t; 31 32 class WrReqQ; 33 w_t w; 34 endclass 35 36 initial begin 37 if ($bits(w_t) != WIDTH * 16) $stop; 38 end 39 40endmodule 41