1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2015 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/); 8 9 reg [32767:0] a; 10 11 initial begin 12 // verilator lint_off WIDTHCONCAT 13 a = {32768{1'b1}}; 14 // verilator lint_on WIDTHCONCAT 15 if (a[32000] != 1'b1) $stop; 16 $write("*-* All Finished *-*\n"); 17 $finish; 18 end 19 20endmodule 21