1// DESCRIPTION: Verilator: Verilog Test module 2// 3// Copyright 2009 by Wilson Snyder. This program is free software; you can 4// redistribute it and/or modify it under the terms of either the GNU 5// Lesser General Public License Version 3 or the Perl Artistic License 6// Version 2.0. 7// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 8 9module t (/*AUTOARG*/ 10 // Inputs 11 clk 12 ); 13 input clk; 14 15 parameter integer BLKS = 3; 16 17 generate 18 for (genvar blkIdx=0; blkIdx < BLKS; blkIdx=blkIdx+1 ) begin : slice 19 20 import "DPI-C" context function void dpi_genvarTest (); 21 22 initial begin 23 dpi_genvarTest(); 24 $display("slice = %0d : %m", blkIdx); 25 end 26 end 27 endgenerate 28 29 always @ (posedge clk) begin 30 $write("*-* All Finished *-*\n"); 31 $finish; 32 end 33 34endmodule 35