1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2021 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7// issue3005 8 9module t #(parameter NV = 2000) 10 ( 11 input a, 12 input w1, 13 input [127:0] w2, 14 output [ 31:0] o, 15 16 input [319:0] bi, 17 output [319:0] bo 18 ); 19 20 // verilator lint_off WIDTH 21 wire [NV-1:0] d = a ? NV'(0) : {NV{w2}}; 22 // verilator lint_on WIDTH 23 assign o = d[31:0]; 24 25 assign bo = ~bi; 26 27endmodule 28