1// -*- Verilog -*- 2// DESCRIPTION: Verilator: Verilog Test module 3// 4// This file ONLY is placed under the Creative Commons Public Domain, for 5// any use, without warranty, 2003 by Wilson Snyder. 6// SPDX-License-Identifier: CC0-1.0 7 8// This file is named .vi to test +libext+ flags. 9module t_inst_v2k__sub 10 ( 11 output reg [7:0] osizedreg, 12 output wire oonewire /*verilator public*/, 13 input [7:0] isizedwire, 14 input wire ionewire, 15 output reg [1:0] tied = 2'b10 16 ); 17 18 assign oonewire = ionewire; 19 20 always @* begin 21 osizedreg = isizedwire; 22 end 23 24endmodule 25