1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed into the Public Domain, for any use,
4// without warranty.
5// SPDX-License-Identifier: CC0-1.0
6
7// bug1005
8
9module foo_module;
10   generate
11      for (genvar i = 0; i < 2; i = i + 1) begin : my_gen_block
12	 logic baz;
13      end
14   endgenerate
15endmodule
16
17module bar_module;
18   foo_module foo();
19endmodule
20
21module t;
22   bar_module bar();
23   initial begin
24      bar.foo.my_gen_block[0].baz = 1;
25      if (bar.foo.my_gen_block[0].baz) begin
26	 $write("*-* All Finished *-*\n");
27	 $finish;
28      end
29   end
30endmodule
31