1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2010 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t
8   (
9   input wire i,
10   input wire i2 = i   // BAD
11   );
12
13endmodule
14