1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed into the Public Domain, for any use,
4// without warranty, 2014 by Clifford Wolf.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/
8   // Inputs
9   clk
10   );
11   input clk;
12
13   integer 	cyc = 0;
14
15   wire [31:0] y;
16   reg 	       a;
17   test004 sub (/*AUTOINST*/
18		// Outputs
19		.y			(y[31:0]),
20		// Inputs
21		.a			(a));
22
23   // Test loop
24   always @ (posedge clk) begin
25`ifdef TEST_VERBOSE
26      $write("[%0t] cyc==%0d a=%x y=%x\n", $time, cyc, a, y);
27`endif
28      cyc <= cyc + 1;
29      if (cyc==0) begin
30	 a <= 0;
31      end
32      else if (cyc==1) begin
33	 a <= 1;
34	 if (y != 32'h0) $stop;
35      end
36      else if (cyc==2) begin
37	 if (y != 32'h010000ff) $stop;
38      end
39      else if (cyc==99) begin
40	 $write("*-* All Finished *-*\n");
41	 $finish;
42      end
43   end
44
45endmodule
46
47module test004(a, y);
48  input a;
49  output [31:0] y;
50
51  wire [7:0] y0;
52  wire [7:0] y1;
53  wire [7:0] y2;
54  wire [7:0] y3;
55  assign y = {y0,y1,y2,y3};
56
57  localparam [7:0] v0 = +8'sd1 ** -8'sd2; //'h01
58  localparam [7:0] v1 = +8'sd2 ** -8'sd2; //'h00
59  localparam [7:0] v2 = -8'sd2 ** -8'sd3; //'h00
60  localparam [7:0] v3 = -8'sd1 ** -8'sd3; //'hff
61  localparam [7:0] zero = 0;
62
63   initial $display("v0=%x v1=%x v2=%x v3=%x", v0,v1,v2,v3);
64
65  assign y0 = a ? v0 : zero;
66  assign y1 = a ? v1 : zero;
67  assign y2 = a ? v2 : zero;
68  assign y3 = a ? v3 : zero;
69endmodule
70