1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2017 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Outputs 9 i65, j65, i33, j33, i30, j30, q65, r65, q33, r33, q30, r30, w65, x65, w33, 10 x33, w30, x30, 11 // Inputs 12 a, a40, a70 13 ); 14 15 input [3:0] a; 16 input [39:0] a40; 17 input [69:0] a70; 18 19 // -- Verilator 621c515 creates code that uses the undeclared function VL_POW_WWI() 20 // verilator lint_off WIDTH 21 output [3:0] i65 = 65'd3 ** a; // WWI 22 output [3:0] j65 = a ** 65'd3; // IIW 23 output [3:0] i33 = 33'd3 ** a; // QQI 24 output [3:0] j33 = a ** 33'd3; // IIQ 25 output [3:0] i30 = 30'd3 ** a; // III 26 output [3:0] j30 = a ** 30'd3; // III 27 28 output [39:0] q65 = 65'd3 ** a40; // WWQ 29 output [39:0] r65 = a40 ** 65'd3; // WWQ 30 output [39:0] q33 = 33'd3 ** a40; // QQQ 31 output [39:0] r33 = a40 ** 33'd3; // QQQ 32 output [39:0] q30 = 30'd3 ** a40; // QQI 33 output [39:0] r30 = a40 ** 30'd3; // QQI 34 35 output [69:0] w65 = 65'd3 ** a70; // WWW 36 output [69:0] x65 = a70 ** 65'd3; // WWW 37 output [69:0] w33 = 33'd3 ** a70; // WWW 38 output [69:0] x33 = a70 ** 33'd3; // WWW 39 output [69:0] w30 = 30'd3 ** a70; // WWW 40 output [69:0] x30 = a70 ** 30'd3; // WWW 41 // verilator lint_on WIDTH 42 43 initial begin 44 $write("*-* All Finished *-*\n"); 45 $finish; 46 end 47endmodule 48