1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2006 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/
8   // Inputs
9   clk
10   );
11
12   input clk;
13
14   integer cyc; initial cyc = 0;
15   reg [63:0] crc;
16   reg [31:0] sum;
17
18   wire [15:0]		out0;
19   wire [15:0]		out1;
20   wire [15:0] 		inData = crc[15:0];
21   wire  		wr0a = crc[16];
22   wire  		wr0b = crc[17];
23   wire  		wr1a = crc[18];
24   wire  		wr1b = crc[19];
25
26   fifo fifo (
27	      // Outputs
28	      .out0			(out0[15:0]),
29	      .out1			(out1[15:0]),
30	      // Inputs
31	      .clk			(clk),
32	      .wr0a			(wr0a),
33	      .wr0b			(wr0b),
34	      .wr1a			(wr1a),
35	      .wr1b			(wr1b),
36	      .inData			(inData[15:0]));
37
38   always @ (posedge clk) begin
39      //$write("[%0t] cyc==%0d crc=%x q=%x\n", $time, cyc, crc, sum);
40      cyc <= cyc + 1;
41      crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
42      if (cyc==0) begin
43	 // Setup
44	 crc <= 64'h5aef0c8d_d70a4497;
45	 sum <= 32'h0;
46      end
47      else if (cyc>10 && cyc<90) begin
48	 sum <= {sum[30:0],sum[31]} ^ {out1, out0};
49      end
50      else if (cyc==99) begin
51	 if (sum !== 32'he8bbd130) $stop;
52	 $write("*-* All Finished *-*\n");
53	 $finish;
54      end
55   end
56
57endmodule
58
59module fifo (/*AUTOARG*/
60   // Outputs
61   out0, out1,
62   // Inputs
63   clk, wr0a, wr0b, wr1a, wr1b, inData
64   );
65
66   input         clk;
67   input 	 wr0a;
68   input 	 wr0b;
69   input 	 wr1a;
70   input 	 wr1b;
71   input [15:0]  inData;
72
73   output [15:0] out0;
74   output [15:0] out1;
75
76   reg [15:0] 	 mem [1:0];
77   reg [15:0] 	 memtemp2 [1:0];
78   reg [15:0] 	 memtemp3 [1:0];
79
80   assign 	 out0 = {mem[0] ^ memtemp2[0]};
81   assign 	 out1 = {mem[1] ^ memtemp3[1]};
82
83   always @(posedge clk) begin
84      // These mem assignments must be done in order after processing
85      if (wr0a) begin
86	 memtemp2[0] <= inData;
87	 mem[0] <=  inData;
88      end
89      if (wr0b) begin
90	 memtemp3[0] <= inData;
91	 mem[0] <= ~inData;
92      end
93      if (wr1a) begin
94	 memtemp3[1] <= inData;
95	 mem[1] <=  inData;
96      end
97      if (wr1b) begin
98	 memtemp2[1] <= inData;
99	 mem[1] <= ~inData;
100      end
101   end
102
103endmodule
104