1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2003 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/
8   // Inputs
9   clk
10   );
11   input clk;
12   integer cyc; initial cyc=1;
13
14   // verilator lint_off LATCH
15   // verilator lint_off UNOPT
16   // verilator lint_off UNOPTFLAT
17   reg [31:0] runner;  initial runner = 5;
18   reg [31:0] runnerm1;
19   reg [59:0] runnerq;
20   reg [89:0] runnerw;
21   always @ (posedge clk) begin
22      if (cyc!=0) begin
23	 cyc <= cyc + 1;
24	 if (cyc==1) begin
25`ifdef verilator
26	    if (runner != 0) $stop;  // Initial settlement failed
27`endif
28	 end
29	 if (cyc==2) begin
30	    runner = 20;
31	    runnerq = 60'h0;
32	    runnerw = 90'h0;
33	 end
34	 if (cyc==3) begin
35	    if (runner != 0) $stop;
36	    $write("*-* All Finished *-*\n");
37	    $finish;
38	 end
39      end
40   end
41
42   // This forms a "loop" where we keep going through the always till runner=0
43   // This isn't "regular" beh code, but ensures our change detection is working properly
44   always @ (/*AS*/runner) begin
45      runnerm1 = runner - 32'd1;
46   end
47
48   always @ (/*AS*/runnerm1) begin
49      if (runner > 0) begin
50	 runner = runnerm1;
51	 runnerq = runnerq - 60'd1;
52	 runnerw = runnerw - 90'd1;
53	 $write ("[%0t] runner=%d\n", $time, runner);
54      end
55   end
56
57endmodule
58