1 // -*- mode: C++; c-file-style: "cc-mode" -*-
2 //
3 // DESCRIPTION: Verilator: Verilog Test module
4 //
5 // This file ONLY is placed under the Creative Commons Public Domain, for
6 // any use, without warranty, 2010 by Wilson Snyder.
7 // SPDX-License-Identifier: CC0-1.0
8
9 #include <verilated.h>
10 #include "Vt_order_quad.h"
11
12 //======================================================================
13
14 unsigned int main_time = 0;
15
sc_time_stamp()16 double sc_time_stamp() { return main_time; }
17
18 VM_PREFIX* topp = nullptr;
19 bool fail = false;
20
check(QData got,QData exp)21 void check(QData got, QData exp) {
22 if (got != exp) {
23 VL_PRINTF("%%Error: got=0x%" VL_PRI64 "x exp=0x%" VL_PRI64 "x\n", got, exp);
24 fail = true;
25 }
26 }
27
main(int argc,char * argv[])28 int main(int argc, char* argv[]) {
29 topp = new VM_PREFIX;
30
31 Verilated::debug(0);
32
33 topp->a0 = 0;
34 topp->eval();
35 check(topp->y, 0x0ULL);
36
37 topp->a0 = 15;
38 topp->eval();
39 check(topp->y, 0x3c00000000ULL);
40
41 if (!fail) {
42 VL_PRINTF("*-* All Finished *-*\n");
43 topp->final();
44 } else {
45 vl_fatal(__FILE__, __LINE__, "top", "Unexpected results\n");
46 }
47
48 VL_DO_DANGLING(delete topp, topp);
49 return 0;
50 }
51