1// DESCRIPTION: Verilator: Verilog Test module
2//
3// We see Verilator assumes a 1-bit parameter is a scalar rather than a 1-bit
4// long vector. This causes the following code to fail.
5//
6// Other event drive simulators accept this.
7//
8// This file ONLY is placed into the Public Domain, for any use,
9// without warranty, 2013 by Jeremy Bennett.
10// SPDX-License-Identifier: CC0-1.0
11
12module t (/*AUTOARG*/
13   // Inputs
14   clk
15   );
16   input clk;
17
18   // At this point it is ambiguous whether a is scalar or vector
19   parameter a = 1'b0;
20   wire  b = a[0];
21   // Note however b[0] is illegal.
22
23   always @(posedge clk) begin
24      if (b == 1'b0) begin
25	 $write("*-* All Finished *-*\n");
26	 $finish;
27      end
28      else begin
29	 $stop;
30      end
31   end
32
33endmodule
34