1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2011 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6// 7// bug445 8 9`define WIDTH 12 10`define SEL_NUM_BITS `WIDTH-`SEL_NUM_BITS +: `SEL_NUM_BITS 11`define SEL_BITS `WIDTH-`SEL_NUM_BITS +: `SEL_NUM_BITS 12`define ADDR_BITS 0 +: `WIDTH-`SEL_NUM_BITS 13 14typedef logic [`SEL_NUM_BITS-1:0] d_t; 15