1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2010 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7//See bug289
8
9`define A1(x)
10`define A2(x,y)
11
12`A1
13`A1(1,2)
14`A2
15`A2(1)
16`A2(1,2,3)
17
18module t;
19endmodule
20