1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2008 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Inputs 9 clk 10 ); 11 input clk; 12 13 reg [1:0] in; 14 15 /*AUTOWIRE*/ 16 // Beginning of automatic wires (for undeclared instantiated-module outputs) 17 wire [1:0] out10; // From test of Test.v 18 wire [1:0] out32; // From test of Test.v 19 // End of automatics 20 21 Test test (/*AUTOINST*/ 22 // Outputs 23 .out32 (out32[1:0]), 24 .out10 (out10[1:0]), 25 // Inputs 26 .in (in[1:0])); 27 28 // Test loop 29 always @ (posedge clk) begin 30 in <= in + 1; 31`ifdef TEST_VERBOSE 32 $write("[%0t] in=%d out32=%d out10=%d\n", $time, in, out32, out10); 33`endif 34 if (in==3) begin 35 $write("*-* All Finished *-*\n"); 36 $finish; 37 end 38 end 39endmodule 40 41module Test (/*AUTOARG*/ 42 // Outputs 43 out32, out10, 44 // Inputs 45 in 46 ); 47 input [1:0] in; 48 output [1:0] out32; 49 output [1:0] out10; 50 51 assign out32 = in[3:2]; 52 assign out10 = in[1:0]; 53endmodule 54