1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under The Creative Commons Public Domain, for 4// any use, without warranty, 2021 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7timeunit 10ps; 8timeprecision 10ps; 9 10task show; 11 $printtimescale; 12endtask 13 14module from_unit; 15 task show; 16 $printtimescale; 17 endtask 18endmodule 19 20module t; 21 from_unit from_unit(); 22 timeunit 100ps; 23 initial begin 24 show(); 25 from_unit.show(); 26 $printtimescale; 27 $write("*-* All Finished *-*\n"); 28 $finish; 29 end 30endmodule 31