1// DESCRIPTION: Verilator: Verilog Test module
2//
3// Copyright 2010 by Wilson Snyder. This program is free software; you can
4// redistribute it and/or modify it under the terms of either the GNU
5// Lesser General Public License Version 3 or the Perl Artistic License
6// Version 2.0.
7// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
8
9module t;
10
11   // bug1081 - We don't use VPI, just need SC with VPI
12
13   initial begin
14      $write("%0t: Hello\n", $time);
15      $write("*-* All Finished *-*\n");
16      $finish;
17   end
18
19endmodule : t
20