1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2018 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (
8   output o,
9   output [1:0] oa,
10   output reg ro,
11   output reg [1:0] roa,
12   output wire wo,
13   output wire [1:0] woa,
14   // 1800 only
15   output var vo,
16   output var [1:0] voa
17   );
18
19   wire w;
20   reg  r;
21
22   initial begin
23      w = '0;  // Error
24      o = '0;  // Error
25      oa = '0;  // Error
26      wo = '0;  // Error
27      woa = '0;  // Error
28      r = '0;  // Not an error
29      ro = '0;  // Not an error
30      roa = '0;  // Not an error
31      vo = '0;  // Not an error
32      voa = '0;  // Not an error
33   end
34
35endmodule
36