1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 #include "kernel/yosys.h"
22 #include "kernel/sigtools.h"
23 #include <deque>
24
25 USING_YOSYS_NAMESPACE
26 PRIVATE_NAMESPACE_BEGIN
27
28 #include "passes/pmgen/xilinx_dsp_pm.h"
29 #include "passes/pmgen/xilinx_dsp48a_pm.h"
30 #include "passes/pmgen/xilinx_dsp_CREG_pm.h"
31 #include "passes/pmgen/xilinx_dsp_cascade_pm.h"
32
addDsp(Module * module)33 static Cell* addDsp(Module *module) {
34 Cell *cell = module->addCell(NEW_ID, ID(DSP48E1));
35 cell->setParam(ID(ACASCREG), 0);
36 cell->setParam(ID(ADREG), 0);
37 cell->setParam(ID(A_INPUT), Const("DIRECT"));
38 cell->setParam(ID(ALUMODEREG), 0);
39 cell->setParam(ID(AREG), 0);
40 cell->setParam(ID(BCASCREG), 0);
41 cell->setParam(ID(B_INPUT), Const("DIRECT"));
42 cell->setParam(ID(BREG), 0);
43 cell->setParam(ID(CARRYINREG), 0);
44 cell->setParam(ID(CARRYINSELREG), 0);
45 cell->setParam(ID(CREG), 0);
46 cell->setParam(ID(DREG), 0);
47 cell->setParam(ID(INMODEREG), 0);
48 cell->setParam(ID(MREG), 0);
49 cell->setParam(ID(OPMODEREG), 0);
50 cell->setParam(ID(PREG), 0);
51 cell->setParam(ID(USE_MULT), Const("NONE"));
52 cell->setParam(ID(USE_SIMD), Const("ONE48"));
53 cell->setParam(ID(USE_DPORT), Const("FALSE"));
54
55 cell->setPort(ID::D, Const(0, 25));
56 cell->setPort(ID(INMODE), Const(0, 5));
57 cell->setPort(ID(ALUMODE), Const(0, 4));
58 cell->setPort(ID(OPMODE), Const(0, 7));
59 cell->setPort(ID(CARRYINSEL), Const(0, 3));
60 cell->setPort(ID(ACIN), Const(0, 30));
61 cell->setPort(ID(BCIN), Const(0, 18));
62 cell->setPort(ID(PCIN), Const(0, 48));
63 cell->setPort(ID(CARRYIN), Const(0, 1));
64 return cell;
65 }
66
xilinx_simd_pack(Module * module,const std::vector<Cell * > & selected_cells)67 void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
68 {
69 std::deque<Cell*> simd12_add, simd12_sub;
70 std::deque<Cell*> simd24_add, simd24_sub;
71
72 for (auto cell : selected_cells) {
73 if (!cell->type.in(ID($add), ID($sub)))
74 continue;
75 SigSpec Y = cell->getPort(ID::Y);
76 if (!Y.is_chunk())
77 continue;
78 if (!Y.as_chunk().wire->get_strpool_attribute(ID(use_dsp)).count("simd"))
79 continue;
80 if (GetSize(Y) > 25)
81 continue;
82 SigSpec A = cell->getPort(ID::A);
83 SigSpec B = cell->getPort(ID::B);
84 if (GetSize(Y) <= 13) {
85 if (GetSize(A) > 12)
86 continue;
87 if (GetSize(B) > 12)
88 continue;
89 if (cell->type == ID($add))
90 simd12_add.push_back(cell);
91 else if (cell->type == ID($sub))
92 simd12_sub.push_back(cell);
93 }
94 else if (GetSize(Y) <= 25) {
95 if (GetSize(A) > 24)
96 continue;
97 if (GetSize(B) > 24)
98 continue;
99 if (cell->type == ID($add))
100 simd24_add.push_back(cell);
101 else if (cell->type == ID($sub))
102 simd24_sub.push_back(cell);
103 }
104 else
105 log_abort();
106 }
107
108 auto f12 = [module](SigSpec &AB, SigSpec &C, SigSpec &P, SigSpec &CARRYOUT, Cell *lane) {
109 SigSpec A = lane->getPort(ID::A);
110 SigSpec B = lane->getPort(ID::B);
111 SigSpec Y = lane->getPort(ID::Y);
112 A.extend_u0(12, lane->getParam(ID::A_SIGNED).as_bool());
113 B.extend_u0(12, lane->getParam(ID::B_SIGNED).as_bool());
114 AB.append(A);
115 C.append(B);
116 if (GetSize(Y) < 13)
117 Y.append(module->addWire(NEW_ID, 13-GetSize(Y)));
118 else
119 log_assert(GetSize(Y) == 13);
120 P.append(Y.extract(0, 12));
121 CARRYOUT.append(Y[12]);
122 };
123 auto g12 = [&f12,module](std::deque<Cell*> &simd12) {
124 while (simd12.size() > 1) {
125 SigSpec AB, C, P, CARRYOUT;
126
127 Cell *lane1 = simd12.front();
128 simd12.pop_front();
129 Cell *lane2 = simd12.front();
130 simd12.pop_front();
131 Cell *lane3 = nullptr;
132 Cell *lane4 = nullptr;
133
134 if (!simd12.empty()) {
135 lane3 = simd12.front();
136 simd12.pop_front();
137 if (!simd12.empty()) {
138 lane4 = simd12.front();
139 simd12.pop_front();
140 }
141 }
142
143 log("Analysing %s.%s for Xilinx DSP SIMD12 packing.\n", log_id(module), log_id(lane1));
144
145 Cell *cell = addDsp(module);
146 cell->setParam(ID(USE_SIMD), Const("FOUR12"));
147 // X = A:B
148 // Y = 0
149 // Z = C
150 cell->setPort(ID(OPMODE), Const::from_string("0110011"));
151
152 log_assert(lane1);
153 log_assert(lane2);
154 f12(AB, C, P, CARRYOUT, lane1);
155 f12(AB, C, P, CARRYOUT, lane2);
156 if (lane3) {
157 f12(AB, C, P, CARRYOUT, lane3);
158 if (lane4)
159 f12(AB, C, P, CARRYOUT, lane4);
160 else {
161 AB.append(Const(0, 12));
162 C.append(Const(0, 12));
163 P.append(module->addWire(NEW_ID, 12));
164 CARRYOUT.append(module->addWire(NEW_ID, 1));
165 }
166 }
167 else {
168 AB.append(Const(0, 24));
169 C.append(Const(0, 24));
170 P.append(module->addWire(NEW_ID, 24));
171 CARRYOUT.append(module->addWire(NEW_ID, 2));
172 }
173 log_assert(GetSize(AB) == 48);
174 log_assert(GetSize(C) == 48);
175 log_assert(GetSize(P) == 48);
176 log_assert(GetSize(CARRYOUT) == 4);
177 cell->setPort(ID::A, AB.extract(18, 30));
178 cell->setPort(ID::B, AB.extract(0, 18));
179 cell->setPort(ID::C, C);
180 cell->setPort(ID::P, P);
181 cell->setPort(ID(CARRYOUT), CARRYOUT);
182 if (lane1->type == ID($sub))
183 cell->setPort(ID(ALUMODE), Const::from_string("0011"));
184
185 module->remove(lane1);
186 module->remove(lane2);
187 if (lane3) module->remove(lane3);
188 if (lane4) module->remove(lane4);
189
190 module->design->select(module, cell);
191 }
192 };
193 g12(simd12_add);
194 g12(simd12_sub);
195
196 auto f24 = [module](SigSpec &AB, SigSpec &C, SigSpec &P, SigSpec &CARRYOUT, Cell *lane) {
197 SigSpec A = lane->getPort(ID::A);
198 SigSpec B = lane->getPort(ID::B);
199 SigSpec Y = lane->getPort(ID::Y);
200 A.extend_u0(24, lane->getParam(ID::A_SIGNED).as_bool());
201 B.extend_u0(24, lane->getParam(ID::B_SIGNED).as_bool());
202 C.append(A);
203 AB.append(B);
204 if (GetSize(Y) < 25)
205 Y.append(module->addWire(NEW_ID, 25-GetSize(Y)));
206 else
207 log_assert(GetSize(Y) == 25);
208 P.append(Y.extract(0, 24));
209 CARRYOUT.append(module->addWire(NEW_ID)); // TWO24 uses every other bit
210 CARRYOUT.append(Y[24]);
211 };
212 auto g24 = [&f24,module](std::deque<Cell*> &simd24) {
213 while (simd24.size() > 1) {
214 SigSpec AB;
215 SigSpec C;
216 SigSpec P;
217 SigSpec CARRYOUT;
218
219 Cell *lane1 = simd24.front();
220 simd24.pop_front();
221 Cell *lane2 = simd24.front();
222 simd24.pop_front();
223
224 log("Analysing %s.%s for Xilinx DSP SIMD24 packing.\n", log_id(module), log_id(lane1));
225
226 Cell *cell = addDsp(module);
227 cell->setParam(ID(USE_SIMD), Const("TWO24"));
228 // X = A:B
229 // Y = 0
230 // Z = C
231 cell->setPort(ID(OPMODE), Const::from_string("0110011"));
232
233 log_assert(lane1);
234 log_assert(lane2);
235 f24(AB, C, P, CARRYOUT, lane1);
236 f24(AB, C, P, CARRYOUT, lane2);
237 log_assert(GetSize(AB) == 48);
238 log_assert(GetSize(C) == 48);
239 log_assert(GetSize(P) == 48);
240 log_assert(GetSize(CARRYOUT) == 4);
241 cell->setPort(ID::A, AB.extract(18, 30));
242 cell->setPort(ID::B, AB.extract(0, 18));
243 cell->setPort(ID::C, C);
244 cell->setPort(ID::P, P);
245 cell->setPort(ID(CARRYOUT), CARRYOUT);
246 if (lane1->type == ID($sub))
247 cell->setPort(ID(ALUMODE), Const::from_string("0011"));
248
249 module->remove(lane1);
250 module->remove(lane2);
251
252 module->design->select(module, cell);
253 }
254 };
255 g24(simd24_add);
256 g24(simd24_sub);
257 }
258
xilinx_dsp_pack(xilinx_dsp_pm & pm)259 void xilinx_dsp_pack(xilinx_dsp_pm &pm)
260 {
261 auto &st = pm.st_xilinx_dsp_pack;
262
263 log("Analysing %s.%s for Xilinx DSP packing.\n", log_id(pm.module), log_id(st.dsp));
264
265 log_debug("preAdd: %s\n", log_id(st.preAdd, "--"));
266 log_debug("ffAD: %s\n", log_id(st.ffAD, "--"));
267 log_debug("ffA2: %s\n", log_id(st.ffA2, "--"));
268 log_debug("ffA1: %s\n", log_id(st.ffA1, "--"));
269 log_debug("ffB2: %s\n", log_id(st.ffB2, "--"));
270 log_debug("ffB1: %s\n", log_id(st.ffB1, "--"));
271 log_debug("ffD: %s\n", log_id(st.ffD, "--"));
272 log_debug("dsp: %s\n", log_id(st.dsp, "--"));
273 log_debug("ffM: %s\n", log_id(st.ffM, "--"));
274 log_debug("postAdd: %s\n", log_id(st.postAdd, "--"));
275 log_debug("postAddMux: %s\n", log_id(st.postAddMux, "--"));
276 log_debug("ffP: %s\n", log_id(st.ffP, "--"));
277 log_debug("overflow: %s\n", log_id(st.overflow, "--"));
278
279 Cell *cell = st.dsp;
280
281 if (st.preAdd) {
282 log(" preadder %s (%s)\n", log_id(st.preAdd), log_id(st.preAdd->type));
283 bool A_SIGNED = st.preAdd->getParam(ID::A_SIGNED).as_bool();
284 bool D_SIGNED = st.preAdd->getParam(ID::B_SIGNED).as_bool();
285 if (st.sigA == st.preAdd->getPort(ID::B))
286 std::swap(A_SIGNED, D_SIGNED);
287 st.sigA.extend_u0(30, A_SIGNED);
288 st.sigD.extend_u0(25, D_SIGNED);
289 cell->setPort(ID::A, st.sigA);
290 cell->setPort(ID::D, st.sigD);
291 cell->setPort(ID(INMODE), Const::from_string("00100"));
292
293 if (st.ffAD) {
294 if (st.ffAD->type.in(ID($dffe), ID($sdffe))) {
295 bool pol = st.ffAD->getParam(ID::EN_POLARITY).as_bool();
296 SigSpec S = st.ffAD->getPort(ID::EN);
297 cell->setPort(ID(CEAD), pol ? S : pm.module->Not(NEW_ID, S));
298 }
299 else
300 cell->setPort(ID(CEAD), State::S1);
301 cell->setParam(ID(ADREG), 1);
302 }
303
304 cell->setParam(ID(USE_DPORT), Const("TRUE"));
305
306 pm.autoremove(st.preAdd);
307 }
308 if (st.postAdd) {
309 log(" postadder %s (%s)\n", log_id(st.postAdd), log_id(st.postAdd->type));
310
311 SigSpec &opmode = cell->connections_.at(ID(OPMODE));
312 if (st.postAddMux) {
313 log_assert(st.ffP);
314 opmode[4] = st.postAddMux->getPort(ID::S);
315 pm.autoremove(st.postAddMux);
316 }
317 else if (st.ffP && st.sigC == st.sigP)
318 opmode[4] = State::S0;
319 else
320 opmode[4] = State::S1;
321 opmode[6] = State::S0;
322 opmode[5] = State::S1;
323
324 if (opmode[4] != State::S0) {
325 if (st.postAddMuxAB == ID::A)
326 st.sigC.extend_u0(48, st.postAdd->getParam(ID::B_SIGNED).as_bool());
327 else
328 st.sigC.extend_u0(48, st.postAdd->getParam(ID::A_SIGNED).as_bool());
329 cell->setPort(ID::C, st.sigC);
330 }
331
332 pm.autoremove(st.postAdd);
333 }
334 if (st.overflow) {
335 log(" overflow %s (%s)\n", log_id(st.overflow), log_id(st.overflow->type));
336 cell->setParam(ID(USE_PATTERN_DETECT), Const("PATDET"));
337 cell->setParam(ID(SEL_PATTERN), Const("PATTERN"));
338 cell->setParam(ID(SEL_MASK), Const("MASK"));
339
340 if (st.overflow->type == ID($ge)) {
341 Const B = st.overflow->getPort(ID::B).as_const();
342 log_assert(std::count(B.bits.begin(), B.bits.end(), State::S1) == 1);
343 // Since B is an exact power of 2, subtract 1
344 // by inverting all bits up until hitting
345 // that one hi bit
346 for (auto &b : B.bits)
347 if (b == State::S0) b = State::S1;
348 else if (b == State::S1) {
349 b = State::S0;
350 break;
351 }
352 B.extu(48);
353
354 cell->setParam(ID(MASK), B);
355 cell->setParam(ID(PATTERN), Const(0, 48));
356 cell->setPort(ID(OVERFLOW), st.overflow->getPort(ID::Y));
357 }
358 else log_abort();
359
360 pm.autoremove(st.overflow);
361 }
362
363 if (st.clock != SigBit())
364 {
365 cell->setPort(ID::CLK, st.clock);
366
367 auto f = [&pm,cell](SigSpec &A, Cell* ff, IdString ceport, IdString rstport) {
368 SigSpec D = ff->getPort(ID::D);
369 SigSpec Q = pm.sigmap(ff->getPort(ID::Q));
370 if (!A.empty())
371 A.replace(Q, D);
372 if (rstport != IdString()) {
373 if (ff->type.in(ID($sdff), ID($sdffe))) {
374 SigSpec srst = ff->getPort(ID::SRST);
375 bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool();
376 cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_ID, srst));
377 } else {
378 cell->setPort(rstport, State::S0);
379 }
380 }
381 if (ff->type.in(ID($dffe), ID($sdffe))) {
382 SigSpec ce = ff->getPort(ID::EN);
383 bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
384 cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
385 }
386 else
387 cell->setPort(ceport, State::S1);
388
389 for (auto c : Q.chunks()) {
390 auto it = c.wire->attributes.find(ID::init);
391 if (it == c.wire->attributes.end())
392 continue;
393 for (int i = c.offset; i < c.offset+c.width; i++) {
394 log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
395 it->second[i] = State::Sx;
396 }
397 }
398 };
399
400 if (st.ffA2) {
401 SigSpec A = cell->getPort(ID::A);
402 f(A, st.ffA2, ID(CEA2), ID(RSTA));
403 if (st.ffA1) {
404 f(A, st.ffA1, ID(CEA1), IdString());
405 cell->setParam(ID(AREG), 2);
406 cell->setParam(ID(ACASCREG), 2);
407 }
408 else {
409 cell->setParam(ID(AREG), 1);
410 cell->setParam(ID(ACASCREG), 1);
411 }
412 pm.add_siguser(A, cell);
413 cell->setPort(ID::A, A);
414 }
415 if (st.ffB2) {
416 SigSpec B = cell->getPort(ID::B);
417 f(B, st.ffB2, ID(CEB2), ID(RSTB));
418 if (st.ffB1) {
419 f(B, st.ffB1, ID(CEB1), IdString());
420 cell->setParam(ID(BREG), 2);
421 cell->setParam(ID(BCASCREG), 2);
422 }
423 else {
424 cell->setParam(ID(BREG), 1);
425 cell->setParam(ID(BCASCREG), 1);
426 }
427 pm.add_siguser(B, cell);
428 cell->setPort(ID::B, B);
429 }
430 if (st.ffD) {
431 SigSpec D = cell->getPort(ID::D);
432 f(D, st.ffD, ID(CED), ID(RSTD));
433 pm.add_siguser(D, cell);
434 cell->setPort(ID::D, D);
435 cell->setParam(ID(DREG), 1);
436 }
437 if (st.ffM) {
438 SigSpec M; // unused
439 f(M, st.ffM, ID(CEM), ID(RSTM));
440 st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM)));
441 cell->setParam(ID(MREG), State::S1);
442 }
443 if (st.ffP) {
444 SigSpec P; // unused
445 f(P, st.ffP, ID(CEP), ID(RSTP));
446 st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP)));
447 cell->setParam(ID(PREG), State::S1);
448 }
449
450 log(" clock: %s (%s)", log_signal(st.clock), "posedge");
451
452 if (st.ffA2) {
453 log(" ffA2:%s", log_id(st.ffA2));
454 if (st.ffA1)
455 log(" ffA1:%s", log_id(st.ffA1));
456 }
457
458 if (st.ffAD)
459 log(" ffAD:%s", log_id(st.ffAD));
460
461 if (st.ffB2) {
462 log(" ffB2:%s", log_id(st.ffB2));
463 if (st.ffB1)
464 log(" ffB1:%s", log_id(st.ffB1));
465 }
466
467 if (st.ffD)
468 log(" ffD:%s", log_id(st.ffD));
469
470 if (st.ffM)
471 log(" ffM:%s", log_id(st.ffM));
472
473 if (st.ffP)
474 log(" ffP:%s", log_id(st.ffP));
475 }
476 log("\n");
477
478 SigSpec P = st.sigP;
479 if (GetSize(P) < 48)
480 P.append(pm.module->addWire(NEW_ID, 48-GetSize(P)));
481 cell->setPort(ID::P, P);
482
483 pm.blacklist(cell);
484 }
485
xilinx_dsp48a_pack(xilinx_dsp48a_pm & pm)486 void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
487 {
488 auto &st = pm.st_xilinx_dsp48a_pack;
489
490 log("Analysing %s.%s for Xilinx DSP48A/DSP48A1 packing.\n", log_id(pm.module), log_id(st.dsp));
491
492 log_debug("preAdd: %s\n", log_id(st.preAdd, "--"));
493 log_debug("ffA1: %s\n", log_id(st.ffA1, "--"));
494 log_debug("ffA0: %s\n", log_id(st.ffA0, "--"));
495 log_debug("ffB1: %s\n", log_id(st.ffB1, "--"));
496 log_debug("ffB0: %s\n", log_id(st.ffB0, "--"));
497 log_debug("ffD: %s\n", log_id(st.ffD, "--"));
498 log_debug("dsp: %s\n", log_id(st.dsp, "--"));
499 log_debug("ffM: %s\n", log_id(st.ffM, "--"));
500 log_debug("postAdd: %s\n", log_id(st.postAdd, "--"));
501 log_debug("postAddMux: %s\n", log_id(st.postAddMux, "--"));
502 log_debug("ffP: %s\n", log_id(st.ffP, "--"));
503
504 Cell *cell = st.dsp;
505 SigSpec &opmode = cell->connections_.at(ID(OPMODE));
506
507 if (st.preAdd) {
508 log(" preadder %s (%s)\n", log_id(st.preAdd), log_id(st.preAdd->type));
509 bool D_SIGNED = st.preAdd->getParam(ID::A_SIGNED).as_bool();
510 bool B_SIGNED = st.preAdd->getParam(ID::B_SIGNED).as_bool();
511 st.sigB.extend_u0(18, B_SIGNED);
512 st.sigD.extend_u0(18, D_SIGNED);
513 cell->setPort(ID::B, st.sigB);
514 cell->setPort(ID::D, st.sigD);
515 opmode[4] = State::S1;
516 if (st.preAdd->type == ID($add))
517 opmode[6] = State::S0;
518 else if (st.preAdd->type == ID($sub))
519 opmode[6] = State::S1;
520 else
521 log_assert(!"strange pre-adder type");
522
523 pm.autoremove(st.preAdd);
524 }
525 if (st.postAdd) {
526 log(" postadder %s (%s)\n", log_id(st.postAdd), log_id(st.postAdd->type));
527
528 if (st.postAddMux) {
529 log_assert(st.ffP);
530 opmode[2] = st.postAddMux->getPort(ID::S);
531 pm.autoremove(st.postAddMux);
532 }
533 else if (st.ffP && st.sigC == st.sigP)
534 opmode[2] = State::S0;
535 else
536 opmode[2] = State::S1;
537 opmode[3] = State::S1;
538
539 if (opmode[2] != State::S0) {
540 if (st.postAddMuxAB == ID::A)
541 st.sigC.extend_u0(48, st.postAdd->getParam(ID::B_SIGNED).as_bool());
542 else
543 st.sigC.extend_u0(48, st.postAdd->getParam(ID::A_SIGNED).as_bool());
544 cell->setPort(ID::C, st.sigC);
545 }
546
547 pm.autoremove(st.postAdd);
548 }
549
550 if (st.clock != SigBit())
551 {
552 cell->setPort(ID::CLK, st.clock);
553
554 auto f = [&pm,cell](SigSpec &A, Cell* ff, IdString ceport, IdString rstport) {
555 SigSpec D = ff->getPort(ID::D);
556 SigSpec Q = pm.sigmap(ff->getPort(ID::Q));
557 if (!A.empty())
558 A.replace(Q, D);
559 if (rstport != IdString()) {
560 if (ff->type.in(ID($sdff), ID($sdffe))) {
561 SigSpec srst = ff->getPort(ID::SRST);
562 bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool();
563 cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_ID, srst));
564 } else {
565 cell->setPort(rstport, State::S0);
566 }
567 }
568 if (ff->type.in(ID($dffe), ID($sdffe))) {
569 SigSpec ce = ff->getPort(ID::EN);
570 bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
571 cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
572 }
573 else
574 cell->setPort(ceport, State::S1);
575
576 for (auto c : Q.chunks()) {
577 auto it = c.wire->attributes.find(ID::init);
578 if (it == c.wire->attributes.end())
579 continue;
580 for (int i = c.offset; i < c.offset+c.width; i++) {
581 log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
582 it->second[i] = State::Sx;
583 }
584 }
585 };
586
587 if (st.ffA0 || st.ffA1) {
588 SigSpec A = cell->getPort(ID::A);
589 if (st.ffA1) {
590 f(A, st.ffA1, ID(CEA), ID(RSTA));
591 cell->setParam(ID(A1REG), 1);
592 }
593 if (st.ffA0) {
594 f(A, st.ffA0, ID(CEA), ID(RSTA));
595 cell->setParam(ID(A0REG), 1);
596 }
597 pm.add_siguser(A, cell);
598 cell->setPort(ID::A, A);
599 }
600 if (st.ffB0 || st.ffB1) {
601 SigSpec B = cell->getPort(ID::B);
602 if (st.ffB1) {
603 f(B, st.ffB1, ID(CEB), ID(RSTB));
604 cell->setParam(ID(B1REG), 1);
605 }
606 if (st.ffB0) {
607 f(B, st.ffB0, ID(CEB), ID(RSTB));
608 cell->setParam(ID(B0REG), 1);
609 }
610 pm.add_siguser(B, cell);
611 cell->setPort(ID::B, B);
612 }
613 if (st.ffD) {
614 SigSpec D = cell->getPort(ID::D);
615 f(D, st.ffD, ID(CED), ID(RSTD));
616 pm.add_siguser(D, cell);
617 cell->setPort(ID::D, D);
618 cell->setParam(ID(DREG), 1);
619 }
620 if (st.ffM) {
621 SigSpec M; // unused
622 f(M, st.ffM, ID(CEM), ID(RSTM));
623 st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM)));
624 cell->setParam(ID(MREG), State::S1);
625 }
626 if (st.ffP) {
627 SigSpec P; // unused
628 f(P, st.ffP, ID(CEP), ID(RSTP));
629 st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP)));
630 cell->setParam(ID(PREG), State::S1);
631 }
632
633 log(" clock: %s (%s)", log_signal(st.clock), "posedge");
634
635 if (st.ffA0)
636 log(" ffA0:%s", log_id(st.ffA0));
637 if (st.ffA1)
638 log(" ffA1:%s", log_id(st.ffA1));
639
640 if (st.ffB0)
641 log(" ffB0:%s", log_id(st.ffB0));
642 if (st.ffB1)
643 log(" ffB1:%s", log_id(st.ffB1));
644
645 if (st.ffD)
646 log(" ffD:%s", log_id(st.ffD));
647
648 if (st.ffM)
649 log(" ffM:%s", log_id(st.ffM));
650
651 if (st.ffP)
652 log(" ffP:%s", log_id(st.ffP));
653 }
654 log("\n");
655
656 SigSpec P = st.sigP;
657 if (GetSize(P) < 48)
658 P.append(pm.module->addWire(NEW_ID, 48-GetSize(P)));
659 cell->setPort(ID::P, P);
660
661 pm.blacklist(cell);
662 }
663
xilinx_dsp_packC(xilinx_dsp_CREG_pm & pm)664 void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
665 {
666 auto &st = pm.st_xilinx_dsp_packC;
667
668 log_debug("Analysing %s.%s for Xilinx DSP packing (CREG).\n", log_id(pm.module), log_id(st.dsp));
669 log_debug("ffC: %s\n", log_id(st.ffC, "--"));
670
671 Cell *cell = st.dsp;
672
673 if (st.clock != SigBit())
674 {
675 cell->setPort(ID::CLK, st.clock);
676
677 auto f = [&pm,cell](SigSpec &A, Cell* ff, IdString ceport, IdString rstport) {
678 SigSpec D = ff->getPort(ID::D);
679 SigSpec Q = pm.sigmap(ff->getPort(ID::Q));
680 if (!A.empty())
681 A.replace(Q, D);
682 if (rstport != IdString()) {
683 if (ff->type.in(ID($sdff), ID($sdffe))) {
684 SigSpec srst = ff->getPort(ID::SRST);
685 bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool();
686 cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_ID, srst));
687 } else {
688 cell->setPort(rstport, State::S0);
689 }
690 }
691 if (ff->type.in(ID($dffe), ID($sdffe))) {
692 SigSpec ce = ff->getPort(ID::EN);
693 bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
694 cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
695 }
696 else
697 cell->setPort(ceport, State::S1);
698
699 for (auto c : Q.chunks()) {
700 auto it = c.wire->attributes.find(ID::init);
701 if (it == c.wire->attributes.end())
702 continue;
703 for (int i = c.offset; i < c.offset+c.width; i++) {
704 log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
705 it->second[i] = State::Sx;
706 }
707 }
708 };
709
710 if (st.ffC) {
711 SigSpec C = cell->getPort(ID::C);
712 f(C, st.ffC, ID(CEC), ID(RSTC));
713 pm.add_siguser(C, cell);
714 cell->setPort(ID::C, C);
715 cell->setParam(ID(CREG), 1);
716 }
717
718 log(" clock: %s (%s)", log_signal(st.clock), "posedge");
719
720 if (st.ffC)
721 log(" ffC:%s", log_id(st.ffC));
722 log("\n");
723 }
724
725 pm.blacklist(cell);
726 }
727
728 struct XilinxDspPass : public Pass {
XilinxDspPassXilinxDspPass729 XilinxDspPass() : Pass("xilinx_dsp", "Xilinx: pack resources into DSPs") { }
helpXilinxDspPass730 void help() override
731 {
732 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
733 log("\n");
734 log(" xilinx_dsp [options] [selection]\n");
735 log("\n");
736 log("Pack input registers (A2, A1, B2, B1, C, D, AD; with optional enable/reset),\n");
737 log("pipeline registers (M; with optional enable/reset), output registers (P; with\n");
738 log("optional enable/reset), pre-adder and/or post-adder into Xilinx DSP resources.\n");
739 log("\n");
740 log("Multiply-accumulate operations using the post-adder with feedback on the 'C'\n");
741 log("input will be folded into the DSP. In this scenario only, the 'C' input can be\n");
742 log("used to override the current accumulation result with a new value, which will\n");
743 log("be added to the multiplier result to form the next accumulation result.\n");
744 log("\n");
745 log("Use of the dedicated 'PCOUT' -> 'PCIN' cascade path is detected for 'P' -> 'C'\n");
746 log("connections (optionally, where 'P' is right-shifted by 17-bits and used as an\n");
747 log("input to the post-adder -- a pattern common for summing partial products to\n");
748 log("implement wide multipliers). Limited support also exists for similar cascading\n");
749 log("for A and B using '[AB]COUT' -> '[AB]CIN'. Currently, cascade chains are limited\n");
750 log("to a maximum length of 20 cells, corresponding to the smallest Xilinx 7 Series\n");
751 log("device.\n");
752 log("\n");
753 log("This pass is a no-op if the scratchpad variable 'xilinx_dsp.multonly' is set\n");
754 log("to 1.\n");
755 log("\n");
756 log("\n");
757 log("Experimental feature: addition/subtractions less than 12 or 24 bits with the\n");
758 log("'(* use_dsp=\"simd\" *)' attribute attached to the output wire or attached to\n");
759 log("the add/subtract operator will cause those operations to be implemented using\n");
760 log("the 'SIMD' feature of DSPs.\n");
761 log("\n");
762 log("Experimental feature: the presence of a `$ge' cell attached to the registered\n");
763 log("P output implementing the operation \"(P >= <power-of-2>)\" will be transformed\n");
764 log("into using the DSP48E1's pattern detector feature for overflow detection.\n");
765 log("\n");
766 log(" -family {xcup|xcu|xc7|xc6v|xc5v|xc4v|xc6s|xc3sda}\n");
767 log(" select the family to target\n");
768 log(" default: xc7\n");
769 log("\n");
770 }
executeXilinxDspPass771 void execute(std::vector<std::string> args, RTLIL::Design *design) override
772 {
773 log_header(design, "Executing XILINX_DSP pass (pack resources into DSPs).\n");
774
775 std::string family = "xc7";
776 size_t argidx;
777 for (argidx = 1; argidx < args.size(); argidx++)
778 {
779 if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx+1 < args.size()) {
780 family = args[++argidx];
781 continue;
782 }
783 break;
784 }
785 extra_args(args, argidx, design);
786
787 // Don't bother distinguishing between those.
788 if (family == "xc6v")
789 family = "xc7";
790 if (family == "xcup")
791 family = "xcu";
792
793 for (auto module : design->selected_modules()) {
794
795 if (design->scratchpad_get_bool("xilinx_dsp.multonly"))
796 continue;
797
798 // Experimental feature: pack $add/$sub cells with
799 // (* use_dsp48="simd" *) into DSP48E1's using its
800 // SIMD feature
801 if (family == "xc7")
802 xilinx_simd_pack(module, module->selected_cells());
803
804 // Match for all features ([ABDMP][12]?REG, pre-adder,
805 // post-adder, pattern detector, etc.) except for CREG
806 if (family == "xc7") {
807 xilinx_dsp_pm pm(module, module->selected_cells());
808 pm.run_xilinx_dsp_pack(xilinx_dsp_pack);
809 } else if (family == "xc6s" || family == "xc3sda") {
810 xilinx_dsp48a_pm pm(module, module->selected_cells());
811 pm.run_xilinx_dsp48a_pack(xilinx_dsp48a_pack);
812 }
813 // Separating out CREG packing is necessary since there
814 // is no guarantee that the cell ordering corresponds
815 // to the "expected" case (i.e. the order in which
816 // they appear in the source) thus the possiblity
817 // existed that a register got packed as a CREG into a
818 // downstream DSP that should have otherwise been a
819 // PREG of an upstream DSP that had not been visited
820 // yet
821 {
822 xilinx_dsp_CREG_pm pm(module, module->selected_cells());
823 pm.run_xilinx_dsp_packC(xilinx_dsp_packC);
824 }
825 // Lastly, identify and utilise PCOUT -> PCIN,
826 // ACOUT -> ACIN, and BCOUT-> BCIN dedicated cascade
827 // chains
828 {
829 xilinx_dsp_cascade_pm pm(module, module->selected_cells());
830 pm.run_xilinx_dsp_cascade();
831 }
832 }
833 }
834 } XilinxDspPass;
835
836 PRIVATE_NAMESPACE_END
837