1read_verilog ../common/add_sub.v 2hierarchy -top top 3proc 4design -save orig 5 6equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check 7design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) 8cd top # Constrain all select calls below inside the top module 9stat 10select -assert-count 10 t:LUT4 11select -assert-none t:IB t:OB t:VLO t:LUT4 %% t:* %D 12 13design -load orig 14 15equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus -abc9 # equivalency check 16design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) 17cd top # Constrain all select calls below inside the top module 18stat 19select -assert-count 6 t:LUT4 20select -assert-count 4 t:WIDEFN9 21select -assert-none t:IB t:OB t:VLO t:LUT4 t:WIDEFN9 %% t:* %D 22