1read_verilog ../common/tribuf.v 2hierarchy -top tristate 3proc 4tribuf 5flatten 6synth 7equiv_opt -assert -map +/nexus/cells_sim.v -map +/simcells.v synth_nexus # equivalency check 8design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) 9cd tristate # Constrain all select calls below inside the top module 10select -assert-count 1 t:OBZ 11select -assert-count 1 t:INV 12select -assert-none t:OBZ t:INV t:IB t:OB t:VLO t:VHI %% t:* %D 13