1;; Constraint definitions for IA-64
2;; Copyright (C) 2006-2018 Free Software Foundation, Inc.
3;;
4;; This file is part of GCC.
5;;
6;; GCC is free software; you can redistribute it and/or modify
7;; it under the terms of the GNU General Public License as published by
8;; the Free Software Foundation; either version 3, or (at your option)
9;; any later version.
10;;
11;; GCC is distributed in the hope that it will be useful,
12;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14;; GNU General Public License for more details.
15;;
16;; You should have received a copy of the GNU General Public License
17;; along with GCC; see the file COPYING3.  If not see
18;; <http://www.gnu.org/licenses/>.
19
20;; Register constraints
21
22(define_register_constraint "a" "ADDL_REGS"
23  "addl register")
24
25(define_register_constraint "b" "BR_REGS"
26  "branch register")
27
28(define_register_constraint "c" "PR_REGS"
29  "predicate register")
30
31(define_register_constraint "d" "AR_M_REGS"
32  "memory pipeline application register")
33
34(define_register_constraint "e" "AR_I_REGS"
35  "integer pipeline application register")
36
37(define_register_constraint "f" "FR_REGS"
38  "floating-point register")
39
40(define_register_constraint "x" "FP_REGS"
41  "floating-point register, excluding f31 and f127, used for fldp")
42
43;; Integer constraints
44
45(define_constraint "I"
46  "14 bit signed immediate for arithmetic instructions"
47  (and (match_code "const_int")
48       (match_test "(unsigned HOST_WIDE_INT)ival + 0x2000 < 0x4000")))
49
50(define_constraint "J"
51  "22 bit signed immediate for arith instructions with r0/r1/r2/r3 source"
52  (and (match_code "const_int")
53       (match_test "(unsigned HOST_WIDE_INT)ival + 0x200000 < 0x400000")))
54
55(define_constraint "j"
56  "(2**32-2**13)..(2**32-1) for addp4 instructions"
57  (and (match_code "const_int")
58       (match_test "(unsigned HOST_WIDE_INT)ival >= 0xffffe000
59		    && (unsigned HOST_WIDE_INT)ival <= 0xffffffff")))
60
61(define_constraint "K"
62  "8 bit signed immediate for logical instructions"
63  (and (match_code "const_int")
64       (match_test "(unsigned HOST_WIDE_INT)ival + 0x80 < 0x100")))
65
66(define_constraint "L"
67  "8 bit adjusted signed immediate for compare pseudo-ops"
68  (and (match_code "const_int")
69       (match_test "(unsigned HOST_WIDE_INT)ival + 0x7F < 0x100")))
70
71(define_constraint "M"
72  "6 bit unsigned immediate for shift counts"
73  (and (match_code "const_int")
74       (match_test "(unsigned HOST_WIDE_INT)ival < 0x40")))
75
76(define_constraint "N"
77  "9 bit signed immediate for load/store post-increments"
78  (and (match_code "const_int")
79       (match_test "(unsigned HOST_WIDE_INT)ival + 0x100 < 0x200")))
80
81(define_constraint "O"
82  "constant zero"
83  (and (match_code "const_int")
84       (match_test "ival == 0")))
85
86(define_constraint "P"
87  "0 or -1 for dep instruction"
88  (and (match_code "const_int")
89       (match_test "ival == 0 || ival == -1")))
90
91;; Floating-point constraints
92
93(define_constraint "G"
94  "0.0 and 1.0 for fr0 and fr1"
95  (and (match_code "const_double")
96       (match_test "op == CONST0_RTX (mode) || op == CONST1_RTX (mode)")))
97
98(define_constraint "Z"
99  "1.0 or (0.0 and !flag_signed_zeros)"
100  (and (match_code "const_double")
101       (ior (match_test "op == CONST1_RTX (mode)")
102	    (and (match_test "op == CONST0_RTX (mode)")
103		 (match_test "!flag_signed_zeros")))))
104
105(define_constraint "H"
106  "0.0"
107  (and (match_code "const_double")
108       (match_test "op == CONST0_RTX (mode)")))
109
110;; Extra constraints
111
112;; Note that while this accepts mem, it only accepts non-volatile mem,
113;; and so cannot be "fixed" by adjusting the address.  Thus it cannot
114;; and does not use define_memory_constraint.
115(define_constraint "Q"
116  "Non-volatile memory for FP_REG loads/stores"
117  (and (match_operand 0 "memory_operand")
118       (match_test "!MEM_VOLATILE_P (op)")))
119
120(define_constraint "R"
121  "1..4 for shladd arguments"
122  (and (match_code "const_int")
123       (match_test "ival >= 1 && ival <= 4")))
124
125(define_constraint "T"
126  "Symbol ref to small-address-area"
127  (match_operand 0 "small_addr_symbolic_operand"))
128
129(define_constraint "U"
130  "vector zero constant"
131  (and (match_code "const_vector")
132       (match_test "op == CONST0_RTX (mode)")))
133
134(define_constraint "W"
135  "An integer vector, such that conversion to an integer yields a
136   value appropriate for an integer 'J' constraint."
137  (and (match_code "const_vector")
138       (match_test "GET_MODE_CLASS (mode) == MODE_VECTOR_INT")
139       (match_test
140	"satisfies_constraint_J (simplify_subreg (DImode, op, mode, 0))")))
141
142(define_constraint "Y"
143  "A V2SF vector containing elements that satisfy 'G'"
144  (and (match_code "const_vector")
145       (match_test "mode == V2SFmode")
146       (match_test "satisfies_constraint_G (XVECEXP (op, 0, 0))")
147       (match_test "satisfies_constraint_G (XVECEXP (op, 0, 1))")))
148
149;; Memory constraints
150
151(define_memory_constraint "S"
152  "Non-post-inc memory for asms and other unsavory creatures"
153  (and (match_code "mem")
154       (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != RTX_AUTOINC")))
155