1;;- Machine description for GNU compiler -- S/390 / zSeries version. 2;; Copyright (C) 1999-2018 Free Software Foundation, Inc. 3;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and 4;; Ulrich Weigand (uweigand@de.ibm.com) and 5;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) 6 7;; This file is part of GCC. 8 9;; GCC is free software; you can redistribute it and/or modify it under 10;; the terms of the GNU General Public License as published by the Free 11;; Software Foundation; either version 3, or (at your option) any later 12;; version. 13 14;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY 15;; WARRANTY; without even the implied warranty of MERCHANTABILITY or 16;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17;; for more details. 18 19;; You should have received a copy of the GNU General Public License 20;; along with GCC; see the file COPYING3. If not see 21;; <http://www.gnu.org/licenses/>. 22 23;; 24;; See constraints.md for a description of constraints specific to s390. 25;; 26 27;; Special formats used for outputting 390 instructions. 28;; 29;; %C: print opcode suffix for branch condition. 30;; %D: print opcode suffix for inverse branch condition. 31;; %J: print tls_load/tls_gdcall/tls_ldcall suffix 32;; %G: print the size of the operand in bytes. 33;; %O: print only the displacement of a memory reference. 34;; %R: print only the base register of a memory reference. 35;; %S: print S-type memory reference (base+displacement). 36;; %N: print the second word of a DImode operand. 37;; %M: print the second word of a TImode operand. 38;; %Y: print shift count operand. 39;; 40;; %b: print integer X as if it's an unsigned byte. 41;; %c: print integer X as if it's an signed byte. 42;; %x: print integer X as if it's an unsigned halfword. 43;; %h: print integer X as if it's a signed halfword. 44;; %i: print the first nonzero HImode part of X. 45;; %j: print the first HImode part unequal to -1 of X. 46;; %k: print the first nonzero SImode part of X. 47;; %m: print the first SImode part unequal to -1 of X. 48;; %o: print integer X as if it's an unsigned 32bit word. 49;; 50;; We have a special constraint for pattern matching. 51;; 52;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. 53;; 54 55;; 56;; UNSPEC usage 57;; 58 59(define_c_enum "unspec" [ 60 ; Miscellaneous 61 UNSPEC_ROUND 62 UNSPEC_ICM 63 UNSPEC_TIE 64 65 ; Convert CC into a str comparison result and copy it into an 66 ; integer register 67 ; cc0->0, cc1->1, cc2->-1, (cc3->-1) 68 UNSPEC_STRCMPCC_TO_INT 69 70 ; Copy CC as is into the lower 2 bits of an integer register 71 UNSPEC_CC_TO_INT 72 73 ; The right hand side of an setmem 74 UNSPEC_REPLICATE_BYTE 75 76 ; GOT/PLT and lt-relative accesses 77 UNSPEC_LTREL_OFFSET 78 UNSPEC_LTREL_BASE 79 UNSPEC_POOL_OFFSET 80 UNSPEC_GOTENT 81 UNSPEC_GOT 82 UNSPEC_GOTOFF 83 UNSPEC_PLT 84 UNSPEC_PLTOFF 85 86 ; Literal pool 87 UNSPEC_RELOAD_BASE 88 UNSPEC_MAIN_BASE 89 UNSPEC_LTREF 90 UNSPEC_INSN 91 UNSPEC_EXECUTE 92 UNSPEC_EXECUTE_JUMP 93 94 ; Atomic Support 95 UNSPEC_MB 96 UNSPEC_MOVA 97 98 ; TLS relocation specifiers 99 UNSPEC_TLSGD 100 UNSPEC_TLSLDM 101 UNSPEC_NTPOFF 102 UNSPEC_DTPOFF 103 UNSPEC_GOTNTPOFF 104 UNSPEC_INDNTPOFF 105 106 ; TLS support 107 UNSPEC_TLSLDM_NTPOFF 108 UNSPEC_TLS_LOAD 109 110 ; String Functions 111 UNSPEC_SRST 112 UNSPEC_MVST 113 114 ; Stack Smashing Protector 115 UNSPEC_SP_SET 116 UNSPEC_SP_TEST 117 118 ; Split stack support 119 UNSPEC_STACK_CHECK 120 121 ; Test Data Class (TDC) 122 UNSPEC_TDC_INSN 123 124 ; Population Count 125 UNSPEC_POPCNT 126 UNSPEC_COPYSIGN 127 128 ; Load FP Integer 129 UNSPEC_FPINT_FLOOR 130 UNSPEC_FPINT_BTRUNC 131 UNSPEC_FPINT_ROUND 132 UNSPEC_FPINT_CEIL 133 UNSPEC_FPINT_NEARBYINT 134 UNSPEC_FPINT_RINT 135 136 UNSPEC_LCBB 137 138 ; Vector 139 UNSPEC_VEC_SMULT_HI 140 UNSPEC_VEC_UMULT_HI 141 UNSPEC_VEC_SMULT_LO 142 UNSPEC_VEC_SMULT_EVEN 143 UNSPEC_VEC_UMULT_EVEN 144 UNSPEC_VEC_SMULT_ODD 145 UNSPEC_VEC_UMULT_ODD 146 147 UNSPEC_VEC_VMAL 148 UNSPEC_VEC_VMAH 149 UNSPEC_VEC_VMALH 150 UNSPEC_VEC_VMAE 151 UNSPEC_VEC_VMALE 152 UNSPEC_VEC_VMAO 153 UNSPEC_VEC_VMALO 154 155 UNSPEC_VEC_GATHER 156 UNSPEC_VEC_EXTRACT 157 UNSPEC_VEC_INSERT_AND_ZERO 158 UNSPEC_VEC_LOAD_BNDRY 159 UNSPEC_VEC_LOAD_LEN 160 UNSPEC_VEC_LOAD_LEN_R 161 UNSPEC_VEC_MERGEH 162 UNSPEC_VEC_MERGEL 163 UNSPEC_VEC_PACK 164 UNSPEC_VEC_PACK_SATURATE 165 UNSPEC_VEC_PACK_SATURATE_CC 166 UNSPEC_VEC_PACK_SATURATE_GENCC 167 UNSPEC_VEC_PACK_UNSIGNED_SATURATE 168 UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC 169 UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC 170 UNSPEC_VEC_PERM 171 UNSPEC_VEC_PERMI 172 UNSPEC_VEC_EXTEND 173 UNSPEC_VEC_STORE_LEN 174 UNSPEC_VEC_STORE_LEN_R 175 UNSPEC_VEC_VBPERM 176 UNSPEC_VEC_UNPACKH 177 UNSPEC_VEC_UNPACKH_L 178 UNSPEC_VEC_UNPACKL 179 UNSPEC_VEC_UNPACKL_L 180 UNSPEC_VEC_ADDC 181 UNSPEC_VEC_ADDE_U128 182 UNSPEC_VEC_ADDEC_U128 183 UNSPEC_VEC_AVG 184 UNSPEC_VEC_AVGU 185 UNSPEC_VEC_CHECKSUM 186 UNSPEC_VEC_GFMSUM 187 UNSPEC_VEC_GFMSUM_128 188 UNSPEC_VEC_GFMSUM_ACCUM 189 UNSPEC_VEC_GFMSUM_ACCUM_128 190 UNSPEC_VEC_SET 191 192 UNSPEC_VEC_VSUMG 193 UNSPEC_VEC_VSUMQ 194 UNSPEC_VEC_VSUM 195 UNSPEC_VEC_RL_MASK 196 UNSPEC_VEC_SLL 197 UNSPEC_VEC_SLB 198 UNSPEC_VEC_SLDB 199 UNSPEC_VEC_SRAL 200 UNSPEC_VEC_SRAB 201 UNSPEC_VEC_SRL 202 UNSPEC_VEC_SRLB 203 204 UNSPEC_VEC_SUBC 205 UNSPEC_VEC_SUBE_U128 206 UNSPEC_VEC_SUBEC_U128 207 208 UNSPEC_VEC_TEST_MASK 209 210 UNSPEC_VEC_VFAE 211 UNSPEC_VEC_VFAECC 212 213 UNSPEC_VEC_VFEE 214 UNSPEC_VEC_VFEECC 215 UNSPEC_VEC_VFENE 216 UNSPEC_VEC_VFENECC 217 218 UNSPEC_VEC_VISTR 219 UNSPEC_VEC_VISTRCC 220 221 UNSPEC_VEC_VSTRC 222 UNSPEC_VEC_VSTRCCC 223 224 UNSPEC_VEC_VCDGB 225 UNSPEC_VEC_VCDLGB 226 227 UNSPEC_VEC_VCGDB 228 UNSPEC_VEC_VCLGDB 229 230 UNSPEC_VEC_VFI 231 232 UNSPEC_VEC_VFLL ; vector fp load lengthened 233 UNSPEC_VEC_VFLR ; vector fp load rounded 234 235 UNSPEC_VEC_VFTCI 236 UNSPEC_VEC_VFTCICC 237 238 UNSPEC_VEC_MSUM 239 240 UNSPEC_VEC_VFMIN 241 UNSPEC_VEC_VFMAX 242]) 243 244;; 245;; UNSPEC_VOLATILE usage 246;; 247 248(define_c_enum "unspecv" [ 249 ; Blockage 250 UNSPECV_BLOCKAGE 251 252 ; TPF Support 253 UNSPECV_TPF_PROLOGUE 254 UNSPECV_TPF_EPILOGUE 255 256 ; Literal pool 257 UNSPECV_POOL 258 UNSPECV_POOL_SECTION 259 UNSPECV_POOL_ALIGN 260 UNSPECV_POOL_ENTRY 261 UNSPECV_MAIN_POOL 262 263 ; TLS support 264 UNSPECV_SET_TP 265 266 ; Atomic Support 267 UNSPECV_CAS 268 UNSPECV_ATOMIC_OP 269 270 ; Non-branch nops used for compare-and-branch adjustments on z10 271 UNSPECV_NOP_LR_0 272 UNSPECV_NOP_LR_1 273 274 ; Hotpatching (unremovable NOPs) 275 UNSPECV_NOP_2_BYTE 276 UNSPECV_NOP_4_BYTE 277 UNSPECV_NOP_6_BYTE 278 279 ; Transactional Execution support 280 UNSPECV_TBEGIN 281 UNSPECV_TBEGIN_TDB 282 UNSPECV_TBEGINC 283 UNSPECV_TEND 284 UNSPECV_TABORT 285 UNSPECV_ETND 286 UNSPECV_NTSTG 287 UNSPECV_PPA 288 289 ; Set and get floating point control register 290 UNSPECV_SFPC 291 UNSPECV_EFPC 292 293 ; Split stack support 294 UNSPECV_SPLIT_STACK_CALL 295 UNSPECV_SPLIT_STACK_DATA 296 297 UNSPECV_OSC_BREAK 298 ]) 299 300;; 301;; Registers 302;; 303 304; Registers with special meaning 305 306(define_constants 307 [ 308 ; Sibling call register. 309 (SIBCALL_REGNUM 1) 310 ; A call-clobbered reg which can be used in indirect branch thunks 311 (INDIRECT_BRANCH_THUNK_REGNUM 1) 312 ; Literal pool base register. 313 (BASE_REGNUM 13) 314 ; Return address register. 315 (RETURN_REGNUM 14) 316 ; Stack pointer register. 317 (STACK_REGNUM 15) 318 ; Condition code register. 319 (CC_REGNUM 33) 320 ; Thread local storage pointer register. 321 (TP_REGNUM 36) 322 ]) 323 324; Hardware register names 325 326(define_constants 327 [ 328 ; General purpose registers 329 (GPR0_REGNUM 0) 330 (GPR1_REGNUM 1) 331 (GPR2_REGNUM 2) 332 (GPR6_REGNUM 6) 333 ; Floating point registers. 334 (FPR0_REGNUM 16) 335 (FPR1_REGNUM 20) 336 (FPR2_REGNUM 17) 337 (FPR3_REGNUM 21) 338 (FPR4_REGNUM 18) 339 (FPR5_REGNUM 22) 340 (FPR6_REGNUM 19) 341 (FPR7_REGNUM 23) 342 (FPR8_REGNUM 24) 343 (FPR9_REGNUM 28) 344 (FPR10_REGNUM 25) 345 (FPR11_REGNUM 29) 346 (FPR12_REGNUM 26) 347 (FPR13_REGNUM 30) 348 (FPR14_REGNUM 27) 349 (FPR15_REGNUM 31) 350 (VR0_REGNUM 16) 351 (VR16_REGNUM 38) 352 (VR23_REGNUM 45) 353 (VR24_REGNUM 46) 354 (VR31_REGNUM 53) 355 ]) 356 357; Rounding modes for binary floating point numbers 358(define_constants 359 [(BFP_RND_CURRENT 0) 360 (BFP_RND_NEAREST_TIE_AWAY_FROM_0 1) 361 (BFP_RND_PREP_FOR_SHORT_PREC 3) 362 (BFP_RND_NEAREST_TIE_TO_EVEN 4) 363 (BFP_RND_TOWARD_0 5) 364 (BFP_RND_TOWARD_INF 6) 365 (BFP_RND_TOWARD_MINF 7)]) 366 367; Rounding modes for decimal floating point numbers 368; 1-7 were introduced with the floating point extension facility 369; available with z196 370; With these rounding modes (1-7) a quantum exception might occur 371; which is suppressed for the other modes. 372(define_constants 373 [(DFP_RND_CURRENT 0) 374 (DFP_RND_NEAREST_TIE_AWAY_FROM_0_QUANTEXC 1) 375 (DFP_RND_CURRENT_QUANTEXC 2) 376 (DFP_RND_PREP_FOR_SHORT_PREC_QUANTEXC 3) 377 (DFP_RND_NEAREST_TIE_TO_EVEN_QUANTEXC 4) 378 (DFP_RND_TOWARD_0_QUANTEXC 5) 379 (DFP_RND_TOWARD_INF_QUANTEXC 6) 380 (DFP_RND_TOWARD_MINF_QUANTEXC 7) 381 (DFP_RND_NEAREST_TIE_TO_EVEN 8) 382 (DFP_RND_TOWARD_0 9) 383 (DFP_RND_TOWARD_INF 10) 384 (DFP_RND_TOWARD_MINF 11) 385 (DFP_RND_NEAREST_TIE_AWAY_FROM_0 12) 386 (DFP_RND_NEAREST_TIE_TO_0 13) 387 (DFP_RND_AWAY_FROM_0 14) 388 (DFP_RND_PREP_FOR_SHORT_PREC 15)]) 389 390;; 391;; PFPO GPR0 argument format 392;; 393 394(define_constants 395 [ 396 ; PFPO operation type 397 (PFPO_CONVERT 0x1000000) 398 ; PFPO operand types 399 (PFPO_OP_TYPE_SF 0x5) 400 (PFPO_OP_TYPE_DF 0x6) 401 (PFPO_OP_TYPE_TF 0x7) 402 (PFPO_OP_TYPE_SD 0x8) 403 (PFPO_OP_TYPE_DD 0x9) 404 (PFPO_OP_TYPE_TD 0xa) 405 ; Bitposition of operand types 406 (PFPO_OP0_TYPE_SHIFT 16) 407 (PFPO_OP1_TYPE_SHIFT 8) 408 ; Decide whether current DFP or BFD rounding mode should be used 409 ; for the conversion. 410 (PFPO_RND_MODE_DFP 0) 411 (PFPO_RND_MODE_BFP 1) 412 ]) 413 414; Immediate operands for tbegin and tbeginc 415(define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c 416(define_constants [(TBEGINC_MASK 65288)]) ; 0xff08 417 418;; Instruction operand type as used in the Principles of Operation. 419;; Used to determine defaults for length and other attribute values. 420 421(define_attr "op_type" 422 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX,VSI" 423 (const_string "NN")) 424 425;; Instruction type attribute used for scheduling. 426 427(define_attr "type" "none,integer,load,lr,la,larl,lm,stm, 428 cs,vs,store,sem,idiv, 429 imulhi,imulsi,imuldi, 430 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex, 431 floadtf,floaddf,floadsf,fstoredf,fstoresf, 432 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, 433 ftoi,fsqrttf,fsqrtdf,fsqrtsf, 434 fmadddf,fmaddsf, 435 ftrunctf,ftruncdf, ftruncsd, ftruncdd, 436 itoftf, itofdf, itofsf, itofdd, itoftd, 437 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, 438 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd, 439 ftoidfp, other" 440 (cond [(eq_attr "op_type" "NN") (const_string "other") 441 (eq_attr "op_type" "SS") (const_string "cs")] 442 (const_string "integer"))) 443 444;; Another attribute used for scheduling purposes: 445;; agen: Instruction uses the address generation unit 446;; reg: Instruction does not use the agen unit 447 448(define_attr "atype" "agen,reg" 449 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF") 450 (const_string "reg") 451 (const_string "agen"))) 452 453;; Properties concerning Z10 execution grouping and value forwarding. 454;; z10_super: instruction is superscalar. 455;; z10_super_c: instruction is superscalar and meets the condition of z10_c. 456;; z10_fwd: The instruction reads the value of an operand and stores it into a 457;; target register. It can forward this value to a second instruction that reads 458;; the same register if that second instruction is issued in the same group. 459;; z10_rec: The instruction is in the T pipeline and reads a register. If the 460;; instruction in the S pipe writes to the register, then the T instruction 461;; can immediately read the new value. 462;; z10_fr: union of Z10_fwd and z10_rec. 463;; z10_c: second operand of instruction is a register and read with complemented bits. 464;; 465;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass. 466 467 468(define_attr "z10prop" "none, 469 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1, 470 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1, 471 z10_rec, 472 z10_fr, z10_fr_A3, z10_fr_E1, 473 z10_c" 474 (const_string "none")) 475 476;; Properties concerning Z196 decoding 477;; z196_alone: must group alone 478;; z196_end: ends a group 479;; z196_cracked: instruction is cracked or expanded 480(define_attr "z196prop" "none, 481 z196_alone, z196_ends, 482 z196_cracked" 483 (const_string "none")) 484 485; mnemonics which only get defined through if_then_else currently 486; don't get added to the list values automatically and hence need to 487; be listed here. 488(define_attr "mnemonic" "b,bas,bc,bcr_flush,unknown" (const_string "unknown")) 489 490;; Length in bytes. 491 492(define_attr "length" "" 493 (cond [(eq_attr "op_type" "E,RR") (const_int 2) 494 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF") (const_int 4)] 495 (const_int 6))) 496 497 498;; Processor type. This attribute must exactly match the processor_type 499;; enumeration in s390.h. The current machine description does not 500;; distinguish between g5 and g6, but there are differences between the two 501;; CPUs could in theory be modeled. 502 503(define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13,arch12" 504 (const (symbol_ref "s390_tune_attr"))) 505 506(define_attr "cpu_facility" 507 "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vx,z13,arch12,vxe" 508 (const_string "standard")) 509 510(define_attr "enabled" "" 511 (cond [(eq_attr "cpu_facility" "standard") 512 (const_int 1) 513 514 (and (eq_attr "cpu_facility" "ieee") 515 (match_test "TARGET_CPU_IEEE_FLOAT")) 516 (const_int 1) 517 518 (and (eq_attr "cpu_facility" "zarch") 519 (match_test "TARGET_ZARCH")) 520 (const_int 1) 521 522 (and (eq_attr "cpu_facility" "longdisp") 523 (match_test "TARGET_LONG_DISPLACEMENT")) 524 (const_int 1) 525 526 (and (eq_attr "cpu_facility" "extimm") 527 (match_test "TARGET_EXTIMM")) 528 (const_int 1) 529 530 (and (eq_attr "cpu_facility" "dfp") 531 (match_test "TARGET_DFP")) 532 (const_int 1) 533 534 (and (eq_attr "cpu_facility" "cpu_zarch") 535 (match_test "TARGET_CPU_ZARCH")) 536 (const_int 1) 537 538 (and (eq_attr "cpu_facility" "z10") 539 (match_test "TARGET_Z10")) 540 (const_int 1) 541 542 (and (eq_attr "cpu_facility" "z196") 543 (match_test "TARGET_Z196")) 544 (const_int 1) 545 546 (and (eq_attr "cpu_facility" "zEC12") 547 (match_test "TARGET_ZEC12")) 548 (const_int 1) 549 550 (and (eq_attr "cpu_facility" "vx") 551 (match_test "TARGET_VX")) 552 (const_int 1) 553 554 (and (eq_attr "cpu_facility" "z13") 555 (match_test "TARGET_Z13")) 556 (const_int 1) 557 558 (and (eq_attr "cpu_facility" "arch12") 559 (match_test "TARGET_ARCH12")) 560 (const_int 1) 561 562 (and (eq_attr "cpu_facility" "vxe") 563 (match_test "TARGET_VXE")) 564 (const_int 1) 565 ] 566 (const_int 0))) 567 568;; Pipeline description for z900. For lack of anything better, 569;; this description is also used for the g5 and g6. 570(include "2064.md") 571 572;; Pipeline description for z990, z9-109 and z9-ec. 573(include "2084.md") 574 575;; Pipeline description for z10 576(include "2097.md") 577 578;; Pipeline description for z196 579(include "2817.md") 580 581;; Pipeline description for zEC12 582(include "2827.md") 583 584;; Pipeline description for z13 585(include "2964.md") 586 587;; Predicates 588(include "predicates.md") 589 590;; Constraint definitions 591(include "constraints.md") 592 593;; Other includes 594(include "tpf.md") 595 596;; Iterators 597 598(define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF]) 599 600;; These mode iterators allow floating point patterns to be generated from the 601;; same template. 602(define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP") 603 (SD "TARGET_HARD_DFP")]) 604(define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")]) 605(define_mode_iterator BFP [TF DF SF]) 606(define_mode_iterator DFP [TD DD]) 607(define_mode_iterator DFP_ALL [TD DD SD]) 608(define_mode_iterator DSF [DF SF]) 609(define_mode_iterator SD_SF [SF SD]) 610(define_mode_iterator DD_DF [DF DD]) 611(define_mode_iterator TD_TF [TF TD]) 612 613;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated 614;; from the same template. 615(define_mode_iterator GPR [(DI "TARGET_ZARCH") SI]) 616(define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI]) 617(define_mode_iterator DSI [DI SI]) 618(define_mode_iterator TDI [TI DI]) 619 620;; These mode iterators allow :P to be used for patterns that operate on 621;; pointer-sized quantities. Exactly one of the two alternatives will match. 622(define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) 623 624;; These macros refer to the actual word_mode of the configuration. 625;; This is equal to Pmode except on 31-bit machines in zarch mode. 626(define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")]) 627(define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")]) 628 629;; Used by the umul pattern to express modes having half the size. 630(define_mode_attr DWH [(TI "DI") (DI "SI")]) 631(define_mode_attr dwh [(TI "di") (DI "si")]) 632 633;; This mode iterator allows the QI and HI patterns to be defined from 634;; the same template. 635(define_mode_iterator HQI [HI QI]) 636 637;; This mode iterator allows the integer patterns to be defined from the 638;; same template. 639(define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI]) 640(define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI]) 641(define_mode_iterator SINT [SI HI QI]) 642 643;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from 644;; the same template. 645(define_code_iterator SHIFT [ashift lshiftrt]) 646 647;; This iterator allows r[ox]sbg to be defined with the same template 648(define_code_iterator IXOR [ior xor]) 649 650;; This iterator is used to expand the patterns for the nearest 651;; integer functions. 652(define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC 653 UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL 654 UNSPEC_FPINT_NEARBYINT]) 655(define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor") 656 (UNSPEC_FPINT_BTRUNC "btrunc") 657 (UNSPEC_FPINT_ROUND "round") 658 (UNSPEC_FPINT_CEIL "ceil") 659 (UNSPEC_FPINT_NEARBYINT "nearbyint")]) 660(define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7") 661 (UNSPEC_FPINT_BTRUNC "5") 662 (UNSPEC_FPINT_ROUND "1") 663 (UNSPEC_FPINT_CEIL "6") 664 (UNSPEC_FPINT_NEARBYINT "0")]) 665 666;; This iterator and attribute allow to combine most atomic operations. 667(define_code_iterator ATOMIC [and ior xor plus minus mult]) 668(define_code_iterator ATOMIC_Z196 [and ior xor plus]) 669(define_code_attr atomic [(and "and") (ior "or") (xor "xor") 670 (plus "add") (minus "sub") (mult "nand")]) 671(define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")]) 672 673;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in 674;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode. 675(define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")]) 676 677;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in 678;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in 679;; SDmode. 680(define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")]) 681 682;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise. 683;; Likewise for "<RXe>". 684(define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")]) 685(define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")]) 686 687;; The decimal floating point variants of add, sub, div and mul support 3 688;; fp register operands. The following attributes allow to merge the bfp and 689;; dfp variants in a single insn definition. 690 691;; These mode attributes are supposed to be used in the `enabled' insn 692;; attribute to disable certain alternatives for certain modes. 693(define_mode_attr nBFP [(TF "0") (DF "0") (SF "0") (TD "*") (DD "*") (DD "*")]) 694(define_mode_attr nDFP [(TF "*") (DF "*") (SF "*") (TD "0") (DD "0") (DD "0")]) 695(define_mode_attr DSF [(TF "0") (DF "*") (SF "*") (TD "0") (DD "0") (SD "0")]) 696(define_mode_attr DFDI [(TF "0") (DF "*") (SF "0") 697 (TD "0") (DD "0") (DD "0") 698 (TI "0") (DI "*") (SI "0")]) 699(define_mode_attr DF [(TF "0") (DF "*") (SF "0") 700 (TD "0") (DD "0") (DD "0") 701 (TI "0") (DI "0") (SI "0")]) 702(define_mode_attr SF [(TF "0") (DF "0") (SF "*") 703 (TD "0") (DD "0") (DD "0") 704 (TI "0") (DI "0") (SI "0")]) 705 706;; This attribute is used in the operand constraint list 707;; for instructions dealing with the sign bit of 32 or 64bit fp values. 708;; TFmode values are represented by a fp register pair. Since the 709;; sign bit instructions only handle single source and target fp registers 710;; these instructions can only be used for TFmode values if the source and 711;; target operand uses the same fp register. 712(define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")]) 713 714;; This attribute adds b for bfp instructions and t for dfp instructions and is used 715;; within instruction mnemonics. 716(define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")]) 717 718;; This attribute is used within instruction mnemonics. It evaluates to d for dfp 719;; modes and to an empty string for bfp modes. 720(define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")]) 721 722;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode 723;; and "0" in SImode. This allows to combine instructions of which the 31bit 724;; version only operates on one register. 725(define_mode_attr d0 [(DI "d") (SI "0")]) 726 727;; In combination with d0 this allows to combine instructions of which the 31bit 728;; version only operates on one register. The DImode version needs an additional 729;; register for the assembler output. 730(define_mode_attr 1 [(DI "%1,") (SI "")]) 731 732;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in 733;; 'ashift' and "srdl" in 'lshiftrt'. 734(define_code_attr lr [(ashift "l") (lshiftrt "r")]) 735 736;; In SHIFT templates, this attribute holds the correct standard name for the 737;; pattern itself and the corresponding function calls. 738(define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) 739 740;; This attribute handles differences in the instruction 'type' and will result 741;; in "RRE" for DImode and "RR" for SImode. 742(define_mode_attr E [(DI "E") (SI "")]) 743 744;; This attribute handles differences in the instruction 'type' and makes RX<Y> 745;; to result in "RXY" for DImode and "RX" for SImode. 746(define_mode_attr Y [(DI "Y") (SI "")]) 747 748;; This attribute handles differences in the instruction 'type' and will result 749;; in "RSE" for TImode and "RS" for DImode. 750(define_mode_attr TE [(TI "E") (DI "")]) 751 752;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode 753;; and "lcr" in SImode. 754(define_mode_attr g [(DI "g") (SI "")]) 755 756;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode 757;; and "sly" in SImode. This is useful because on 64bit the ..g instructions 758;; were enhanced with long displacements whereas 31bit instructions got a ..y 759;; variant for long displacements. 760(define_mode_attr y [(DI "g") (SI "y")]) 761 762;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode 763;; and "cds" in DImode. 764(define_mode_attr tg [(TI "g") (DI "")]) 765 766;; In TDI templates, a string like "c<d>sg". 767(define_mode_attr td [(TI "d") (DI "")]) 768 769;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode 770;; and "cfdbr" in SImode. 771(define_mode_attr gf [(DI "g") (SI "f")]) 772 773;; In GPR templates, a string like sll<gk> will expand to sllg for DI 774;; and sllk for SI. This way it is possible to merge the new z196 SI 775;; 3 operands shift instructions into the existing patterns. 776(define_mode_attr gk [(DI "g") (SI "k")]) 777 778;; ICM mask required to load MODE value into the lowest subreg 779;; of a SImode register. 780(define_mode_attr icm_lo [(HI "3") (QI "1")]) 781 782;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in 783;; HImode and "llgc" in QImode. 784(define_mode_attr hc [(HI "h") (QI "c")]) 785 786;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI" 787;; in SImode. 788(define_mode_attr DBL [(DI "TI") (SI "DI")]) 789 790;; This attribute expands to DF for TFmode and to DD for TDmode . It is 791;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies. 792(define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")]) 793 794;; Maximum unsigned integer that fits in MODE. 795(define_mode_attr max_uint [(HI "65535") (QI "255")]) 796 797;; Start and end field computations for RISBG et al. 798(define_mode_attr bfstart [(DI "s") (SI "t")]) 799(define_mode_attr bfend [(DI "e") (SI "f")]) 800 801;; In place of GET_MODE_BITSIZE (<MODE>mode) 802(define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")]) 803;; 64 - bitsize 804(define_mode_attr bitoff [(DI "0") (SI "32") (HI "48") (QI "56")]) 805(define_mode_attr bitoff_plus [(DI "") (SI "32+") (HI "48+") (QI "56+")]) 806 807;; In place of GET_MODE_SIZE (<MODE>mode) 808(define_mode_attr modesize [(DI "8") (SI "4")]) 809 810;; Allow return and simple_return to be defined from a single template. 811(define_code_iterator ANY_RETURN [return simple_return]) 812 813 814 815; Condition code modes generated by vector fp comparisons. These will 816; be used also in single element mode. 817(define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE]) 818; Used with VFCMP to expand part of the mnemonic 819; For fp we have a mismatch: eq in the insn name - e in asm 820(define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")]) 821(define_mode_attr insn_cmp [(CCVEQ "eq") (CCVIH "h") (CCVIHU "hl") (CCVFH "h") (CCVFHE "he")]) 822 823;; Subst pattern definitions 824(include "subst.md") 825 826(include "vector.md") 827 828;; 829;;- Compare instructions. 830;; 831 832; Test-under-Mask instructions 833 834(define_insn "*tmqi_mem" 835 [(set (reg CC_REGNUM) 836 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") 837 (match_operand:QI 1 "immediate_operand" "n,n")) 838 (match_operand:QI 2 "immediate_operand" "n,n")))] 839 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" 840 "@ 841 tm\t%S0,%b1 842 tmy\t%S0,%b1" 843 [(set_attr "op_type" "SI,SIY") 844 (set_attr "cpu_facility" "*,longdisp") 845 (set_attr "z10prop" "z10_super,z10_super")]) 846 847(define_insn "*tmdi_reg" 848 [(set (reg CC_REGNUM) 849 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") 850 (match_operand:DI 1 "immediate_operand" 851 "N0HD0,N1HD0,N2HD0,N3HD0")) 852 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] 853 "TARGET_ZARCH 854 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) 855 && s390_single_part (operands[1], DImode, HImode, 0) >= 0" 856 "@ 857 tmhh\t%0,%i1 858 tmhl\t%0,%i1 859 tmlh\t%0,%i1 860 tmll\t%0,%i1" 861 [(set_attr "op_type" "RI") 862 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")]) 863 864(define_insn "*tmsi_reg" 865 [(set (reg CC_REGNUM) 866 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") 867 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) 868 (match_operand:SI 2 "immediate_operand" "n,n")))] 869 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) 870 && s390_single_part (operands[1], SImode, HImode, 0) >= 0" 871 "@ 872 tmh\t%0,%i1 873 tml\t%0,%i1" 874 [(set_attr "op_type" "RI") 875 (set_attr "z10prop" "z10_super,z10_super")]) 876 877(define_insn "*tm<mode>_full" 878 [(set (reg CC_REGNUM) 879 (compare (match_operand:HQI 0 "register_operand" "d") 880 (match_operand:HQI 1 "immediate_operand" "n")))] 881 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" 882 "tml\t%0,<max_uint>" 883 [(set_attr "op_type" "RI") 884 (set_attr "z10prop" "z10_super")]) 885 886 887; 888; Load-and-Test instructions 889; 890 891; tst(di|si) instruction pattern(s). 892 893(define_insn "*tstdi_sign" 894 [(set (reg CC_REGNUM) 895 (compare 896 (ashiftrt:DI 897 (ashift:DI 898 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,T") 0) 899 (const_int 32)) (const_int 32)) 900 (match_operand:DI 1 "const0_operand" ""))) 901 (set (match_operand:DI 2 "register_operand" "=d,d") 902 (sign_extend:DI (match_dup 0)))] 903 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH" 904 "ltgfr\t%2,%0 905 ltgf\t%2,%0" 906 [(set_attr "op_type" "RRE,RXY") 907 (set_attr "cpu_facility" "*,z10") 908 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ]) 909 910; ltr, lt, ltgr, ltg 911(define_insn "*tst<mode>_extimm" 912 [(set (reg CC_REGNUM) 913 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T") 914 (match_operand:GPR 1 "const0_operand" ""))) 915 (set (match_operand:GPR 2 "register_operand" "=d,d") 916 (match_dup 0))] 917 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" 918 "@ 919 lt<g>r\t%2,%0 920 lt<g>\t%2,%0" 921 [(set_attr "op_type" "RR<E>,RXY") 922 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ]) 923 924; Peephole to combine a load-and-test from volatile memory which combine does 925; not do. 926(define_peephole2 927 [(set (match_operand:GPR 0 "register_operand") 928 (match_operand:GPR 2 "memory_operand")) 929 (set (reg CC_REGNUM) 930 (compare (match_dup 0) (match_operand:GPR 1 "const0_operand")))] 931 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM 932 && GENERAL_REG_P (operands[0]) 933 && satisfies_constraint_T (operands[2])" 934 [(parallel 935 [(set (reg:CCS CC_REGNUM) 936 (compare:CCS (match_dup 2) (match_dup 1))) 937 (set (match_dup 0) (match_dup 2))])]) 938 939; ltr, lt, ltgr, ltg 940(define_insn "*tst<mode>_cconly_extimm" 941 [(set (reg CC_REGNUM) 942 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T") 943 (match_operand:GPR 1 "const0_operand" ""))) 944 (clobber (match_scratch:GPR 2 "=X,d"))] 945 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" 946 "@ 947 lt<g>r\t%0,%0 948 lt<g>\t%2,%0" 949 [(set_attr "op_type" "RR<E>,RXY") 950 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")]) 951 952(define_insn "*tstdi" 953 [(set (reg CC_REGNUM) 954 (compare (match_operand:DI 0 "register_operand" "d") 955 (match_operand:DI 1 "const0_operand" ""))) 956 (set (match_operand:DI 2 "register_operand" "=d") 957 (match_dup 0))] 958 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM" 959 "ltgr\t%2,%0" 960 [(set_attr "op_type" "RRE") 961 (set_attr "z10prop" "z10_fr_E1")]) 962 963(define_insn "*tstsi" 964 [(set (reg CC_REGNUM) 965 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") 966 (match_operand:SI 1 "const0_operand" ""))) 967 (set (match_operand:SI 2 "register_operand" "=d,d,d") 968 (match_dup 0))] 969 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM" 970 "@ 971 ltr\t%2,%0 972 icm\t%2,15,%S0 973 icmy\t%2,15,%S0" 974 [(set_attr "op_type" "RR,RS,RSY") 975 (set_attr "cpu_facility" "*,*,longdisp") 976 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) 977 978(define_insn "*tstsi_cconly" 979 [(set (reg CC_REGNUM) 980 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") 981 (match_operand:SI 1 "const0_operand" ""))) 982 (clobber (match_scratch:SI 2 "=X,d,d"))] 983 "s390_match_ccmode(insn, CCSmode)" 984 "@ 985 ltr\t%0,%0 986 icm\t%2,15,%S0 987 icmy\t%2,15,%S0" 988 [(set_attr "op_type" "RR,RS,RSY") 989 (set_attr "cpu_facility" "*,*,longdisp") 990 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) 991 992(define_insn "*tstdi_cconly_31" 993 [(set (reg CC_REGNUM) 994 (compare (match_operand:DI 0 "register_operand" "d") 995 (match_operand:DI 1 "const0_operand" "")))] 996 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH" 997 "srda\t%0,0" 998 [(set_attr "op_type" "RS") 999 (set_attr "atype" "reg")]) 1000 1001; ltr, ltgr 1002(define_insn "*tst<mode>_cconly2" 1003 [(set (reg CC_REGNUM) 1004 (compare (match_operand:GPR 0 "register_operand" "d") 1005 (match_operand:GPR 1 "const0_operand" "")))] 1006 "s390_match_ccmode(insn, CCSmode)" 1007 "lt<g>r\t%0,%0" 1008 [(set_attr "op_type" "RR<E>") 1009 (set_attr "z10prop" "z10_fr_E1")]) 1010 1011; tst(hi|qi) instruction pattern(s). 1012 1013(define_insn "*tst<mode>CCT" 1014 [(set (reg CC_REGNUM) 1015 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") 1016 (match_operand:HQI 1 "const0_operand" ""))) 1017 (set (match_operand:HQI 2 "register_operand" "=d,d,0") 1018 (match_dup 0))] 1019 "s390_match_ccmode(insn, CCTmode)" 1020 "@ 1021 icm\t%2,<icm_lo>,%S0 1022 icmy\t%2,<icm_lo>,%S0 1023 tml\t%0,<max_uint>" 1024 [(set_attr "op_type" "RS,RSY,RI") 1025 (set_attr "cpu_facility" "*,longdisp,*") 1026 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) 1027 1028(define_insn "*tsthiCCT_cconly" 1029 [(set (reg CC_REGNUM) 1030 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") 1031 (match_operand:HI 1 "const0_operand" ""))) 1032 (clobber (match_scratch:HI 2 "=d,d,X"))] 1033 "s390_match_ccmode(insn, CCTmode)" 1034 "@ 1035 icm\t%2,3,%S0 1036 icmy\t%2,3,%S0 1037 tml\t%0,65535" 1038 [(set_attr "op_type" "RS,RSY,RI") 1039 (set_attr "cpu_facility" "*,longdisp,*") 1040 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) 1041 1042(define_insn "*tstqiCCT_cconly" 1043 [(set (reg CC_REGNUM) 1044 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") 1045 (match_operand:QI 1 "const0_operand" "")))] 1046 "s390_match_ccmode(insn, CCTmode)" 1047 "@ 1048 cli\t%S0,0 1049 cliy\t%S0,0 1050 tml\t%0,255" 1051 [(set_attr "op_type" "SI,SIY,RI") 1052 (set_attr "cpu_facility" "*,longdisp,*") 1053 (set_attr "z10prop" "z10_super,z10_super,z10_super")]) 1054 1055(define_insn "*tst<mode>" 1056 [(set (reg CC_REGNUM) 1057 (compare (match_operand:HQI 0 "s_operand" "Q,S") 1058 (match_operand:HQI 1 "const0_operand" ""))) 1059 (set (match_operand:HQI 2 "register_operand" "=d,d") 1060 (match_dup 0))] 1061 "s390_match_ccmode(insn, CCSmode)" 1062 "@ 1063 icm\t%2,<icm_lo>,%S0 1064 icmy\t%2,<icm_lo>,%S0" 1065 [(set_attr "op_type" "RS,RSY") 1066 (set_attr "cpu_facility" "*,longdisp") 1067 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 1068 1069(define_insn "*tst<mode>_cconly" 1070 [(set (reg CC_REGNUM) 1071 (compare (match_operand:HQI 0 "s_operand" "Q,S") 1072 (match_operand:HQI 1 "const0_operand" ""))) 1073 (clobber (match_scratch:HQI 2 "=d,d"))] 1074 "s390_match_ccmode(insn, CCSmode)" 1075 "@ 1076 icm\t%2,<icm_lo>,%S0 1077 icmy\t%2,<icm_lo>,%S0" 1078 [(set_attr "op_type" "RS,RSY") 1079 (set_attr "cpu_facility" "*,longdisp") 1080 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 1081 1082 1083; Compare (equality) instructions 1084 1085(define_insn "*cmpdi_cct" 1086 [(set (reg CC_REGNUM) 1087 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") 1088 (match_operand:DI 1 "general_operand" "d,K,Os,T,BQ")))] 1089 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH" 1090 "@ 1091 cgr\t%0,%1 1092 cghi\t%0,%h1 1093 cgfi\t%0,%1 1094 cg\t%0,%1 1095 #" 1096 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS") 1097 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")]) 1098 1099(define_insn "*cmpsi_cct" 1100 [(set (reg CC_REGNUM) 1101 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q") 1102 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))] 1103 "s390_match_ccmode (insn, CCTmode)" 1104 "@ 1105 cr\t%0,%1 1106 chi\t%0,%h1 1107 cfi\t%0,%1 1108 c\t%0,%1 1109 cy\t%0,%1 1110 #" 1111 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS") 1112 (set_attr "cpu_facility" "*,*,*,*,longdisp,*") 1113 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")]) 1114 1115; Compare (signed) instructions 1116 1117(define_insn "*cmpdi_ccs_sign" 1118 [(set (reg CC_REGNUM) 1119 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" 1120 "d,T,b")) 1121 (match_operand:DI 0 "register_operand" "d, d,d")))] 1122 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH" 1123 "@ 1124 cgfr\t%0,%1 1125 cgf\t%0,%1 1126 cgfrl\t%0,%1" 1127 [(set_attr "op_type" "RRE,RXY,RIL") 1128 (set_attr "z10prop" "z10_c,*,*") 1129 (set_attr "type" "*,*,larl")]) 1130 1131 1132 1133(define_insn "*cmpsi_ccs_sign" 1134 [(set (reg CC_REGNUM) 1135 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b")) 1136 (match_operand:SI 0 "register_operand" "d,d,d")))] 1137 "s390_match_ccmode(insn, CCSRmode)" 1138 "@ 1139 ch\t%0,%1 1140 chy\t%0,%1 1141 chrl\t%0,%1" 1142 [(set_attr "op_type" "RX,RXY,RIL") 1143 (set_attr "cpu_facility" "*,longdisp,z10") 1144 (set_attr "type" "*,*,larl") 1145 (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")]) 1146 1147(define_insn "*cmphi_ccs_z10" 1148 [(set (reg CC_REGNUM) 1149 (compare (match_operand:HI 0 "s_operand" "Q") 1150 (match_operand:HI 1 "immediate_operand" "K")))] 1151 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10" 1152 "chhsi\t%0,%1" 1153 [(set_attr "op_type" "SIL") 1154 (set_attr "z196prop" "z196_cracked")]) 1155 1156(define_insn "*cmpdi_ccs_signhi_rl" 1157 [(set (reg CC_REGNUM) 1158 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "T,b")) 1159 (match_operand:GPR 0 "register_operand" "d,d")))] 1160 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10" 1161 "@ 1162 cgh\t%0,%1 1163 cghrl\t%0,%1" 1164 [(set_attr "op_type" "RXY,RIL") 1165 (set_attr "type" "*,larl")]) 1166 1167; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl 1168(define_insn "*cmp<mode>_ccs" 1169 [(set (reg CC_REGNUM) 1170 (compare (match_operand:GPR 0 "nonimmediate_operand" 1171 "d,d,Q, d,d,d,d") 1172 (match_operand:GPR 1 "general_operand" 1173 "d,K,K,Os,R,T,b")))] 1174 "s390_match_ccmode(insn, CCSmode)" 1175 "@ 1176 c<g>r\t%0,%1 1177 c<g>hi\t%0,%h1 1178 c<g>hsi\t%0,%h1 1179 c<g>fi\t%0,%1 1180 c<g>\t%0,%1 1181 c<y>\t%0,%1 1182 c<g>rl\t%0,%1" 1183 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") 1184 (set_attr "cpu_facility" "*,*,z10,extimm,*,longdisp,z10") 1185 (set_attr "type" "*,*,*,*,*,*,larl") 1186 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")]) 1187 1188 1189; Compare (unsigned) instructions 1190 1191(define_insn "*cmpsi_ccu_zerohi_rlsi" 1192 [(set (reg CC_REGNUM) 1193 (compare (zero_extend:SI (mem:HI (match_operand:SI 1 1194 "larl_operand" "X"))) 1195 (match_operand:SI 0 "register_operand" "d")))] 1196 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" 1197 "clhrl\t%0,%1" 1198 [(set_attr "op_type" "RIL") 1199 (set_attr "type" "larl") 1200 (set_attr "z10prop" "z10_super")]) 1201 1202; clhrl, clghrl 1203(define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi" 1204 [(set (reg CC_REGNUM) 1205 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1 1206 "larl_operand" "X"))) 1207 (match_operand:GPR 0 "register_operand" "d")))] 1208 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" 1209 "cl<g>hrl\t%0,%1" 1210 [(set_attr "op_type" "RIL") 1211 (set_attr "type" "larl") 1212 (set_attr "z10prop" "z10_super")]) 1213 1214(define_insn "*cmpdi_ccu_zero" 1215 [(set (reg CC_REGNUM) 1216 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" 1217 "d,T,b")) 1218 (match_operand:DI 0 "register_operand" "d,d,d")))] 1219 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH" 1220 "@ 1221 clgfr\t%0,%1 1222 clgf\t%0,%1 1223 clgfrl\t%0,%1" 1224 [(set_attr "op_type" "RRE,RXY,RIL") 1225 (set_attr "cpu_facility" "*,*,z10") 1226 (set_attr "type" "*,*,larl") 1227 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")]) 1228 1229(define_insn "*cmpdi_ccu" 1230 [(set (reg CC_REGNUM) 1231 (compare (match_operand:DI 0 "nonimmediate_operand" 1232 "d, d,d,Q,d, Q,BQ") 1233 (match_operand:DI 1 "general_operand" 1234 "d,Op,b,D,T,BQ,Q")))] 1235 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH" 1236 "@ 1237 clgr\t%0,%1 1238 clgfi\t%0,%1 1239 clgrl\t%0,%1 1240 clghsi\t%0,%x1 1241 clg\t%0,%1 1242 # 1243 #" 1244 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS") 1245 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*") 1246 (set_attr "type" "*,*,larl,*,*,*,*") 1247 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")]) 1248 1249(define_insn "*cmpsi_ccu" 1250 [(set (reg CC_REGNUM) 1251 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ") 1252 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))] 1253 "s390_match_ccmode (insn, CCUmode)" 1254 "@ 1255 clr\t%0,%1 1256 clfi\t%0,%o1 1257 clrl\t%0,%1 1258 clfhsi\t%0,%x1 1259 cl\t%0,%1 1260 cly\t%0,%1 1261 # 1262 #" 1263 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") 1264 (set_attr "cpu_facility" "*,extimm,z10,z10,*,longdisp,*,*") 1265 (set_attr "type" "*,*,larl,*,*,*,*,*") 1266 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")]) 1267 1268(define_insn "*cmphi_ccu" 1269 [(set (reg CC_REGNUM) 1270 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ") 1271 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))] 1272 "s390_match_ccmode (insn, CCUmode) 1273 && !register_operand (operands[1], HImode)" 1274 "@ 1275 clm\t%0,3,%S1 1276 clmy\t%0,3,%S1 1277 clhhsi\t%0,%1 1278 # 1279 #" 1280 [(set_attr "op_type" "RS,RSY,SIL,SS,SS") 1281 (set_attr "cpu_facility" "*,longdisp,z10,*,*") 1282 (set_attr "z10prop" "*,*,z10_super,*,*")]) 1283 1284(define_insn "*cmpqi_ccu" 1285 [(set (reg CC_REGNUM) 1286 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") 1287 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] 1288 "s390_match_ccmode (insn, CCUmode) 1289 && !register_operand (operands[1], QImode)" 1290 "@ 1291 clm\t%0,1,%S1 1292 clmy\t%0,1,%S1 1293 cli\t%S0,%b1 1294 cliy\t%S0,%b1 1295 # 1296 #" 1297 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS") 1298 (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*") 1299 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")]) 1300 1301 1302; Block compare (CLC) instruction patterns. 1303 1304(define_insn "*clc" 1305 [(set (reg CC_REGNUM) 1306 (compare (match_operand:BLK 0 "memory_operand" "Q") 1307 (match_operand:BLK 1 "memory_operand" "Q"))) 1308 (use (match_operand 2 "const_int_operand" "n"))] 1309 "s390_match_ccmode (insn, CCUmode) 1310 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" 1311 "clc\t%O0(%2,%R0),%S1" 1312 [(set_attr "op_type" "SS")]) 1313 1314(define_split 1315 [(set (reg CC_REGNUM) 1316 (compare (match_operand 0 "memory_operand" "") 1317 (match_operand 1 "memory_operand" "")))] 1318 "reload_completed 1319 && s390_match_ccmode (insn, CCUmode) 1320 && GET_MODE (operands[0]) == GET_MODE (operands[1]) 1321 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" 1322 [(parallel 1323 [(set (match_dup 0) (match_dup 1)) 1324 (use (match_dup 2))])] 1325{ 1326 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); 1327 operands[0] = adjust_address (operands[0], BLKmode, 0); 1328 operands[1] = adjust_address (operands[1], BLKmode, 0); 1329 1330 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), 1331 operands[0], operands[1]); 1332 operands[0] = SET_DEST (PATTERN (curr_insn)); 1333}) 1334 1335 1336; (TF|DF|SF|TD|DD|SD) instructions 1337 1338 1339; FIXME: load and test instructions turn SNaN into QNaN what is not 1340; acceptable if the target will be used afterwards. On the other hand 1341; they are quite convenient for implementing comparisons with 0.0. So 1342; try to enable them via splitter/peephole if the value isn't needed anymore. 1343; See testcases: load-and-test-fp-1.c and load-and-test-fp-2.c 1344 1345; ltxbr, ltdbr, ltebr, ltxtr, ltdtr 1346(define_insn "*cmp<mode>_ccs_0" 1347 [(set (reg CC_REGNUM) 1348 (compare (match_operand:FP 0 "register_operand" "f") 1349 (match_operand:FP 1 "const0_operand" ""))) 1350 (clobber (match_operand:FP 2 "register_operand" "=0"))] 1351 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" 1352 "lt<xde><bt>r\t%0,%0" 1353 [(set_attr "op_type" "RRE") 1354 (set_attr "type" "fsimp<mode>")]) 1355 1356; VX: TFmode in FPR pairs: use cxbr instead of wfcxb 1357; cxtr, cdtr, cxbr, cdbr, cebr, cdb, ceb, wfcsb, wfcdb 1358(define_insn "*cmp<mode>_ccs" 1359 [(set (reg CC_REGNUM) 1360 (compare (match_operand:FP 0 "register_operand" "f,f,v,v") 1361 (match_operand:FP 1 "general_operand" "f,R,v,v")))] 1362 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" 1363 "@ 1364 c<xde><bt>r\t%0,%1 1365 c<xde>b\t%0,%1 1366 wfcdb\t%0,%1 1367 wfcsb\t%0,%1" 1368 [(set_attr "op_type" "RRE,RXE,VRR,VRR") 1369 (set_attr "cpu_facility" "*,*,vx,vxe") 1370 (set_attr "enabled" "*,<DSF>,<DF>,<SF>")]) 1371 1372; Compare and Branch instructions 1373 1374; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr 1375; The following instructions do a complementary access of their second 1376; operand (z01 only): crj_c, cgrjc, cr, cgr 1377(define_insn "*cmp_and_br_signed_<mode>" 1378 [(set (pc) 1379 (if_then_else (match_operator 0 "s390_signed_integer_comparison" 1380 [(match_operand:GPR 1 "register_operand" "d,d") 1381 (match_operand:GPR 2 "nonmemory_operand" "d,C")]) 1382 (label_ref (match_operand 3 "" "")) 1383 (pc))) 1384 (clobber (reg:CC CC_REGNUM))] 1385 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" 1386{ 1387 if (get_attr_length (insn) == 6) 1388 return which_alternative ? 1389 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3"; 1390 else 1391 return which_alternative ? 1392 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3"; 1393} 1394 [(set_attr "op_type" "RIE") 1395 (set_attr "type" "branch") 1396 (set_attr "z10prop" "z10_super_c,z10_super") 1397 (set (attr "length") 1398 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) 1399 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg 1400 ; 10 byte for cgr/jg 1401 1402; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr 1403; The following instructions do a complementary access of their second 1404; operand (z10 only): clrj, clgrj, clr, clgr 1405(define_insn "*cmp_and_br_unsigned_<mode>" 1406 [(set (pc) 1407 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" 1408 [(match_operand:GPR 1 "register_operand" "d,d") 1409 (match_operand:GPR 2 "nonmemory_operand" "d,I")]) 1410 (label_ref (match_operand 3 "" "")) 1411 (pc))) 1412 (clobber (reg:CC CC_REGNUM))] 1413 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" 1414{ 1415 if (get_attr_length (insn) == 6) 1416 return which_alternative ? 1417 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3"; 1418 else 1419 return which_alternative ? 1420 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3"; 1421} 1422 [(set_attr "op_type" "RIE") 1423 (set_attr "type" "branch") 1424 (set_attr "z10prop" "z10_super_c,z10_super") 1425 (set (attr "length") 1426 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) 1427 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg 1428 ; 10 byte for clgr/jg 1429 1430; And now the same two patterns as above but with a negated CC mask. 1431 1432; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr 1433; The following instructions do a complementary access of their second 1434; operand (z01 only): crj_c, cgrjc, cr, cgr 1435(define_insn "*icmp_and_br_signed_<mode>" 1436 [(set (pc) 1437 (if_then_else (match_operator 0 "s390_signed_integer_comparison" 1438 [(match_operand:GPR 1 "register_operand" "d,d") 1439 (match_operand:GPR 2 "nonmemory_operand" "d,C")]) 1440 (pc) 1441 (label_ref (match_operand 3 "" "")))) 1442 (clobber (reg:CC CC_REGNUM))] 1443 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" 1444{ 1445 if (get_attr_length (insn) == 6) 1446 return which_alternative ? 1447 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3"; 1448 else 1449 return which_alternative ? 1450 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3"; 1451} 1452 [(set_attr "op_type" "RIE") 1453 (set_attr "type" "branch") 1454 (set_attr "z10prop" "z10_super_c,z10_super") 1455 (set (attr "length") 1456 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) 1457 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg 1458 ; 10 byte for cgr/jg 1459 1460; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr 1461; The following instructions do a complementary access of their second 1462; operand (z10 only): clrj, clgrj, clr, clgr 1463(define_insn "*icmp_and_br_unsigned_<mode>" 1464 [(set (pc) 1465 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" 1466 [(match_operand:GPR 1 "register_operand" "d,d") 1467 (match_operand:GPR 2 "nonmemory_operand" "d,I")]) 1468 (pc) 1469 (label_ref (match_operand 3 "" "")))) 1470 (clobber (reg:CC CC_REGNUM))] 1471 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" 1472{ 1473 if (get_attr_length (insn) == 6) 1474 return which_alternative ? 1475 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3"; 1476 else 1477 return which_alternative ? 1478 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3"; 1479} 1480 [(set_attr "op_type" "RIE") 1481 (set_attr "type" "branch") 1482 (set_attr "z10prop" "z10_super_c,z10_super") 1483 (set (attr "length") 1484 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) 1485 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg 1486 ; 10 byte for clgr/jg 1487 1488;; 1489;;- Move instructions. 1490;; 1491 1492; 1493; movti instruction pattern(s). 1494; 1495 1496 1497; Separate out the register pair alternative since constraints (P) are 1498; not able to deal with const_wide_int's. But predicates do. 1499(define_insn "*movti_bigconst" 1500 [(set (match_operand:TI 0 "register_operand" "=d") 1501 (match_operand:TI 1 "reload_const_wide_int_operand" ""))] 1502 "TARGET_ZARCH" 1503 "#") 1504 1505; FIXME: More constants are possible by enabling jxx, jyy constraints 1506; for TImode (use double-int for the calculations) 1507(define_insn "movti" 1508 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,S,v, v, v,v,d,v,R, d,o") 1509 (match_operand:TI 1 "general_operand" " S,d,v,j00,jm1,d,v,R,v,dT,d"))] 1510 "TARGET_ZARCH" 1511 "@ 1512 lmg\t%0,%N0,%S1 1513 stmg\t%1,%N1,%S0 1514 vlr\t%v0,%v1 1515 vzero\t%v0 1516 vone\t%v0 1517 vlvgp\t%v0,%1,%N1 1518 # 1519 vl\t%v0,%1 1520 vst\t%v1,%0 1521 # 1522 #" 1523 [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*") 1524 (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*") 1525 (set_attr "cpu_facility" "*,*,vx,vx,vx,vx,vx,vx,vx,*,*")]) 1526 1527(define_split 1528 [(set (match_operand:TI 0 "nonimmediate_operand" "") 1529 (match_operand:TI 1 "general_operand" ""))] 1530 "TARGET_ZARCH && reload_completed 1531 && !s_operand (operands[0], TImode) 1532 && !s_operand (operands[1], TImode) 1533 && s390_split_ok_p (operands[0], operands[1], TImode, 0)" 1534 [(set (match_dup 2) (match_dup 4)) 1535 (set (match_dup 3) (match_dup 5))] 1536{ 1537 operands[2] = operand_subword (operands[0], 0, 0, TImode); 1538 operands[3] = operand_subword (operands[0], 1, 0, TImode); 1539 operands[4] = operand_subword (operands[1], 0, 0, TImode); 1540 operands[5] = operand_subword (operands[1], 1, 0, TImode); 1541}) 1542 1543(define_split 1544 [(set (match_operand:TI 0 "nonimmediate_operand" "") 1545 (match_operand:TI 1 "general_operand" ""))] 1546 "TARGET_ZARCH && reload_completed 1547 && !s_operand (operands[0], TImode) 1548 && !s_operand (operands[1], TImode) 1549 && s390_split_ok_p (operands[0], operands[1], TImode, 1)" 1550 [(set (match_dup 2) (match_dup 4)) 1551 (set (match_dup 3) (match_dup 5))] 1552{ 1553 operands[2] = operand_subword (operands[0], 1, 0, TImode); 1554 operands[3] = operand_subword (operands[0], 0, 0, TImode); 1555 operands[4] = operand_subword (operands[1], 1, 0, TImode); 1556 operands[5] = operand_subword (operands[1], 0, 0, TImode); 1557}) 1558 1559; Use part of the TImode target reg to perform the address 1560; calculation. If the TImode value is supposed to be copied into a VR 1561; this splitter is not necessary. 1562(define_split 1563 [(set (match_operand:TI 0 "register_operand" "") 1564 (match_operand:TI 1 "memory_operand" ""))] 1565 "TARGET_ZARCH && reload_completed 1566 && !VECTOR_REG_P (operands[0]) 1567 && !s_operand (operands[1], VOIDmode)" 1568 [(set (match_dup 0) (match_dup 1))] 1569{ 1570 rtx addr = operand_subword (operands[0], 1, 0, TImode); 1571 addr = gen_lowpart (Pmode, addr); 1572 s390_load_address (addr, XEXP (operands[1], 0)); 1573 operands[1] = replace_equiv_address (operands[1], addr); 1574}) 1575 1576 1577; Split a VR -> GPR TImode move into 2 vector load GR from VR element. 1578; For the higher order bits we do simply a DImode move while the 1579; second part is done via vec extract. Both will end up as vlgvg. 1580(define_split 1581 [(set (match_operand:TI 0 "register_operand" "") 1582 (match_operand:TI 1 "register_operand" ""))] 1583 "TARGET_VX && reload_completed 1584 && GENERAL_REG_P (operands[0]) 1585 && VECTOR_REG_P (operands[1])" 1586 [(set (match_dup 2) (match_dup 4)) 1587 (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)] 1588 UNSPEC_VEC_EXTRACT))] 1589{ 1590 operands[2] = operand_subword (operands[0], 0, 0, TImode); 1591 operands[3] = operand_subword (operands[0], 1, 0, TImode); 1592 operands[4] = gen_rtx_REG (DImode, REGNO (operands[1])); 1593 operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1])); 1594}) 1595 1596; 1597; Patterns used for secondary reloads 1598; 1599 1600; z10 provides move instructions accepting larl memory operands. 1601; Unfortunately there is no such variant for QI, TI and FP mode moves. 1602; These patterns are also used for unaligned SI and DI accesses. 1603 1604(define_expand "reload<ALL:mode><P:mode>_tomem_z10" 1605 [(parallel [(match_operand:ALL 0 "memory_operand" "") 1606 (match_operand:ALL 1 "register_operand" "=d") 1607 (match_operand:P 2 "register_operand" "=&a")])] 1608 "TARGET_Z10" 1609{ 1610 s390_reload_symref_address (operands[1], operands[0], operands[2], 1); 1611 DONE; 1612}) 1613 1614(define_expand "reload<ALL:mode><P:mode>_toreg_z10" 1615 [(parallel [(match_operand:ALL 0 "register_operand" "=d") 1616 (match_operand:ALL 1 "memory_operand" "") 1617 (match_operand:P 2 "register_operand" "=a")])] 1618 "TARGET_Z10" 1619{ 1620 s390_reload_symref_address (operands[0], operands[1], operands[2], 0); 1621 DONE; 1622}) 1623 1624(define_expand "reload<P:mode>_larl_odd_addend_z10" 1625 [(parallel [(match_operand:P 0 "register_operand" "=d") 1626 (match_operand:P 1 "larl_operand" "") 1627 (match_operand:P 2 "register_operand" "=a")])] 1628 "TARGET_Z10" 1629{ 1630 s390_reload_larl_operand (operands[0], operands[1], operands[2]); 1631 DONE; 1632}) 1633 1634; Handles loading a PLUS (load address) expression 1635 1636(define_expand "reload<mode>_plus" 1637 [(parallel [(match_operand:P 0 "register_operand" "=a") 1638 (match_operand:P 1 "s390_plus_operand" "") 1639 (match_operand:P 2 "register_operand" "=&a")])] 1640 "" 1641{ 1642 s390_expand_plus_operand (operands[0], operands[1], operands[2]); 1643 DONE; 1644}) 1645 1646; Not all the indirect memory access instructions support the full 1647; format (long disp + index + base). So whenever a move from/to such 1648; an address is required and the instruction cannot deal with it we do 1649; a load address into a scratch register first and use this as the new 1650; base register. 1651; This in particular is used for: 1652; - non-offsetable memory accesses for multiword moves 1653; - full vector reg moves with long displacements 1654 1655(define_expand "reload<mode>_la_in" 1656 [(parallel [(match_operand 0 "register_operand" "") 1657 (match_operand 1 "" "") 1658 (match_operand:P 2 "register_operand" "=&a")])] 1659 "" 1660{ 1661 gcc_assert (MEM_P (operands[1])); 1662 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0))); 1663 operands[1] = replace_equiv_address (operands[1], operands[2]); 1664 emit_move_insn (operands[0], operands[1]); 1665 DONE; 1666}) 1667 1668(define_expand "reload<mode>_la_out" 1669 [(parallel [(match_operand 0 "" "") 1670 (match_operand 1 "register_operand" "") 1671 (match_operand:P 2 "register_operand" "=&a")])] 1672 "" 1673{ 1674 gcc_assert (MEM_P (operands[0])); 1675 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); 1676 operands[0] = replace_equiv_address (operands[0], operands[2]); 1677 emit_move_insn (operands[0], operands[1]); 1678 DONE; 1679}) 1680 1681(define_expand "reload<mode>_PIC_addr" 1682 [(parallel [(match_operand 0 "register_operand" "=d") 1683 (match_operand 1 "larl_operand" "") 1684 (match_operand:P 2 "register_operand" "=a")])] 1685 "" 1686{ 1687 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]); 1688 emit_move_insn (operands[0], new_rtx); 1689}) 1690 1691; 1692; movdi instruction pattern(s). 1693; 1694 1695(define_expand "movdi" 1696 [(set (match_operand:DI 0 "general_operand" "") 1697 (match_operand:DI 1 "general_operand" ""))] 1698 "" 1699{ 1700 /* Handle symbolic constants. */ 1701 if (TARGET_64BIT 1702 && (SYMBOLIC_CONST (operands[1]) 1703 || (GET_CODE (operands[1]) == PLUS 1704 && XEXP (operands[1], 0) == pic_offset_table_rtx 1705 && SYMBOLIC_CONST (XEXP (operands[1], 1))))) 1706 emit_symbolic_move (operands); 1707}) 1708 1709(define_insn "*movdi_larl" 1710 [(set (match_operand:DI 0 "register_operand" "=d") 1711 (match_operand:DI 1 "larl_operand" "X"))] 1712 "TARGET_64BIT 1713 && !FP_REG_P (operands[0])" 1714 "larl\t%0,%1" 1715 [(set_attr "op_type" "RIL") 1716 (set_attr "type" "larl") 1717 (set_attr "z10prop" "z10_super_A1")]) 1718 1719(define_insn "*movdi_64" 1720 [(set (match_operand:DI 0 "nonimmediate_operand" 1721 "=d, d, d, d, d, d, d, d,f,d,d,d,d,d,T,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d,v,R") 1722 (match_operand:DI 1 "general_operand" 1723 " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,T,d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,R,v"))] 1724 "TARGET_ZARCH" 1725 "@ 1726 lghi\t%0,%h1 1727 llihh\t%0,%i1 1728 llihl\t%0,%i1 1729 llilh\t%0,%i1 1730 llill\t%0,%i1 1731 lgfi\t%0,%1 1732 llihf\t%0,%k1 1733 llilf\t%0,%k1 1734 ldgr\t%0,%1 1735 lgdr\t%0,%1 1736 lay\t%0,%a1 1737 lgrl\t%0,%1 1738 lgr\t%0,%1 1739 lg\t%0,%1 1740 stg\t%1,%0 1741 ldr\t%0,%1 1742 ld\t%0,%1 1743 ldy\t%0,%1 1744 std\t%1,%0 1745 stdy\t%1,%0 1746 stgrl\t%1,%0 1747 mvghi\t%0,%1 1748 # 1749 # 1750 stam\t%1,%N1,%S0 1751 lam\t%0,%N0,%S1 1752 vleig\t%v0,%h1,0 1753 vlr\t%v0,%v1 1754 vlvgg\t%v0,%1,0 1755 vlgvg\t%0,%v1,0 1756 vleg\t%v0,%1,0 1757 vsteg\t%v1,%0,0" 1758 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY, 1759 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS,VRX,VRX") 1760 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store, 1761 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*, 1762 *,*,*,*,*,*,*") 1763 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp, 1764 z10,*,*,*,*,*,longdisp,*,longdisp, 1765 z10,z10,*,*,*,*,vx,vx,vx,vx,vx,vx") 1766 (set_attr "z10prop" "z10_fwd_A1, 1767 z10_fwd_E1, 1768 z10_fwd_E1, 1769 z10_fwd_E1, 1770 z10_fwd_E1, 1771 z10_fwd_A1, 1772 z10_fwd_E1, 1773 z10_fwd_E1, 1774 *, 1775 *, 1776 z10_fwd_A1, 1777 z10_fwd_A3, 1778 z10_fr_E1, 1779 z10_fwd_A3, 1780 z10_rec, 1781 *, 1782 *, 1783 *, 1784 *, 1785 *, 1786 z10_rec, 1787 z10_super, 1788 *, 1789 *, 1790 *, 1791 *,*,*,*,*,*,*") 1792]) 1793 1794(define_split 1795 [(set (match_operand:DI 0 "register_operand" "") 1796 (match_operand:DI 1 "register_operand" ""))] 1797 "TARGET_ZARCH && ACCESS_REG_P (operands[1])" 1798 [(set (match_dup 2) (match_dup 3)) 1799 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) 1800 (set (strict_low_part (match_dup 2)) (match_dup 4))] 1801 "operands[2] = gen_lowpart (SImode, operands[0]); 1802 s390_split_access_reg (operands[1], &operands[4], &operands[3]);") 1803 1804(define_split 1805 [(set (match_operand:DI 0 "register_operand" "") 1806 (match_operand:DI 1 "register_operand" ""))] 1807 "TARGET_ZARCH && ACCESS_REG_P (operands[0]) 1808 && dead_or_set_p (insn, operands[1])" 1809 [(set (match_dup 3) (match_dup 2)) 1810 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) 1811 (set (match_dup 4) (match_dup 2))] 1812 "operands[2] = gen_lowpart (SImode, operands[1]); 1813 s390_split_access_reg (operands[0], &operands[3], &operands[4]);") 1814 1815(define_split 1816 [(set (match_operand:DI 0 "register_operand" "") 1817 (match_operand:DI 1 "register_operand" ""))] 1818 "TARGET_ZARCH && ACCESS_REG_P (operands[0]) 1819 && !dead_or_set_p (insn, operands[1])" 1820 [(set (match_dup 3) (match_dup 2)) 1821 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) 1822 (set (match_dup 4) (match_dup 2)) 1823 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] 1824 "operands[2] = gen_lowpart (SImode, operands[1]); 1825 s390_split_access_reg (operands[0], &operands[3], &operands[4]);") 1826 1827(define_insn "*movdi_31" 1828 [(set (match_operand:DI 0 "nonimmediate_operand" 1829 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") 1830 (match_operand:DI 1 "general_operand" 1831 " Q,S,d,d,dPT,d, *f, R, T,*f,*f,b"))] 1832 "!TARGET_ZARCH" 1833 "@ 1834 lm\t%0,%N0,%S1 1835 lmy\t%0,%N0,%S1 1836 stm\t%1,%N1,%S0 1837 stmy\t%1,%N1,%S0 1838 # 1839 # 1840 ldr\t%0,%1 1841 ld\t%0,%1 1842 ldy\t%0,%1 1843 std\t%1,%0 1844 stdy\t%1,%0 1845 #" 1846 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*") 1847 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*") 1848 (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*,*,*,longdisp,*,longdisp,z10")]) 1849 1850; For a load from a symbol ref we can use one of the target registers 1851; together with larl to load the address. 1852(define_split 1853 [(set (match_operand:DI 0 "register_operand" "") 1854 (match_operand:DI 1 "memory_operand" ""))] 1855 "!TARGET_ZARCH && reload_completed && TARGET_Z10 1856 && larl_operand (XEXP (operands[1], 0), SImode)" 1857 [(set (match_dup 2) (match_dup 3)) 1858 (set (match_dup 0) (match_dup 1))] 1859{ 1860 operands[2] = operand_subword (operands[0], 1, 0, DImode); 1861 operands[3] = XEXP (operands[1], 0); 1862 operands[1] = replace_equiv_address (operands[1], operands[2]); 1863}) 1864 1865(define_split 1866 [(set (match_operand:DI 0 "nonimmediate_operand" "") 1867 (match_operand:DI 1 "general_operand" ""))] 1868 "!TARGET_ZARCH && reload_completed 1869 && !s_operand (operands[0], DImode) 1870 && !s_operand (operands[1], DImode) 1871 && s390_split_ok_p (operands[0], operands[1], DImode, 0)" 1872 [(set (match_dup 2) (match_dup 4)) 1873 (set (match_dup 3) (match_dup 5))] 1874{ 1875 operands[2] = operand_subword (operands[0], 0, 0, DImode); 1876 operands[3] = operand_subword (operands[0], 1, 0, DImode); 1877 operands[4] = operand_subword (operands[1], 0, 0, DImode); 1878 operands[5] = operand_subword (operands[1], 1, 0, DImode); 1879}) 1880 1881(define_split 1882 [(set (match_operand:DI 0 "nonimmediate_operand" "") 1883 (match_operand:DI 1 "general_operand" ""))] 1884 "!TARGET_ZARCH && reload_completed 1885 && !s_operand (operands[0], DImode) 1886 && !s_operand (operands[1], DImode) 1887 && s390_split_ok_p (operands[0], operands[1], DImode, 1)" 1888 [(set (match_dup 2) (match_dup 4)) 1889 (set (match_dup 3) (match_dup 5))] 1890{ 1891 operands[2] = operand_subword (operands[0], 1, 0, DImode); 1892 operands[3] = operand_subword (operands[0], 0, 0, DImode); 1893 operands[4] = operand_subword (operands[1], 1, 0, DImode); 1894 operands[5] = operand_subword (operands[1], 0, 0, DImode); 1895}) 1896 1897(define_split 1898 [(set (match_operand:DI 0 "register_operand" "") 1899 (match_operand:DI 1 "memory_operand" ""))] 1900 "!TARGET_ZARCH && reload_completed 1901 && !FP_REG_P (operands[0]) 1902 && !s_operand (operands[1], VOIDmode)" 1903 [(set (match_dup 0) (match_dup 1))] 1904{ 1905 rtx addr = operand_subword (operands[0], 1, 0, DImode); 1906 s390_load_address (addr, XEXP (operands[1], 0)); 1907 operands[1] = replace_equiv_address (operands[1], addr); 1908}) 1909 1910(define_peephole2 1911 [(set (match_operand:DI 0 "register_operand" "") 1912 (mem:DI (match_operand 1 "address_operand" "")))] 1913 "TARGET_ZARCH 1914 && !FP_REG_P (operands[0]) 1915 && GET_CODE (operands[1]) == SYMBOL_REF 1916 && CONSTANT_POOL_ADDRESS_P (operands[1]) 1917 && get_pool_mode (operands[1]) == DImode 1918 && legitimate_reload_constant_p (get_pool_constant (operands[1]))" 1919 [(set (match_dup 0) (match_dup 2))] 1920 "operands[2] = get_pool_constant (operands[1]);") 1921 1922(define_insn "*la_64" 1923 [(set (match_operand:DI 0 "register_operand" "=d,d") 1924 (match_operand:QI 1 "address_operand" "ZR,ZT"))] 1925 "TARGET_64BIT" 1926 "@ 1927 la\t%0,%a1 1928 lay\t%0,%a1" 1929 [(set_attr "op_type" "RX,RXY") 1930 (set_attr "type" "la") 1931 (set_attr "cpu_facility" "*,longdisp") 1932 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) 1933 1934(define_peephole2 1935 [(parallel 1936 [(set (match_operand:DI 0 "register_operand" "") 1937 (match_operand:QI 1 "address_operand" "")) 1938 (clobber (reg:CC CC_REGNUM))])] 1939 "TARGET_64BIT 1940 && preferred_la_operand_p (operands[1], const0_rtx)" 1941 [(set (match_dup 0) (match_dup 1))] 1942 "") 1943 1944(define_peephole2 1945 [(set (match_operand:DI 0 "register_operand" "") 1946 (match_operand:DI 1 "register_operand" "")) 1947 (parallel 1948 [(set (match_dup 0) 1949 (plus:DI (match_dup 0) 1950 (match_operand:DI 2 "nonmemory_operand" ""))) 1951 (clobber (reg:CC CC_REGNUM))])] 1952 "TARGET_64BIT 1953 && !reg_overlap_mentioned_p (operands[0], operands[2]) 1954 && preferred_la_operand_p (operands[1], operands[2])" 1955 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] 1956 "") 1957 1958; 1959; movsi instruction pattern(s). 1960; 1961 1962(define_expand "movsi" 1963 [(set (match_operand:SI 0 "general_operand" "") 1964 (match_operand:SI 1 "general_operand" ""))] 1965 "" 1966{ 1967 /* Handle symbolic constants. */ 1968 if (!TARGET_64BIT 1969 && (SYMBOLIC_CONST (operands[1]) 1970 || (GET_CODE (operands[1]) == PLUS 1971 && XEXP (operands[1], 0) == pic_offset_table_rtx 1972 && SYMBOLIC_CONST (XEXP(operands[1], 1))))) 1973 emit_symbolic_move (operands); 1974}) 1975 1976(define_insn "*movsi_larl" 1977 [(set (match_operand:SI 0 "register_operand" "=d") 1978 (match_operand:SI 1 "larl_operand" "X"))] 1979 "!TARGET_64BIT && TARGET_CPU_ZARCH 1980 && !FP_REG_P (operands[0])" 1981 "larl\t%0,%1" 1982 [(set_attr "op_type" "RIL") 1983 (set_attr "type" "larl") 1984 (set_attr "z10prop" "z10_fwd_A1")]) 1985 1986(define_insn "*movsi_zarch" 1987 [(set (match_operand:SI 0 "nonimmediate_operand" 1988 "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d,v,R") 1989 (match_operand:SI 1 "general_operand" 1990 " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,R,v"))] 1991 "TARGET_ZARCH" 1992 "@ 1993 lhi\t%0,%h1 1994 llilh\t%0,%i1 1995 llill\t%0,%i1 1996 iilf\t%0,%o1 1997 lay\t%0,%a1 1998 lrl\t%0,%1 1999 lr\t%0,%1 2000 l\t%0,%1 2001 ly\t%0,%1 2002 st\t%1,%0 2003 sty\t%1,%0 2004 ldr\t%0,%1 2005 ler\t%0,%1 2006 lde\t%0,%1 2007 le\t%0,%1 2008 ley\t%0,%1 2009 ste\t%1,%0 2010 stey\t%1,%0 2011 ear\t%0,%1 2012 sar\t%0,%1 2013 stam\t%1,%1,%S0 2014 strl\t%1,%0 2015 mvhi\t%0,%1 2016 lam\t%0,%0,%S1 2017 vleif\t%v0,%h1,0 2018 vlr\t%v0,%v1 2019 vlvgf\t%v0,%1,0 2020 vlgvf\t%0,%v1,0 2021 vlef\t%v0,%1,0 2022 vstef\t%v1,%0,0" 2023 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY, 2024 RR,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX") 2025 (set_attr "type" "*, 2026 *, 2027 *, 2028 *, 2029 la, 2030 larl, 2031 lr, 2032 load, 2033 load, 2034 store, 2035 store, 2036 floadsf, 2037 floadsf, 2038 floadsf, 2039 floadsf, 2040 floadsf, 2041 fstoresf, 2042 fstoresf, 2043 *, 2044 *, 2045 *, 2046 larl, 2047 *, 2048 *,*,*,*,*,*,*") 2049 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp, 2050 vx,*,vx,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vx,vx,vx,vx,vx,vx") 2051 (set_attr "z10prop" "z10_fwd_A1, 2052 z10_fwd_E1, 2053 z10_fwd_E1, 2054 z10_fwd_A1, 2055 z10_fwd_A1, 2056 z10_fwd_A3, 2057 z10_fr_E1, 2058 z10_fwd_A3, 2059 z10_fwd_A3, 2060 z10_rec, 2061 z10_rec, 2062 *, 2063 *, 2064 *, 2065 *, 2066 *, 2067 *, 2068 *, 2069 z10_super_E1, 2070 z10_super, 2071 *, 2072 z10_rec, 2073 z10_super, 2074 *,*,*,*,*,*,*")]) 2075 2076(define_insn "*movsi_esa" 2077 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t") 2078 (match_operand:SI 1 "general_operand" "K,d,R,d, *f, *f, R, R,*f,t,d,t,Q"))] 2079 "!TARGET_ZARCH" 2080 "@ 2081 lhi\t%0,%h1 2082 lr\t%0,%1 2083 l\t%0,%1 2084 st\t%1,%0 2085 ldr\t%0,%1 2086 ler\t%0,%1 2087 lde\t%0,%1 2088 le\t%0,%1 2089 ste\t%1,%0 2090 ear\t%0,%1 2091 sar\t%0,%1 2092 stam\t%1,%1,%S0 2093 lam\t%0,%0,%S1" 2094 [(set_attr "op_type" "RI,RR,RX,RX,RR,RR,RXE,RX,RX,RRE,RRE,RS,RS") 2095 (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*") 2096 (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1, 2097 z10_super,*,*") 2098 (set_attr "cpu_facility" "*,*,*,*,vx,*,vx,*,*,*,*,*,*") 2099]) 2100 2101(define_peephole2 2102 [(set (match_operand:SI 0 "register_operand" "") 2103 (mem:SI (match_operand 1 "address_operand" "")))] 2104 "!FP_REG_P (operands[0]) 2105 && GET_CODE (operands[1]) == SYMBOL_REF 2106 && CONSTANT_POOL_ADDRESS_P (operands[1]) 2107 && get_pool_mode (operands[1]) == SImode 2108 && legitimate_reload_constant_p (get_pool_constant (operands[1]))" 2109 [(set (match_dup 0) (match_dup 2))] 2110 "operands[2] = get_pool_constant (operands[1]);") 2111 2112(define_insn "*la_31" 2113 [(set (match_operand:SI 0 "register_operand" "=d,d") 2114 (match_operand:QI 1 "address_operand" "ZR,ZT"))] 2115 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" 2116 "@ 2117 la\t%0,%a1 2118 lay\t%0,%a1" 2119 [(set_attr "op_type" "RX,RXY") 2120 (set_attr "type" "la") 2121 (set_attr "cpu_facility" "*,longdisp") 2122 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) 2123 2124(define_peephole2 2125 [(parallel 2126 [(set (match_operand:SI 0 "register_operand" "") 2127 (match_operand:QI 1 "address_operand" "")) 2128 (clobber (reg:CC CC_REGNUM))])] 2129 "!TARGET_64BIT 2130 && preferred_la_operand_p (operands[1], const0_rtx)" 2131 [(set (match_dup 0) (match_dup 1))] 2132 "") 2133 2134(define_peephole2 2135 [(set (match_operand:SI 0 "register_operand" "") 2136 (match_operand:SI 1 "register_operand" "")) 2137 (parallel 2138 [(set (match_dup 0) 2139 (plus:SI (match_dup 0) 2140 (match_operand:SI 2 "nonmemory_operand" ""))) 2141 (clobber (reg:CC CC_REGNUM))])] 2142 "!TARGET_64BIT 2143 && !reg_overlap_mentioned_p (operands[0], operands[2]) 2144 && preferred_la_operand_p (operands[1], operands[2])" 2145 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] 2146 "") 2147 2148(define_insn "*la_31_and" 2149 [(set (match_operand:SI 0 "register_operand" "=d,d") 2150 (and:SI (match_operand:QI 1 "address_operand" "ZR,ZT") 2151 (const_int 2147483647)))] 2152 "!TARGET_64BIT" 2153 "@ 2154 la\t%0,%a1 2155 lay\t%0,%a1" 2156 [(set_attr "op_type" "RX,RXY") 2157 (set_attr "type" "la") 2158 (set_attr "cpu_facility" "*,longdisp") 2159 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) 2160 2161(define_insn_and_split "*la_31_and_cc" 2162 [(set (match_operand:SI 0 "register_operand" "=d") 2163 (and:SI (match_operand:QI 1 "address_operand" "p") 2164 (const_int 2147483647))) 2165 (clobber (reg:CC CC_REGNUM))] 2166 "!TARGET_64BIT" 2167 "#" 2168 "&& reload_completed" 2169 [(set (match_dup 0) 2170 (and:SI (match_dup 1) (const_int 2147483647)))] 2171 "" 2172 [(set_attr "op_type" "RX") 2173 (set_attr "type" "la")]) 2174 2175(define_insn "force_la_31" 2176 [(set (match_operand:SI 0 "register_operand" "=d,d") 2177 (match_operand:QI 1 "address_operand" "ZR,ZT")) 2178 (use (const_int 0))] 2179 "!TARGET_64BIT" 2180 "@ 2181 la\t%0,%a1 2182 lay\t%0,%a1" 2183 [(set_attr "op_type" "RX") 2184 (set_attr "type" "la") 2185 (set_attr "cpu_facility" "*,longdisp") 2186 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) 2187 2188; 2189; movhi instruction pattern(s). 2190; 2191 2192(define_expand "movhi" 2193 [(set (match_operand:HI 0 "nonimmediate_operand" "") 2194 (match_operand:HI 1 "general_operand" ""))] 2195 "" 2196{ 2197 /* Make it explicit that loading a register from memory 2198 always sign-extends (at least) to SImode. */ 2199 if (optimize && can_create_pseudo_p () 2200 && register_operand (operands[0], VOIDmode) 2201 && GET_CODE (operands[1]) == MEM) 2202 { 2203 rtx tmp = gen_reg_rtx (SImode); 2204 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); 2205 emit_insn (gen_rtx_SET (tmp, ext)); 2206 operands[1] = gen_lowpart (HImode, tmp); 2207 } 2208}) 2209 2210(define_insn "*movhi" 2211 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d,v,R") 2212 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,R,v"))] 2213 "" 2214 "@ 2215 lr\t%0,%1 2216 lhi\t%0,%h1 2217 lh\t%0,%1 2218 lhy\t%0,%1 2219 lhrl\t%0,%1 2220 sth\t%1,%0 2221 sthy\t%1,%0 2222 sthrl\t%1,%0 2223 mvhhi\t%0,%1 2224 vleih\t%v0,%h1,0 2225 vlr\t%v0,%v1 2226 vlvgh\t%v0,%1,0 2227 vlgvh\t%0,%v1,0 2228 vleh\t%v0,%1,0 2229 vsteh\t%v1,%0,0" 2230 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX") 2231 (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*") 2232 (set_attr "cpu_facility" "*,*,*,longdisp,z10,*,longdisp,z10,z10,vx,vx,vx,vx,vx,vx") 2233 (set_attr "z10prop" "z10_fr_E1, 2234 z10_fwd_A1, 2235 z10_super_E1, 2236 z10_super_E1, 2237 z10_super_E1, 2238 z10_rec, 2239 z10_rec, 2240 z10_rec, 2241 z10_super,*,*,*,*,*,*")]) 2242 2243(define_peephole2 2244 [(set (match_operand:HI 0 "register_operand" "") 2245 (mem:HI (match_operand 1 "address_operand" "")))] 2246 "GET_CODE (operands[1]) == SYMBOL_REF 2247 && CONSTANT_POOL_ADDRESS_P (operands[1]) 2248 && get_pool_mode (operands[1]) == HImode 2249 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" 2250 [(set (match_dup 0) (match_dup 2))] 2251 "operands[2] = get_pool_constant (operands[1]);") 2252 2253; 2254; movqi instruction pattern(s). 2255; 2256 2257(define_expand "movqi" 2258 [(set (match_operand:QI 0 "nonimmediate_operand" "") 2259 (match_operand:QI 1 "general_operand" ""))] 2260 "" 2261{ 2262 /* On z/Architecture, zero-extending from memory to register 2263 is just as fast as a QImode load. */ 2264 if (TARGET_ZARCH && optimize && can_create_pseudo_p () 2265 && register_operand (operands[0], VOIDmode) 2266 && GET_CODE (operands[1]) == MEM) 2267 { 2268 rtx tmp = gen_reg_rtx (DImode); 2269 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]); 2270 emit_insn (gen_rtx_SET (tmp, ext)); 2271 operands[1] = gen_lowpart (QImode, tmp); 2272 } 2273}) 2274 2275(define_insn "*movqi" 2276 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d,v,R") 2277 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,R,v"))] 2278 "" 2279 "@ 2280 lr\t%0,%1 2281 lhi\t%0,%b1 2282 ic\t%0,%1 2283 icy\t%0,%1 2284 stc\t%1,%0 2285 stcy\t%1,%0 2286 mvi\t%S0,%b1 2287 mviy\t%S0,%b1 2288 # 2289 vleib\t%v0,%b1,0 2290 vlr\t%v0,%v1 2291 vlvgb\t%v0,%1,0 2292 vlgvb\t%0,%v1,0 2293 vleb\t%v0,%1,0 2294 vsteb\t%v1,%0,0" 2295 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX") 2296 (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*") 2297 (set_attr "cpu_facility" "*,*,*,longdisp,*,longdisp,*,longdisp,*,vx,vx,vx,vx,vx,vx") 2298 (set_attr "z10prop" "z10_fr_E1, 2299 z10_fwd_A1, 2300 z10_super_E1, 2301 z10_super_E1, 2302 z10_rec, 2303 z10_rec, 2304 z10_super, 2305 z10_super, 2306 *,*,*,*,*,*,*")]) 2307 2308(define_peephole2 2309 [(set (match_operand:QI 0 "nonimmediate_operand" "") 2310 (mem:QI (match_operand 1 "address_operand" "")))] 2311 "GET_CODE (operands[1]) == SYMBOL_REF 2312 && CONSTANT_POOL_ADDRESS_P (operands[1]) 2313 && get_pool_mode (operands[1]) == QImode 2314 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" 2315 [(set (match_dup 0) (match_dup 2))] 2316 "operands[2] = get_pool_constant (operands[1]);") 2317 2318; 2319; movstrictqi instruction pattern(s). 2320; 2321 2322(define_insn "*movstrictqi" 2323 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) 2324 (match_operand:QI 1 "memory_operand" "R,T"))] 2325 "" 2326 "@ 2327 ic\t%0,%1 2328 icy\t%0,%1" 2329 [(set_attr "op_type" "RX,RXY") 2330 (set_attr "cpu_facility" "*,longdisp") 2331 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 2332 2333; 2334; movstricthi instruction pattern(s). 2335; 2336 2337(define_insn "*movstricthi" 2338 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) 2339 (match_operand:HI 1 "memory_operand" "Q,S")) 2340 (clobber (reg:CC CC_REGNUM))] 2341 "" 2342 "@ 2343 icm\t%0,3,%S1 2344 icmy\t%0,3,%S1" 2345 [(set_attr "op_type" "RS,RSY") 2346 (set_attr "cpu_facility" "*,longdisp") 2347 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 2348 2349; 2350; movstrictsi instruction pattern(s). 2351; 2352 2353(define_insn "movstrictsi" 2354 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) 2355 (match_operand:SI 1 "general_operand" "d,R,T,t"))] 2356 "TARGET_ZARCH" 2357 "@ 2358 lr\t%0,%1 2359 l\t%0,%1 2360 ly\t%0,%1 2361 ear\t%0,%1" 2362 [(set_attr "op_type" "RR,RX,RXY,RRE") 2363 (set_attr "type" "lr,load,load,*") 2364 (set_attr "cpu_facility" "*,*,longdisp,*") 2365 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) 2366 2367; 2368; mov(tf|td) instruction pattern(s). 2369; 2370 2371(define_expand "mov<mode>" 2372 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") 2373 (match_operand:TD_TF 1 "general_operand" ""))] 2374 "" 2375 "") 2376 2377(define_insn "*mov<mode>_64" 2378 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,d,S, d,o") 2379 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,S,d,dT,d"))] 2380 "TARGET_ZARCH" 2381 "@ 2382 lzxr\t%0 2383 lxr\t%0,%1 2384 # 2385 # 2386 lmg\t%0,%N0,%S1 2387 stmg\t%1,%N1,%S0 2388 # 2389 #" 2390 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*") 2391 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*") 2392 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")]) 2393 2394(define_insn "*mov<mode>_31" 2395 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") 2396 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] 2397 "!TARGET_ZARCH" 2398 "@ 2399 lzxr\t%0 2400 lxr\t%0,%1 2401 # 2402 #" 2403 [(set_attr "op_type" "RRE,RRE,*,*") 2404 (set_attr "type" "fsimptf,fsimptf,*,*") 2405 (set_attr "cpu_facility" "z196,*,*,*")]) 2406 2407; TFmode in GPRs splitters 2408 2409(define_split 2410 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") 2411 (match_operand:TD_TF 1 "general_operand" ""))] 2412 "TARGET_ZARCH && reload_completed 2413 && !s_operand (operands[0], <MODE>mode) 2414 && !s_operand (operands[1], <MODE>mode) 2415 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" 2416 [(set (match_dup 2) (match_dup 4)) 2417 (set (match_dup 3) (match_dup 5))] 2418{ 2419 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); 2420 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); 2421 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); 2422 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); 2423}) 2424 2425(define_split 2426 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") 2427 (match_operand:TD_TF 1 "general_operand" ""))] 2428 "TARGET_ZARCH && reload_completed 2429 && !s_operand (operands[0], <MODE>mode) 2430 && !s_operand (operands[1], <MODE>mode) 2431 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" 2432 [(set (match_dup 2) (match_dup 4)) 2433 (set (match_dup 3) (match_dup 5))] 2434{ 2435 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); 2436 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); 2437 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); 2438 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); 2439}) 2440 2441(define_split 2442 [(set (match_operand:TD_TF 0 "register_operand" "") 2443 (match_operand:TD_TF 1 "memory_operand" ""))] 2444 "TARGET_ZARCH && reload_completed 2445 && GENERAL_REG_P (operands[0]) 2446 && !s_operand (operands[1], VOIDmode)" 2447 [(set (match_dup 0) (match_dup 1))] 2448{ 2449 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); 2450 addr = gen_lowpart (Pmode, addr); 2451 s390_load_address (addr, XEXP (operands[1], 0)); 2452 operands[1] = replace_equiv_address (operands[1], addr); 2453}) 2454 2455; TFmode in BFPs splitters 2456 2457(define_split 2458 [(set (match_operand:TD_TF 0 "register_operand" "") 2459 (match_operand:TD_TF 1 "memory_operand" ""))] 2460 "reload_completed && offsettable_memref_p (operands[1]) 2461 && FP_REG_P (operands[0])" 2462 [(set (match_dup 2) (match_dup 4)) 2463 (set (match_dup 3) (match_dup 5))] 2464{ 2465 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], 2466 <MODE>mode, 0); 2467 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], 2468 <MODE>mode, 8); 2469 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0); 2470 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8); 2471}) 2472 2473(define_split 2474 [(set (match_operand:TD_TF 0 "memory_operand" "") 2475 (match_operand:TD_TF 1 "register_operand" ""))] 2476 "reload_completed && offsettable_memref_p (operands[0]) 2477 && FP_REG_P (operands[1])" 2478 [(set (match_dup 2) (match_dup 4)) 2479 (set (match_dup 3) (match_dup 5))] 2480{ 2481 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0); 2482 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8); 2483 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], 2484 <MODE>mode, 0); 2485 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], 2486 <MODE>mode, 8); 2487}) 2488 2489; 2490; mov(df|dd) instruction pattern(s). 2491; 2492 2493(define_expand "mov<mode>" 2494 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") 2495 (match_operand:DD_DF 1 "general_operand" ""))] 2496 "" 2497 "") 2498 2499(define_insn "*mov<mode>_64dfp" 2500 [(set (match_operand:DD_DF 0 "nonimmediate_operand" 2501 "=f,f,f,d,f,f,R,T,d,d,d,d,b,T,v,v,v,d,v,R") 2502 (match_operand:DD_DF 1 "general_operand" 2503 " G,f,d,f,R,T,f,f,G,d,b,T,d,d,v,G,d,v,R,v"))] 2504 "TARGET_DFP" 2505 "@ 2506 lzdr\t%0 2507 ldr\t%0,%1 2508 ldgr\t%0,%1 2509 lgdr\t%0,%1 2510 ld\t%0,%1 2511 ldy\t%0,%1 2512 std\t%1,%0 2513 stdy\t%1,%0 2514 lghi\t%0,0 2515 lgr\t%0,%1 2516 lgrl\t%0,%1 2517 lg\t%0,%1 2518 stgrl\t%1,%0 2519 stg\t%1,%0 2520 vlr\t%v0,%v1 2521 vleig\t%v0,0,0 2522 vlvgg\t%v0,%1,0 2523 vlgvg\t%0,%v1,0 2524 vleg\t%0,%1,0 2525 vsteg\t%1,%0,0" 2526 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRI,VRS,VRS,VRX,VRX") 2527 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, 2528 fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,*,load,store") 2529 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*,*") 2530 (set_attr "cpu_facility" "z196,*,*,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vx,vx,vx,vx,vx,vx")]) 2531 2532(define_insn "*mov<mode>_64" 2533 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,d,b,T") 2534 (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,T,d,d"))] 2535 "TARGET_ZARCH" 2536 "@ 2537 lzdr\t%0 2538 ldr\t%0,%1 2539 ld\t%0,%1 2540 ldy\t%0,%1 2541 std\t%1,%0 2542 stdy\t%1,%0 2543 lghi\t%0,0 2544 lgr\t%0,%1 2545 lgrl\t%0,%1 2546 lg\t%0,%1 2547 stgrl\t%1,%0 2548 stg\t%1,%0" 2549 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY") 2550 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, 2551 fstore<mode>,fstore<mode>,*,lr,load,load,store,store") 2552 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") 2553 (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*")]) 2554 2555(define_insn "*mov<mode>_31" 2556 [(set (match_operand:DD_DF 0 "nonimmediate_operand" 2557 "=f,f,f,f,R,T,d,d,Q,S, d,o") 2558 (match_operand:DD_DF 1 "general_operand" 2559 " G,f,R,T,f,f,Q,S,d,d,dPT,d"))] 2560 "!TARGET_ZARCH" 2561 "@ 2562 lzdr\t%0 2563 ldr\t%0,%1 2564 ld\t%0,%1 2565 ldy\t%0,%1 2566 std\t%1,%0 2567 stdy\t%1,%0 2568 lm\t%0,%N0,%S1 2569 lmy\t%0,%N0,%S1 2570 stm\t%1,%N1,%S0 2571 stmy\t%1,%N1,%S0 2572 # 2573 #" 2574 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") 2575 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, 2576 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*") 2577 (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,longdisp,*,longdisp,*,*")]) 2578 2579(define_split 2580 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") 2581 (match_operand:DD_DF 1 "general_operand" ""))] 2582 "!TARGET_ZARCH && reload_completed 2583 && !s_operand (operands[0], <MODE>mode) 2584 && !s_operand (operands[1], <MODE>mode) 2585 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" 2586 [(set (match_dup 2) (match_dup 4)) 2587 (set (match_dup 3) (match_dup 5))] 2588{ 2589 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); 2590 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); 2591 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); 2592 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); 2593}) 2594 2595(define_split 2596 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") 2597 (match_operand:DD_DF 1 "general_operand" ""))] 2598 "!TARGET_ZARCH && reload_completed 2599 && !s_operand (operands[0], <MODE>mode) 2600 && !s_operand (operands[1], <MODE>mode) 2601 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" 2602 [(set (match_dup 2) (match_dup 4)) 2603 (set (match_dup 3) (match_dup 5))] 2604{ 2605 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); 2606 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); 2607 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); 2608 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); 2609}) 2610 2611(define_split 2612 [(set (match_operand:DD_DF 0 "register_operand" "") 2613 (match_operand:DD_DF 1 "memory_operand" ""))] 2614 "!TARGET_ZARCH && reload_completed 2615 && !FP_REG_P (operands[0]) 2616 && !s_operand (operands[1], VOIDmode)" 2617 [(set (match_dup 0) (match_dup 1))] 2618{ 2619 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); 2620 s390_load_address (addr, XEXP (operands[1], 0)); 2621 operands[1] = replace_equiv_address (operands[1], addr); 2622}) 2623 2624; 2625; mov(sf|sd) instruction pattern(s). 2626; 2627 2628(define_insn "mov<mode>" 2629 [(set (match_operand:SD_SF 0 "nonimmediate_operand" 2630 "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,R") 2631 (match_operand:SD_SF 1 "general_operand" 2632 " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,R,v"))] 2633 "" 2634 "@ 2635 lzer\t%0 2636 ldr\t%0,%1 2637 ler\t%0,%1 2638 lde\t%0,%1 2639 le\t%0,%1 2640 ley\t%0,%1 2641 ste\t%1,%0 2642 stey\t%1,%0 2643 lhi\t%0,0 2644 lr\t%0,%1 2645 lrl\t%0,%1 2646 l\t%0,%1 2647 ly\t%0,%1 2648 strl\t%1,%0 2649 st\t%1,%0 2650 sty\t%1,%0 2651 vlr\t%v0,%v1 2652 vleif\t%v0,0,0 2653 vlvgf\t%v0,%1,0 2654 vlgvf\t%0,%v1,0 2655 vlef\t%0,%1,0 2656 vstef\t%1,%0,0" 2657 [(set_attr "op_type" "RRE,RR,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX") 2658 (set_attr "type" "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>, 2659 fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store") 2660 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*") 2661 (set_attr "cpu_facility" "z196,vx,*,vx,*,longdisp,*,longdisp,*,*,z10,*,longdisp,z10,*,longdisp,vx,vx,vx,vx,vx,vx")]) 2662 2663; 2664; movcc instruction pattern 2665; 2666 2667(define_insn "movcc" 2668 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") 2669 (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))] 2670 "" 2671 "@ 2672 lr\t%0,%1 2673 tmh\t%1,12288 2674 ipm\t%0 2675 l\t%0,%1 2676 ly\t%0,%1 2677 st\t%1,%0 2678 sty\t%1,%0" 2679 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") 2680 (set_attr "type" "lr,*,*,load,load,store,store") 2681 (set_attr "cpu_facility" "*,*,*,*,longdisp,*,longdisp") 2682 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") 2683 (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")]) 2684 2685; 2686; Block move (MVC) patterns. 2687; 2688 2689(define_insn "*mvc" 2690 [(set (match_operand:BLK 0 "memory_operand" "=Q") 2691 (match_operand:BLK 1 "memory_operand" "Q")) 2692 (use (match_operand 2 "const_int_operand" "n"))] 2693 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" 2694 "mvc\t%O0(%2,%R0),%S1" 2695 [(set_attr "op_type" "SS")]) 2696 2697; This splitter converts a QI to QI mode copy into a BLK mode copy in 2698; order to have it implemented with mvc. 2699 2700(define_split 2701 [(set (match_operand:QI 0 "memory_operand" "") 2702 (match_operand:QI 1 "memory_operand" ""))] 2703 "reload_completed" 2704 [(parallel 2705 [(set (match_dup 0) (match_dup 1)) 2706 (use (const_int 1))])] 2707{ 2708 operands[0] = adjust_address (operands[0], BLKmode, 0); 2709 operands[1] = adjust_address (operands[1], BLKmode, 0); 2710}) 2711 2712 2713(define_peephole2 2714 [(parallel 2715 [(set (match_operand:BLK 0 "memory_operand" "") 2716 (match_operand:BLK 1 "memory_operand" "")) 2717 (use (match_operand 2 "const_int_operand" ""))]) 2718 (parallel 2719 [(set (match_operand:BLK 3 "memory_operand" "") 2720 (match_operand:BLK 4 "memory_operand" "")) 2721 (use (match_operand 5 "const_int_operand" ""))])] 2722 "((INTVAL (operands[2]) > 16 && INTVAL (operands[5]) > 16) 2723 || (INTVAL (operands[2]) + INTVAL (operands[5]) <= 16)) 2724 && s390_offset_p (operands[0], operands[3], operands[2]) 2725 && s390_offset_p (operands[1], operands[4], operands[2]) 2726 && !s390_overlap_p (operands[0], operands[1], 2727 INTVAL (operands[2]) + INTVAL (operands[5])) 2728 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" 2729 [(parallel 2730 [(set (match_dup 6) (match_dup 7)) 2731 (use (match_dup 8))])] 2732 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); 2733 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); 2734 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") 2735 2736(define_peephole2 2737 [(parallel 2738 [(set (match_operand:BLK 0 "plus16_Q_operand" "") 2739 (match_operand:BLK 1 "plus16_Q_operand" "")) 2740 (use (match_operand 2 "const_int_operand" ""))])] 2741 "INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32" 2742 [(parallel 2743 [(set (match_dup 0) (match_dup 1)) 2744 (use (const_int 16))]) 2745 (parallel 2746 [(set (match_dup 3) (match_dup 4)) 2747 (use (match_dup 5))])] 2748 "operands[3] = change_address (operands[0], VOIDmode, 2749 plus_constant (Pmode, XEXP (operands[0], 0), 16)); 2750 operands[4] = change_address (operands[1], VOIDmode, 2751 plus_constant (Pmode, XEXP (operands[1], 0), 16)); 2752 operands[5] = GEN_INT (INTVAL (operands[2]) - 16);") 2753 2754 2755; 2756; load_multiple pattern(s). 2757; 2758; ??? Due to reload problems with replacing registers inside match_parallel 2759; we currently support load_multiple/store_multiple only after reload. 2760; 2761 2762(define_expand "load_multiple" 2763 [(match_par_dup 3 [(set (match_operand 0 "" "") 2764 (match_operand 1 "" "")) 2765 (use (match_operand 2 "" ""))])] 2766 "reload_completed" 2767{ 2768 machine_mode mode; 2769 int regno; 2770 int count; 2771 rtx from; 2772 int i, off; 2773 2774 /* Support only loading a constant number of fixed-point registers from 2775 memory and only bother with this if more than two */ 2776 if (GET_CODE (operands[2]) != CONST_INT 2777 || INTVAL (operands[2]) < 2 2778 || INTVAL (operands[2]) > 16 2779 || GET_CODE (operands[1]) != MEM 2780 || GET_CODE (operands[0]) != REG 2781 || REGNO (operands[0]) >= 16) 2782 FAIL; 2783 2784 count = INTVAL (operands[2]); 2785 regno = REGNO (operands[0]); 2786 mode = GET_MODE (operands[0]); 2787 if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) 2788 FAIL; 2789 2790 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); 2791 if (!can_create_pseudo_p ()) 2792 { 2793 if (GET_CODE (XEXP (operands[1], 0)) == REG) 2794 { 2795 from = XEXP (operands[1], 0); 2796 off = 0; 2797 } 2798 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS 2799 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG 2800 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) 2801 { 2802 from = XEXP (XEXP (operands[1], 0), 0); 2803 off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); 2804 } 2805 else 2806 FAIL; 2807 } 2808 else 2809 { 2810 from = force_reg (Pmode, XEXP (operands[1], 0)); 2811 off = 0; 2812 } 2813 2814 for (i = 0; i < count; i++) 2815 XVECEXP (operands[3], 0, i) 2816 = gen_rtx_SET (gen_rtx_REG (mode, regno + i), 2817 change_address (operands[1], mode, 2818 plus_constant (Pmode, from, 2819 off + i * GET_MODE_SIZE (mode)))); 2820}) 2821 2822(define_insn "*load_multiple_di" 2823 [(match_parallel 0 "load_multiple_operation" 2824 [(set (match_operand:DI 1 "register_operand" "=r") 2825 (match_operand:DI 2 "s_operand" "S"))])] 2826 "reload_completed && TARGET_ZARCH" 2827{ 2828 int words = XVECLEN (operands[0], 0); 2829 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); 2830 return "lmg\t%1,%0,%S2"; 2831} 2832 [(set_attr "op_type" "RSY") 2833 (set_attr "type" "lm")]) 2834 2835(define_insn "*load_multiple_si" 2836 [(match_parallel 0 "load_multiple_operation" 2837 [(set (match_operand:SI 1 "register_operand" "=r,r") 2838 (match_operand:SI 2 "s_operand" "Q,S"))])] 2839 "reload_completed" 2840{ 2841 int words = XVECLEN (operands[0], 0); 2842 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); 2843 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; 2844} 2845 [(set_attr "op_type" "RS,RSY") 2846 (set_attr "cpu_facility" "*,longdisp") 2847 (set_attr "type" "lm")]) 2848 2849; 2850; store multiple pattern(s). 2851; 2852 2853(define_expand "store_multiple" 2854 [(match_par_dup 3 [(set (match_operand 0 "" "") 2855 (match_operand 1 "" "")) 2856 (use (match_operand 2 "" ""))])] 2857 "reload_completed" 2858{ 2859 machine_mode mode; 2860 int regno; 2861 int count; 2862 rtx to; 2863 int i, off; 2864 2865 /* Support only storing a constant number of fixed-point registers to 2866 memory and only bother with this if more than two. */ 2867 if (GET_CODE (operands[2]) != CONST_INT 2868 || INTVAL (operands[2]) < 2 2869 || INTVAL (operands[2]) > 16 2870 || GET_CODE (operands[0]) != MEM 2871 || GET_CODE (operands[1]) != REG 2872 || REGNO (operands[1]) >= 16) 2873 FAIL; 2874 2875 count = INTVAL (operands[2]); 2876 regno = REGNO (operands[1]); 2877 mode = GET_MODE (operands[1]); 2878 if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) 2879 FAIL; 2880 2881 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); 2882 2883 if (!can_create_pseudo_p ()) 2884 { 2885 if (GET_CODE (XEXP (operands[0], 0)) == REG) 2886 { 2887 to = XEXP (operands[0], 0); 2888 off = 0; 2889 } 2890 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS 2891 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG 2892 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) 2893 { 2894 to = XEXP (XEXP (operands[0], 0), 0); 2895 off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); 2896 } 2897 else 2898 FAIL; 2899 } 2900 else 2901 { 2902 to = force_reg (Pmode, XEXP (operands[0], 0)); 2903 off = 0; 2904 } 2905 2906 for (i = 0; i < count; i++) 2907 XVECEXP (operands[3], 0, i) 2908 = gen_rtx_SET (change_address (operands[0], mode, 2909 plus_constant (Pmode, to, 2910 off + i * GET_MODE_SIZE (mode))), 2911 gen_rtx_REG (mode, regno + i)); 2912}) 2913 2914(define_insn "*store_multiple_di" 2915 [(match_parallel 0 "store_multiple_operation" 2916 [(set (match_operand:DI 1 "s_operand" "=S") 2917 (match_operand:DI 2 "register_operand" "r"))])] 2918 "reload_completed && TARGET_ZARCH" 2919{ 2920 int words = XVECLEN (operands[0], 0); 2921 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); 2922 return "stmg\t%2,%0,%S1"; 2923} 2924 [(set_attr "op_type" "RSY") 2925 (set_attr "type" "stm")]) 2926 2927 2928(define_insn "*store_multiple_si" 2929 [(match_parallel 0 "store_multiple_operation" 2930 [(set (match_operand:SI 1 "s_operand" "=Q,S") 2931 (match_operand:SI 2 "register_operand" "r,r"))])] 2932 "reload_completed" 2933{ 2934 int words = XVECLEN (operands[0], 0); 2935 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); 2936 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; 2937} 2938 [(set_attr "op_type" "RS,RSY") 2939 (set_attr "cpu_facility" "*,longdisp") 2940 (set_attr "type" "stm")]) 2941 2942;; 2943;; String instructions. 2944;; 2945 2946(define_insn "*execute_rl" 2947 [(match_parallel 0 "execute_operation" 2948 [(unspec [(match_operand 1 "register_operand" "a") 2949 (match_operand 2 "" "") 2950 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])] 2951 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT 2952 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" 2953 "exrl\t%1,%3" 2954 [(set_attr "op_type" "RIL") 2955 (set_attr "type" "cs")]) 2956 2957(define_insn "*execute" 2958 [(match_parallel 0 "execute_operation" 2959 [(unspec [(match_operand 1 "register_operand" "a") 2960 (match_operand:BLK 2 "memory_operand" "R") 2961 (match_operand 3 "" "")] UNSPEC_EXECUTE)])] 2962 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT 2963 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" 2964 "ex\t%1,%2" 2965 [(set_attr "op_type" "RX") 2966 (set_attr "type" "cs")]) 2967 2968 2969; 2970; strlenM instruction pattern(s). 2971; 2972 2973(define_expand "strlen<mode>" 2974 [(match_operand:P 0 "register_operand" "") ; result 2975 (match_operand:BLK 1 "memory_operand" "") ; input string 2976 (match_operand:SI 2 "immediate_operand" "") ; search character 2977 (match_operand:SI 3 "immediate_operand" "")] ; known alignment 2978 "" 2979{ 2980 if (!TARGET_VX || operands[2] != const0_rtx) 2981 emit_insn (gen_strlen_srst<mode> (operands[0], operands[1], 2982 operands[2], operands[3])); 2983 else 2984 s390_expand_vec_strlen (operands[0], operands[1], operands[3]); 2985 2986 DONE; 2987}) 2988 2989(define_expand "strlen_srst<mode>" 2990 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) 2991 (parallel 2992 [(set (match_dup 4) 2993 (unspec:P [(const_int 0) 2994 (match_operand:BLK 1 "memory_operand" "") 2995 (reg:SI 0) 2996 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) 2997 (clobber (scratch:P)) 2998 (clobber (reg:CC CC_REGNUM))]) 2999 (parallel 3000 [(set (match_operand:P 0 "register_operand" "") 3001 (minus:P (match_dup 4) (match_dup 5))) 3002 (clobber (reg:CC CC_REGNUM))])] 3003 "" 3004{ 3005 operands[4] = gen_reg_rtx (Pmode); 3006 operands[5] = gen_reg_rtx (Pmode); 3007 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); 3008 operands[1] = replace_equiv_address (operands[1], operands[5]); 3009}) 3010 3011(define_insn "*strlen<mode>" 3012 [(set (match_operand:P 0 "register_operand" "=a") 3013 (unspec:P [(match_operand:P 2 "general_operand" "0") 3014 (mem:BLK (match_operand:P 3 "register_operand" "1")) 3015 (reg:SI 0) 3016 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) 3017 (clobber (match_scratch:P 1 "=a")) 3018 (clobber (reg:CC CC_REGNUM))] 3019 "" 3020 "srst\t%0,%1\;jo\t.-4" 3021 [(set_attr "length" "8") 3022 (set_attr "type" "vs")]) 3023 3024; 3025; cmpstrM instruction pattern(s). 3026; 3027 3028(define_expand "cmpstrsi" 3029 [(set (reg:SI 0) (const_int 0)) 3030 (parallel 3031 [(clobber (match_operand 3 "" "")) 3032 (clobber (match_dup 4)) 3033 (set (reg:CCU CC_REGNUM) 3034 (compare:CCU (match_operand:BLK 1 "memory_operand" "") 3035 (match_operand:BLK 2 "memory_operand" ""))) 3036 (use (reg:SI 0))]) 3037 (parallel 3038 [(set (match_operand:SI 0 "register_operand" "=d") 3039 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT)) 3040 (clobber (reg:CC CC_REGNUM))])] 3041 "" 3042{ 3043 /* As the result of CMPINT is inverted compared to what we need, 3044 we have to swap the operands. */ 3045 rtx op1 = operands[2]; 3046 rtx op2 = operands[1]; 3047 rtx addr1 = gen_reg_rtx (Pmode); 3048 rtx addr2 = gen_reg_rtx (Pmode); 3049 3050 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); 3051 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX)); 3052 operands[1] = replace_equiv_address_nv (op1, addr1); 3053 operands[2] = replace_equiv_address_nv (op2, addr2); 3054 operands[3] = addr1; 3055 operands[4] = addr2; 3056}) 3057 3058(define_insn "*cmpstr<mode>" 3059 [(clobber (match_operand:P 0 "register_operand" "=d")) 3060 (clobber (match_operand:P 1 "register_operand" "=d")) 3061 (set (reg:CCU CC_REGNUM) 3062 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) 3063 (mem:BLK (match_operand:P 3 "register_operand" "1")))) 3064 (use (reg:SI 0))] 3065 "" 3066 "clst\t%0,%1\;jo\t.-4" 3067 [(set_attr "length" "8") 3068 (set_attr "type" "vs")]) 3069 3070; 3071; movstr instruction pattern. 3072; 3073 3074(define_expand "movstr" 3075 [(match_operand 0 "register_operand" "") 3076 (match_operand 1 "memory_operand" "") 3077 (match_operand 2 "memory_operand" "")] 3078 "" 3079{ 3080 if (TARGET_64BIT) 3081 emit_insn (gen_movstrdi (operands[0], operands[1], operands[2])); 3082 else 3083 emit_insn (gen_movstrsi (operands[0], operands[1], operands[2])); 3084 DONE; 3085}) 3086 3087(define_expand "movstr<P:mode>" 3088 [(set (reg:SI 0) (const_int 0)) 3089 (parallel 3090 [(clobber (match_dup 3)) 3091 (set (match_operand:BLK 1 "memory_operand" "") 3092 (match_operand:BLK 2 "memory_operand" "")) 3093 (set (match_operand:P 0 "register_operand" "") 3094 (unspec:P [(match_dup 1) 3095 (match_dup 2) 3096 (reg:SI 0)] UNSPEC_MVST)) 3097 (clobber (reg:CC CC_REGNUM))])] 3098 "" 3099{ 3100 rtx addr1, addr2; 3101 3102 if (TARGET_VX && optimize_function_for_speed_p (cfun)) 3103 { 3104 s390_expand_vec_movstr (operands[0], operands[1], operands[2]); 3105 DONE; 3106 } 3107 3108 addr1 = gen_reg_rtx (Pmode); 3109 addr2 = gen_reg_rtx (Pmode); 3110 3111 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); 3112 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX)); 3113 operands[1] = replace_equiv_address_nv (operands[1], addr1); 3114 operands[2] = replace_equiv_address_nv (operands[2], addr2); 3115 operands[3] = addr2; 3116}) 3117 3118(define_insn "*movstr" 3119 [(clobber (match_operand:P 2 "register_operand" "=d")) 3120 (set (mem:BLK (match_operand:P 1 "register_operand" "0")) 3121 (mem:BLK (match_operand:P 3 "register_operand" "2"))) 3122 (set (match_operand:P 0 "register_operand" "=d") 3123 (unspec:P [(mem:BLK (match_dup 1)) 3124 (mem:BLK (match_dup 3)) 3125 (reg:SI 0)] UNSPEC_MVST)) 3126 (clobber (reg:CC CC_REGNUM))] 3127 "" 3128 "mvst\t%1,%2\;jo\t.-4" 3129 [(set_attr "length" "8") 3130 (set_attr "type" "vs")]) 3131 3132 3133; 3134; movmemM instruction pattern(s). 3135; 3136 3137(define_expand "movmem<mode>" 3138 [(set (match_operand:BLK 0 "memory_operand" "") ; destination 3139 (match_operand:BLK 1 "memory_operand" "")) ; source 3140 (use (match_operand:GPR 2 "general_operand" "")) ; count 3141 (match_operand 3 "" "")] 3142 "" 3143{ 3144 if (s390_expand_movmem (operands[0], operands[1], operands[2])) 3145 DONE; 3146 else 3147 FAIL; 3148}) 3149 3150; Move a block that is up to 256 bytes in length. 3151; The block length is taken as (operands[2] % 256) + 1. 3152 3153(define_expand "movmem_short" 3154 [(parallel 3155 [(set (match_operand:BLK 0 "memory_operand" "") 3156 (match_operand:BLK 1 "memory_operand" "")) 3157 (use (match_operand 2 "nonmemory_operand" "")) 3158 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) 3159 (clobber (match_dup 3))])] 3160 "" 3161 "operands[3] = gen_rtx_SCRATCH (Pmode);") 3162 3163(define_insn "*movmem_short" 3164 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") 3165 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")) 3166 (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) 3167 (use (match_operand 3 "immediate_operand" "X,R,X,X")) 3168 (clobber (match_scratch:P 4 "=X,X,X,&a"))] 3169 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" 3170 "#" 3171 [(set_attr "type" "cs") 3172 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) 3173 3174(define_split 3175 [(set (match_operand:BLK 0 "memory_operand" "") 3176 (match_operand:BLK 1 "memory_operand" "")) 3177 (use (match_operand 2 "const_int_operand" "")) 3178 (use (match_operand 3 "immediate_operand" "")) 3179 (clobber (scratch))] 3180 "reload_completed" 3181 [(parallel 3182 [(set (match_dup 0) (match_dup 1)) 3183 (use (match_dup 2))])] 3184 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") 3185 3186(define_split 3187 [(set (match_operand:BLK 0 "memory_operand" "") 3188 (match_operand:BLK 1 "memory_operand" "")) 3189 (use (match_operand 2 "register_operand" "")) 3190 (use (match_operand 3 "memory_operand" "")) 3191 (clobber (scratch))] 3192 "reload_completed" 3193 [(parallel 3194 [(unspec [(match_dup 2) (match_dup 3) 3195 (const_int 0)] UNSPEC_EXECUTE) 3196 (set (match_dup 0) (match_dup 1)) 3197 (use (const_int 1))])] 3198 "") 3199 3200(define_split 3201 [(set (match_operand:BLK 0 "memory_operand" "") 3202 (match_operand:BLK 1 "memory_operand" "")) 3203 (use (match_operand 2 "register_operand" "")) 3204 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) 3205 (clobber (scratch))] 3206 "TARGET_Z10 && reload_completed" 3207 [(parallel 3208 [(unspec [(match_dup 2) (const_int 0) 3209 (label_ref (match_dup 3))] UNSPEC_EXECUTE) 3210 (set (match_dup 0) (match_dup 1)) 3211 (use (const_int 1))])] 3212 "operands[3] = gen_label_rtx ();") 3213 3214(define_split 3215 [(set (match_operand:BLK 0 "memory_operand" "") 3216 (match_operand:BLK 1 "memory_operand" "")) 3217 (use (match_operand 2 "register_operand" "")) 3218 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) 3219 (clobber (match_operand 3 "register_operand" ""))] 3220 "reload_completed && TARGET_CPU_ZARCH" 3221 [(set (match_dup 3) (label_ref (match_dup 4))) 3222 (parallel 3223 [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) 3224 (label_ref (match_dup 4))] UNSPEC_EXECUTE) 3225 (set (match_dup 0) (match_dup 1)) 3226 (use (const_int 1))])] 3227 "operands[4] = gen_label_rtx ();") 3228 3229; Move a block of arbitrary length. 3230 3231(define_expand "movmem_long" 3232 [(parallel 3233 [(clobber (match_dup 2)) 3234 (clobber (match_dup 3)) 3235 (set (match_operand:BLK 0 "memory_operand" "") 3236 (match_operand:BLK 1 "memory_operand" "")) 3237 (use (match_operand 2 "general_operand" "")) 3238 (use (match_dup 3)) 3239 (clobber (reg:CC CC_REGNUM))])] 3240 "" 3241{ 3242 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; 3243 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; 3244 rtx reg0 = gen_reg_rtx (dreg_mode); 3245 rtx reg1 = gen_reg_rtx (dreg_mode); 3246 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); 3247 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); 3248 rtx len0 = gen_lowpart (Pmode, reg0); 3249 rtx len1 = gen_lowpart (Pmode, reg1); 3250 3251 emit_clobber (reg0); 3252 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); 3253 emit_move_insn (len0, operands[2]); 3254 3255 emit_clobber (reg1); 3256 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); 3257 emit_move_insn (len1, operands[2]); 3258 3259 operands[0] = replace_equiv_address_nv (operands[0], addr0); 3260 operands[1] = replace_equiv_address_nv (operands[1], addr1); 3261 operands[2] = reg0; 3262 operands[3] = reg1; 3263}) 3264 3265(define_insn "*movmem_long" 3266 [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) 3267 (clobber (match_operand:<DBL> 1 "register_operand" "=d")) 3268 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) 3269 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) 3270 (use (match_dup 2)) 3271 (use (match_dup 3)) 3272 (clobber (reg:CC CC_REGNUM))] 3273 "TARGET_64BIT || !TARGET_ZARCH" 3274 "mvcle\t%0,%1,0\;jo\t.-4" 3275 [(set_attr "length" "8") 3276 (set_attr "type" "vs")]) 3277 3278(define_insn "*movmem_long_31z" 3279 [(clobber (match_operand:TI 0 "register_operand" "=d")) 3280 (clobber (match_operand:TI 1 "register_operand" "=d")) 3281 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) 3282 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))) 3283 (use (match_dup 2)) 3284 (use (match_dup 3)) 3285 (clobber (reg:CC CC_REGNUM))] 3286 "!TARGET_64BIT && TARGET_ZARCH" 3287 "mvcle\t%0,%1,0\;jo\t.-4" 3288 [(set_attr "length" "8") 3289 (set_attr "type" "vs")]) 3290 3291 3292; 3293; Test data class. 3294; 3295 3296(define_expand "signbit<mode>2" 3297 [(set (reg:CCZ CC_REGNUM) 3298 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") 3299 (match_dup 2)] 3300 UNSPEC_TDC_INSN)) 3301 (set (match_operand:SI 0 "register_operand" "=d") 3302 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] 3303 "TARGET_HARD_FLOAT" 3304{ 3305 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET); 3306}) 3307 3308(define_expand "isinf<mode>2" 3309 [(set (reg:CCZ CC_REGNUM) 3310 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") 3311 (match_dup 2)] 3312 UNSPEC_TDC_INSN)) 3313 (set (match_operand:SI 0 "register_operand" "=d") 3314 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] 3315 "TARGET_HARD_FLOAT" 3316{ 3317 operands[2] = GEN_INT (S390_TDC_INFINITY); 3318}) 3319 3320; This extracts CC into a GPR properly shifted. The actual IPM 3321; instruction will be issued by reload. The constraint of operand 1 3322; forces reload to use a GPR. So reload will issue a movcc insn for 3323; copying CC into a GPR first. 3324(define_insn_and_split "*cc_to_int" 3325 [(set (match_operand:SI 0 "nonimmediate_operand" "=d") 3326 (unspec:SI [(match_operand 1 "register_operand" "0")] 3327 UNSPEC_CC_TO_INT))] 3328 "operands != NULL" 3329 "#" 3330 "reload_completed" 3331 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))]) 3332 3333; This insn is used to generate all variants of the Test Data Class 3334; instruction, namely tcxb, tcdb, and tceb. The insn's first operand 3335; is the register to be tested and the second one is the bit mask 3336; specifying the required test(s). 3337; 3338; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet 3339(define_insn "*TDC_insn_<mode>" 3340 [(set (reg:CCZ CC_REGNUM) 3341 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") 3342 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))] 3343 "TARGET_HARD_FLOAT" 3344 "t<_d>c<xde><bt>\t%0,%1" 3345 [(set_attr "op_type" "RXE") 3346 (set_attr "type" "fsimp<mode>")]) 3347 3348 3349 3350; 3351; setmemM instruction pattern(s). 3352; 3353 3354(define_expand "setmem<mode>" 3355 [(set (match_operand:BLK 0 "memory_operand" "") 3356 (match_operand:QI 2 "general_operand" "")) 3357 (use (match_operand:GPR 1 "general_operand" "")) 3358 (match_operand 3 "" "")] 3359 "" 3360 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") 3361 3362; Clear a block that is up to 256 bytes in length. 3363; The block length is taken as (operands[1] % 256) + 1. 3364 3365(define_expand "clrmem_short" 3366 [(parallel 3367 [(set (match_operand:BLK 0 "memory_operand" "") 3368 (const_int 0)) 3369 (use (match_operand 1 "nonmemory_operand" "")) 3370 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) 3371 (clobber (match_dup 2)) 3372 (clobber (reg:CC CC_REGNUM))])] 3373 "" 3374 "operands[2] = gen_rtx_SCRATCH (Pmode);") 3375 3376(define_insn "*clrmem_short" 3377 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") 3378 (const_int 0)) 3379 (use (match_operand 1 "nonmemory_operand" "n,a,a,a")) 3380 (use (match_operand 2 "immediate_operand" "X,R,X,X")) 3381 (clobber (match_scratch:P 3 "=X,X,X,&a")) 3382 (clobber (reg:CC CC_REGNUM))] 3383 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)" 3384 "#" 3385 [(set_attr "type" "cs") 3386 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) 3387 3388(define_split 3389 [(set (match_operand:BLK 0 "memory_operand" "") 3390 (const_int 0)) 3391 (use (match_operand 1 "const_int_operand" "")) 3392 (use (match_operand 2 "immediate_operand" "")) 3393 (clobber (scratch)) 3394 (clobber (reg:CC CC_REGNUM))] 3395 "reload_completed" 3396 [(parallel 3397 [(set (match_dup 0) (const_int 0)) 3398 (use (match_dup 1)) 3399 (clobber (reg:CC CC_REGNUM))])] 3400 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") 3401 3402(define_split 3403 [(set (match_operand:BLK 0 "memory_operand" "") 3404 (const_int 0)) 3405 (use (match_operand 1 "register_operand" "")) 3406 (use (match_operand 2 "memory_operand" "")) 3407 (clobber (scratch)) 3408 (clobber (reg:CC CC_REGNUM))] 3409 "reload_completed" 3410 [(parallel 3411 [(unspec [(match_dup 1) (match_dup 2) 3412 (const_int 0)] UNSPEC_EXECUTE) 3413 (set (match_dup 0) (const_int 0)) 3414 (use (const_int 1)) 3415 (clobber (reg:CC CC_REGNUM))])] 3416 "") 3417 3418(define_split 3419 [(set (match_operand:BLK 0 "memory_operand" "") 3420 (const_int 0)) 3421 (use (match_operand 1 "register_operand" "")) 3422 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) 3423 (clobber (scratch)) 3424 (clobber (reg:CC CC_REGNUM))] 3425 "TARGET_Z10 && reload_completed" 3426 [(parallel 3427 [(unspec [(match_dup 1) (const_int 0) 3428 (label_ref (match_dup 3))] UNSPEC_EXECUTE) 3429 (set (match_dup 0) (const_int 0)) 3430 (use (const_int 1)) 3431 (clobber (reg:CC CC_REGNUM))])] 3432 "operands[3] = gen_label_rtx ();") 3433 3434(define_split 3435 [(set (match_operand:BLK 0 "memory_operand" "") 3436 (const_int 0)) 3437 (use (match_operand 1 "register_operand" "")) 3438 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) 3439 (clobber (match_operand 2 "register_operand" "")) 3440 (clobber (reg:CC CC_REGNUM))] 3441 "reload_completed && TARGET_CPU_ZARCH" 3442 [(set (match_dup 2) (label_ref (match_dup 3))) 3443 (parallel 3444 [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) 3445 (label_ref (match_dup 3))] UNSPEC_EXECUTE) 3446 (set (match_dup 0) (const_int 0)) 3447 (use (const_int 1)) 3448 (clobber (reg:CC CC_REGNUM))])] 3449 "operands[3] = gen_label_rtx ();") 3450 3451; Initialize a block of arbitrary length with (operands[2] % 256). 3452 3453(define_expand "setmem_long_<P:mode>" 3454 [(parallel 3455 [(clobber (match_dup 1)) 3456 (set (match_operand:BLK 0 "memory_operand" "") 3457 (unspec:BLK [(match_operand:P 2 "setmem_operand" "") 3458 (match_dup 4)] UNSPEC_REPLICATE_BYTE)) 3459 (use (match_dup 3)) 3460 (clobber (reg:CC CC_REGNUM))])] 3461 "" 3462{ 3463 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; 3464 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; 3465 rtx reg0 = gen_reg_rtx (dreg_mode); 3466 rtx reg1 = gen_reg_rtx (dreg_mode); 3467 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); 3468 rtx len0 = gen_lowpart (Pmode, reg0); 3469 3470 emit_clobber (reg0); 3471 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); 3472 emit_move_insn (len0, operands[1]); 3473 3474 emit_move_insn (reg1, const0_rtx); 3475 3476 operands[0] = replace_equiv_address_nv (operands[0], addr0); 3477 operands[1] = reg0; 3478 operands[3] = reg1; 3479 operands[4] = gen_lowpart (Pmode, operands[1]); 3480}) 3481 3482; Patterns for 31 bit + Esa and 64 bit + Zarch. 3483 3484(define_insn "*setmem_long" 3485 [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) 3486 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) 3487 (unspec:BLK [(match_operand:P 2 "setmem_operand" "Y") 3488 (subreg:P (match_dup 3) <modesize>)] 3489 UNSPEC_REPLICATE_BYTE)) 3490 (use (match_operand:<DBL> 1 "register_operand" "d")) 3491 (clobber (reg:CC CC_REGNUM))] 3492 "TARGET_64BIT || !TARGET_ZARCH" 3493 "mvcle\t%0,%1,%Y2\;jo\t.-4" 3494 [(set_attr "length" "8") 3495 (set_attr "type" "vs")]) 3496 3497(define_insn "*setmem_long_and" 3498 [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) 3499 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) 3500 (unspec:BLK [(zero_extend:P (match_operand:QI 2 "setmem_operand" "Y")) 3501 (subreg:P (match_dup 3) <modesize>)] 3502 UNSPEC_REPLICATE_BYTE)) 3503 (use (match_operand:<DBL> 1 "register_operand" "d")) 3504 (clobber (reg:CC CC_REGNUM))] 3505 "(TARGET_64BIT || !TARGET_ZARCH)" 3506 "mvcle\t%0,%1,%Y2\;jo\t.-4" 3507 [(set_attr "length" "8") 3508 (set_attr "type" "vs")]) 3509 3510; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets 3511; of the SImode subregs. 3512 3513(define_insn "*setmem_long_31z" 3514 [(clobber (match_operand:TI 0 "register_operand" "=d")) 3515 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) 3516 (unspec:BLK [(match_operand:SI 2 "setmem_operand" "Y") 3517 (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) 3518 (use (match_operand:TI 1 "register_operand" "d")) 3519 (clobber (reg:CC CC_REGNUM))] 3520 "!TARGET_64BIT && TARGET_ZARCH" 3521 "mvcle\t%0,%1,%Y2\;jo\t.-4" 3522 [(set_attr "length" "8") 3523 (set_attr "type" "vs")]) 3524 3525(define_insn "*setmem_long_and_31z" 3526 [(clobber (match_operand:TI 0 "register_operand" "=d")) 3527 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) 3528 (unspec:BLK [(zero_extend:SI (match_operand:QI 2 "setmem_operand" "Y")) 3529 (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) 3530 (use (match_operand:TI 1 "register_operand" "d")) 3531 (clobber (reg:CC CC_REGNUM))] 3532 "(!TARGET_64BIT && TARGET_ZARCH)" 3533 "mvcle\t%0,%1,%Y2\;jo\t.-4" 3534 [(set_attr "length" "8") 3535 (set_attr "type" "vs")]) 3536 3537; 3538; cmpmemM instruction pattern(s). 3539; 3540 3541(define_expand "cmpmemsi" 3542 [(set (match_operand:SI 0 "register_operand" "") 3543 (compare:SI (match_operand:BLK 1 "memory_operand" "") 3544 (match_operand:BLK 2 "memory_operand" "") ) ) 3545 (use (match_operand:SI 3 "general_operand" "")) 3546 (use (match_operand:SI 4 "" ""))] 3547 "" 3548{ 3549 if (s390_expand_cmpmem (operands[0], operands[1], 3550 operands[2], operands[3])) 3551 DONE; 3552 else 3553 FAIL; 3554}) 3555 3556; Compare a block that is up to 256 bytes in length. 3557; The block length is taken as (operands[2] % 256) + 1. 3558 3559(define_expand "cmpmem_short" 3560 [(parallel 3561 [(set (reg:CCU CC_REGNUM) 3562 (compare:CCU (match_operand:BLK 0 "memory_operand" "") 3563 (match_operand:BLK 1 "memory_operand" ""))) 3564 (use (match_operand 2 "nonmemory_operand" "")) 3565 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) 3566 (clobber (match_dup 3))])] 3567 "" 3568 "operands[3] = gen_rtx_SCRATCH (Pmode);") 3569 3570(define_insn "*cmpmem_short" 3571 [(set (reg:CCU CC_REGNUM) 3572 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q") 3573 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))) 3574 (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) 3575 (use (match_operand 3 "immediate_operand" "X,R,X,X")) 3576 (clobber (match_scratch:P 4 "=X,X,X,&a"))] 3577 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" 3578 "#" 3579 [(set_attr "type" "cs") 3580 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) 3581 3582(define_split 3583 [(set (reg:CCU CC_REGNUM) 3584 (compare:CCU (match_operand:BLK 0 "memory_operand" "") 3585 (match_operand:BLK 1 "memory_operand" ""))) 3586 (use (match_operand 2 "const_int_operand" "")) 3587 (use (match_operand 3 "immediate_operand" "")) 3588 (clobber (scratch))] 3589 "reload_completed" 3590 [(parallel 3591 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) 3592 (use (match_dup 2))])] 3593 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") 3594 3595(define_split 3596 [(set (reg:CCU CC_REGNUM) 3597 (compare:CCU (match_operand:BLK 0 "memory_operand" "") 3598 (match_operand:BLK 1 "memory_operand" ""))) 3599 (use (match_operand 2 "register_operand" "")) 3600 (use (match_operand 3 "memory_operand" "")) 3601 (clobber (scratch))] 3602 "reload_completed" 3603 [(parallel 3604 [(unspec [(match_dup 2) (match_dup 3) 3605 (const_int 0)] UNSPEC_EXECUTE) 3606 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) 3607 (use (const_int 1))])] 3608 "") 3609 3610(define_split 3611 [(set (reg:CCU CC_REGNUM) 3612 (compare:CCU (match_operand:BLK 0 "memory_operand" "") 3613 (match_operand:BLK 1 "memory_operand" ""))) 3614 (use (match_operand 2 "register_operand" "")) 3615 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) 3616 (clobber (scratch))] 3617 "TARGET_Z10 && reload_completed" 3618 [(parallel 3619 [(unspec [(match_dup 2) (const_int 0) 3620 (label_ref (match_dup 4))] UNSPEC_EXECUTE) 3621 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) 3622 (use (const_int 1))])] 3623 "operands[4] = gen_label_rtx ();") 3624 3625(define_split 3626 [(set (reg:CCU CC_REGNUM) 3627 (compare:CCU (match_operand:BLK 0 "memory_operand" "") 3628 (match_operand:BLK 1 "memory_operand" ""))) 3629 (use (match_operand 2 "register_operand" "")) 3630 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) 3631 (clobber (match_operand 3 "register_operand" ""))] 3632 "reload_completed && TARGET_CPU_ZARCH" 3633 [(set (match_dup 3) (label_ref (match_dup 4))) 3634 (parallel 3635 [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) 3636 (label_ref (match_dup 4))] UNSPEC_EXECUTE) 3637 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) 3638 (use (const_int 1))])] 3639 "operands[4] = gen_label_rtx ();") 3640 3641; Compare a block of arbitrary length. 3642 3643(define_expand "cmpmem_long" 3644 [(parallel 3645 [(clobber (match_dup 2)) 3646 (clobber (match_dup 3)) 3647 (set (reg:CCU CC_REGNUM) 3648 (compare:CCU (match_operand:BLK 0 "memory_operand" "") 3649 (match_operand:BLK 1 "memory_operand" ""))) 3650 (use (match_operand 2 "general_operand" "")) 3651 (use (match_dup 3))])] 3652 "" 3653{ 3654 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; 3655 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; 3656 rtx reg0 = gen_reg_rtx (dreg_mode); 3657 rtx reg1 = gen_reg_rtx (dreg_mode); 3658 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); 3659 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); 3660 rtx len0 = gen_lowpart (Pmode, reg0); 3661 rtx len1 = gen_lowpart (Pmode, reg1); 3662 3663 emit_clobber (reg0); 3664 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); 3665 emit_move_insn (len0, operands[2]); 3666 3667 emit_clobber (reg1); 3668 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); 3669 emit_move_insn (len1, operands[2]); 3670 3671 operands[0] = replace_equiv_address_nv (operands[0], addr0); 3672 operands[1] = replace_equiv_address_nv (operands[1], addr1); 3673 operands[2] = reg0; 3674 operands[3] = reg1; 3675}) 3676 3677(define_insn "*cmpmem_long" 3678 [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) 3679 (clobber (match_operand:<DBL> 1 "register_operand" "=d")) 3680 (set (reg:CCU CC_REGNUM) 3681 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) 3682 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) 3683 (use (match_dup 2)) 3684 (use (match_dup 3))] 3685 "TARGET_64BIT || !TARGET_ZARCH" 3686 "clcle\t%0,%1,0\;jo\t.-4" 3687 [(set_attr "length" "8") 3688 (set_attr "type" "vs")]) 3689 3690(define_insn "*cmpmem_long_31z" 3691 [(clobber (match_operand:TI 0 "register_operand" "=d")) 3692 (clobber (match_operand:TI 1 "register_operand" "=d")) 3693 (set (reg:CCU CC_REGNUM) 3694 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) 3695 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))) 3696 (use (match_dup 2)) 3697 (use (match_dup 3))] 3698 "!TARGET_64BIT && TARGET_ZARCH" 3699 "clcle\t%0,%1,0\;jo\t.-4" 3700 [(set_attr "op_type" "NN") 3701 (set_attr "type" "vs") 3702 (set_attr "length" "8")]) 3703 3704; Convert CCUmode condition code to integer. 3705; Result is zero if EQ, positive if LTU, negative if GTU. 3706 3707(define_insn_and_split "cmpint" 3708 [(set (match_operand:SI 0 "register_operand" "=d") 3709 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] 3710 UNSPEC_STRCMPCC_TO_INT)) 3711 (clobber (reg:CC CC_REGNUM))] 3712 "" 3713 "#" 3714 "reload_completed" 3715 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) 3716 (parallel 3717 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) 3718 (clobber (reg:CC CC_REGNUM))])]) 3719 3720(define_insn_and_split "*cmpint_cc" 3721 [(set (reg CC_REGNUM) 3722 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] 3723 UNSPEC_STRCMPCC_TO_INT) 3724 (const_int 0))) 3725 (set (match_operand:SI 0 "register_operand" "=d") 3726 (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))] 3727 "s390_match_ccmode (insn, CCSmode)" 3728 "#" 3729 "&& reload_completed" 3730 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) 3731 (parallel 3732 [(set (match_dup 2) (match_dup 3)) 3733 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] 3734{ 3735 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); 3736 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); 3737 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); 3738}) 3739 3740(define_insn_and_split "*cmpint_sign" 3741 [(set (match_operand:DI 0 "register_operand" "=d") 3742 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] 3743 UNSPEC_STRCMPCC_TO_INT))) 3744 (clobber (reg:CC CC_REGNUM))] 3745 "TARGET_ZARCH" 3746 "#" 3747 "&& reload_completed" 3748 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) 3749 (parallel 3750 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) 3751 (clobber (reg:CC CC_REGNUM))])]) 3752 3753(define_insn_and_split "*cmpint_sign_cc" 3754 [(set (reg CC_REGNUM) 3755 (compare (ashiftrt:DI (ashift:DI (subreg:DI 3756 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] 3757 UNSPEC_STRCMPCC_TO_INT) 0) 3758 (const_int 32)) (const_int 32)) 3759 (const_int 0))) 3760 (set (match_operand:DI 0 "register_operand" "=d") 3761 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))] 3762 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH" 3763 "#" 3764 "&& reload_completed" 3765 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) 3766 (parallel 3767 [(set (match_dup 2) (match_dup 3)) 3768 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] 3769{ 3770 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); 3771 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); 3772 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); 3773}) 3774 3775 3776;; 3777;;- Conversion instructions. 3778;; 3779 3780(define_insn "*sethighpartsi" 3781 [(set (match_operand:SI 0 "register_operand" "=d,d") 3782 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S") 3783 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) 3784 (clobber (reg:CC CC_REGNUM))] 3785 "" 3786 "@ 3787 icm\t%0,%2,%S1 3788 icmy\t%0,%2,%S1" 3789 [(set_attr "op_type" "RS,RSY") 3790 (set_attr "cpu_facility" "*,longdisp") 3791 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 3792 3793(define_insn "*sethighpartdi_64" 3794 [(set (match_operand:DI 0 "register_operand" "=d") 3795 (unspec:DI [(match_operand:BLK 1 "s_operand" "S") 3796 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) 3797 (clobber (reg:CC CC_REGNUM))] 3798 "TARGET_ZARCH" 3799 "icmh\t%0,%2,%S1" 3800 [(set_attr "op_type" "RSY") 3801 (set_attr "z10prop" "z10_super")]) 3802 3803(define_insn "*sethighpartdi_31" 3804 [(set (match_operand:DI 0 "register_operand" "=d,d") 3805 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") 3806 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) 3807 (clobber (reg:CC CC_REGNUM))] 3808 "!TARGET_ZARCH" 3809 "@ 3810 icm\t%0,%2,%S1 3811 icmy\t%0,%2,%S1" 3812 [(set_attr "op_type" "RS,RSY") 3813 (set_attr "cpu_facility" "*,longdisp") 3814 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 3815 3816; 3817; extv instruction patterns 3818; 3819 3820; FIXME: This expander needs to be converted from DI to GPR as well 3821; after resolving some issues with it. 3822 3823(define_expand "extzv" 3824 [(parallel 3825 [(set (match_operand:DI 0 "register_operand" "=d") 3826 (zero_extract:DI 3827 (match_operand:DI 1 "register_operand" "d") 3828 (match_operand 2 "const_int_operand" "") ; size 3829 (match_operand 3 "const_int_operand" ""))) ; start 3830 (clobber (reg:CC CC_REGNUM))])] 3831 "TARGET_Z10" 3832{ 3833 if (! EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), 64)) 3834 FAIL; 3835 /* Starting with zEC12 there is risbgn not clobbering CC. */ 3836 if (TARGET_ZEC12) 3837 { 3838 emit_move_insn (operands[0], 3839 gen_rtx_ZERO_EXTRACT (DImode, 3840 operands[1], 3841 operands[2], 3842 operands[3])); 3843 DONE; 3844 } 3845}) 3846 3847(define_insn "*extzv<mode><clobbercc_or_nocc>" 3848 [(set (match_operand:GPR 0 "register_operand" "=d") 3849 (zero_extract:GPR 3850 (match_operand:GPR 1 "register_operand" "d") 3851 (match_operand 2 "const_int_operand" "") ; size 3852 (match_operand 3 "const_int_operand" ""))) ; start 3853 ] 3854 "<z10_or_zEC12_cond> 3855 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), 3856 GET_MODE_BITSIZE (<MODE>mode))" 3857 "<risbg_n>\t%0,%1,64-%2,128+63,<bitoff_plus>%3+%2" ; dst, src, start, end, shift 3858 [(set_attr "op_type" "RIE") 3859 (set_attr "z10prop" "z10_super_E1")]) 3860 3861; 64 bit: (a & -16) | ((b >> 8) & 15) 3862(define_insn "*extzvdi<clobbercc_or_nocc>_lshiftrt" 3863 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") 3864 (match_operand 1 "const_int_operand" "") ; size 3865 (match_operand 2 "const_int_operand" "")) ; start 3866 (lshiftrt:DI (match_operand:DI 3 "register_operand" "d") 3867 (match_operand:DI 4 "nonzero_shift_count_operand" "")))] 3868 "<z10_or_zEC12_cond> 3869 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) 3870 && 64 - UINTVAL (operands[4]) >= UINTVAL (operands[1])" 3871 "<risbg_n>\t%0,%3,%2,%2+%1-1,128-%2-%1-%4" 3872 [(set_attr "op_type" "RIE") 3873 (set_attr "z10prop" "z10_super_E1")]) 3874 3875; 32 bit: (a & -16) | ((b >> 8) & 15) 3876(define_insn "*<risbg_n>_ior_and_sr_ze" 3877 [(set (match_operand:SI 0 "register_operand" "=d") 3878 (ior:SI (and:SI 3879 (match_operand:SI 1 "register_operand" "0") 3880 (match_operand:SI 2 "const_int_operand" "")) 3881 (subreg:SI 3882 (zero_extract:DI 3883 (match_operand:DI 3 "register_operand" "d") 3884 (match_operand 4 "const_int_operand" "") ; size 3885 (match_operand 5 "const_int_operand" "")) ; start 3886 4)))] 3887 "<z10_or_zEC12_cond> 3888 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[4]), INTVAL (operands[5]), 64) 3889 && UINTVAL (operands[2]) == (~(0ULL) << UINTVAL (operands[4]))" 3890 "<risbg_n>\t%0,%3,64-%4,63,%4+%5" 3891 [(set_attr "op_type" "RIE") 3892 (set_attr "z10prop" "z10_super_E1")]) 3893 3894; ((int)foo >> 10) & 1; 3895(define_insn "*extract1bitdi<clobbercc_or_nocc>" 3896 [(set (match_operand:DI 0 "register_operand" "=d") 3897 (ne:DI (zero_extract:DI 3898 (match_operand:DI 1 "register_operand" "d") 3899 (const_int 1) ; size 3900 (match_operand 2 "const_int_operand" "")) ; start 3901 (const_int 0)))] 3902 "<z10_or_zEC12_cond> 3903 && EXTRACT_ARGS_IN_RANGE (1, INTVAL (operands[2]), 64)" 3904 "<risbg_n>\t%0,%1,64-1,128+63,%2+1" ; dst, src, start, end, shift 3905 [(set_attr "op_type" "RIE") 3906 (set_attr "z10prop" "z10_super_E1")]) 3907 3908(define_insn "*<risbg_n>_and_subregdi_rotr" 3909 [(set (match_operand:DI 0 "register_operand" "=d") 3910 (and:DI (subreg:DI 3911 (rotate:SINT (match_operand:SINT 1 "register_operand" "d") 3912 (match_operand:SINT 2 "const_int_operand" "")) 0) 3913 (match_operand:DI 3 "contiguous_bitmask_operand" "")))] 3914 "<z10_or_zEC12_cond> 3915 && UINTVAL (operands[3]) < (1ULL << (UINTVAL (operands[2]) & 0x3f))" 3916 "<risbg_n>\t%0,%1,%s3,128+%e3,<bitoff_plus>%2" ; dst, src, start, end, shift 3917 [(set_attr "op_type" "RIE") 3918 (set_attr "z10prop" "z10_super_E1")]) 3919 3920(define_insn "*<risbg_n>_and_subregdi_rotl" 3921 [(set (match_operand:DI 0 "register_operand" "=d") 3922 (and:DI (subreg:DI 3923 (rotate:SINT (match_operand:SINT 1 "register_operand" "d") 3924 (match_operand:SINT 2 "const_int_operand" "")) 0) 3925 (match_operand:DI 3 "contiguous_bitmask_operand" "")))] 3926 "<z10_or_zEC12_cond> 3927 && !(UINTVAL (operands[3]) & ((1ULL << (UINTVAL (operands[2]) & 0x3f)) - 1))" 3928 "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift 3929 [(set_attr "op_type" "RIE") 3930 (set_attr "z10prop" "z10_super_E1")]) 3931 3932(define_insn "*<risbg_n>_di_and_rot" 3933 [(set (match_operand:DI 0 "register_operand" "=d") 3934 (and:DI (rotate:DI (match_operand:DI 1 "register_operand" "d") 3935 (match_operand:DI 2 "const_int_operand" "")) 3936 (match_operand:DI 3 "contiguous_bitmask_operand" "")))] 3937 "<z10_or_zEC12_cond>" 3938 "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift 3939 [(set_attr "op_type" "RIE") 3940 (set_attr "z10prop" "z10_super_E1")]) 3941 3942(define_insn_and_split "*pre_z10_extzv<mode>" 3943 [(set (match_operand:GPR 0 "register_operand" "=d") 3944 (zero_extract:GPR (match_operand:QI 1 "s_operand" "S") 3945 (match_operand 2 "nonzero_shift_count_operand" "") 3946 (const_int 0))) 3947 (clobber (reg:CC CC_REGNUM))] 3948 "!TARGET_Z10" 3949 "#" 3950 "&& reload_completed" 3951 [(parallel 3952 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) 3953 (clobber (reg:CC CC_REGNUM))]) 3954 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] 3955{ 3956 int bitsize = INTVAL (operands[2]); 3957 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ 3958 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); 3959 3960 operands[1] = adjust_address (operands[1], BLKmode, 0); 3961 set_mem_size (operands[1], size); 3962 operands[2] = GEN_INT (<GPR:bitsize> - bitsize); 3963 operands[3] = GEN_INT (mask); 3964}) 3965 3966(define_insn_and_split "*pre_z10_extv<mode>" 3967 [(set (match_operand:GPR 0 "register_operand" "=d") 3968 (sign_extract:GPR (match_operand:QI 1 "s_operand" "S") 3969 (match_operand 2 "nonzero_shift_count_operand" "") 3970 (const_int 0))) 3971 (clobber (reg:CC CC_REGNUM))] 3972 "" 3973 "#" 3974 "&& reload_completed" 3975 [(parallel 3976 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) 3977 (clobber (reg:CC CC_REGNUM))]) 3978 (parallel 3979 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) 3980 (clobber (reg:CC CC_REGNUM))])] 3981{ 3982 int bitsize = INTVAL (operands[2]); 3983 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ 3984 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); 3985 3986 operands[1] = adjust_address (operands[1], BLKmode, 0); 3987 set_mem_size (operands[1], size); 3988 operands[2] = GEN_INT (<GPR:bitsize> - bitsize); 3989 operands[3] = GEN_INT (mask); 3990}) 3991 3992; 3993; insv instruction patterns 3994; 3995 3996(define_expand "insv" 3997 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") 3998 (match_operand 1 "const_int_operand" "") 3999 (match_operand 2 "const_int_operand" "")) 4000 (match_operand 3 "general_operand" ""))] 4001 "" 4002{ 4003 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3])) 4004 DONE; 4005 FAIL; 4006}) 4007 4008 4009; The normal RTL expansion will never generate a zero_extract where 4010; the location operand isn't word mode. However, we do this in the 4011; back-end when generating atomic operations. See s390_two_part_insv. 4012(define_insn "*insv<mode><clobbercc_or_nocc>" 4013 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") 4014 (match_operand 1 "const_int_operand" "I") ; size 4015 (match_operand 2 "const_int_operand" "I")) ; pos 4016 (match_operand:GPR 3 "nonimmediate_operand" "d"))] 4017 "<z10_or_zEC12_cond> 4018 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 4019 GET_MODE_BITSIZE (<MODE>mode)) 4020 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>" 4021 "<risbg_n>\t%0,%3,<bitoff_plus>%2,<bitoff_plus>%2+%1-1,<bitsize>-%2-%1" 4022 [(set_attr "op_type" "RIE") 4023 (set_attr "z10prop" "z10_super_E1")]) 4024 4025; and op1 with a mask being 1 for the selected bits and 0 for the rest 4026; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest 4027(define_insn "*insv<mode><clobbercc_or_nocc>_noshift" 4028 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d") 4029 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d,0") 4030 (match_operand:GPR 2 "contiguous_bitmask_operand" "")) 4031 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0,d") 4032 (match_operand:GPR 4 "const_int_operand" ""))))] 4033 "<z10_or_zEC12_cond> && INTVAL (operands[2]) == ~INTVAL (operands[4])" 4034 "@ 4035 <risbg_n>\t%0,%1,%<bfstart>2,%<bfend>2,0 4036 <risbg_n>\t%0,%3,%<bfstart>4,%<bfend>4,0" 4037 [(set_attr "op_type" "RIE") 4038 (set_attr "z10prop" "z10_super_E1")]) 4039 4040(define_insn "*insv_z10_noshift_cc" 4041 [(set (reg CC_REGNUM) 4042 (compare 4043 (ior:DI 4044 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0") 4045 (match_operand:DI 2 "contiguous_bitmask_operand" "")) 4046 (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d") 4047 (match_operand:DI 4 "const_int_operand" ""))) 4048 (const_int 0))) 4049 (set (match_operand:DI 0 "nonimmediate_operand" "=d,d") 4050 (ior:DI (and:DI (match_dup 1) (match_dup 2)) 4051 (and:DI (match_dup 3) (match_dup 4))))] 4052 "TARGET_Z10 && s390_match_ccmode (insn, CCSmode) 4053 && INTVAL (operands[2]) == ~INTVAL (operands[4])" 4054 "@ 4055 risbg\t%0,%1,%s2,%e2,0 4056 risbg\t%0,%3,%s4,%e4,0" 4057 [(set_attr "op_type" "RIE") 4058 (set_attr "z10prop" "z10_super_E1")]) 4059 4060(define_insn "*insv_z10_noshift_cconly" 4061 [(set 4062 (reg CC_REGNUM) 4063 (compare 4064 (ior:DI 4065 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0") 4066 (match_operand:DI 2 "contiguous_bitmask_operand" "")) 4067 (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d") 4068 (match_operand:DI 4 "const_int_operand" ""))) 4069 (const_int 0))) 4070 (clobber (match_scratch:DI 0 "=d,d"))] 4071 "TARGET_Z10 && s390_match_ccmode (insn, CCSmode) 4072 && INTVAL (operands[2]) == ~INTVAL (operands[4])" 4073 "@ 4074 risbg\t%0,%1,%s2,%e2,0 4075 risbg\t%0,%3,%s4,%e4,0" 4076 [(set_attr "op_type" "RIE") 4077 (set_attr "z10prop" "z10_super_E1")]) 4078 4079; Implement appending Y on the left of S bits of X 4080; x = (y << s) | (x & ((1 << s) - 1)) 4081(define_insn "*insv<mode><clobbercc_or_nocc>_appendbitsleft" 4082 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") 4083 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0") 4084 (match_operand:GPR 2 "immediate_operand" "")) 4085 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d") 4086 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] 4087 "<z10_or_zEC12_cond> 4088 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1" 4089 "<risbg_n>\t%0,%3,<bitoff>,64-%4-1,%4" 4090 [(set_attr "op_type" "RIE") 4091 (set_attr "z10prop" "z10_super_E1")]) 4092 4093; a = ((i32)a & -16777216) | (((ui32)b) >> 8) 4094(define_insn "*<risbg_n>_<mode>_ior_and_lshiftrt" 4095 [(set (match_operand:GPR 0 "register_operand" "=d") 4096 (ior:GPR (and:GPR 4097 (match_operand:GPR 1 "register_operand" "0") 4098 (match_operand:GPR 2 "const_int_operand" "")) 4099 (lshiftrt:GPR 4100 (match_operand:GPR 3 "register_operand" "d") 4101 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] 4102 "<z10_or_zEC12_cond> && UINTVAL (operands[2]) 4103 == (~(0ULL) << (GET_MODE_BITSIZE (<MODE>mode) - UINTVAL (operands[4])))" 4104 "<risbg_n>\t%0,%3,<bitoff_plus>%4,63,64-%4" 4105 [(set_attr "op_type" "RIE") 4106 (set_attr "z10prop" "z10_super_E1")]) 4107 4108; (ui32)(((ui64)x) >> 48) | ((i32)y & -65536); 4109(define_insn "*<risbg_n>_sidi_ior_and_lshiftrt" 4110 [(set (match_operand:SI 0 "register_operand" "=d") 4111 (ior:SI (and:SI 4112 (match_operand:SI 1 "register_operand" "0") 4113 (match_operand:SI 2 "const_int_operand" "")) 4114 (subreg:SI 4115 (lshiftrt:DI 4116 (match_operand:DI 3 "register_operand" "d") 4117 (match_operand:DI 4 "nonzero_shift_count_operand" "")) 4)))] 4118 "<z10_or_zEC12_cond> 4119 && UINTVAL (operands[2]) == ~(~(0ULL) >> UINTVAL (operands[4]))" 4120 "<risbg_n>\t%0,%3,%4,63,64-%4" 4121 [(set_attr "op_type" "RIE") 4122 (set_attr "z10prop" "z10_super_E1")]) 4123 4124; (ui32)(((ui64)x) >> 12) & -4 4125(define_insn "*trunc_sidi_and_subreg_lshrt<clobbercc_or_nocc>" 4126 [(set (match_operand:SI 0 "register_operand" "=d") 4127 (and:SI 4128 (subreg:SI (lshiftrt:DI 4129 (match_operand:DI 1 "register_operand" "d") 4130 (match_operand:DI 2 "nonzero_shift_count_operand" "")) 4) 4131 (match_operand:SI 3 "contiguous_bitmask_nowrap_operand" "")))] 4132 "<z10_or_zEC12_cond>" 4133 "<risbg_n>\t%0,%1,%t3,128+%f3,64-%2" 4134 [(set_attr "op_type" "RIE") 4135 (set_attr "z10prop" "z10_super_E1")]) 4136 4137; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting 4138; -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1)) 4139; -> z = y >> d; z = risbg; 4140 4141(define_split 4142 [(set (match_operand:GPR 0 "nonimmediate_operand" "") 4143 (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") 4144 (match_operand:GPR 2 "nonzero_shift_count_operand" "")) 4145 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") 4146 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] 4147 "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" 4148 [(set (match_dup 6) 4149 (lshiftrt:GPR (match_dup 1) (match_dup 2))) 4150 (set (match_dup 0) 4151 (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) 4152 (ashift:GPR (match_dup 3) (match_dup 4))))] 4153{ 4154 operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1); 4155 if (reg_overlap_mentioned_p (operands[0], operands[3])) 4156 { 4157 if (!can_create_pseudo_p ()) 4158 FAIL; 4159 operands[6] = gen_reg_rtx (<MODE>mode); 4160 } 4161 else 4162 operands[6] = operands[0]; 4163}) 4164 4165(define_split 4166 [(parallel 4167 [(set (match_operand:GPR 0 "nonimmediate_operand" "") 4168 (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") 4169 (match_operand:GPR 2 "nonzero_shift_count_operand" "")) 4170 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") 4171 (match_operand:GPR 4 "nonzero_shift_count_operand" "")))) 4172 (clobber (reg:CC CC_REGNUM))])] 4173 "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" 4174 [(set (match_dup 6) 4175 (lshiftrt:GPR (match_dup 1) (match_dup 2))) 4176 (parallel 4177 [(set (match_dup 0) 4178 (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) 4179 (ashift:GPR (match_dup 3) (match_dup 4)))) 4180 (clobber (reg:CC CC_REGNUM))])] 4181{ 4182 operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1); 4183 if (reg_overlap_mentioned_p (operands[0], operands[3])) 4184 { 4185 if (!can_create_pseudo_p ()) 4186 FAIL; 4187 operands[6] = gen_reg_rtx (<MODE>mode); 4188 } 4189 else 4190 operands[6] = operands[0]; 4191}) 4192 4193; rosbg, rxsbg 4194(define_insn "*r<noxa>sbg_<mode>_noshift" 4195 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") 4196 (IXOR:GPR 4197 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") 4198 (match_operand:GPR 2 "contiguous_bitmask_operand" "")) 4199 (match_operand:GPR 3 "nonimmediate_operand" "0"))) 4200 (clobber (reg:CC CC_REGNUM))] 4201 "TARGET_Z10" 4202 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0" 4203 [(set_attr "op_type" "RIE")]) 4204 4205; rosbg, rxsbg 4206(define_insn "*r<noxa>sbg_di_rotl" 4207 [(set (match_operand:DI 0 "nonimmediate_operand" "=d") 4208 (IXOR:DI 4209 (and:DI 4210 (rotate:DI 4211 (match_operand:DI 1 "nonimmediate_operand" "d") 4212 (match_operand:DI 3 "const_int_operand" "")) 4213 (match_operand:DI 2 "contiguous_bitmask_operand" "")) 4214 (match_operand:DI 4 "nonimmediate_operand" "0"))) 4215 (clobber (reg:CC CC_REGNUM))] 4216 "TARGET_Z10" 4217 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3" 4218 [(set_attr "op_type" "RIE")]) 4219 4220; rosbg, rxsbg 4221(define_insn "*r<noxa>sbg_<mode>_srl_bitmask" 4222 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") 4223 (IXOR:GPR 4224 (and:GPR 4225 (lshiftrt:GPR 4226 (match_operand:GPR 1 "nonimmediate_operand" "d") 4227 (match_operand:GPR 3 "nonzero_shift_count_operand" "")) 4228 (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" "")) 4229 (match_operand:GPR 4 "nonimmediate_operand" "0"))) 4230 (clobber (reg:CC CC_REGNUM))] 4231 "TARGET_Z10 4232 && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]), 4233 INTVAL (operands[2]))" 4234 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3" 4235 [(set_attr "op_type" "RIE")]) 4236 4237; rosbg, rxsbg 4238(define_insn "*r<noxa>sbg_<mode>_sll_bitmask" 4239 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") 4240 (IXOR:GPR 4241 (and:GPR 4242 (ashift:GPR 4243 (match_operand:GPR 1 "nonimmediate_operand" "d") 4244 (match_operand:GPR 3 "nonzero_shift_count_operand" "")) 4245 (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" "")) 4246 (match_operand:GPR 4 "nonimmediate_operand" "0"))) 4247 (clobber (reg:CC CC_REGNUM))] 4248 "TARGET_Z10 4249 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]), 4250 INTVAL (operands[2]))" 4251 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3" 4252 [(set_attr "op_type" "RIE")]) 4253 4254;; unsigned {int,long} a, b 4255;; a = a | (b << const_int) 4256;; a = a ^ (b << const_int) 4257; rosbg, rxsbg 4258(define_insn "*r<noxa>sbg_<mode>_sll" 4259 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") 4260 (IXOR:GPR 4261 (ashift:GPR 4262 (match_operand:GPR 1 "nonimmediate_operand" "d") 4263 (match_operand:GPR 2 "nonzero_shift_count_operand" "")) 4264 (match_operand:GPR 3 "nonimmediate_operand" "0"))) 4265 (clobber (reg:CC CC_REGNUM))] 4266 "TARGET_Z10" 4267 "r<noxa>sbg\t%0,%1,<bitoff>,63-%2,%2" 4268 [(set_attr "op_type" "RIE")]) 4269 4270;; unsigned {int,long} a, b 4271;; a = a | (b >> const_int) 4272;; a = a ^ (b >> const_int) 4273; rosbg, rxsbg 4274(define_insn "*r<noxa>sbg_<mode>_srl" 4275 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") 4276 (IXOR:GPR 4277 (lshiftrt:GPR 4278 (match_operand:GPR 1 "nonimmediate_operand" "d") 4279 (match_operand:GPR 2 "nonzero_shift_count_operand" "")) 4280 (match_operand:GPR 3 "nonimmediate_operand" "0"))) 4281 (clobber (reg:CC CC_REGNUM))] 4282 "TARGET_Z10" 4283 "r<noxa>sbg\t%0,%1,<bitoff_plus>%2,63,64-%2" 4284 [(set_attr "op_type" "RIE")]) 4285 4286;; These two are generated by combine for s.bf &= val. 4287;; ??? For bitfields smaller than 32-bits, we wind up with SImode 4288;; shifts and ands, which results in some truly awful patterns 4289;; including subregs of operations. Rather unnecessisarily, IMO. 4290;; Instead of 4291;; 4292;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) 4293;; (const_int 24 [0x18]) 4294;; (const_int 0 [0])) 4295;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ]) 4296;; (const_int 40 [0x28])) 4) 4297;; (reg:SI 4 %r4 [ y+4 ])) 0)) 4298;; 4299;; we should instead generate 4300;; 4301;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) 4302;; (const_int 24 [0x18]) 4303;; (const_int 0 [0])) 4304;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ]) 4305;; (const_int 40 [0x28])) 4306;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0))) 4307;; 4308;; by noticing that we can push down the outer paradoxical subreg 4309;; into the operation. 4310 4311(define_insn "*insv_rnsbg_noshift" 4312 [(set (zero_extract:DI 4313 (match_operand:DI 0 "nonimmediate_operand" "+d") 4314 (match_operand 1 "const_int_operand" "") 4315 (match_operand 2 "const_int_operand" "")) 4316 (and:DI 4317 (match_dup 0) 4318 (match_operand:DI 3 "nonimmediate_operand" "d"))) 4319 (clobber (reg:CC CC_REGNUM))] 4320 "TARGET_Z10 4321 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) 4322 && INTVAL (operands[1]) + INTVAL (operands[2]) == 64" 4323 "rnsbg\t%0,%3,%2,63,0" 4324 [(set_attr "op_type" "RIE")]) 4325 4326(define_insn "*insv_rnsbg_srl" 4327 [(set (zero_extract:DI 4328 (match_operand:DI 0 "nonimmediate_operand" "+d") 4329 (match_operand 1 "const_int_operand" "") 4330 (match_operand 2 "const_int_operand" "")) 4331 (and:DI 4332 (lshiftrt:DI 4333 (match_dup 0) 4334 (match_operand 3 "const_int_operand" "")) 4335 (match_operand:DI 4 "nonimmediate_operand" "d"))) 4336 (clobber (reg:CC CC_REGNUM))] 4337 "TARGET_Z10 4338 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) 4339 && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])" 4340 "rnsbg\t%0,%4,%2,%2+%1-1,%3" 4341 [(set_attr "op_type" "RIE")]) 4342 4343(define_insn "*insv<mode>_mem_reg" 4344 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S") 4345 (match_operand 1 "const_int_operand" "n,n") 4346 (const_int 0)) 4347 (match_operand:W 2 "register_operand" "d,d"))] 4348 "EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64) 4349 && INTVAL (operands[1]) > 0 4350 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) 4351 && INTVAL (operands[1]) % BITS_PER_UNIT == 0" 4352{ 4353 int size = INTVAL (operands[1]) / BITS_PER_UNIT; 4354 4355 operands[1] = GEN_INT ((1ul << size) - 1); 4356 return (which_alternative == 0) ? "stcm\t%2,%1,%S0" 4357 : "stcmy\t%2,%1,%S0"; 4358} 4359 [(set_attr "op_type" "RS,RSY") 4360 (set_attr "cpu_facility" "*,longdisp") 4361 (set_attr "z10prop" "z10_super,z10_super")]) 4362 4363(define_insn "*insvdi_mem_reghigh" 4364 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+S") 4365 (match_operand 1 "const_int_operand" "n") 4366 (const_int 0)) 4367 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") 4368 (const_int 32)))] 4369 "TARGET_ZARCH 4370 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64) 4371 && INTVAL (operands[1]) > 0 4372 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) 4373 && INTVAL (operands[1]) % BITS_PER_UNIT == 0" 4374{ 4375 int size = INTVAL (operands[1]) / BITS_PER_UNIT; 4376 4377 operands[1] = GEN_INT ((1ul << size) - 1); 4378 return "stcmh\t%2,%1,%S0"; 4379} 4380[(set_attr "op_type" "RSY") 4381 (set_attr "z10prop" "z10_super")]) 4382 4383(define_insn "*insvdi_reg_imm" 4384 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") 4385 (const_int 16) 4386 (match_operand 1 "const_int_operand" "n")) 4387 (match_operand:DI 2 "const_int_operand" "n"))] 4388 "TARGET_ZARCH 4389 && EXTRACT_ARGS_IN_RANGE (16, INTVAL (operands[1]), 64) 4390 && INTVAL (operands[1]) >= 0 4391 && INTVAL (operands[1]) < BITS_PER_WORD 4392 && INTVAL (operands[1]) % 16 == 0" 4393{ 4394 switch (BITS_PER_WORD - INTVAL (operands[1])) 4395 { 4396 case 64: return "iihh\t%0,%x2"; break; 4397 case 48: return "iihl\t%0,%x2"; break; 4398 case 32: return "iilh\t%0,%x2"; break; 4399 case 16: return "iill\t%0,%x2"; break; 4400 default: gcc_unreachable(); 4401 } 4402} 4403 [(set_attr "op_type" "RI") 4404 (set_attr "z10prop" "z10_super_E1")]) 4405 4406; Update the left-most 32 bit of a DI. 4407(define_insn "*insv_h_di_reg_extimm" 4408 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") 4409 (const_int 32) 4410 (const_int 0)) 4411 (match_operand:DI 1 "const_int_operand" "n"))] 4412 "TARGET_EXTIMM" 4413 "iihf\t%0,%o1" 4414 [(set_attr "op_type" "RIL") 4415 (set_attr "z10prop" "z10_fwd_E1")]) 4416 4417; Update the right-most 32 bit of a DI. 4418(define_insn "*insv_l_di_reg_extimm" 4419 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") 4420 (const_int 32) 4421 (const_int 32)) 4422 (match_operand:DI 1 "const_int_operand" "n"))] 4423 "TARGET_EXTIMM" 4424 "iilf\t%0,%o1" 4425 [(set_attr "op_type" "RIL") 4426 (set_attr "z10prop" "z10_fwd_A1")]) 4427 4428; 4429; extendsidi2 instruction pattern(s). 4430; 4431 4432(define_expand "extendsidi2" 4433 [(set (match_operand:DI 0 "register_operand" "") 4434 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] 4435 "" 4436{ 4437 if (!TARGET_ZARCH) 4438 { 4439 emit_clobber (operands[0]); 4440 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); 4441 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); 4442 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); 4443 DONE; 4444 } 4445}) 4446 4447(define_insn "*extendsidi2" 4448 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 4449 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))] 4450 "TARGET_ZARCH" 4451 "@ 4452 lgfr\t%0,%1 4453 lgf\t%0,%1 4454 lgfrl\t%0,%1" 4455 [(set_attr "op_type" "RRE,RXY,RIL") 4456 (set_attr "type" "*,*,larl") 4457 (set_attr "cpu_facility" "*,*,z10") 4458 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) 4459 4460; 4461; extend(hi|qi)(si|di)2 instruction pattern(s). 4462; 4463 4464(define_expand "extend<HQI:mode><DSI:mode>2" 4465 [(set (match_operand:DSI 0 "register_operand" "") 4466 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] 4467 "" 4468{ 4469 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH) 4470 { 4471 rtx tmp = gen_reg_rtx (SImode); 4472 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); 4473 emit_insn (gen_extendsidi2 (operands[0], tmp)); 4474 DONE; 4475 } 4476 else if (!TARGET_EXTIMM) 4477 { 4478 rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>); 4479 4480 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]); 4481 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount)); 4482 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount)); 4483 DONE; 4484 } 4485}) 4486 4487; 4488; extendhidi2 instruction pattern(s). 4489; 4490 4491(define_insn "*extendhidi2_extimm" 4492 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 4493 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,T,b")))] 4494 "TARGET_ZARCH && TARGET_EXTIMM" 4495 "@ 4496 lghr\t%0,%1 4497 lgh\t%0,%1 4498 lghrl\t%0,%1" 4499 [(set_attr "op_type" "RRE,RXY,RIL") 4500 (set_attr "type" "*,*,larl") 4501 (set_attr "cpu_facility" "extimm,extimm,z10") 4502 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) 4503 4504(define_insn "*extendhidi2" 4505 [(set (match_operand:DI 0 "register_operand" "=d") 4506 (sign_extend:DI (match_operand:HI 1 "memory_operand" "T")))] 4507 "TARGET_ZARCH" 4508 "lgh\t%0,%1" 4509 [(set_attr "op_type" "RXY") 4510 (set_attr "z10prop" "z10_super_E1")]) 4511 4512; 4513; extendhisi2 instruction pattern(s). 4514; 4515 4516(define_insn "*extendhisi2_extimm" 4517 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") 4518 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))] 4519 "TARGET_EXTIMM" 4520 "@ 4521 lhr\t%0,%1 4522 lh\t%0,%1 4523 lhy\t%0,%1 4524 lhrl\t%0,%1" 4525 [(set_attr "op_type" "RRE,RX,RXY,RIL") 4526 (set_attr "type" "*,*,*,larl") 4527 (set_attr "cpu_facility" "extimm,extimm,extimm,z10") 4528 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) 4529 4530(define_insn "*extendhisi2" 4531 [(set (match_operand:SI 0 "register_operand" "=d,d") 4532 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] 4533 "!TARGET_EXTIMM" 4534 "@ 4535 lh\t%0,%1 4536 lhy\t%0,%1" 4537 [(set_attr "op_type" "RX,RXY") 4538 (set_attr "cpu_facility" "*,longdisp") 4539 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 4540 4541; 4542; extendqi(si|di)2 instruction pattern(s). 4543; 4544 4545; lbr, lgbr, lb, lgb 4546(define_insn "*extendqi<mode>2_extimm" 4547 [(set (match_operand:GPR 0 "register_operand" "=d,d") 4548 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,T")))] 4549 "TARGET_EXTIMM" 4550 "@ 4551 l<g>br\t%0,%1 4552 l<g>b\t%0,%1" 4553 [(set_attr "op_type" "RRE,RXY") 4554 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 4555 4556; lb, lgb 4557(define_insn "*extendqi<mode>2" 4558 [(set (match_operand:GPR 0 "register_operand" "=d") 4559 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "T")))] 4560 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" 4561 "l<g>b\t%0,%1" 4562 [(set_attr "op_type" "RXY") 4563 (set_attr "z10prop" "z10_super_E1")]) 4564 4565(define_insn_and_split "*extendqi<mode>2_short_displ" 4566 [(set (match_operand:GPR 0 "register_operand" "=d") 4567 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q"))) 4568 (clobber (reg:CC CC_REGNUM))] 4569 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT" 4570 "#" 4571 "&& reload_completed" 4572 [(parallel 4573 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM)) 4574 (clobber (reg:CC CC_REGNUM))]) 4575 (parallel 4576 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) 4577 (clobber (reg:CC CC_REGNUM))])] 4578{ 4579 operands[1] = adjust_address (operands[1], BLKmode, 0); 4580 set_mem_size (operands[1], GET_MODE_SIZE (QImode)); 4581 operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT); 4582}) 4583 4584; 4585; zero_extendsidi2 instruction pattern(s). 4586; 4587 4588(define_expand "zero_extendsidi2" 4589 [(set (match_operand:DI 0 "register_operand" "") 4590 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] 4591 "" 4592{ 4593 if (!TARGET_ZARCH) 4594 { 4595 emit_clobber (operands[0]); 4596 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); 4597 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); 4598 DONE; 4599 } 4600}) 4601 4602(define_insn "*zero_extendsidi2" 4603 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 4604 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))] 4605 "TARGET_ZARCH" 4606 "@ 4607 llgfr\t%0,%1 4608 llgf\t%0,%1 4609 llgfrl\t%0,%1" 4610 [(set_attr "op_type" "RRE,RXY,RIL") 4611 (set_attr "type" "*,*,larl") 4612 (set_attr "cpu_facility" "*,*,z10") 4613 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")]) 4614 4615; 4616; LLGT-type instructions (zero-extend from 31 bit to 64 bit). 4617; 4618 4619(define_insn "*llgt_sidi" 4620 [(set (match_operand:DI 0 "register_operand" "=d") 4621 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0) 4622 (const_int 2147483647)))] 4623 "TARGET_ZARCH" 4624 "llgt\t%0,%1" 4625 [(set_attr "op_type" "RXE") 4626 (set_attr "z10prop" "z10_super_E1")]) 4627 4628(define_insn_and_split "*llgt_sidi_split" 4629 [(set (match_operand:DI 0 "register_operand" "=d") 4630 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0) 4631 (const_int 2147483647))) 4632 (clobber (reg:CC CC_REGNUM))] 4633 "TARGET_ZARCH" 4634 "#" 4635 "&& reload_completed" 4636 [(set (match_dup 0) 4637 (and:DI (subreg:DI (match_dup 1) 0) 4638 (const_int 2147483647)))] 4639 "") 4640 4641(define_insn "*llgt_sisi" 4642 [(set (match_operand:SI 0 "register_operand" "=d,d") 4643 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,T") 4644 (const_int 2147483647)))] 4645 "TARGET_ZARCH" 4646 "@ 4647 llgtr\t%0,%1 4648 llgt\t%0,%1" 4649 [(set_attr "op_type" "RRE,RXE") 4650 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 4651 4652(define_insn "*llgt_didi" 4653 [(set (match_operand:DI 0 "register_operand" "=d,d") 4654 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") 4655 (const_int 2147483647)))] 4656 "TARGET_ZARCH" 4657 "@ 4658 llgtr\t%0,%1 4659 llgt\t%0,%N1" 4660 [(set_attr "op_type" "RRE,RXE") 4661 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 4662 4663(define_split 4664 [(set (match_operand:DSI 0 "register_operand" "") 4665 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "") 4666 (const_int 2147483647))) 4667 (clobber (reg:CC CC_REGNUM))] 4668 "TARGET_ZARCH && reload_completed" 4669 [(set (match_dup 0) 4670 (and:DSI (match_dup 1) 4671 (const_int 2147483647)))] 4672 "") 4673 4674; 4675; zero_extend(hi|qi)(si|di)2 instruction pattern(s). 4676; 4677 4678(define_expand "zero_extend<mode>di2" 4679 [(set (match_operand:DI 0 "register_operand" "") 4680 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] 4681 "" 4682{ 4683 if (!TARGET_ZARCH) 4684 { 4685 rtx tmp = gen_reg_rtx (SImode); 4686 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); 4687 emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); 4688 DONE; 4689 } 4690 else if (!TARGET_EXTIMM) 4691 { 4692 rtx bitcount = GEN_INT (64 - <HQI:bitsize>); 4693 operands[1] = gen_lowpart (DImode, operands[1]); 4694 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); 4695 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); 4696 DONE; 4697 } 4698}) 4699 4700(define_expand "zero_extend<mode>si2" 4701 [(set (match_operand:SI 0 "register_operand" "") 4702 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] 4703 "" 4704{ 4705 if (!TARGET_EXTIMM) 4706 { 4707 operands[1] = gen_lowpart (SImode, operands[1]); 4708 emit_insn (gen_andsi3 (operands[0], operands[1], 4709 GEN_INT ((1 << <HQI:bitsize>) - 1))); 4710 DONE; 4711 } 4712}) 4713 4714; llhrl, llghrl 4715(define_insn "*zero_extendhi<mode>2_z10" 4716 [(set (match_operand:GPR 0 "register_operand" "=d,d,d") 4717 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,T,b")))] 4718 "TARGET_Z10" 4719 "@ 4720 ll<g>hr\t%0,%1 4721 ll<g>h\t%0,%1 4722 ll<g>hrl\t%0,%1" 4723 [(set_attr "op_type" "RXY,RRE,RIL") 4724 (set_attr "type" "*,*,larl") 4725 (set_attr "cpu_facility" "*,*,z10") 4726 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")]) 4727 4728; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc 4729(define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" 4730 [(set (match_operand:GPR 0 "register_operand" "=d,d") 4731 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,T")))] 4732 "TARGET_EXTIMM" 4733 "@ 4734 ll<g><hc>r\t%0,%1 4735 ll<g><hc>\t%0,%1" 4736 [(set_attr "op_type" "RRE,RXY") 4737 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")]) 4738 4739; llgh, llgc 4740(define_insn "*zero_extend<HQI:mode><GPR:mode>2" 4741 [(set (match_operand:GPR 0 "register_operand" "=d") 4742 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "T")))] 4743 "TARGET_ZARCH && !TARGET_EXTIMM" 4744 "llg<hc>\t%0,%1" 4745 [(set_attr "op_type" "RXY") 4746 (set_attr "z10prop" "z10_fwd_A3")]) 4747 4748(define_insn_and_split "*zero_extendhisi2_31" 4749 [(set (match_operand:SI 0 "register_operand" "=&d") 4750 (zero_extend:SI (match_operand:HI 1 "s_operand" "S"))) 4751 (clobber (reg:CC CC_REGNUM))] 4752 "!TARGET_ZARCH" 4753 "#" 4754 "&& reload_completed" 4755 [(set (match_dup 0) (const_int 0)) 4756 (parallel 4757 [(set (strict_low_part (match_dup 2)) (match_dup 1)) 4758 (clobber (reg:CC CC_REGNUM))])] 4759 "operands[2] = gen_lowpart (HImode, operands[0]);") 4760 4761(define_insn_and_split "*zero_extendqisi2_31" 4762 [(set (match_operand:SI 0 "register_operand" "=&d") 4763 (zero_extend:SI (match_operand:QI 1 "memory_operand" "T")))] 4764 "!TARGET_ZARCH" 4765 "#" 4766 "&& reload_completed" 4767 [(set (match_dup 0) (const_int 0)) 4768 (set (strict_low_part (match_dup 2)) (match_dup 1))] 4769 "operands[2] = gen_lowpart (QImode, operands[0]);") 4770 4771; 4772; zero_extendqihi2 instruction pattern(s). 4773; 4774 4775(define_expand "zero_extendqihi2" 4776 [(set (match_operand:HI 0 "register_operand" "") 4777 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] 4778 "TARGET_ZARCH && !TARGET_EXTIMM" 4779{ 4780 operands[1] = gen_lowpart (HImode, operands[1]); 4781 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); 4782 DONE; 4783}) 4784 4785(define_insn "*zero_extendqihi2_64" 4786 [(set (match_operand:HI 0 "register_operand" "=d") 4787 (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))] 4788 "TARGET_ZARCH && !TARGET_EXTIMM" 4789 "llgc\t%0,%1" 4790 [(set_attr "op_type" "RXY") 4791 (set_attr "z10prop" "z10_fwd_A3")]) 4792 4793(define_insn_and_split "*zero_extendqihi2_31" 4794 [(set (match_operand:HI 0 "register_operand" "=&d") 4795 (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))] 4796 "!TARGET_ZARCH" 4797 "#" 4798 "&& reload_completed" 4799 [(set (match_dup 0) (const_int 0)) 4800 (set (strict_low_part (match_dup 2)) (match_dup 1))] 4801 "operands[2] = gen_lowpart (QImode, operands[0]);") 4802 4803; 4804; fixuns_trunc(dd|td|sf|df|tf)(si|di)2 expander 4805; 4806 4807; This is the only entry point for fixuns_trunc. It multiplexes the 4808; expansion to either the *_emu expanders below for pre z196 machines 4809; or emits the default pattern otherwise. 4810(define_expand "fixuns_trunc<FP:mode><GPR:mode>2" 4811 [(parallel 4812 [(set (match_operand:GPR 0 "register_operand" "") 4813 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" ""))) 4814 (unspec:GPR [(match_dup 2)] UNSPEC_ROUND) 4815 (clobber (reg:CC CC_REGNUM))])] 4816 "TARGET_HARD_FLOAT" 4817{ 4818 if (!TARGET_Z196) 4819 { 4820 /* We don't provide emulation for TD|DD->SI. */ 4821 if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT 4822 && <GPR:MODE>mode == SImode) 4823 FAIL; 4824 emit_insn (gen_fixuns_trunc<FP:mode><GPR:mode>2_emu (operands[0], 4825 operands[1])); 4826 DONE; 4827 } 4828 4829 if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT) 4830 operands[2] = GEN_INT (DFP_RND_TOWARD_0); 4831 else 4832 operands[2] = GEN_INT (BFP_RND_TOWARD_0); 4833}) 4834 4835; (sf|df|tf)->unsigned (si|di) 4836 4837; Emulate the unsigned conversion with the signed version for pre z196 4838; machines. 4839(define_expand "fixuns_trunc<BFP:mode><GPR:mode>2_emu" 4840 [(parallel 4841 [(set (match_operand:GPR 0 "register_operand" "") 4842 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" ""))) 4843 (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) 4844 (clobber (reg:CC CC_REGNUM))])] 4845 "!TARGET_Z196 && TARGET_HARD_FLOAT" 4846{ 4847 rtx_code_label *label1 = gen_label_rtx (); 4848 rtx_code_label *label2 = gen_label_rtx (); 4849 rtx temp = gen_reg_rtx (<BFP:MODE>mode); 4850 REAL_VALUE_TYPE cmp, sub; 4851 4852 operands[1] = force_reg (<BFP:MODE>mode, operands[1]); 4853 real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode); 4854 real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode); 4855 4856 emit_cmp_and_jump_insns (operands[1], 4857 const_double_from_real_value (cmp, <BFP:MODE>mode), 4858 LT, NULL_RTX, VOIDmode, 0, label1); 4859 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1], 4860 const_double_from_real_value (sub, <BFP:MODE>mode))); 4861 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp, 4862 GEN_INT (BFP_RND_TOWARD_MINF))); 4863 emit_jump (label2); 4864 4865 emit_label (label1); 4866 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], 4867 operands[1], 4868 GEN_INT (BFP_RND_TOWARD_0))); 4869 emit_label (label2); 4870 DONE; 4871}) 4872 4873; dd->unsigned di 4874 4875; Emulate the unsigned conversion with the signed version for pre z196 4876; machines. 4877(define_expand "fixuns_truncdddi2_emu" 4878 [(parallel 4879 [(set (match_operand:DI 0 "register_operand" "") 4880 (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) 4881 (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) 4882 (clobber (reg:CC CC_REGNUM))])] 4883 4884 "!TARGET_Z196 && TARGET_HARD_DFP" 4885{ 4886 rtx_code_label *label1 = gen_label_rtx (); 4887 rtx_code_label *label2 = gen_label_rtx (); 4888 rtx temp = gen_reg_rtx (TDmode); 4889 REAL_VALUE_TYPE cmp, sub; 4890 4891 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ 4892 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ 4893 4894 /* 2^63 can't be represented as 64bit DFP number with full precision. The 4895 solution is doing the check and the subtraction in TD mode and using a 4896 TD -> DI convert afterwards. */ 4897 emit_insn (gen_extendddtd2 (temp, operands[1])); 4898 temp = force_reg (TDmode, temp); 4899 emit_cmp_and_jump_insns (temp, 4900 const_double_from_real_value (cmp, TDmode), 4901 LT, NULL_RTX, VOIDmode, 0, label1); 4902 emit_insn (gen_subtd3 (temp, temp, 4903 const_double_from_real_value (sub, TDmode))); 4904 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, 4905 GEN_INT (DFP_RND_TOWARD_MINF))); 4906 emit_jump (label2); 4907 4908 emit_label (label1); 4909 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], 4910 GEN_INT (DFP_RND_TOWARD_0))); 4911 emit_label (label2); 4912 DONE; 4913}) 4914 4915; td->unsigned di 4916 4917; Emulate the unsigned conversion with the signed version for pre z196 4918; machines. 4919(define_expand "fixuns_trunctddi2_emu" 4920 [(parallel 4921 [(set (match_operand:DI 0 "register_operand" "") 4922 (unsigned_fix:DI (match_operand:TD 1 "register_operand" ""))) 4923 (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) 4924 (clobber (reg:CC CC_REGNUM))])] 4925 4926 "!TARGET_Z196 && TARGET_HARD_DFP" 4927{ 4928 rtx_code_label *label1 = gen_label_rtx (); 4929 rtx_code_label *label2 = gen_label_rtx (); 4930 rtx temp = gen_reg_rtx (TDmode); 4931 REAL_VALUE_TYPE cmp, sub; 4932 4933 operands[1] = force_reg (TDmode, operands[1]); 4934 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ 4935 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ 4936 4937 emit_cmp_and_jump_insns (operands[1], 4938 const_double_from_real_value (cmp, TDmode), 4939 LT, NULL_RTX, VOIDmode, 0, label1); 4940 emit_insn (gen_subtd3 (temp, operands[1], 4941 const_double_from_real_value (sub, TDmode))); 4942 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, 4943 GEN_INT (DFP_RND_TOWARD_MINF))); 4944 emit_jump (label2); 4945 4946 emit_label (label1); 4947 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], 4948 GEN_INT (DFP_RND_TOWARD_0))); 4949 emit_label (label2); 4950 DONE; 4951}) 4952 4953; Just a dummy to make the code in the first expander a bit easier. 4954(define_expand "fixuns_trunc<mode>si2_emu" 4955 [(parallel 4956 [(set (match_operand:SI 0 "register_operand" "") 4957 (unsigned_fix:SI (match_operand:DFP 1 "register_operand" ""))) 4958 (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) 4959 (clobber (reg:CC CC_REGNUM))])] 4960 4961 "!TARGET_Z196 && TARGET_HARD_DFP" 4962 { 4963 FAIL; 4964 }) 4965 4966 4967; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns. 4968 4969; df -> unsigned di 4970(define_insn "*fixuns_truncdfdi2_vx" 4971 [(set (match_operand:DI 0 "register_operand" "=d,v") 4972 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f,v"))) 4973 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) 4974 (clobber (reg:CC CC_REGNUM))] 4975 "TARGET_VX && TARGET_HARD_FLOAT" 4976 "@ 4977 clgdbr\t%0,%h2,%1,0 4978 wclgdb\t%v0,%v1,0,%h2" 4979 [(set_attr "op_type" "RRF,VRR") 4980 (set_attr "type" "ftoi")]) 4981 4982; (dd|td|sf|df|tf)->unsigned (di|si) 4983; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr 4984; clfdtr, clfxtr, clgdtr, clgxtr 4985(define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196" 4986 [(set (match_operand:GPR 0 "register_operand" "=d") 4987 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f"))) 4988 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) 4989 (clobber (reg:CC CC_REGNUM))] 4990 "TARGET_Z196 && TARGET_HARD_FLOAT 4991 && (!TARGET_VX || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)" 4992 "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0" 4993 [(set_attr "op_type" "RRF") 4994 (set_attr "type" "ftoi")]) 4995 4996(define_expand "fix_trunc<DSF:mode><GPR:mode>2" 4997 [(set (match_operand:GPR 0 "register_operand" "") 4998 (fix:GPR (match_operand:DSF 1 "register_operand" "")))] 4999 "TARGET_HARD_FLOAT" 5000{ 5001 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1], 5002 GEN_INT (BFP_RND_TOWARD_0))); 5003 DONE; 5004}) 5005 5006(define_insn "*fix_truncdfdi2_bfp_z13" 5007 [(set (match_operand:DI 0 "register_operand" "=d,v") 5008 (fix:DI (match_operand:DF 1 "register_operand" "f,v"))) 5009 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) 5010 (clobber (reg:CC CC_REGNUM))] 5011 "TARGET_VX && TARGET_HARD_FLOAT" 5012 "@ 5013 cgdbr\t%0,%h2,%1 5014 wcgdb\t%v0,%v1,0,%h2" 5015 [(set_attr "op_type" "RRE,VRR") 5016 (set_attr "type" "ftoi")]) 5017 5018; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr 5019(define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp" 5020 [(set (match_operand:GPR 0 "register_operand" "=d") 5021 (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) 5022 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) 5023 (clobber (reg:CC CC_REGNUM))] 5024 "TARGET_HARD_FLOAT 5025 && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)" 5026 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1" 5027 [(set_attr "op_type" "RRE") 5028 (set_attr "type" "ftoi")]) 5029 5030(define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp" 5031 [(parallel 5032 [(set (match_operand:GPR 0 "register_operand" "=d") 5033 (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) 5034 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) 5035 (clobber (reg:CC CC_REGNUM))])] 5036 "TARGET_HARD_FLOAT") 5037; 5038; fix_trunc(td|dd)di2 instruction pattern(s). 5039; 5040 5041(define_expand "fix_trunc<mode>di2" 5042 [(set (match_operand:DI 0 "register_operand" "") 5043 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))] 5044 "TARGET_ZARCH && TARGET_HARD_DFP" 5045{ 5046 operands[1] = force_reg (<MODE>mode, operands[1]); 5047 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1], 5048 GEN_INT (DFP_RND_TOWARD_0))); 5049 DONE; 5050}) 5051 5052; cgxtr, cgdtr 5053(define_insn "fix_trunc<DFP:mode>di2_dfp" 5054 [(set (match_operand:DI 0 "register_operand" "=d") 5055 (fix:DI (match_operand:DFP 1 "register_operand" "f"))) 5056 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) 5057 (clobber (reg:CC CC_REGNUM))] 5058 "TARGET_ZARCH && TARGET_HARD_DFP" 5059 "cg<DFP:xde>tr\t%0,%h2,%1" 5060 [(set_attr "op_type" "RRF") 5061 (set_attr "type" "ftoidfp")]) 5062 5063 5064; 5065; fix_trunctf(si|di)2 instruction pattern(s). 5066; 5067 5068(define_expand "fix_trunctf<mode>2" 5069 [(parallel [(set (match_operand:GPR 0 "register_operand" "") 5070 (fix:GPR (match_operand:TF 1 "register_operand" ""))) 5071 (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) 5072 (clobber (reg:CC CC_REGNUM))])] 5073 "TARGET_HARD_FLOAT" 5074 "") 5075 5076 5077; 5078; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). 5079; 5080 5081; cxgbr, cdgbr, cegbr, cxgtr, cdgtr 5082(define_insn "floatdi<mode>2" 5083 [(set (match_operand:FP 0 "register_operand" "=f,v") 5084 (float:FP (match_operand:DI 1 "register_operand" "d,v")))] 5085 "TARGET_ZARCH && TARGET_HARD_FLOAT" 5086 "@ 5087 c<xde>g<bt>r\t%0,%1 5088 wcdgb\t%v0,%v1,0,0" 5089 [(set_attr "op_type" "RRE,VRR") 5090 (set_attr "type" "itof<mode>" ) 5091 (set_attr "cpu_facility" "*,vx") 5092 (set_attr "enabled" "*,<DFDI>")]) 5093 5094; cxfbr, cdfbr, cefbr 5095(define_insn "floatsi<mode>2" 5096 [(set (match_operand:BFP 0 "register_operand" "=f") 5097 (float:BFP (match_operand:SI 1 "register_operand" "d")))] 5098 "TARGET_HARD_FLOAT" 5099 "c<xde>fbr\t%0,%1" 5100 [(set_attr "op_type" "RRE") 5101 (set_attr "type" "itof<mode>" )]) 5102 5103; cxftr, cdftr 5104(define_insn "floatsi<mode>2" 5105 [(set (match_operand:DFP 0 "register_operand" "=f") 5106 (float:DFP (match_operand:SI 1 "register_operand" "d")))] 5107 "TARGET_Z196 && TARGET_HARD_FLOAT" 5108 "c<xde>ftr\t%0,0,%1,0" 5109 [(set_attr "op_type" "RRE") 5110 (set_attr "type" "itof<mode>" )]) 5111 5112; 5113; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). 5114; 5115 5116(define_insn "*floatunsdidf2_z13" 5117 [(set (match_operand:DF 0 "register_operand" "=f,v") 5118 (unsigned_float:DF (match_operand:DI 1 "register_operand" "d,v")))] 5119 "TARGET_VX && TARGET_HARD_FLOAT" 5120 "@ 5121 cdlgbr\t%0,0,%1,0 5122 wcdlgb\t%v0,%v1,0,0" 5123 [(set_attr "op_type" "RRE,VRR") 5124 (set_attr "type" "itofdf")]) 5125 5126; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr 5127; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr 5128(define_insn "*floatuns<GPR:mode><FP:mode>2" 5129 [(set (match_operand:FP 0 "register_operand" "=f") 5130 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))] 5131 "TARGET_Z196 && TARGET_HARD_FLOAT 5132 && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)" 5133 "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0" 5134 [(set_attr "op_type" "RRE") 5135 (set_attr "type" "itof<FP:mode>")]) 5136 5137(define_expand "floatuns<GPR:mode><FP:mode>2" 5138 [(set (match_operand:FP 0 "register_operand" "") 5139 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))] 5140 "TARGET_Z196 && TARGET_HARD_FLOAT") 5141 5142; 5143; truncdfsf2 instruction pattern(s). 5144; 5145 5146(define_insn "truncdfsf2" 5147 [(set (match_operand:SF 0 "register_operand" "=f,v") 5148 (float_truncate:SF (match_operand:DF 1 "register_operand" "f,v")))] 5149 "TARGET_HARD_FLOAT" 5150 "@ 5151 ledbr\t%0,%1 5152 wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed 5153 ; According to BFP rounding mode 5154 [(set_attr "op_type" "RRE,VRR") 5155 (set_attr "type" "ftruncdf") 5156 (set_attr "cpu_facility" "*,vx")]) 5157 5158; 5159; trunctf(df|sf)2 instruction pattern(s). 5160; 5161 5162; ldxbr, lexbr 5163(define_insn "trunctf<mode>2" 5164 [(set (match_operand:DSF 0 "register_operand" "=f") 5165 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f"))) 5166 (clobber (match_scratch:TF 2 "=f"))] 5167 "TARGET_HARD_FLOAT" 5168 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2" 5169 [(set_attr "length" "6") 5170 (set_attr "type" "ftrunctf")]) 5171 5172; 5173; trunctddd2 and truncddsd2 instruction pattern(s). 5174; 5175 5176 5177(define_expand "trunctddd2" 5178 [(parallel 5179 [(set (match_operand:DD 0 "register_operand" "") 5180 (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) 5181 (unspec:DI [(const_int DFP_RND_CURRENT)] UNSPEC_ROUND) 5182 (clobber (scratch:TD))])] 5183 "TARGET_HARD_DFP") 5184 5185(define_insn "*trunctddd2" 5186 [(set (match_operand:DD 0 "register_operand" "=f") 5187 (float_truncate:DD (match_operand:TD 1 "register_operand" "f"))) 5188 (unspec:DI [(match_operand:DI 2 "const_mask_operand" "I")] UNSPEC_ROUND) 5189 (clobber (match_scratch:TD 3 "=f"))] 5190 "TARGET_HARD_DFP" 5191 "ldxtr\t%3,%2,%1,0\;ldr\t%0,%3" 5192 [(set_attr "length" "6") 5193 (set_attr "type" "ftruncdd")]) 5194 5195(define_insn "truncddsd2" 5196 [(set (match_operand:SD 0 "register_operand" "=f") 5197 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))] 5198 "TARGET_HARD_DFP" 5199 "ledtr\t%0,0,%1,0" 5200 [(set_attr "op_type" "RRF") 5201 (set_attr "type" "ftruncsd")]) 5202 5203(define_expand "trunctdsd2" 5204 [(parallel 5205 [(set (match_dup 2) 5206 (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) 5207 (unspec:DI [(const_int DFP_RND_PREP_FOR_SHORT_PREC)] UNSPEC_ROUND) 5208 (clobber (match_scratch:TD 3 ""))]) 5209 (set (match_operand:SD 0 "register_operand" "") 5210 (float_truncate:SD (match_dup 2)))] 5211 "TARGET_HARD_DFP" 5212{ 5213 operands[2] = gen_reg_rtx (DDmode); 5214}) 5215 5216; 5217; extend(sf|df)(df|tf)2 instruction pattern(s). 5218; 5219 5220; wflls 5221(define_insn "*extendsfdf2_z13" 5222 [(set (match_operand:DF 0 "register_operand" "=f,f,v") 5223 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R,v")))] 5224 "TARGET_VX && TARGET_HARD_FLOAT" 5225 "@ 5226 ldebr\t%0,%1 5227 ldeb\t%0,%1 5228 wldeb\t%v0,%v1" 5229 [(set_attr "op_type" "RRE,RXE,VRR") 5230 (set_attr "type" "fsimpdf, floaddf,fsimpdf")]) 5231 5232; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb 5233(define_insn "*extend<DSF:mode><BFP:mode>2" 5234 [(set (match_operand:BFP 0 "register_operand" "=f,f") 5235 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))] 5236 "TARGET_HARD_FLOAT 5237 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode) 5238 && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)" 5239 "@ 5240 l<BFP:xde><DSF:xde>br\t%0,%1 5241 l<BFP:xde><DSF:xde>b\t%0,%1" 5242 [(set_attr "op_type" "RRE,RXE") 5243 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")]) 5244 5245(define_expand "extend<DSF:mode><BFP:mode>2" 5246 [(set (match_operand:BFP 0 "register_operand" "") 5247 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))] 5248 "TARGET_HARD_FLOAT 5249 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)") 5250 5251; 5252; extendddtd2 and extendsddd2 instruction pattern(s). 5253; 5254 5255(define_insn "extendddtd2" 5256 [(set (match_operand:TD 0 "register_operand" "=f") 5257 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))] 5258 "TARGET_HARD_DFP" 5259 "lxdtr\t%0,%1,0" 5260 [(set_attr "op_type" "RRF") 5261 (set_attr "type" "fsimptf")]) 5262 5263(define_insn "extendsddd2" 5264 [(set (match_operand:DD 0 "register_operand" "=f") 5265 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))] 5266 "TARGET_HARD_DFP" 5267 "ldetr\t%0,%1,0" 5268 [(set_attr "op_type" "RRF") 5269 (set_attr "type" "fsimptf")]) 5270 5271(define_expand "extendsdtd2" 5272 [(set (match_dup 2) 5273 (float_extend:DD (match_operand:SD 1 "register_operand" ""))) 5274 (set (match_operand:TD 0 "register_operand" "") 5275 (float_extend:TD (match_dup 2)))] 5276 "TARGET_HARD_DFP" 5277{ 5278 operands[2] = gen_reg_rtx (DDmode); 5279}) 5280 5281; Binary Floating Point - load fp integer 5282 5283; Expanders for: floor, btrunc, round, ceil, and nearbyint 5284; For all of them the inexact exceptions are suppressed. 5285 5286; fiebra, fidbra, fixbra 5287(define_insn "<FPINT:fpint_name><BFP:mode>2" 5288 [(set (match_operand:BFP 0 "register_operand" "=f") 5289 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] 5290 FPINT))] 5291 "TARGET_Z196" 5292 "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4" 5293 [(set_attr "op_type" "RRF") 5294 (set_attr "type" "fsimp<BFP:mode>")]) 5295 5296; rint is supposed to raise an inexact exception so we can use the 5297; older instructions. 5298 5299; fiebr, fidbr, fixbr 5300(define_insn "rint<BFP:mode>2" 5301 [(set (match_operand:BFP 0 "register_operand" "=f") 5302 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] 5303 UNSPEC_FPINT_RINT))] 5304 "" 5305 "fi<BFP:xde>br\t%0,0,%1" 5306 [(set_attr "op_type" "RRF") 5307 (set_attr "type" "fsimp<BFP:mode>")]) 5308 5309 5310; Decimal Floating Point - load fp integer 5311 5312; fidtr, fixtr 5313(define_insn "<FPINT:fpint_name><DFP:mode>2" 5314 [(set (match_operand:DFP 0 "register_operand" "=f") 5315 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] 5316 FPINT))] 5317 "TARGET_HARD_DFP" 5318 "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4" 5319 [(set_attr "op_type" "RRF") 5320 (set_attr "type" "fsimp<DFP:mode>")]) 5321 5322; fidtr, fixtr 5323(define_insn "rint<DFP:mode>2" 5324 [(set (match_operand:DFP 0 "register_operand" "=f") 5325 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] 5326 UNSPEC_FPINT_RINT))] 5327 "TARGET_HARD_DFP" 5328 "fi<DFP:xde>tr\t%0,0,%1,0" 5329 [(set_attr "op_type" "RRF") 5330 (set_attr "type" "fsimp<DFP:mode>")]) 5331 5332; 5333; Binary <-> Decimal floating point trunc patterns 5334; 5335 5336(define_insn "*trunc<BFP:mode><DFP_ALL:mode>2" 5337 [(set (reg:DFP_ALL FPR0_REGNUM) 5338 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) 5339 (use (reg:SI GPR0_REGNUM)) 5340 (clobber (reg:CC CC_REGNUM)) 5341 (clobber (reg:SI GPR1_REGNUM))] 5342 "TARGET_HARD_DFP" 5343 "pfpo") 5344 5345(define_insn "*trunc<DFP_ALL:mode><BFP:mode>2" 5346 [(set (reg:BFP FPR0_REGNUM) 5347 (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) 5348 (use (reg:SI GPR0_REGNUM)) 5349 (clobber (reg:CC CC_REGNUM)) 5350 (clobber (reg:SI GPR1_REGNUM))] 5351 "TARGET_HARD_DFP" 5352 "pfpo") 5353 5354(define_expand "trunc<BFP:mode><DFP_ALL:mode>2" 5355 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) 5356 (set (reg:SI GPR0_REGNUM) (match_dup 2)) 5357 (parallel 5358 [(set (reg:DFP_ALL FPR0_REGNUM) 5359 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) 5360 (use (reg:SI GPR0_REGNUM)) 5361 (clobber (reg:CC CC_REGNUM)) 5362 (clobber (reg:SI GPR1_REGNUM))]) 5363 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") 5364 (reg:DFP_ALL FPR0_REGNUM))] 5365 "TARGET_HARD_DFP 5366 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)" 5367{ 5368 HOST_WIDE_INT flags; 5369 5370 /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the 5371 rounding mode of the target format needs to be used. */ 5372 5373 flags = (PFPO_CONVERT | 5374 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | 5375 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT | 5376 PFPO_RND_MODE_DFP); 5377 5378 operands[2] = GEN_INT (flags); 5379}) 5380 5381(define_expand "trunc<DFP_ALL:mode><BFP:mode>2" 5382 [(set (reg:DFP_ALL FPR4_REGNUM) 5383 (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) 5384 (set (reg:SI GPR0_REGNUM) (match_dup 2)) 5385 (parallel 5386 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) 5387 (use (reg:SI GPR0_REGNUM)) 5388 (clobber (reg:CC CC_REGNUM)) 5389 (clobber (reg:SI GPR1_REGNUM))]) 5390 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] 5391 "TARGET_HARD_DFP 5392 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)" 5393{ 5394 HOST_WIDE_INT flags; 5395 5396 /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the 5397 rounding mode of the target format needs to be used. */ 5398 5399 flags = (PFPO_CONVERT | 5400 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | 5401 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT | 5402 PFPO_RND_MODE_BFP); 5403 5404 operands[2] = GEN_INT (flags); 5405}) 5406 5407; 5408; Binary <-> Decimal floating point extend patterns 5409; 5410 5411(define_insn "*extend<BFP:mode><DFP_ALL:mode>2" 5412 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) 5413 (use (reg:SI GPR0_REGNUM)) 5414 (clobber (reg:CC CC_REGNUM)) 5415 (clobber (reg:SI GPR1_REGNUM))] 5416 "TARGET_HARD_DFP" 5417 "pfpo") 5418 5419(define_insn "*extend<DFP_ALL:mode><BFP:mode>2" 5420 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) 5421 (use (reg:SI GPR0_REGNUM)) 5422 (clobber (reg:CC CC_REGNUM)) 5423 (clobber (reg:SI GPR1_REGNUM))] 5424 "TARGET_HARD_DFP" 5425 "pfpo") 5426 5427(define_expand "extend<BFP:mode><DFP_ALL:mode>2" 5428 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) 5429 (set (reg:SI GPR0_REGNUM) (match_dup 2)) 5430 (parallel 5431 [(set (reg:DFP_ALL FPR0_REGNUM) 5432 (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) 5433 (use (reg:SI GPR0_REGNUM)) 5434 (clobber (reg:CC CC_REGNUM)) 5435 (clobber (reg:SI GPR1_REGNUM))]) 5436 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") 5437 (reg:DFP_ALL FPR0_REGNUM))] 5438 "TARGET_HARD_DFP 5439 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)" 5440{ 5441 HOST_WIDE_INT flags; 5442 5443 /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the 5444 rounding mode of the target format needs to be used. */ 5445 5446 flags = (PFPO_CONVERT | 5447 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | 5448 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT | 5449 PFPO_RND_MODE_DFP); 5450 5451 operands[2] = GEN_INT (flags); 5452}) 5453 5454(define_expand "extend<DFP_ALL:mode><BFP:mode>2" 5455 [(set (reg:DFP_ALL FPR4_REGNUM) 5456 (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) 5457 (set (reg:SI GPR0_REGNUM) (match_dup 2)) 5458 (parallel 5459 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) 5460 (use (reg:SI GPR0_REGNUM)) 5461 (clobber (reg:CC CC_REGNUM)) 5462 (clobber (reg:SI GPR1_REGNUM))]) 5463 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] 5464 "TARGET_HARD_DFP 5465 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)" 5466{ 5467 HOST_WIDE_INT flags; 5468 5469 /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the 5470 rounding mode of the target format needs to be used. */ 5471 5472 flags = (PFPO_CONVERT | 5473 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | 5474 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT | 5475 PFPO_RND_MODE_BFP); 5476 5477 operands[2] = GEN_INT (flags); 5478}) 5479 5480 5481;; 5482;; ARITHMETIC OPERATIONS 5483;; 5484; arithmetic operations set the ConditionCode, 5485; because of unpredictable Bits in Register for Halfword and Byte 5486; the ConditionCode can be set wrong in operations for Halfword and Byte 5487 5488;; 5489;;- Add instructions. 5490;; 5491 5492; 5493; addti3 instruction pattern(s). 5494; 5495 5496(define_expand "addti3" 5497 [(parallel 5498 [(set (match_operand:TI 0 "register_operand" "") 5499 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "") 5500 (match_operand:TI 2 "general_operand" "") ) ) 5501 (clobber (reg:CC CC_REGNUM))])] 5502 "TARGET_ZARCH" 5503{ 5504 /* For z13 we have vaq which doesn't set CC. */ 5505 if (TARGET_VX) 5506 { 5507 emit_insn (gen_rtx_SET (operands[0], 5508 gen_rtx_PLUS (TImode, 5509 copy_to_mode_reg (TImode, operands[1]), 5510 copy_to_mode_reg (TImode, operands[2])))); 5511 DONE; 5512 } 5513}) 5514 5515(define_insn_and_split "*addti3" 5516 [(set (match_operand:TI 0 "register_operand" "=&d") 5517 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") 5518 (match_operand:TI 2 "general_operand" "do") ) ) 5519 (clobber (reg:CC CC_REGNUM))] 5520 "TARGET_ZARCH" 5521 "#" 5522 "&& reload_completed" 5523 [(parallel 5524 [(set (reg:CCL1 CC_REGNUM) 5525 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) 5526 (match_dup 7))) 5527 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) 5528 (parallel 5529 [(set (match_dup 3) (plus:DI 5530 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)) 5531 (match_dup 4)) (match_dup 5))) 5532 (clobber (reg:CC CC_REGNUM))])] 5533 "operands[3] = operand_subword (operands[0], 0, 0, TImode); 5534 operands[4] = operand_subword (operands[1], 0, 0, TImode); 5535 operands[5] = operand_subword (operands[2], 0, 0, TImode); 5536 operands[6] = operand_subword (operands[0], 1, 0, TImode); 5537 operands[7] = operand_subword (operands[1], 1, 0, TImode); 5538 operands[8] = operand_subword (operands[2], 1, 0, TImode);" 5539 [(set_attr "op_type" "*") 5540 (set_attr "cpu_facility" "*")]) 5541 5542; 5543; adddi3 instruction pattern(s). 5544; 5545 5546(define_expand "adddi3" 5547 [(parallel 5548 [(set (match_operand:DI 0 "nonimmediate_operand" "") 5549 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") 5550 (match_operand:DI 2 "general_operand" ""))) 5551 (clobber (reg:CC CC_REGNUM))])] 5552 "" 5553 "") 5554 5555(define_insn "*adddi3_sign" 5556 [(set (match_operand:DI 0 "register_operand" "=d,d") 5557 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")) 5558 (match_operand:DI 1 "register_operand" "0,0"))) 5559 (clobber (reg:CC CC_REGNUM))] 5560 "TARGET_ZARCH" 5561 "@ 5562 agfr\t%0,%2 5563 agf\t%0,%2" 5564 [(set_attr "op_type" "RRE,RXY") 5565 (set_attr "z196prop" "z196_cracked,z196_cracked")]) 5566 5567(define_insn "*adddi3_zero_cc" 5568 [(set (reg CC_REGNUM) 5569 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) 5570 (match_operand:DI 1 "register_operand" "0,0")) 5571 (const_int 0))) 5572 (set (match_operand:DI 0 "register_operand" "=d,d") 5573 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] 5574 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" 5575 "@ 5576 algfr\t%0,%2 5577 algf\t%0,%2" 5578 [(set_attr "op_type" "RRE,RXY") 5579 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 5580 5581(define_insn "*adddi3_zero_cconly" 5582 [(set (reg CC_REGNUM) 5583 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) 5584 (match_operand:DI 1 "register_operand" "0,0")) 5585 (const_int 0))) 5586 (clobber (match_scratch:DI 0 "=d,d"))] 5587 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" 5588 "@ 5589 algfr\t%0,%2 5590 algf\t%0,%2" 5591 [(set_attr "op_type" "RRE,RXY") 5592 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 5593 5594(define_insn "*adddi3_zero" 5595 [(set (match_operand:DI 0 "register_operand" "=d,d") 5596 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) 5597 (match_operand:DI 1 "register_operand" "0,0"))) 5598 (clobber (reg:CC CC_REGNUM))] 5599 "TARGET_ZARCH" 5600 "@ 5601 algfr\t%0,%2 5602 algf\t%0,%2" 5603 [(set_attr "op_type" "RRE,RXY") 5604 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 5605 5606(define_insn_and_split "*adddi3_31z" 5607 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") 5608 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") 5609 (match_operand:DI 2 "general_operand" "do") ) ) 5610 (clobber (reg:CC CC_REGNUM))] 5611 "!TARGET_ZARCH && TARGET_CPU_ZARCH" 5612 "#" 5613 "&& reload_completed" 5614 [(parallel 5615 [(set (reg:CCL1 CC_REGNUM) 5616 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) 5617 (match_dup 7))) 5618 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) 5619 (parallel 5620 [(set (match_dup 3) (plus:SI 5621 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)) 5622 (match_dup 4)) (match_dup 5))) 5623 (clobber (reg:CC CC_REGNUM))])] 5624 "operands[3] = operand_subword (operands[0], 0, 0, DImode); 5625 operands[4] = operand_subword (operands[1], 0, 0, DImode); 5626 operands[5] = operand_subword (operands[2], 0, 0, DImode); 5627 operands[6] = operand_subword (operands[0], 1, 0, DImode); 5628 operands[7] = operand_subword (operands[1], 1, 0, DImode); 5629 operands[8] = operand_subword (operands[2], 1, 0, DImode);") 5630 5631(define_insn_and_split "*adddi3_31" 5632 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") 5633 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") 5634 (match_operand:DI 2 "general_operand" "do") ) ) 5635 (clobber (reg:CC CC_REGNUM))] 5636 "!TARGET_CPU_ZARCH" 5637 "#" 5638 "&& reload_completed" 5639 [(parallel 5640 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) 5641 (clobber (reg:CC CC_REGNUM))]) 5642 (parallel 5643 [(set (reg:CCL1 CC_REGNUM) 5644 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) 5645 (match_dup 7))) 5646 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) 5647 (set (pc) 5648 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0)) 5649 (pc) 5650 (label_ref (match_dup 9)))) 5651 (parallel 5652 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) 5653 (clobber (reg:CC CC_REGNUM))]) 5654 (match_dup 9)] 5655 "operands[3] = operand_subword (operands[0], 0, 0, DImode); 5656 operands[4] = operand_subword (operands[1], 0, 0, DImode); 5657 operands[5] = operand_subword (operands[2], 0, 0, DImode); 5658 operands[6] = operand_subword (operands[0], 1, 0, DImode); 5659 operands[7] = operand_subword (operands[1], 1, 0, DImode); 5660 operands[8] = operand_subword (operands[2], 1, 0, DImode); 5661 operands[9] = gen_label_rtx ();") 5662 5663; 5664; addsi3 instruction pattern(s). 5665; 5666 5667(define_expand "addsi3" 5668 [(parallel 5669 [(set (match_operand:SI 0 "nonimmediate_operand" "") 5670 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") 5671 (match_operand:SI 2 "general_operand" ""))) 5672 (clobber (reg:CC CC_REGNUM))])] 5673 "" 5674 "") 5675 5676(define_insn "*addsi3_sign" 5677 [(set (match_operand:SI 0 "register_operand" "=d,d") 5678 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) 5679 (match_operand:SI 1 "register_operand" "0,0"))) 5680 (clobber (reg:CC CC_REGNUM))] 5681 "" 5682 "@ 5683 ah\t%0,%2 5684 ahy\t%0,%2" 5685 [(set_attr "op_type" "RX,RXY") 5686 (set_attr "cpu_facility" "*,longdisp") 5687 (set_attr "z196prop" "z196_cracked,z196_cracked")]) 5688 5689; 5690; add(di|si)3 instruction pattern(s). 5691; 5692 5693; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi 5694(define_insn "*add<mode>3" 5695 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,S") 5696 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0,0") 5697 (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T,C") ) ) 5698 (clobber (reg:CC CC_REGNUM))] 5699 "" 5700 "@ 5701 a<g>r\t%0,%2 5702 a<g>rk\t%0,%1,%2 5703 a<g>hi\t%0,%h2 5704 a<g>hik\t%0,%1,%h2 5705 al<g>fi\t%0,%2 5706 sl<g>fi\t%0,%n2 5707 a<g>\t%0,%2 5708 a<y>\t%0,%2 5709 a<g>si\t%0,%c2" 5710 [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY") 5711 (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,longdisp,z10") 5712 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1, 5713 z10_super_E1,z10_super_E1,z10_super_E1")]) 5714 5715; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik 5716(define_insn "*add<mode>3_carry1_cc" 5717 [(set (reg CC_REGNUM) 5718 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") 5719 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) 5720 (match_dup 1))) 5721 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d") 5722 (plus:GPR (match_dup 1) (match_dup 2)))] 5723 "s390_match_ccmode (insn, CCL1mode)" 5724 "@ 5725 al<g>r\t%0,%2 5726 al<g>rk\t%0,%1,%2 5727 al<g>fi\t%0,%2 5728 sl<g>fi\t%0,%n2 5729 al<g>hsik\t%0,%1,%h2 5730 al<g>\t%0,%2 5731 al<y>\t%0,%2 5732 al<g>si\t%0,%c2" 5733 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") 5734 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") 5735 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, 5736 z10_super_E1,z10_super_E1,z10_super_E1")]) 5737 5738; alr, al, aly, algr, alg, alrk, algrk 5739(define_insn "*add<mode>3_carry1_cconly" 5740 [(set (reg CC_REGNUM) 5741 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") 5742 (match_operand:GPR 2 "general_operand" "d,d,R,T")) 5743 (match_dup 1))) 5744 (clobber (match_scratch:GPR 0 "=d,d,d,d"))] 5745 "s390_match_ccmode (insn, CCL1mode)" 5746 "@ 5747 al<g>r\t%0,%2 5748 al<g>rk\t%0,%1,%2 5749 al<g>\t%0,%2 5750 al<y>\t%0,%2" 5751 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 5752 (set_attr "cpu_facility" "*,z196,*,longdisp") 5753 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) 5754 5755; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik 5756(define_insn "*add<mode>3_carry2_cc" 5757 [(set (reg CC_REGNUM) 5758 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") 5759 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) 5760 (match_dup 2))) 5761 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") 5762 (plus:GPR (match_dup 1) (match_dup 2)))] 5763 "s390_match_ccmode (insn, CCL1mode)" 5764 "@ 5765 al<g>r\t%0,%2 5766 al<g>rk\t%0,%1,%2 5767 al<g>fi\t%0,%2 5768 sl<g>fi\t%0,%n2 5769 al<g>hsik\t%0,%1,%h2 5770 al<g>\t%0,%2 5771 al<y>\t%0,%2 5772 al<g>si\t%0,%c2" 5773 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") 5774 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") 5775 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, 5776 z10_super_E1,z10_super_E1,z10_super_E1")]) 5777 5778; alr, al, aly, algr, alg, alrk, algrk 5779(define_insn "*add<mode>3_carry2_cconly" 5780 [(set (reg CC_REGNUM) 5781 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") 5782 (match_operand:GPR 2 "general_operand" "d,d,R,T")) 5783 (match_dup 2))) 5784 (clobber (match_scratch:GPR 0 "=d,d,d,d"))] 5785 "s390_match_ccmode (insn, CCL1mode)" 5786 "@ 5787 al<g>r\t%0,%2 5788 al<g>rk\t%0,%1,%2 5789 al<g>\t%0,%2 5790 al<y>\t%0,%2" 5791 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 5792 (set_attr "cpu_facility" "*,z196,*,longdisp") 5793 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) 5794 5795; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik 5796(define_insn "*add<mode>3_cc" 5797 [(set (reg CC_REGNUM) 5798 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") 5799 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) 5800 (const_int 0))) 5801 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") 5802 (plus:GPR (match_dup 1) (match_dup 2)))] 5803 "s390_match_ccmode (insn, CCLmode)" 5804 "@ 5805 al<g>r\t%0,%2 5806 al<g>rk\t%0,%1,%2 5807 al<g>fi\t%0,%2 5808 sl<g>fi\t%0,%n2 5809 al<g>hsik\t%0,%1,%h2 5810 al<g>\t%0,%2 5811 al<y>\t%0,%2 5812 al<g>si\t%0,%c2" 5813 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") 5814 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") 5815 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1, 5816 *,z10_super_E1,z10_super_E1,z10_super_E1")]) 5817 5818; alr, al, aly, algr, alg, alrk, algrk 5819(define_insn "*add<mode>3_cconly" 5820 [(set (reg CC_REGNUM) 5821 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") 5822 (match_operand:GPR 2 "general_operand" "d,d,R,T")) 5823 (const_int 0))) 5824 (clobber (match_scratch:GPR 0 "=d,d,d,d"))] 5825 "s390_match_ccmode (insn, CCLmode)" 5826 "@ 5827 al<g>r\t%0,%2 5828 al<g>rk\t%0,%1,%2 5829 al<g>\t%0,%2 5830 al<y>\t%0,%2" 5831 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 5832 (set_attr "cpu_facility" "*,z196,*,longdisp") 5833 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) 5834 5835; alr, al, aly, algr, alg, alrk, algrk 5836(define_insn "*add<mode>3_cconly2" 5837 [(set (reg CC_REGNUM) 5838 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") 5839 (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T")))) 5840 (clobber (match_scratch:GPR 0 "=d,d,d,d"))] 5841 "s390_match_ccmode(insn, CCLmode)" 5842 "@ 5843 al<g>r\t%0,%2 5844 al<g>rk\t%0,%1,%2 5845 al<g>\t%0,%2 5846 al<y>\t%0,%2" 5847 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 5848 (set_attr "cpu_facility" "*,z196,*,longdisp") 5849 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) 5850 5851; ahi, afi, aghi, agfi, asi, agsi 5852(define_insn "*add<mode>3_imm_cc" 5853 [(set (reg CC_REGNUM) 5854 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0") 5855 (match_operand:GPR 2 "const_int_operand" " K, K,Os,C")) 5856 (const_int 0))) 5857 (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d, S") 5858 (plus:GPR (match_dup 1) (match_dup 2)))] 5859 "s390_match_ccmode (insn, CCAmode) 5860 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") 5861 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") 5862 /* Avoid INT32_MIN on 32 bit. */ 5863 && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))" 5864 "@ 5865 a<g>hi\t%0,%h2 5866 a<g>hik\t%0,%1,%h2 5867 a<g>fi\t%0,%2 5868 a<g>si\t%0,%c2" 5869 [(set_attr "op_type" "RI,RIE,RIL,SIY") 5870 (set_attr "cpu_facility" "*,z196,extimm,z10") 5871 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) 5872 5873(define_insn "*adddi3_sign" 5874 [(set (match_operand:DI 0 "register_operand" "=d") 5875 (plus:DI (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")) 5876 (match_operand:DI 1 "register_operand" "0"))) 5877 (clobber (reg:CC CC_REGNUM))] 5878 "TARGET_ARCH12" 5879 "agh\t%0,%2" 5880 [(set_attr "op_type" "RXY")]) 5881 5882; 5883; add(tf|df|sf|td|dd)3 instruction pattern(s). 5884; 5885 5886; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr 5887; FIXME: wfadb does not clobber cc 5888(define_insn "add<mode>3" 5889 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") 5890 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v,v") 5891 (match_operand:FP 2 "general_operand" "f,f,R,v,v"))) 5892 (clobber (reg:CC CC_REGNUM))] 5893 "TARGET_HARD_FLOAT" 5894 "@ 5895 a<xde>tr\t%0,%1,%2 5896 a<xde>br\t%0,%2 5897 a<xde>b\t%0,%2 5898 wfadb\t%v0,%v1,%v2 5899 wfasb\t%v0,%v1,%v2" 5900 [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") 5901 (set_attr "type" "fsimp<mode>") 5902 (set_attr "cpu_facility" "*,*,*,vx,vxe") 5903 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) 5904 5905; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr 5906(define_insn "*add<mode>3_cc" 5907 [(set (reg CC_REGNUM) 5908 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") 5909 (match_operand:FP 2 "general_operand" "f,f,R")) 5910 (match_operand:FP 3 "const0_operand" ""))) 5911 (set (match_operand:FP 0 "register_operand" "=f,f,f") 5912 (plus:FP (match_dup 1) (match_dup 2)))] 5913 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 5914 "@ 5915 a<xde>tr\t%0,%1,%2 5916 a<xde>br\t%0,%2 5917 a<xde>b\t%0,%2" 5918 [(set_attr "op_type" "RRF,RRE,RXE") 5919 (set_attr "type" "fsimp<mode>") 5920 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) 5921 5922; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr 5923(define_insn "*add<mode>3_cconly" 5924 [(set (reg CC_REGNUM) 5925 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") 5926 (match_operand:FP 2 "general_operand" "f,f,R")) 5927 (match_operand:FP 3 "const0_operand" ""))) 5928 (clobber (match_scratch:FP 0 "=f,f,f"))] 5929 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 5930 "@ 5931 a<xde>tr\t%0,%1,%2 5932 a<xde>br\t%0,%2 5933 a<xde>b\t%0,%2" 5934 [(set_attr "op_type" "RRF,RRE,RXE") 5935 (set_attr "type" "fsimp<mode>") 5936 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) 5937 5938; 5939; Pointer add instruction patterns 5940; 5941 5942; This will match "*la_64" 5943(define_expand "addptrdi3" 5944 [(set (match_operand:DI 0 "register_operand" "") 5945 (plus:DI (match_operand:DI 1 "register_operand" "") 5946 (match_operand:DI 2 "nonmemory_operand" "")))] 5947 "TARGET_64BIT" 5948{ 5949 if (GET_CODE (operands[2]) == CONST_INT) 5950 { 5951 HOST_WIDE_INT c = INTVAL (operands[2]); 5952 5953 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") 5954 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) 5955 { 5956 operands[2] = force_const_mem (DImode, operands[2]); 5957 operands[2] = force_reg (DImode, operands[2]); 5958 } 5959 else if (!DISP_IN_RANGE (INTVAL (operands[2]))) 5960 operands[2] = force_reg (DImode, operands[2]); 5961 } 5962}) 5963 5964; For 31 bit we have to prevent the generated pattern from matching 5965; normal ADDs since la only does a 31 bit add. This is supposed to 5966; match "force_la_31". 5967(define_expand "addptrsi3" 5968 [(parallel 5969 [(set (match_operand:SI 0 "register_operand" "") 5970 (plus:SI (match_operand:SI 1 "register_operand" "") 5971 (match_operand:SI 2 "nonmemory_operand" ""))) 5972 (use (const_int 0))])] 5973 "!TARGET_64BIT" 5974{ 5975 if (GET_CODE (operands[2]) == CONST_INT) 5976 { 5977 HOST_WIDE_INT c = INTVAL (operands[2]); 5978 5979 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") 5980 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) 5981 { 5982 operands[2] = force_const_mem (SImode, operands[2]); 5983 operands[2] = force_reg (SImode, operands[2]); 5984 } 5985 else if (!DISP_IN_RANGE (INTVAL (operands[2]))) 5986 operands[2] = force_reg (SImode, operands[2]); 5987 } 5988}) 5989 5990;; 5991;;- Subtract instructions. 5992;; 5993 5994; 5995; subti3 instruction pattern(s). 5996; 5997 5998(define_expand "subti3" 5999 [(parallel 6000 [(set (match_operand:TI 0 "register_operand" "") 6001 (minus:TI (match_operand:TI 1 "register_operand" "") 6002 (match_operand:TI 2 "general_operand" "") ) ) 6003 (clobber (reg:CC CC_REGNUM))])] 6004 "TARGET_ZARCH" 6005{ 6006 /* For z13 we have vsq which doesn't set CC. */ 6007 if (TARGET_VX) 6008 { 6009 emit_insn (gen_rtx_SET (operands[0], 6010 gen_rtx_MINUS (TImode, 6011 operands[1], 6012 copy_to_mode_reg (TImode, operands[2])))); 6013 DONE; 6014 } 6015}) 6016 6017(define_insn_and_split "*subti3" 6018 [(set (match_operand:TI 0 "register_operand" "=&d") 6019 (minus:TI (match_operand:TI 1 "register_operand" "0") 6020 (match_operand:TI 2 "general_operand" "do") ) ) 6021 (clobber (reg:CC CC_REGNUM))] 6022 "TARGET_ZARCH" 6023 "#" 6024 "&& reload_completed" 6025 [(parallel 6026 [(set (reg:CCL2 CC_REGNUM) 6027 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) 6028 (match_dup 7))) 6029 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) 6030 (parallel 6031 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) 6032 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) 6033 (clobber (reg:CC CC_REGNUM))])] 6034 "operands[3] = operand_subword (operands[0], 0, 0, TImode); 6035 operands[4] = operand_subword (operands[1], 0, 0, TImode); 6036 operands[5] = operand_subword (operands[2], 0, 0, TImode); 6037 operands[6] = operand_subword (operands[0], 1, 0, TImode); 6038 operands[7] = operand_subword (operands[1], 1, 0, TImode); 6039 operands[8] = operand_subword (operands[2], 1, 0, TImode);" 6040 [(set_attr "op_type" "*") 6041 (set_attr "cpu_facility" "*")]) 6042 6043; 6044; subdi3 instruction pattern(s). 6045; 6046 6047(define_expand "subdi3" 6048 [(parallel 6049 [(set (match_operand:DI 0 "register_operand" "") 6050 (minus:DI (match_operand:DI 1 "register_operand" "") 6051 (match_operand:DI 2 "general_operand" ""))) 6052 (clobber (reg:CC CC_REGNUM))])] 6053 "" 6054 "") 6055 6056(define_insn "*subdi3_sign" 6057 [(set (match_operand:DI 0 "register_operand" "=d,d") 6058 (minus:DI (match_operand:DI 1 "register_operand" "0,0") 6059 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")))) 6060 (clobber (reg:CC CC_REGNUM))] 6061 "TARGET_ZARCH" 6062 "@ 6063 sgfr\t%0,%2 6064 sgf\t%0,%2" 6065 [(set_attr "op_type" "RRE,RXY") 6066 (set_attr "z10prop" "z10_c,*") 6067 (set_attr "z196prop" "z196_cracked")]) 6068 6069(define_insn "*subdi3_zero_cc" 6070 [(set (reg CC_REGNUM) 6071 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") 6072 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))) 6073 (const_int 0))) 6074 (set (match_operand:DI 0 "register_operand" "=d,d") 6075 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] 6076 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" 6077 "@ 6078 slgfr\t%0,%2 6079 slgf\t%0,%2" 6080 [(set_attr "op_type" "RRE,RXY") 6081 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) 6082 6083(define_insn "*subdi3_zero_cconly" 6084 [(set (reg CC_REGNUM) 6085 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") 6086 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))) 6087 (const_int 0))) 6088 (clobber (match_scratch:DI 0 "=d,d"))] 6089 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" 6090 "@ 6091 slgfr\t%0,%2 6092 slgf\t%0,%2" 6093 [(set_attr "op_type" "RRE,RXY") 6094 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) 6095 6096(define_insn "*subdi3_zero" 6097 [(set (match_operand:DI 0 "register_operand" "=d,d") 6098 (minus:DI (match_operand:DI 1 "register_operand" "0,0") 6099 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))) 6100 (clobber (reg:CC CC_REGNUM))] 6101 "TARGET_ZARCH" 6102 "@ 6103 slgfr\t%0,%2 6104 slgf\t%0,%2" 6105 [(set_attr "op_type" "RRE,RXY") 6106 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) 6107 6108(define_insn_and_split "*subdi3_31z" 6109 [(set (match_operand:DI 0 "register_operand" "=&d") 6110 (minus:DI (match_operand:DI 1 "register_operand" "0") 6111 (match_operand:DI 2 "general_operand" "do") ) ) 6112 (clobber (reg:CC CC_REGNUM))] 6113 "!TARGET_ZARCH && TARGET_CPU_ZARCH" 6114 "#" 6115 "&& reload_completed" 6116 [(parallel 6117 [(set (reg:CCL2 CC_REGNUM) 6118 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) 6119 (match_dup 7))) 6120 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) 6121 (parallel 6122 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) 6123 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) 6124 (clobber (reg:CC CC_REGNUM))])] 6125 "operands[3] = operand_subword (operands[0], 0, 0, DImode); 6126 operands[4] = operand_subword (operands[1], 0, 0, DImode); 6127 operands[5] = operand_subword (operands[2], 0, 0, DImode); 6128 operands[6] = operand_subword (operands[0], 1, 0, DImode); 6129 operands[7] = operand_subword (operands[1], 1, 0, DImode); 6130 operands[8] = operand_subword (operands[2], 1, 0, DImode);") 6131 6132(define_insn_and_split "*subdi3_31" 6133 [(set (match_operand:DI 0 "register_operand" "=&d") 6134 (minus:DI (match_operand:DI 1 "register_operand" "0") 6135 (match_operand:DI 2 "general_operand" "do") ) ) 6136 (clobber (reg:CC CC_REGNUM))] 6137 "!TARGET_CPU_ZARCH" 6138 "#" 6139 "&& reload_completed" 6140 [(parallel 6141 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) 6142 (clobber (reg:CC CC_REGNUM))]) 6143 (parallel 6144 [(set (reg:CCL2 CC_REGNUM) 6145 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) 6146 (match_dup 7))) 6147 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) 6148 (set (pc) 6149 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0)) 6150 (pc) 6151 (label_ref (match_dup 9)))) 6152 (parallel 6153 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) 6154 (clobber (reg:CC CC_REGNUM))]) 6155 (match_dup 9)] 6156 "operands[3] = operand_subword (operands[0], 0, 0, DImode); 6157 operands[4] = operand_subword (operands[1], 0, 0, DImode); 6158 operands[5] = operand_subword (operands[2], 0, 0, DImode); 6159 operands[6] = operand_subword (operands[0], 1, 0, DImode); 6160 operands[7] = operand_subword (operands[1], 1, 0, DImode); 6161 operands[8] = operand_subword (operands[2], 1, 0, DImode); 6162 operands[9] = gen_label_rtx ();") 6163 6164; 6165; subsi3 instruction pattern(s). 6166; 6167 6168(define_expand "subsi3" 6169 [(parallel 6170 [(set (match_operand:SI 0 "register_operand" "") 6171 (minus:SI (match_operand:SI 1 "register_operand" "") 6172 (match_operand:SI 2 "general_operand" ""))) 6173 (clobber (reg:CC CC_REGNUM))])] 6174 "" 6175 "") 6176 6177(define_insn "*subsi3_sign" 6178 [(set (match_operand:SI 0 "register_operand" "=d,d") 6179 (minus:SI (match_operand:SI 1 "register_operand" "0,0") 6180 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) 6181 (clobber (reg:CC CC_REGNUM))] 6182 "" 6183 "@ 6184 sh\t%0,%2 6185 shy\t%0,%2" 6186 [(set_attr "op_type" "RX,RXY") 6187 (set_attr "cpu_facility" "*,longdisp") 6188 (set_attr "z196prop" "z196_cracked,z196_cracked")]) 6189 6190; 6191; sub(di|si)3 instruction pattern(s). 6192; 6193 6194; sr, s, sy, sgr, sg, srk, sgrk 6195(define_insn "*sub<mode>3" 6196 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") 6197 (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") 6198 (match_operand:GPR 2 "general_operand" "d,d,R,T") ) ) 6199 (clobber (reg:CC CC_REGNUM))] 6200 "" 6201 "@ 6202 s<g>r\t%0,%2 6203 s<g>rk\t%0,%1,%2 6204 s<g>\t%0,%2 6205 s<y>\t%0,%2" 6206 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 6207 (set_attr "cpu_facility" "*,z196,*,longdisp") 6208 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) 6209 6210; slr, sl, sly, slgr, slg, slrk, slgrk 6211(define_insn "*sub<mode>3_borrow_cc" 6212 [(set (reg CC_REGNUM) 6213 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") 6214 (match_operand:GPR 2 "general_operand" "d,d,R,T")) 6215 (match_dup 1))) 6216 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") 6217 (minus:GPR (match_dup 1) (match_dup 2)))] 6218 "s390_match_ccmode (insn, CCL2mode)" 6219 "@ 6220 sl<g>r\t%0,%2 6221 sl<g>rk\t%0,%1,%2 6222 sl<g>\t%0,%2 6223 sl<y>\t%0,%2" 6224 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 6225 (set_attr "cpu_facility" "*,z196,*,longdisp") 6226 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) 6227 6228; slr, sl, sly, slgr, slg, slrk, slgrk 6229(define_insn "*sub<mode>3_borrow_cconly" 6230 [(set (reg CC_REGNUM) 6231 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") 6232 (match_operand:GPR 2 "general_operand" "d,d,R,T")) 6233 (match_dup 1))) 6234 (clobber (match_scratch:GPR 0 "=d,d,d,d"))] 6235 "s390_match_ccmode (insn, CCL2mode)" 6236 "@ 6237 sl<g>r\t%0,%2 6238 sl<g>rk\t%0,%1,%2 6239 sl<g>\t%0,%2 6240 sl<y>\t%0,%2" 6241 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 6242 (set_attr "cpu_facility" "*,z196,*,longdisp") 6243 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) 6244 6245; slr, sl, sly, slgr, slg, slrk, slgrk 6246(define_insn "*sub<mode>3_cc" 6247 [(set (reg CC_REGNUM) 6248 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") 6249 (match_operand:GPR 2 "general_operand" "d,d,R,T")) 6250 (const_int 0))) 6251 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") 6252 (minus:GPR (match_dup 1) (match_dup 2)))] 6253 "s390_match_ccmode (insn, CCLmode)" 6254 "@ 6255 sl<g>r\t%0,%2 6256 sl<g>rk\t%0,%1,%2 6257 sl<g>\t%0,%2 6258 sl<y>\t%0,%2" 6259 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 6260 (set_attr "cpu_facility" "*,z196,*,longdisp") 6261 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) 6262 6263; slr, sl, sly, slgr, slg, slrk, slgrk 6264(define_insn "*sub<mode>3_cc2" 6265 [(set (reg CC_REGNUM) 6266 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") 6267 (match_operand:GPR 2 "general_operand" "d,d,R,T"))) 6268 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") 6269 (minus:GPR (match_dup 1) (match_dup 2)))] 6270 "s390_match_ccmode (insn, CCL3mode)" 6271 "@ 6272 sl<g>r\t%0,%2 6273 sl<g>rk\t%0,%1,%2 6274 sl<g>\t%0,%2 6275 sl<y>\t%0,%2" 6276 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 6277 (set_attr "cpu_facility" "*,z196,*,longdisp") 6278 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) 6279 6280; slr, sl, sly, slgr, slg, slrk, slgrk 6281(define_insn "*sub<mode>3_cconly" 6282 [(set (reg CC_REGNUM) 6283 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") 6284 (match_operand:GPR 2 "general_operand" "d,d,R,T")) 6285 (const_int 0))) 6286 (clobber (match_scratch:GPR 0 "=d,d,d,d"))] 6287 "s390_match_ccmode (insn, CCLmode)" 6288 "@ 6289 sl<g>r\t%0,%2 6290 sl<g>rk\t%0,%1,%2 6291 sl<g>\t%0,%2 6292 sl<y>\t%0,%2" 6293 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 6294 (set_attr "cpu_facility" "*,z196,*,longdisp") 6295 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) 6296 6297 6298; slr, sl, sly, slgr, slg, slrk, slgrk 6299(define_insn "*sub<mode>3_cconly2" 6300 [(set (reg CC_REGNUM) 6301 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") 6302 (match_operand:GPR 2 "general_operand" "d,d,R,T"))) 6303 (clobber (match_scratch:GPR 0 "=d,d,d,d"))] 6304 "s390_match_ccmode (insn, CCL3mode)" 6305 "@ 6306 sl<g>r\t%0,%2 6307 sl<g>rk\t%0,%1,%2 6308 sl<g>\t%0,%2 6309 sl<y>\t%0,%2" 6310 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 6311 (set_attr "cpu_facility" "*,z196,*,longdisp") 6312 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) 6313 6314(define_insn "*subdi3_sign" 6315 [(set (match_operand:DI 0 "register_operand" "=d") 6316 (minus:DI (match_operand:DI 1 "register_operand" "0") 6317 (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")))) 6318 (clobber (reg:CC CC_REGNUM))] 6319 "TARGET_ARCH12" 6320 "sgh\t%0,%2" 6321 [(set_attr "op_type" "RXY")]) 6322 6323 6324; 6325; sub(tf|df|sf|td|dd)3 instruction pattern(s). 6326; 6327 6328; FIXME: (clobber (match_scratch:CC 3 "=c,c,c,X,X")) does not work - why? 6329; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr 6330(define_insn "sub<mode>3" 6331 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") 6332 (minus:FP (match_operand:FP 1 "register_operand" "f,0,0,v,v") 6333 (match_operand:FP 2 "general_operand" "f,f,R,v,v"))) 6334 (clobber (reg:CC CC_REGNUM))] 6335 "TARGET_HARD_FLOAT" 6336 "@ 6337 s<xde>tr\t%0,%1,%2 6338 s<xde>br\t%0,%2 6339 s<xde>b\t%0,%2 6340 wfsdb\t%v0,%v1,%v2 6341 wfssb\t%v0,%v1,%v2" 6342 [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") 6343 (set_attr "type" "fsimp<mode>") 6344 (set_attr "cpu_facility" "*,*,*,vx,vxe") 6345 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) 6346 6347; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr 6348(define_insn "*sub<mode>3_cc" 6349 [(set (reg CC_REGNUM) 6350 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") 6351 (match_operand:FP 2 "general_operand" "f,f,R")) 6352 (match_operand:FP 3 "const0_operand" ""))) 6353 (set (match_operand:FP 0 "register_operand" "=f,f,f") 6354 (minus:FP (match_dup 1) (match_dup 2)))] 6355 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 6356 "@ 6357 s<xde>tr\t%0,%1,%2 6358 s<xde>br\t%0,%2 6359 s<xde>b\t%0,%2" 6360 [(set_attr "op_type" "RRF,RRE,RXE") 6361 (set_attr "type" "fsimp<mode>") 6362 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) 6363 6364; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr 6365(define_insn "*sub<mode>3_cconly" 6366 [(set (reg CC_REGNUM) 6367 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") 6368 (match_operand:FP 2 "general_operand" "f,f,R")) 6369 (match_operand:FP 3 "const0_operand" ""))) 6370 (clobber (match_scratch:FP 0 "=f,f,f"))] 6371 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 6372 "@ 6373 s<xde>tr\t%0,%1,%2 6374 s<xde>br\t%0,%2 6375 s<xde>b\t%0,%2" 6376 [(set_attr "op_type" "RRF,RRE,RXE") 6377 (set_attr "type" "fsimp<mode>") 6378 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) 6379 6380 6381;; 6382;;- Conditional add/subtract instructions. 6383;; 6384 6385; 6386; add(di|si)cc instruction pattern(s). 6387; 6388 6389; the following 4 patterns are used when the result of an add with 6390; carry is checked for an overflow condition 6391 6392; op1 + op2 + c < op1 6393 6394; alcr, alc, alcgr, alcg 6395(define_insn "*add<mode>3_alc_carry1_cc" 6396 [(set (reg CC_REGNUM) 6397 (compare 6398 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") 6399 (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) 6400 (match_operand:GPR 2 "general_operand" "d,T")) 6401 (match_dup 1))) 6402 (set (match_operand:GPR 0 "register_operand" "=d,d") 6403 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] 6404 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" 6405 "@ 6406 alc<g>r\t%0,%2 6407 alc<g>\t%0,%2" 6408 [(set_attr "op_type" "RRE,RXY") 6409 (set_attr "z196prop" "z196_alone,z196_alone")]) 6410 6411; alcr, alc, alcgr, alcg 6412(define_insn "*add<mode>3_alc_carry1_cconly" 6413 [(set (reg CC_REGNUM) 6414 (compare 6415 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") 6416 (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) 6417 (match_operand:GPR 2 "general_operand" "d,T")) 6418 (match_dup 1))) 6419 (clobber (match_scratch:GPR 0 "=d,d"))] 6420 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" 6421 "@ 6422 alc<g>r\t%0,%2 6423 alc<g>\t%0,%2" 6424 [(set_attr "op_type" "RRE,RXY") 6425 (set_attr "z196prop" "z196_alone,z196_alone")]) 6426 6427; op1 + op2 + c < op2 6428 6429; alcr, alc, alcgr, alcg 6430(define_insn "*add<mode>3_alc_carry2_cc" 6431 [(set (reg CC_REGNUM) 6432 (compare 6433 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") 6434 (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) 6435 (match_operand:GPR 2 "general_operand" "d,T")) 6436 (match_dup 2))) 6437 (set (match_operand:GPR 0 "register_operand" "=d,d") 6438 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] 6439 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" 6440 "@ 6441 alc<g>r\t%0,%2 6442 alc<g>\t%0,%2" 6443 [(set_attr "op_type" "RRE,RXY")]) 6444 6445; alcr, alc, alcgr, alcg 6446(define_insn "*add<mode>3_alc_carry2_cconly" 6447 [(set (reg CC_REGNUM) 6448 (compare 6449 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") 6450 (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) 6451 (match_operand:GPR 2 "general_operand" "d,T")) 6452 (match_dup 2))) 6453 (clobber (match_scratch:GPR 0 "=d,d"))] 6454 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" 6455 "@ 6456 alc<g>r\t%0,%2 6457 alc<g>\t%0,%2" 6458 [(set_attr "op_type" "RRE,RXY")]) 6459 6460; alcr, alc, alcgr, alcg 6461(define_insn "*add<mode>3_alc_cc" 6462 [(set (reg CC_REGNUM) 6463 (compare 6464 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") 6465 (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) 6466 (match_operand:GPR 2 "general_operand" "d,T")) 6467 (const_int 0))) 6468 (set (match_operand:GPR 0 "register_operand" "=d,d") 6469 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] 6470 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" 6471 "@ 6472 alc<g>r\t%0,%2 6473 alc<g>\t%0,%2" 6474 [(set_attr "op_type" "RRE,RXY")]) 6475 6476; alcr, alc, alcgr, alcg 6477(define_insn "*add<mode>3_alc" 6478 [(set (match_operand:GPR 0 "register_operand" "=d,d") 6479 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") 6480 (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) 6481 (match_operand:GPR 2 "general_operand" "d,T"))) 6482 (clobber (reg:CC CC_REGNUM))] 6483 "TARGET_CPU_ZARCH" 6484 "@ 6485 alc<g>r\t%0,%2 6486 alc<g>\t%0,%2" 6487 [(set_attr "op_type" "RRE,RXY")]) 6488 6489; slbr, slb, slbgr, slbg 6490(define_insn "*sub<mode>3_slb_cc" 6491 [(set (reg CC_REGNUM) 6492 (compare 6493 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") 6494 (match_operand:GPR 2 "general_operand" "d,T")) 6495 (match_operand:GPR 3 "s390_slb_comparison" "")) 6496 (const_int 0))) 6497 (set (match_operand:GPR 0 "register_operand" "=d,d") 6498 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] 6499 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" 6500 "@ 6501 slb<g>r\t%0,%2 6502 slb<g>\t%0,%2" 6503 [(set_attr "op_type" "RRE,RXY") 6504 (set_attr "z10prop" "z10_c,*")]) 6505 6506; slbr, slb, slbgr, slbg 6507(define_insn "*sub<mode>3_slb" 6508 [(set (match_operand:GPR 0 "register_operand" "=d,d") 6509 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") 6510 (match_operand:GPR 2 "general_operand" "d,T")) 6511 (match_operand:GPR 3 "s390_slb_comparison" ""))) 6512 (clobber (reg:CC CC_REGNUM))] 6513 "TARGET_CPU_ZARCH" 6514 "@ 6515 slb<g>r\t%0,%2 6516 slb<g>\t%0,%2" 6517 [(set_attr "op_type" "RRE,RXY") 6518 (set_attr "z10prop" "z10_c,*")]) 6519 6520(define_expand "add<mode>cc" 6521 [(match_operand:GPR 0 "register_operand" "") 6522 (match_operand 1 "comparison_operator" "") 6523 (match_operand:GPR 2 "register_operand" "") 6524 (match_operand:GPR 3 "const_int_operand" "")] 6525 "TARGET_CPU_ZARCH" 6526 "if (!s390_expand_addcc (GET_CODE (operands[1]), 6527 XEXP (operands[1], 0), XEXP (operands[1], 1), 6528 operands[0], operands[2], 6529 operands[3])) FAIL; DONE;") 6530 6531; 6532; scond instruction pattern(s). 6533; 6534 6535(define_insn_and_split "*scond<mode>" 6536 [(set (match_operand:GPR 0 "register_operand" "=&d") 6537 (match_operand:GPR 1 "s390_alc_comparison" "")) 6538 (clobber (reg:CC CC_REGNUM))] 6539 "TARGET_CPU_ZARCH" 6540 "#" 6541 "&& reload_completed" 6542 [(set (match_dup 0) (const_int 0)) 6543 (parallel 6544 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0)) 6545 (match_dup 0))) 6546 (clobber (reg:CC CC_REGNUM))])] 6547 "") 6548 6549(define_insn_and_split "*scond<mode>_neg" 6550 [(set (match_operand:GPR 0 "register_operand" "=&d") 6551 (match_operand:GPR 1 "s390_slb_comparison" "")) 6552 (clobber (reg:CC CC_REGNUM))] 6553 "TARGET_CPU_ZARCH" 6554 "#" 6555 "&& reload_completed" 6556 [(set (match_dup 0) (const_int 0)) 6557 (parallel 6558 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) 6559 (match_dup 1))) 6560 (clobber (reg:CC CC_REGNUM))]) 6561 (parallel 6562 [(set (match_dup 0) (neg:GPR (match_dup 0))) 6563 (clobber (reg:CC CC_REGNUM))])] 6564 "") 6565 6566 6567(define_expand "cstore<mode>4" 6568 [(set (match_operand:SI 0 "register_operand" "") 6569 (match_operator:SI 1 "s390_scond_operator" 6570 [(match_operand:GPR 2 "register_operand" "") 6571 (match_operand:GPR 3 "general_operand" "")]))] 6572 "TARGET_CPU_ZARCH" 6573 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3], 6574 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") 6575 6576(define_expand "cstorecc4" 6577 [(parallel 6578 [(set (match_operand:SI 0 "register_operand" "") 6579 (match_operator:SI 1 "s390_eqne_operator" 6580 [(match_operand 2 "cc_reg_operand") 6581 (match_operand 3 "const0_operand")])) 6582 (clobber (reg:CC CC_REGNUM))])] 6583 "" 6584 "machine_mode mode = GET_MODE (operands[2]); 6585 if (TARGET_Z196) 6586 { 6587 rtx cond, ite; 6588 6589 if (GET_CODE (operands[1]) == NE) 6590 cond = gen_rtx_NE (VOIDmode, operands[2], const0_rtx); 6591 else 6592 cond = gen_rtx_EQ (VOIDmode, operands[2], const0_rtx); 6593 ite = gen_rtx_IF_THEN_ELSE (SImode, cond, const1_rtx, const0_rtx); 6594 emit_insn (gen_rtx_SET (operands[0], ite)); 6595 } 6596 else 6597 { 6598 if (mode != CCZ1mode) 6599 FAIL; 6600 emit_insn (gen_sne (operands[0], operands[2])); 6601 if (GET_CODE (operands[1]) == EQ) 6602 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx)); 6603 } 6604 DONE;") 6605 6606(define_insn_and_split "sne" 6607 [(set (match_operand:SI 0 "register_operand" "=d") 6608 (ne:SI (match_operand:CCZ1 1 "register_operand" "0") 6609 (const_int 0))) 6610 (clobber (reg:CC CC_REGNUM))] 6611 "" 6612 "#" 6613 "reload_completed" 6614 [(parallel 6615 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) 6616 (clobber (reg:CC CC_REGNUM))])]) 6617 6618 6619;; 6620;; - Conditional move instructions (introduced with z196) 6621;; 6622 6623(define_expand "mov<mode>cc" 6624 [(set (match_operand:GPR 0 "nonimmediate_operand" "") 6625 (if_then_else:GPR (match_operand 1 "comparison_operator" "") 6626 (match_operand:GPR 2 "nonimmediate_operand" "") 6627 (match_operand:GPR 3 "nonimmediate_operand" "")))] 6628 "TARGET_Z196" 6629{ 6630 /* Emit the comparison insn in case we do not already have a comparison result. */ 6631 if (!s390_comparison (operands[1], VOIDmode)) 6632 operands[1] = s390_emit_compare (GET_CODE (operands[1]), 6633 XEXP (operands[1], 0), 6634 XEXP (operands[1], 1)); 6635}) 6636 6637; locr, loc, stoc, locgr, locg, stocg, lochi, locghi 6638(define_insn "*mov<mode>cc" 6639 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,S,S") 6640 (if_then_else:GPR 6641 (match_operator 1 "s390_comparison" 6642 [(match_operand 2 "cc_reg_operand" " c,c,c,c,c,c,c,c") 6643 (match_operand 5 "const_int_operand" "")]) 6644 (match_operand:GPR 3 "loc_operand" " d,0,S,0,K,0,d,0") 6645 (match_operand:GPR 4 "loc_operand" " 0,d,0,S,0,K,0,d")))] 6646 "TARGET_Z196" 6647 "@ 6648 loc<g>r%C1\t%0,%3 6649 loc<g>r%D1\t%0,%4 6650 loc<g>%C1\t%0,%3 6651 loc<g>%D1\t%0,%4 6652 loc<g>hi%C1\t%0,%h3 6653 loc<g>hi%D1\t%0,%h4 6654 stoc<g>%C1\t%3,%0 6655 stoc<g>%D1\t%4,%0" 6656 [(set_attr "op_type" "RRF,RRF,RSY,RSY,RIE,RIE,RSY,RSY") 6657 (set_attr "cpu_facility" "*,*,*,*,z13,z13,*,*")]) 6658 6659;; 6660;;- Multiply instructions. 6661;; 6662 6663; 6664; muldi3 instruction pattern(s). 6665; 6666 6667(define_expand "muldi3" 6668 [(parallel 6669 [(set (match_operand:DI 0 "register_operand") 6670 (mult:DI (match_operand:DI 1 "nonimmediate_operand") 6671 (match_operand:DI 2 "general_operand"))) 6672 (clobber (reg:CC CC_REGNUM))])] 6673 "TARGET_ZARCH") 6674 6675(define_insn "*muldi3_sign" 6676 [(set (match_operand:DI 0 "register_operand" "=d,d") 6677 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")) 6678 (match_operand:DI 1 "register_operand" "0,0")))] 6679 "TARGET_ZARCH" 6680 "@ 6681 msgfr\t%0,%2 6682 msgf\t%0,%2" 6683 [(set_attr "op_type" "RRE,RXY") 6684 (set_attr "type" "imuldi")]) 6685 6686(define_insn "*muldi3" 6687 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d") 6688 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0,0,0") 6689 (match_operand:DI 2 "general_operand" "d,d,K,T,Os"))) 6690 (clobber (match_scratch:CC 3 "=X,c,X,X,X"))] 6691 "TARGET_ZARCH" 6692 "@ 6693 msgr\t%0,%2 6694 msgrkc\t%0,%1,%2 6695 mghi\t%0,%h2 6696 msg\t%0,%2 6697 msgfi\t%0,%2" 6698 [(set_attr "op_type" "RRE,RRF,RI,RXY,RIL") 6699 (set_attr "type" "imuldi") 6700 (set_attr "cpu_facility" "*,arch12,*,*,z10")]) 6701 6702(define_insn "mulditi3" 6703 [(set (match_operand:TI 0 "register_operand" "=d,d") 6704 (mult:TI (sign_extend:TI 6705 (match_operand:DI 1 "register_operand" "%d,0")) 6706 (sign_extend:TI 6707 (match_operand:DI 2 "nonimmediate_operand" " d,T"))))] 6708 "TARGET_ARCH12" 6709 "@ 6710 mgrk\t%0,%1,%2 6711 mg\t%0,%2" 6712 [(set_attr "op_type" "RRF,RXY")]) 6713 6714; Combine likes op1 and op2 to be swapped sometimes. 6715(define_insn "mulditi3_2" 6716 [(set (match_operand:TI 0 "register_operand" "=d,d") 6717 (mult:TI (sign_extend:TI 6718 (match_operand:DI 1 "nonimmediate_operand" "%d,T")) 6719 (sign_extend:TI 6720 (match_operand:DI 2 "register_operand" " d,0"))))] 6721 "TARGET_ARCH12" 6722 "@ 6723 mgrk\t%0,%1,%2 6724 mg\t%0,%1" 6725 [(set_attr "op_type" "RRF,RXY")]) 6726 6727(define_insn "*muldi3_sign" 6728 [(set (match_operand:DI 0 "register_operand" "=d") 6729 (mult:DI (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")) 6730 (match_operand:DI 1 "register_operand" "0")))] 6731 "TARGET_ARCH12" 6732 "mgh\t%0,%2" 6733 [(set_attr "op_type" "RXY")]) 6734 6735 6736; 6737; mulsi3 instruction pattern(s). 6738; 6739 6740(define_expand "mulsi3" 6741 [(parallel 6742 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d") 6743 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,d,0,0,0,0") 6744 (match_operand:SI 2 "general_operand" "d,d,K,R,T,Os"))) 6745 (clobber (reg:CC CC_REGNUM))])] 6746 "") 6747 6748(define_insn "*mulsi3_sign" 6749 [(set (match_operand:SI 0 "register_operand" "=d,d") 6750 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) 6751 (match_operand:SI 1 "register_operand" "0,0")))] 6752 "" 6753 "@ 6754 mh\t%0,%2 6755 mhy\t%0,%2" 6756 [(set_attr "op_type" "RX,RXY") 6757 (set_attr "type" "imulhi") 6758 (set_attr "cpu_facility" "*,z10")]) 6759 6760(define_insn "*mulsi3" 6761 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d") 6762 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,d,0,0,0,0") 6763 (match_operand:SI 2 "general_operand" "d,d,K,R,T,Os"))) 6764 (clobber (match_scratch:CC 3 "=X,c,X,X,X,X"))] 6765 "" 6766 "@ 6767 msr\t%0,%2 6768 msrkc\t%0,%1,%2 6769 mhi\t%0,%h2 6770 ms\t%0,%2 6771 msy\t%0,%2 6772 msfi\t%0,%2" 6773 [(set_attr "op_type" "RRE,RRF,RI,RX,RXY,RIL") 6774 (set_attr "type" "imulsi,*,imulhi,imulsi,imulsi,imulsi") 6775 (set_attr "cpu_facility" "*,arch12,*,*,longdisp,z10")]) 6776 6777; 6778; mulsidi3 instruction pattern(s). 6779; 6780 6781(define_insn "mulsidi3" 6782 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 6783 (mult:DI (sign_extend:DI 6784 (match_operand:SI 1 "register_operand" "%0,0,0")) 6785 (sign_extend:DI 6786 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] 6787 "!TARGET_ZARCH" 6788 "@ 6789 mr\t%0,%2 6790 m\t%0,%2 6791 mfy\t%0,%2" 6792 [(set_attr "op_type" "RR,RX,RXY") 6793 (set_attr "type" "imulsi") 6794 (set_attr "cpu_facility" "*,*,z10")]) 6795 6796; 6797; umul instruction pattern(s). 6798; 6799 6800; mlr, ml, mlgr, mlg 6801(define_insn "umul<dwh><mode>3" 6802 [(set (match_operand:DW 0 "register_operand" "=d,d") 6803 (mult:DW (zero_extend:DW 6804 (match_operand:<DWH> 1 "register_operand" "%0,0")) 6805 (zero_extend:DW 6806 (match_operand:<DWH> 2 "nonimmediate_operand" " d,T"))))] 6807 "TARGET_CPU_ZARCH" 6808 "@ 6809 ml<tg>r\t%0,%2 6810 ml<tg>\t%0,%2" 6811 [(set_attr "op_type" "RRE,RXY") 6812 (set_attr "type" "imul<dwh>")]) 6813 6814; 6815; mul(tf|df|sf|td|dd)3 instruction pattern(s). 6816; 6817 6818; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr 6819(define_insn "mul<mode>3" 6820 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") 6821 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v,v") 6822 (match_operand:FP 2 "general_operand" "f,f,R,v,v")))] 6823 "TARGET_HARD_FLOAT" 6824 "@ 6825 m<xdee>tr\t%0,%1,%2 6826 m<xdee>br\t%0,%2 6827 m<xdee>b\t%0,%2 6828 wfmdb\t%v0,%v1,%v2 6829 wfmsb\t%v0,%v1,%v2" 6830 [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") 6831 (set_attr "type" "fmul<mode>") 6832 (set_attr "cpu_facility" "*,*,*,vx,vxe") 6833 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) 6834 6835; madbr, maebr, maxb, madb, maeb 6836(define_insn "fma<mode>4" 6837 [(set (match_operand:DSF 0 "register_operand" "=f,f,v,v") 6838 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v,v") 6839 (match_operand:DSF 2 "nonimmediate_operand" "f,R,v,v") 6840 (match_operand:DSF 3 "register_operand" "0,0,v,v")))] 6841 "TARGET_HARD_FLOAT" 6842 "@ 6843 ma<xde>br\t%0,%1,%2 6844 ma<xde>b\t%0,%1,%2 6845 wfmadb\t%v0,%v1,%v2,%v3 6846 wfmasb\t%v0,%v1,%v2,%v3" 6847 [(set_attr "op_type" "RRE,RXE,VRR,VRR") 6848 (set_attr "type" "fmadd<mode>") 6849 (set_attr "cpu_facility" "*,*,vx,vxe") 6850 (set_attr "enabled" "*,*,<DF>,<SF>")]) 6851 6852; msxbr, msdbr, msebr, msxb, msdb, mseb 6853(define_insn "fms<mode>4" 6854 [(set (match_operand:DSF 0 "register_operand" "=f,f,v,v") 6855 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v,v") 6856 (match_operand:DSF 2 "nonimmediate_operand" "f,R,v,v") 6857 (neg:DSF (match_operand:DSF 3 "register_operand" "0,0,v,v"))))] 6858 "TARGET_HARD_FLOAT" 6859 "@ 6860 ms<xde>br\t%0,%1,%2 6861 ms<xde>b\t%0,%1,%2 6862 wfmsdb\t%v0,%v1,%v2,%v3 6863 wfmssb\t%v0,%v1,%v2,%v3" 6864 [(set_attr "op_type" "RRE,RXE,VRR,VRR") 6865 (set_attr "type" "fmadd<mode>") 6866 (set_attr "cpu_facility" "*,*,vx,vxe") 6867 (set_attr "enabled" "*,*,<DF>,<SF>")]) 6868 6869;; 6870;;- Divide and modulo instructions. 6871;; 6872 6873; 6874; divmoddi4 instruction pattern(s). 6875; 6876 6877(define_expand "divmoddi4" 6878 [(parallel [(set (match_operand:DI 0 "general_operand" "") 6879 (div:DI (match_operand:DI 1 "register_operand" "") 6880 (match_operand:DI 2 "general_operand" ""))) 6881 (set (match_operand:DI 3 "general_operand" "") 6882 (mod:DI (match_dup 1) (match_dup 2)))]) 6883 (clobber (match_dup 4))] 6884 "TARGET_ZARCH" 6885{ 6886 rtx div_equal, mod_equal; 6887 rtx_insn *insn; 6888 6889 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); 6890 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); 6891 6892 operands[4] = gen_reg_rtx(TImode); 6893 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); 6894 6895 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); 6896 set_unique_reg_note (insn, REG_EQUAL, div_equal); 6897 6898 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); 6899 set_unique_reg_note (insn, REG_EQUAL, mod_equal); 6900 6901 DONE; 6902}) 6903 6904(define_insn "divmodtidi3" 6905 [(set (match_operand:TI 0 "register_operand" "=d,d") 6906 (ior:TI 6907 (ashift:TI 6908 (zero_extend:TI 6909 (mod:DI (match_operand:DI 1 "register_operand" "0,0") 6910 (match_operand:DI 2 "general_operand" "d,T"))) 6911 (const_int 64)) 6912 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] 6913 "TARGET_ZARCH" 6914 "@ 6915 dsgr\t%0,%2 6916 dsg\t%0,%2" 6917 [(set_attr "op_type" "RRE,RXY") 6918 (set_attr "type" "idiv")]) 6919 6920(define_insn "divmodtisi3" 6921 [(set (match_operand:TI 0 "register_operand" "=d,d") 6922 (ior:TI 6923 (ashift:TI 6924 (zero_extend:TI 6925 (mod:DI (match_operand:DI 1 "register_operand" "0,0") 6926 (sign_extend:DI 6927 (match_operand:SI 2 "nonimmediate_operand" "d,T")))) 6928 (const_int 64)) 6929 (zero_extend:TI 6930 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] 6931 "TARGET_ZARCH" 6932 "@ 6933 dsgfr\t%0,%2 6934 dsgf\t%0,%2" 6935 [(set_attr "op_type" "RRE,RXY") 6936 (set_attr "type" "idiv")]) 6937 6938; 6939; udivmoddi4 instruction pattern(s). 6940; 6941 6942(define_expand "udivmoddi4" 6943 [(parallel [(set (match_operand:DI 0 "general_operand" "") 6944 (udiv:DI (match_operand:DI 1 "general_operand" "") 6945 (match_operand:DI 2 "nonimmediate_operand" ""))) 6946 (set (match_operand:DI 3 "general_operand" "") 6947 (umod:DI (match_dup 1) (match_dup 2)))]) 6948 (clobber (match_dup 4))] 6949 "TARGET_ZARCH" 6950{ 6951 rtx div_equal, mod_equal, equal; 6952 rtx_insn *insn; 6953 6954 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); 6955 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); 6956 equal = gen_rtx_IOR (TImode, 6957 gen_rtx_ASHIFT (TImode, 6958 gen_rtx_ZERO_EXTEND (TImode, mod_equal), 6959 GEN_INT (64)), 6960 gen_rtx_ZERO_EXTEND (TImode, div_equal)); 6961 6962 operands[4] = gen_reg_rtx(TImode); 6963 emit_clobber (operands[4]); 6964 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); 6965 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); 6966 6967 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); 6968 set_unique_reg_note (insn, REG_EQUAL, equal); 6969 6970 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); 6971 set_unique_reg_note (insn, REG_EQUAL, div_equal); 6972 6973 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); 6974 set_unique_reg_note (insn, REG_EQUAL, mod_equal); 6975 6976 DONE; 6977}) 6978 6979(define_insn "udivmodtidi3" 6980 [(set (match_operand:TI 0 "register_operand" "=d,d") 6981 (ior:TI 6982 (ashift:TI 6983 (zero_extend:TI 6984 (truncate:DI 6985 (umod:TI (match_operand:TI 1 "register_operand" "0,0") 6986 (zero_extend:TI 6987 (match_operand:DI 2 "nonimmediate_operand" "d,T"))))) 6988 (const_int 64)) 6989 (zero_extend:TI 6990 (truncate:DI 6991 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] 6992 "TARGET_ZARCH" 6993 "@ 6994 dlgr\t%0,%2 6995 dlg\t%0,%2" 6996 [(set_attr "op_type" "RRE,RXY") 6997 (set_attr "type" "idiv")]) 6998 6999; 7000; divmodsi4 instruction pattern(s). 7001; 7002 7003(define_expand "divmodsi4" 7004 [(parallel [(set (match_operand:SI 0 "general_operand" "") 7005 (div:SI (match_operand:SI 1 "general_operand" "") 7006 (match_operand:SI 2 "nonimmediate_operand" ""))) 7007 (set (match_operand:SI 3 "general_operand" "") 7008 (mod:SI (match_dup 1) (match_dup 2)))]) 7009 (clobber (match_dup 4))] 7010 "!TARGET_ZARCH" 7011{ 7012 rtx div_equal, mod_equal, equal; 7013 rtx_insn *insn; 7014 7015 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); 7016 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); 7017 equal = gen_rtx_IOR (DImode, 7018 gen_rtx_ASHIFT (DImode, 7019 gen_rtx_ZERO_EXTEND (DImode, mod_equal), 7020 GEN_INT (32)), 7021 gen_rtx_ZERO_EXTEND (DImode, div_equal)); 7022 7023 operands[4] = gen_reg_rtx(DImode); 7024 emit_insn (gen_extendsidi2 (operands[4], operands[1])); 7025 7026 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); 7027 set_unique_reg_note (insn, REG_EQUAL, equal); 7028 7029 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); 7030 set_unique_reg_note (insn, REG_EQUAL, div_equal); 7031 7032 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); 7033 set_unique_reg_note (insn, REG_EQUAL, mod_equal); 7034 7035 DONE; 7036}) 7037 7038(define_insn "divmoddisi3" 7039 [(set (match_operand:DI 0 "register_operand" "=d,d") 7040 (ior:DI 7041 (ashift:DI 7042 (zero_extend:DI 7043 (truncate:SI 7044 (mod:DI (match_operand:DI 1 "register_operand" "0,0") 7045 (sign_extend:DI 7046 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) 7047 (const_int 32)) 7048 (zero_extend:DI 7049 (truncate:SI 7050 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] 7051 "!TARGET_ZARCH" 7052 "@ 7053 dr\t%0,%2 7054 d\t%0,%2" 7055 [(set_attr "op_type" "RR,RX") 7056 (set_attr "type" "idiv")]) 7057 7058; 7059; udivsi3 and umodsi3 instruction pattern(s). 7060; 7061 7062(define_expand "udivmodsi4" 7063 [(parallel [(set (match_operand:SI 0 "general_operand" "") 7064 (udiv:SI (match_operand:SI 1 "general_operand" "") 7065 (match_operand:SI 2 "nonimmediate_operand" ""))) 7066 (set (match_operand:SI 3 "general_operand" "") 7067 (umod:SI (match_dup 1) (match_dup 2)))]) 7068 (clobber (match_dup 4))] 7069 "!TARGET_ZARCH && TARGET_CPU_ZARCH" 7070{ 7071 rtx div_equal, mod_equal, equal; 7072 rtx_insn *insn; 7073 7074 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); 7075 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); 7076 equal = gen_rtx_IOR (DImode, 7077 gen_rtx_ASHIFT (DImode, 7078 gen_rtx_ZERO_EXTEND (DImode, mod_equal), 7079 GEN_INT (32)), 7080 gen_rtx_ZERO_EXTEND (DImode, div_equal)); 7081 7082 operands[4] = gen_reg_rtx(DImode); 7083 emit_clobber (operands[4]); 7084 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); 7085 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); 7086 7087 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); 7088 set_unique_reg_note (insn, REG_EQUAL, equal); 7089 7090 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); 7091 set_unique_reg_note (insn, REG_EQUAL, div_equal); 7092 7093 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); 7094 set_unique_reg_note (insn, REG_EQUAL, mod_equal); 7095 7096 DONE; 7097}) 7098 7099(define_insn "udivmoddisi3" 7100 [(set (match_operand:DI 0 "register_operand" "=d,d") 7101 (ior:DI 7102 (ashift:DI 7103 (zero_extend:DI 7104 (truncate:SI 7105 (umod:DI (match_operand:DI 1 "register_operand" "0,0") 7106 (zero_extend:DI 7107 (match_operand:SI 2 "nonimmediate_operand" "d,T"))))) 7108 (const_int 32)) 7109 (zero_extend:DI 7110 (truncate:SI 7111 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] 7112 "!TARGET_ZARCH && TARGET_CPU_ZARCH" 7113 "@ 7114 dlr\t%0,%2 7115 dl\t%0,%2" 7116 [(set_attr "op_type" "RRE,RXY") 7117 (set_attr "type" "idiv")]) 7118 7119(define_expand "udivsi3" 7120 [(set (match_operand:SI 0 "register_operand" "=d") 7121 (udiv:SI (match_operand:SI 1 "general_operand" "") 7122 (match_operand:SI 2 "general_operand" ""))) 7123 (clobber (match_dup 3))] 7124 "!TARGET_ZARCH && !TARGET_CPU_ZARCH" 7125{ 7126 rtx udiv_equal, umod_equal, equal; 7127 rtx_insn *insn; 7128 7129 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); 7130 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); 7131 equal = gen_rtx_IOR (DImode, 7132 gen_rtx_ASHIFT (DImode, 7133 gen_rtx_ZERO_EXTEND (DImode, umod_equal), 7134 GEN_INT (32)), 7135 gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); 7136 7137 operands[3] = gen_reg_rtx (DImode); 7138 7139 if (CONSTANT_P (operands[2])) 7140 { 7141 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) 7142 { 7143 rtx_code_label *label1 = gen_label_rtx (); 7144 7145 operands[1] = make_safe_from (operands[1], operands[0]); 7146 emit_move_insn (operands[0], const0_rtx); 7147 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX, 7148 SImode, 1, label1); 7149 emit_move_insn (operands[0], const1_rtx); 7150 emit_label (label1); 7151 } 7152 else 7153 { 7154 operands[2] = force_reg (SImode, operands[2]); 7155 operands[2] = make_safe_from (operands[2], operands[0]); 7156 7157 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); 7158 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], 7159 operands[2])); 7160 set_unique_reg_note (insn, REG_EQUAL, equal); 7161 7162 insn = emit_move_insn (operands[0], 7163 gen_lowpart (SImode, operands[3])); 7164 set_unique_reg_note (insn, REG_EQUAL, udiv_equal); 7165 } 7166 } 7167 else 7168 { 7169 rtx_code_label *label1 = gen_label_rtx (); 7170 rtx_code_label *label2 = gen_label_rtx (); 7171 rtx_code_label *label3 = gen_label_rtx (); 7172 7173 operands[1] = force_reg (SImode, operands[1]); 7174 operands[1] = make_safe_from (operands[1], operands[0]); 7175 operands[2] = force_reg (SImode, operands[2]); 7176 operands[2] = make_safe_from (operands[2], operands[0]); 7177 7178 emit_move_insn (operands[0], const0_rtx); 7179 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, 7180 SImode, 1, label3); 7181 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, 7182 SImode, 0, label2); 7183 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, 7184 SImode, 0, label1); 7185 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); 7186 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], 7187 operands[2])); 7188 set_unique_reg_note (insn, REG_EQUAL, equal); 7189 7190 insn = emit_move_insn (operands[0], 7191 gen_lowpart (SImode, operands[3])); 7192 set_unique_reg_note (insn, REG_EQUAL, udiv_equal); 7193 7194 emit_jump (label3); 7195 emit_label (label1); 7196 emit_move_insn (operands[0], operands[1]); 7197 emit_jump (label3); 7198 emit_label (label2); 7199 emit_move_insn (operands[0], const1_rtx); 7200 emit_label (label3); 7201 } 7202 emit_move_insn (operands[0], operands[0]); 7203 DONE; 7204}) 7205 7206(define_expand "umodsi3" 7207 [(set (match_operand:SI 0 "register_operand" "=d") 7208 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") 7209 (match_operand:SI 2 "nonimmediate_operand" ""))) 7210 (clobber (match_dup 3))] 7211 "!TARGET_ZARCH && !TARGET_CPU_ZARCH" 7212{ 7213 rtx udiv_equal, umod_equal, equal; 7214 rtx_insn *insn; 7215 7216 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); 7217 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); 7218 equal = gen_rtx_IOR (DImode, 7219 gen_rtx_ASHIFT (DImode, 7220 gen_rtx_ZERO_EXTEND (DImode, umod_equal), 7221 GEN_INT (32)), 7222 gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); 7223 7224 operands[3] = gen_reg_rtx (DImode); 7225 7226 if (CONSTANT_P (operands[2])) 7227 { 7228 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) 7229 { 7230 rtx_code_label *label1 = gen_label_rtx (); 7231 7232 operands[1] = make_safe_from (operands[1], operands[0]); 7233 emit_move_insn (operands[0], operands[1]); 7234 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX, 7235 SImode, 1, label1); 7236 emit_insn (gen_abssi2 (operands[0], operands[2])); 7237 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); 7238 emit_label (label1); 7239 } 7240 else 7241 { 7242 operands[2] = force_reg (SImode, operands[2]); 7243 operands[2] = make_safe_from (operands[2], operands[0]); 7244 7245 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); 7246 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], 7247 operands[2])); 7248 set_unique_reg_note (insn, REG_EQUAL, equal); 7249 7250 insn = emit_move_insn (operands[0], 7251 gen_highpart (SImode, operands[3])); 7252 set_unique_reg_note (insn, REG_EQUAL, umod_equal); 7253 } 7254 } 7255 else 7256 { 7257 rtx_code_label *label1 = gen_label_rtx (); 7258 rtx_code_label *label2 = gen_label_rtx (); 7259 rtx_code_label *label3 = gen_label_rtx (); 7260 7261 operands[1] = force_reg (SImode, operands[1]); 7262 operands[1] = make_safe_from (operands[1], operands[0]); 7263 operands[2] = force_reg (SImode, operands[2]); 7264 operands[2] = make_safe_from (operands[2], operands[0]); 7265 7266 emit_move_insn(operands[0], operands[1]); 7267 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, 7268 SImode, 1, label3); 7269 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, 7270 SImode, 0, label2); 7271 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, 7272 SImode, 0, label1); 7273 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); 7274 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], 7275 operands[2])); 7276 set_unique_reg_note (insn, REG_EQUAL, equal); 7277 7278 insn = emit_move_insn (operands[0], 7279 gen_highpart (SImode, operands[3])); 7280 set_unique_reg_note (insn, REG_EQUAL, umod_equal); 7281 7282 emit_jump (label3); 7283 emit_label (label1); 7284 emit_move_insn (operands[0], const0_rtx); 7285 emit_jump (label3); 7286 emit_label (label2); 7287 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); 7288 emit_label (label3); 7289 } 7290 DONE; 7291}) 7292 7293; 7294; div(df|sf)3 instruction pattern(s). 7295; 7296 7297; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr 7298(define_insn "div<mode>3" 7299 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") 7300 (div:FP (match_operand:FP 1 "register_operand" "f,0,0,v,v") 7301 (match_operand:FP 2 "general_operand" "f,f,R,v,v")))] 7302 "TARGET_HARD_FLOAT" 7303 "@ 7304 d<xde>tr\t%0,%1,%2 7305 d<xde>br\t%0,%2 7306 d<xde>b\t%0,%2 7307 wfddb\t%v0,%v1,%v2 7308 wfdsb\t%v0,%v1,%v2" 7309 [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") 7310 (set_attr "type" "fdiv<mode>") 7311 (set_attr "cpu_facility" "*,*,*,vx,vxe") 7312 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) 7313 7314 7315;; 7316;;- And instructions. 7317;; 7318 7319(define_expand "and<mode>3" 7320 [(set (match_operand:INT 0 "nonimmediate_operand" "") 7321 (and:INT (match_operand:INT 1 "nonimmediate_operand" "") 7322 (match_operand:INT 2 "general_operand" ""))) 7323 (clobber (reg:CC CC_REGNUM))] 7324 "" 7325 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;") 7326 7327; 7328; anddi3 instruction pattern(s). 7329; 7330 7331(define_insn "*anddi3_cc" 7332 [(set (reg CC_REGNUM) 7333 (compare 7334 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d") 7335 (match_operand:DI 2 "general_operand" " d,d,T,NxxDw")) 7336 (const_int 0))) 7337 (set (match_operand:DI 0 "register_operand" "=d,d,d, d") 7338 (and:DI (match_dup 1) (match_dup 2)))] 7339 "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)" 7340 "@ 7341 ngr\t%0,%2 7342 ngrk\t%0,%1,%2 7343 ng\t%0,%2 7344 risbg\t%0,%1,%s2,128+%e2,0" 7345 [(set_attr "op_type" "RRE,RRF,RXY,RIE") 7346 (set_attr "cpu_facility" "*,z196,*,z10") 7347 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) 7348 7349(define_insn "*anddi3_cconly" 7350 [(set (reg CC_REGNUM) 7351 (compare 7352 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d") 7353 (match_operand:DI 2 "general_operand" " d,d,T,NxxDw")) 7354 (const_int 0))) 7355 (clobber (match_scratch:DI 0 "=d,d,d, d"))] 7356 "TARGET_ZARCH 7357 && s390_match_ccmode(insn, CCTmode) 7358 /* Do not steal TM patterns. */ 7359 && s390_single_part (operands[2], DImode, HImode, 0) < 0" 7360 "@ 7361 ngr\t%0,%2 7362 ngrk\t%0,%1,%2 7363 ng\t%0,%2 7364 risbg\t%0,%1,%s2,128+%e2,0" 7365 [(set_attr "op_type" "RRE,RRF,RXY,RIE") 7366 (set_attr "cpu_facility" "*,z196,*,z10") 7367 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) 7368 7369(define_insn "*anddi3" 7370 [(set (match_operand:DI 0 "nonimmediate_operand" 7371 "=d,d, d, d, d, d, d, d,d,d,d, d, AQ,Q") 7372 (and:DI 7373 (match_operand:DI 1 "nonimmediate_operand" 7374 "%d,o, 0, 0, 0, 0, 0, 0,0,d,0, d, 0,0") 7375 (match_operand:DI 2 "general_operand" 7376 "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,T,NxxDw,NxQDF,Q"))) 7377 (clobber (reg:CC CC_REGNUM))] 7378 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7379 "@ 7380 # 7381 # 7382 nihh\t%0,%j2 7383 nihl\t%0,%j2 7384 nilh\t%0,%j2 7385 nill\t%0,%j2 7386 nihf\t%0,%m2 7387 nilf\t%0,%m2 7388 ngr\t%0,%2 7389 ngrk\t%0,%1,%2 7390 ng\t%0,%2 7391 risbg\t%0,%1,%s2,128+%e2,0 7392 # 7393 #" 7394 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS") 7395 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*") 7396 (set_attr "z10prop" "*, 7397 *, 7398 z10_super_E1, 7399 z10_super_E1, 7400 z10_super_E1, 7401 z10_super_E1, 7402 z10_super_E1, 7403 z10_super_E1, 7404 z10_super_E1, 7405 *, 7406 z10_super_E1, 7407 z10_super_E1, 7408 *, 7409 *")]) 7410 7411(define_split 7412 [(set (match_operand:DI 0 "s_operand" "") 7413 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) 7414 (clobber (reg:CC CC_REGNUM))] 7415 "reload_completed" 7416 [(parallel 7417 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) 7418 (clobber (reg:CC CC_REGNUM))])] 7419 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") 7420 7421;; These two are what combine generates for (ashift (zero_extract)). 7422(define_insn "*extzv_<mode>_srl<clobbercc_or_nocc>" 7423 [(set (match_operand:GPR 0 "register_operand" "=d") 7424 (and:GPR (lshiftrt:GPR 7425 (match_operand:GPR 1 "register_operand" "d") 7426 (match_operand:GPR 2 "nonzero_shift_count_operand" "")) 7427 (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))] 7428 "<z10_or_zEC12_cond> 7429 /* Note that even for the SImode pattern, the rotate is always DImode. */ 7430 && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]), 7431 INTVAL (operands[3]))" 7432 "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2" 7433 [(set_attr "op_type" "RIE") 7434 (set_attr "z10prop" "z10_super_E1")]) 7435 7436(define_insn "*extzv_<mode>_sll<clobbercc_or_nocc>" 7437 [(set (match_operand:GPR 0 "register_operand" "=d") 7438 (and:GPR (ashift:GPR 7439 (match_operand:GPR 1 "register_operand" "d") 7440 (match_operand:GPR 2 "nonzero_shift_count_operand" "")) 7441 (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))] 7442 "<z10_or_zEC12_cond> 7443 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]), 7444 INTVAL (operands[3]))" 7445 "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,%2" 7446 [(set_attr "op_type" "RIE") 7447 (set_attr "z10prop" "z10_super_E1")]) 7448 7449 7450; 7451; andsi3 instruction pattern(s). 7452; 7453 7454(define_insn "*andsi3_cc" 7455 [(set (reg CC_REGNUM) 7456 (compare 7457 (and:SI 7458 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") 7459 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) 7460 (const_int 0))) 7461 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d") 7462 (and:SI (match_dup 1) (match_dup 2)))] 7463 "s390_match_ccmode(insn, CCTmode)" 7464 "@ 7465 nilf\t%0,%o2 7466 nr\t%0,%2 7467 nrk\t%0,%1,%2 7468 n\t%0,%2 7469 ny\t%0,%2 7470 risbg\t%0,%1,%t2,128+%f2,0" 7471 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") 7472 (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10") 7473 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, 7474 z10_super_E1,z10_super_E1,z10_super_E1")]) 7475 7476(define_insn "*andsi3_cconly" 7477 [(set (reg CC_REGNUM) 7478 (compare 7479 (and:SI 7480 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") 7481 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) 7482 (const_int 0))) 7483 (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))] 7484 "s390_match_ccmode(insn, CCTmode) 7485 /* Do not steal TM patterns. */ 7486 && s390_single_part (operands[2], SImode, HImode, 0) < 0" 7487 "@ 7488 nilf\t%0,%o2 7489 nr\t%0,%2 7490 nrk\t%0,%1,%2 7491 n\t%0,%2 7492 ny\t%0,%2 7493 risbg\t%0,%1,%t2,128+%f2,0" 7494 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") 7495 (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10") 7496 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, 7497 z10_super_E1,z10_super_E1,z10_super_E1")]) 7498 7499(define_insn "*andsi3_zarch" 7500 [(set (match_operand:SI 0 "nonimmediate_operand" 7501 "=d,d, d, d, d,d,d,d,d, d, AQ,Q") 7502 (and:SI (match_operand:SI 1 "nonimmediate_operand" 7503 "%d,o, 0, 0, 0,0,d,0,0, d, 0,0") 7504 (match_operand:SI 2 "general_operand" 7505 " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSw,NxQSF,Q"))) 7506 (clobber (reg:CC CC_REGNUM))] 7507 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7508 "@ 7509 # 7510 # 7511 nilh\t%0,%j2 7512 nill\t%0,%j2 7513 nilf\t%0,%o2 7514 nr\t%0,%2 7515 nrk\t%0,%1,%2 7516 n\t%0,%2 7517 ny\t%0,%2 7518 risbg\t%0,%1,%t2,128+%f2,0 7519 # 7520 #" 7521 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS") 7522 (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,longdisp,z10,*,*") 7523 (set_attr "z10prop" "*, 7524 *, 7525 z10_super_E1, 7526 z10_super_E1, 7527 z10_super_E1, 7528 z10_super_E1, 7529 *, 7530 z10_super_E1, 7531 z10_super_E1, 7532 z10_super_E1, 7533 *, 7534 *")]) 7535 7536(define_insn "*andsi3_esa" 7537 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q") 7538 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0") 7539 (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q"))) 7540 (clobber (reg:CC CC_REGNUM))] 7541 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7542 "@ 7543 nr\t%0,%2 7544 n\t%0,%2 7545 # 7546 #" 7547 [(set_attr "op_type" "RR,RX,SI,SS") 7548 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) 7549 7550 7551(define_split 7552 [(set (match_operand:SI 0 "s_operand" "") 7553 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) 7554 (clobber (reg:CC CC_REGNUM))] 7555 "reload_completed" 7556 [(parallel 7557 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) 7558 (clobber (reg:CC CC_REGNUM))])] 7559 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") 7560 7561; 7562; andhi3 instruction pattern(s). 7563; 7564 7565(define_insn "*andhi3_zarch" 7566 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") 7567 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") 7568 (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q"))) 7569 (clobber (reg:CC CC_REGNUM))] 7570 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7571 "@ 7572 nr\t%0,%2 7573 nrk\t%0,%1,%2 7574 nill\t%0,%x2 7575 # 7576 #" 7577 [(set_attr "op_type" "RR,RRF,RI,SI,SS") 7578 (set_attr "cpu_facility" "*,z196,*,*,*") 7579 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*") 7580]) 7581 7582(define_insn "*andhi3_esa" 7583 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") 7584 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") 7585 (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) 7586 (clobber (reg:CC CC_REGNUM))] 7587 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7588 "@ 7589 nr\t%0,%2 7590 # 7591 #" 7592 [(set_attr "op_type" "RR,SI,SS") 7593 (set_attr "z10prop" "z10_super_E1,*,*") 7594]) 7595 7596(define_split 7597 [(set (match_operand:HI 0 "s_operand" "") 7598 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) 7599 (clobber (reg:CC CC_REGNUM))] 7600 "reload_completed" 7601 [(parallel 7602 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) 7603 (clobber (reg:CC CC_REGNUM))])] 7604 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") 7605 7606; 7607; andqi3 instruction pattern(s). 7608; 7609 7610(define_insn "*andqi3_zarch" 7611 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") 7612 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") 7613 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) 7614 (clobber (reg:CC CC_REGNUM))] 7615 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7616 "@ 7617 nr\t%0,%2 7618 nrk\t%0,%1,%2 7619 nill\t%0,%b2 7620 ni\t%S0,%b2 7621 niy\t%S0,%b2 7622 #" 7623 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") 7624 (set_attr "cpu_facility" "*,z196,*,*,longdisp,*") 7625 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")]) 7626 7627(define_insn "*andqi3_esa" 7628 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") 7629 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") 7630 (match_operand:QI 2 "general_operand" "d,n,Q"))) 7631 (clobber (reg:CC CC_REGNUM))] 7632 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7633 "@ 7634 nr\t%0,%2 7635 ni\t%S0,%b2 7636 #" 7637 [(set_attr "op_type" "RR,SI,SS") 7638 (set_attr "z10prop" "z10_super_E1,z10_super,*")]) 7639 7640; 7641; And with complement 7642; 7643; c = ~b & a = (b & a) ^ a 7644 7645(define_insn_and_split "*andc_split_<mode>" 7646 [(set (match_operand:GPR 0 "nonimmediate_operand" "") 7647 (and:GPR (not:GPR (match_operand:GPR 1 "nonimmediate_operand" "")) 7648 (match_operand:GPR 2 "general_operand" ""))) 7649 (clobber (reg:CC CC_REGNUM))] 7650 "! reload_completed 7651 && (GET_CODE (operands[0]) != MEM 7652 /* Ensure that s390_logical_operator_ok_p will succeed even 7653 on the split xor if (b & a) is stored into a pseudo. */ 7654 || rtx_equal_p (operands[0], operands[2]))" 7655 "#" 7656 "&& 1" 7657 [ 7658 (parallel 7659 [(set (match_dup 3) (and:GPR (match_dup 1) (match_dup 2))) 7660 (clobber (reg:CC CC_REGNUM))]) 7661 (parallel 7662 [(set (match_dup 0) (xor:GPR (match_dup 3) (match_dup 2))) 7663 (clobber (reg:CC CC_REGNUM))])] 7664{ 7665 if (reg_overlap_mentioned_p (operands[0], operands[2])) 7666 operands[3] = gen_reg_rtx (<MODE>mode); 7667 else 7668 operands[3] = operands[0]; 7669}) 7670 7671; 7672; Block and (NC) patterns. 7673; 7674 7675(define_insn "*nc" 7676 [(set (match_operand:BLK 0 "memory_operand" "=Q") 7677 (and:BLK (match_dup 0) 7678 (match_operand:BLK 1 "memory_operand" "Q"))) 7679 (use (match_operand 2 "const_int_operand" "n")) 7680 (clobber (reg:CC CC_REGNUM))] 7681 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" 7682 "nc\t%O0(%2,%R0),%S1" 7683 [(set_attr "op_type" "SS") 7684 (set_attr "z196prop" "z196_cracked")]) 7685 7686(define_split 7687 [(set (match_operand 0 "memory_operand" "") 7688 (and (match_dup 0) 7689 (match_operand 1 "memory_operand" ""))) 7690 (clobber (reg:CC CC_REGNUM))] 7691 "reload_completed 7692 && GET_MODE (operands[0]) == GET_MODE (operands[1]) 7693 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" 7694 [(parallel 7695 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) 7696 (use (match_dup 2)) 7697 (clobber (reg:CC CC_REGNUM))])] 7698{ 7699 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); 7700 operands[0] = adjust_address (operands[0], BLKmode, 0); 7701 operands[1] = adjust_address (operands[1], BLKmode, 0); 7702}) 7703 7704(define_peephole2 7705 [(parallel 7706 [(set (match_operand:BLK 0 "memory_operand" "") 7707 (and:BLK (match_dup 0) 7708 (match_operand:BLK 1 "memory_operand" ""))) 7709 (use (match_operand 2 "const_int_operand" "")) 7710 (clobber (reg:CC CC_REGNUM))]) 7711 (parallel 7712 [(set (match_operand:BLK 3 "memory_operand" "") 7713 (and:BLK (match_dup 3) 7714 (match_operand:BLK 4 "memory_operand" ""))) 7715 (use (match_operand 5 "const_int_operand" "")) 7716 (clobber (reg:CC CC_REGNUM))])] 7717 "s390_offset_p (operands[0], operands[3], operands[2]) 7718 && s390_offset_p (operands[1], operands[4], operands[2]) 7719 && !s390_overlap_p (operands[0], operands[1], 7720 INTVAL (operands[2]) + INTVAL (operands[5])) 7721 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" 7722 [(parallel 7723 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) 7724 (use (match_dup 8)) 7725 (clobber (reg:CC CC_REGNUM))])] 7726 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); 7727 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); 7728 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") 7729 7730 7731;; 7732;;- Bit set (inclusive or) instructions. 7733;; 7734 7735(define_expand "ior<mode>3" 7736 [(set (match_operand:INT 0 "nonimmediate_operand" "") 7737 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") 7738 (match_operand:INT 2 "general_operand" ""))) 7739 (clobber (reg:CC CC_REGNUM))] 7740 "" 7741 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;") 7742 7743; 7744; iordi3 instruction pattern(s). 7745; 7746 7747(define_insn "*iordi3_cc" 7748 [(set (reg CC_REGNUM) 7749 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") 7750 (match_operand:DI 2 "general_operand" " d,d,T")) 7751 (const_int 0))) 7752 (set (match_operand:DI 0 "register_operand" "=d,d,d") 7753 (ior:DI (match_dup 1) (match_dup 2)))] 7754 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" 7755 "@ 7756 ogr\t%0,%2 7757 ogrk\t%0,%1,%2 7758 og\t%0,%2" 7759 [(set_attr "op_type" "RRE,RRF,RXY") 7760 (set_attr "cpu_facility" "*,z196,*") 7761 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) 7762 7763(define_insn "*iordi3_cconly" 7764 [(set (reg CC_REGNUM) 7765 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") 7766 (match_operand:DI 2 "general_operand" " d,d,T")) 7767 (const_int 0))) 7768 (clobber (match_scratch:DI 0 "=d,d,d"))] 7769 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" 7770 "@ 7771 ogr\t%0,%2 7772 ogrk\t%0,%1,%2 7773 og\t%0,%2" 7774 [(set_attr "op_type" "RRE,RRF,RXY") 7775 (set_attr "cpu_facility" "*,z196,*") 7776 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) 7777 7778(define_insn "*iordi3" 7779 [(set (match_operand:DI 0 "nonimmediate_operand" 7780 "=d, d, d, d, d, d,d,d,d, AQ,Q") 7781 (ior:DI (match_operand:DI 1 "nonimmediate_operand" 7782 " %0, 0, 0, 0, 0, 0,0,d,0, 0,0") 7783 (match_operand:DI 2 "general_operand" 7784 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,T,NxQD0,Q"))) 7785 (clobber (reg:CC CC_REGNUM))] 7786 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7787 "@ 7788 oihh\t%0,%i2 7789 oihl\t%0,%i2 7790 oilh\t%0,%i2 7791 oill\t%0,%i2 7792 oihf\t%0,%k2 7793 oilf\t%0,%k2 7794 ogr\t%0,%2 7795 ogrk\t%0,%1,%2 7796 og\t%0,%2 7797 # 7798 #" 7799 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS") 7800 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*") 7801 (set_attr "z10prop" "z10_super_E1, 7802 z10_super_E1, 7803 z10_super_E1, 7804 z10_super_E1, 7805 z10_super_E1, 7806 z10_super_E1, 7807 z10_super_E1, 7808 *, 7809 z10_super_E1, 7810 *, 7811 *")]) 7812 7813(define_split 7814 [(set (match_operand:DI 0 "s_operand" "") 7815 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) 7816 (clobber (reg:CC CC_REGNUM))] 7817 "reload_completed" 7818 [(parallel 7819 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) 7820 (clobber (reg:CC CC_REGNUM))])] 7821 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") 7822 7823; 7824; iorsi3 instruction pattern(s). 7825; 7826 7827(define_insn "*iorsi3_cc" 7828 [(set (reg CC_REGNUM) 7829 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") 7830 (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) 7831 (const_int 0))) 7832 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") 7833 (ior:SI (match_dup 1) (match_dup 2)))] 7834 "s390_match_ccmode(insn, CCTmode)" 7835 "@ 7836 oilf\t%0,%o2 7837 or\t%0,%2 7838 ork\t%0,%1,%2 7839 o\t%0,%2 7840 oy\t%0,%2" 7841 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") 7842 (set_attr "cpu_facility" "*,*,z196,*,longdisp") 7843 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) 7844 7845(define_insn "*iorsi3_cconly" 7846 [(set (reg CC_REGNUM) 7847 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") 7848 (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) 7849 (const_int 0))) 7850 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] 7851 "s390_match_ccmode(insn, CCTmode)" 7852 "@ 7853 oilf\t%0,%o2 7854 or\t%0,%2 7855 ork\t%0,%1,%2 7856 o\t%0,%2 7857 oy\t%0,%2" 7858 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") 7859 (set_attr "cpu_facility" "*,*,z196,*,longdisp") 7860 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) 7861 7862(define_insn "*iorsi3_zarch" 7863 [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q") 7864 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0") 7865 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q"))) 7866 (clobber (reg:CC CC_REGNUM))] 7867 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7868 "@ 7869 oilh\t%0,%i2 7870 oill\t%0,%i2 7871 oilf\t%0,%o2 7872 or\t%0,%2 7873 ork\t%0,%1,%2 7874 o\t%0,%2 7875 oy\t%0,%2 7876 # 7877 #" 7878 [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS") 7879 (set_attr "cpu_facility" "*,*,*,*,z196,*,longdisp,*,*") 7880 (set_attr "z10prop" "z10_super_E1, 7881 z10_super_E1, 7882 z10_super_E1, 7883 z10_super_E1, 7884 *, 7885 z10_super_E1, 7886 z10_super_E1, 7887 *, 7888 *")]) 7889 7890(define_insn "*iorsi3_esa" 7891 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") 7892 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") 7893 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) 7894 (clobber (reg:CC CC_REGNUM))] 7895 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7896 "@ 7897 or\t%0,%2 7898 o\t%0,%2 7899 # 7900 #" 7901 [(set_attr "op_type" "RR,RX,SI,SS") 7902 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) 7903 7904(define_split 7905 [(set (match_operand:SI 0 "s_operand" "") 7906 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) 7907 (clobber (reg:CC CC_REGNUM))] 7908 "reload_completed" 7909 [(parallel 7910 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) 7911 (clobber (reg:CC CC_REGNUM))])] 7912 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") 7913 7914; 7915; iorhi3 instruction pattern(s). 7916; 7917 7918(define_insn "*iorhi3_zarch" 7919 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") 7920 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") 7921 (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q"))) 7922 (clobber (reg:CC CC_REGNUM))] 7923 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7924 "@ 7925 or\t%0,%2 7926 ork\t%0,%1,%2 7927 oill\t%0,%x2 7928 # 7929 #" 7930 [(set_attr "op_type" "RR,RRF,RI,SI,SS") 7931 (set_attr "cpu_facility" "*,z196,*,*,*") 7932 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")]) 7933 7934(define_insn "*iorhi3_esa" 7935 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") 7936 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") 7937 (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) 7938 (clobber (reg:CC CC_REGNUM))] 7939 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7940 "@ 7941 or\t%0,%2 7942 # 7943 #" 7944 [(set_attr "op_type" "RR,SI,SS") 7945 (set_attr "z10prop" "z10_super_E1,*,*")]) 7946 7947(define_split 7948 [(set (match_operand:HI 0 "s_operand" "") 7949 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) 7950 (clobber (reg:CC CC_REGNUM))] 7951 "reload_completed" 7952 [(parallel 7953 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) 7954 (clobber (reg:CC CC_REGNUM))])] 7955 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") 7956 7957; 7958; iorqi3 instruction pattern(s). 7959; 7960 7961(define_insn "*iorqi3_zarch" 7962 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") 7963 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") 7964 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) 7965 (clobber (reg:CC CC_REGNUM))] 7966 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7967 "@ 7968 or\t%0,%2 7969 ork\t%0,%1,%2 7970 oill\t%0,%b2 7971 oi\t%S0,%b2 7972 oiy\t%S0,%b2 7973 #" 7974 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") 7975 (set_attr "cpu_facility" "*,z196,*,*,longdisp,*") 7976 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1, 7977 z10_super,z10_super,*")]) 7978 7979(define_insn "*iorqi3_esa" 7980 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") 7981 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") 7982 (match_operand:QI 2 "general_operand" "d,n,Q"))) 7983 (clobber (reg:CC CC_REGNUM))] 7984 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7985 "@ 7986 or\t%0,%2 7987 oi\t%S0,%b2 7988 #" 7989 [(set_attr "op_type" "RR,SI,SS") 7990 (set_attr "z10prop" "z10_super_E1,z10_super,*")]) 7991 7992; 7993; Block inclusive or (OC) patterns. 7994; 7995 7996(define_insn "*oc" 7997 [(set (match_operand:BLK 0 "memory_operand" "=Q") 7998 (ior:BLK (match_dup 0) 7999 (match_operand:BLK 1 "memory_operand" "Q"))) 8000 (use (match_operand 2 "const_int_operand" "n")) 8001 (clobber (reg:CC CC_REGNUM))] 8002 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" 8003 "oc\t%O0(%2,%R0),%S1" 8004 [(set_attr "op_type" "SS") 8005 (set_attr "z196prop" "z196_cracked")]) 8006 8007(define_split 8008 [(set (match_operand 0 "memory_operand" "") 8009 (ior (match_dup 0) 8010 (match_operand 1 "memory_operand" ""))) 8011 (clobber (reg:CC CC_REGNUM))] 8012 "reload_completed 8013 && GET_MODE (operands[0]) == GET_MODE (operands[1]) 8014 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" 8015 [(parallel 8016 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) 8017 (use (match_dup 2)) 8018 (clobber (reg:CC CC_REGNUM))])] 8019{ 8020 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); 8021 operands[0] = adjust_address (operands[0], BLKmode, 0); 8022 operands[1] = adjust_address (operands[1], BLKmode, 0); 8023}) 8024 8025(define_peephole2 8026 [(parallel 8027 [(set (match_operand:BLK 0 "memory_operand" "") 8028 (ior:BLK (match_dup 0) 8029 (match_operand:BLK 1 "memory_operand" ""))) 8030 (use (match_operand 2 "const_int_operand" "")) 8031 (clobber (reg:CC CC_REGNUM))]) 8032 (parallel 8033 [(set (match_operand:BLK 3 "memory_operand" "") 8034 (ior:BLK (match_dup 3) 8035 (match_operand:BLK 4 "memory_operand" ""))) 8036 (use (match_operand 5 "const_int_operand" "")) 8037 (clobber (reg:CC CC_REGNUM))])] 8038 "s390_offset_p (operands[0], operands[3], operands[2]) 8039 && s390_offset_p (operands[1], operands[4], operands[2]) 8040 && !s390_overlap_p (operands[0], operands[1], 8041 INTVAL (operands[2]) + INTVAL (operands[5])) 8042 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" 8043 [(parallel 8044 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) 8045 (use (match_dup 8)) 8046 (clobber (reg:CC CC_REGNUM))])] 8047 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); 8048 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); 8049 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") 8050 8051 8052;; 8053;;- Xor instructions. 8054;; 8055 8056(define_expand "xor<mode>3" 8057 [(set (match_operand:INT 0 "nonimmediate_operand" "") 8058 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") 8059 (match_operand:INT 2 "general_operand" ""))) 8060 (clobber (reg:CC CC_REGNUM))] 8061 "" 8062 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") 8063 8064; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing 8065; simplifications. So its better to have something matching. 8066(define_split 8067 [(set (match_operand:INT 0 "nonimmediate_operand" "") 8068 (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))] 8069 "" 8070 [(parallel 8071 [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2))) 8072 (clobber (reg:CC CC_REGNUM))])] 8073{ 8074 operands[2] = constm1_rtx; 8075 if (!s390_logical_operator_ok_p (operands)) 8076 FAIL; 8077}) 8078 8079; 8080; xordi3 instruction pattern(s). 8081; 8082 8083(define_insn "*xordi3_cc" 8084 [(set (reg CC_REGNUM) 8085 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") 8086 (match_operand:DI 2 "general_operand" " d,d,T")) 8087 (const_int 0))) 8088 (set (match_operand:DI 0 "register_operand" "=d,d,d") 8089 (xor:DI (match_dup 1) (match_dup 2)))] 8090 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" 8091 "@ 8092 xgr\t%0,%2 8093 xgrk\t%0,%1,%2 8094 xg\t%0,%2" 8095 [(set_attr "op_type" "RRE,RRF,RXY") 8096 (set_attr "cpu_facility" "*,z196,*") 8097 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) 8098 8099(define_insn "*xordi3_cconly" 8100 [(set (reg CC_REGNUM) 8101 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") 8102 (match_operand:DI 2 "general_operand" " d,d,T")) 8103 (const_int 0))) 8104 (clobber (match_scratch:DI 0 "=d,d,d"))] 8105 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" 8106 "@ 8107 xgr\t%0,%2 8108 xgrk\t%0,%1,%2 8109 xg\t%0,%2" 8110 [(set_attr "op_type" "RRE,RRF,RXY") 8111 (set_attr "cpu_facility" "*,z196,*") 8112 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) 8113 8114(define_insn "*xordi3" 8115 [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d,d, AQ,Q") 8116 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d,0, 0,0") 8117 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,T,NxQD0,Q"))) 8118 (clobber (reg:CC CC_REGNUM))] 8119 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 8120 "@ 8121 xihf\t%0,%k2 8122 xilf\t%0,%k2 8123 xgr\t%0,%2 8124 xgrk\t%0,%1,%2 8125 xg\t%0,%2 8126 # 8127 #" 8128 [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS") 8129 (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*") 8130 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1, 8131 *,z10_super_E1,*,*")]) 8132 8133(define_split 8134 [(set (match_operand:DI 0 "s_operand" "") 8135 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) 8136 (clobber (reg:CC CC_REGNUM))] 8137 "reload_completed" 8138 [(parallel 8139 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) 8140 (clobber (reg:CC CC_REGNUM))])] 8141 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") 8142 8143; 8144; xorsi3 instruction pattern(s). 8145; 8146 8147(define_insn "*xorsi3_cc" 8148 [(set (reg CC_REGNUM) 8149 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") 8150 (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) 8151 (const_int 0))) 8152 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") 8153 (xor:SI (match_dup 1) (match_dup 2)))] 8154 "s390_match_ccmode(insn, CCTmode)" 8155 "@ 8156 xilf\t%0,%o2 8157 xr\t%0,%2 8158 xrk\t%0,%1,%2 8159 x\t%0,%2 8160 xy\t%0,%2" 8161 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") 8162 (set_attr "cpu_facility" "*,*,z196,*,longdisp") 8163 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, 8164 z10_super_E1,z10_super_E1")]) 8165 8166(define_insn "*xorsi3_cconly" 8167 [(set (reg CC_REGNUM) 8168 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") 8169 (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) 8170 (const_int 0))) 8171 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] 8172 "s390_match_ccmode(insn, CCTmode)" 8173 "@ 8174 xilf\t%0,%o2 8175 xr\t%0,%2 8176 xrk\t%0,%1,%2 8177 x\t%0,%2 8178 xy\t%0,%2" 8179 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") 8180 (set_attr "cpu_facility" "*,*,z196,*,longdisp") 8181 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, 8182 z10_super_E1,z10_super_E1")]) 8183 8184(define_insn "*xorsi3" 8185 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q") 8186 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0") 8187 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q"))) 8188 (clobber (reg:CC CC_REGNUM))] 8189 "s390_logical_operator_ok_p (operands)" 8190 "@ 8191 xilf\t%0,%o2 8192 xr\t%0,%2 8193 xrk\t%0,%1,%2 8194 x\t%0,%2 8195 xy\t%0,%2 8196 # 8197 #" 8198 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS") 8199 (set_attr "cpu_facility" "*,*,z196,*,longdisp,*,*") 8200 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, 8201 z10_super_E1,z10_super_E1,*,*")]) 8202 8203(define_split 8204 [(set (match_operand:SI 0 "s_operand" "") 8205 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) 8206 (clobber (reg:CC CC_REGNUM))] 8207 "reload_completed" 8208 [(parallel 8209 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) 8210 (clobber (reg:CC CC_REGNUM))])] 8211 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") 8212 8213; 8214; xorhi3 instruction pattern(s). 8215; 8216 8217(define_insn "*xorhi3" 8218 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") 8219 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0") 8220 (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q"))) 8221 (clobber (reg:CC CC_REGNUM))] 8222 "s390_logical_operator_ok_p (operands)" 8223 "@ 8224 xilf\t%0,%x2 8225 xr\t%0,%2 8226 xrk\t%0,%1,%2 8227 # 8228 #" 8229 [(set_attr "op_type" "RIL,RR,RRF,SI,SS") 8230 (set_attr "cpu_facility" "*,*,z196,*,*") 8231 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")]) 8232 8233(define_split 8234 [(set (match_operand:HI 0 "s_operand" "") 8235 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) 8236 (clobber (reg:CC CC_REGNUM))] 8237 "reload_completed" 8238 [(parallel 8239 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) 8240 (clobber (reg:CC CC_REGNUM))])] 8241 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") 8242 8243; 8244; xorqi3 instruction pattern(s). 8245; 8246 8247(define_insn "*xorqi3" 8248 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") 8249 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0") 8250 (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q"))) 8251 (clobber (reg:CC CC_REGNUM))] 8252 "s390_logical_operator_ok_p (operands)" 8253 "@ 8254 xilf\t%0,%b2 8255 xr\t%0,%2 8256 xrk\t%0,%1,%2 8257 xi\t%S0,%b2 8258 xiy\t%S0,%b2 8259 #" 8260 [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS") 8261 (set_attr "cpu_facility" "*,*,z196,*,longdisp,*") 8262 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")]) 8263 8264 8265; 8266; Block exclusive or (XC) patterns. 8267; 8268 8269(define_insn "*xc" 8270 [(set (match_operand:BLK 0 "memory_operand" "=Q") 8271 (xor:BLK (match_dup 0) 8272 (match_operand:BLK 1 "memory_operand" "Q"))) 8273 (use (match_operand 2 "const_int_operand" "n")) 8274 (clobber (reg:CC CC_REGNUM))] 8275 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" 8276 "xc\t%O0(%2,%R0),%S1" 8277 [(set_attr "op_type" "SS")]) 8278 8279(define_split 8280 [(set (match_operand 0 "memory_operand" "") 8281 (xor (match_dup 0) 8282 (match_operand 1 "memory_operand" ""))) 8283 (clobber (reg:CC CC_REGNUM))] 8284 "reload_completed 8285 && GET_MODE (operands[0]) == GET_MODE (operands[1]) 8286 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" 8287 [(parallel 8288 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) 8289 (use (match_dup 2)) 8290 (clobber (reg:CC CC_REGNUM))])] 8291{ 8292 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); 8293 operands[0] = adjust_address (operands[0], BLKmode, 0); 8294 operands[1] = adjust_address (operands[1], BLKmode, 0); 8295}) 8296 8297(define_peephole2 8298 [(parallel 8299 [(set (match_operand:BLK 0 "memory_operand" "") 8300 (xor:BLK (match_dup 0) 8301 (match_operand:BLK 1 "memory_operand" ""))) 8302 (use (match_operand 2 "const_int_operand" "")) 8303 (clobber (reg:CC CC_REGNUM))]) 8304 (parallel 8305 [(set (match_operand:BLK 3 "memory_operand" "") 8306 (xor:BLK (match_dup 3) 8307 (match_operand:BLK 4 "memory_operand" ""))) 8308 (use (match_operand 5 "const_int_operand" "")) 8309 (clobber (reg:CC CC_REGNUM))])] 8310 "s390_offset_p (operands[0], operands[3], operands[2]) 8311 && s390_offset_p (operands[1], operands[4], operands[2]) 8312 && !s390_overlap_p (operands[0], operands[1], 8313 INTVAL (operands[2]) + INTVAL (operands[5])) 8314 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" 8315 [(parallel 8316 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) 8317 (use (match_dup 8)) 8318 (clobber (reg:CC CC_REGNUM))])] 8319 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); 8320 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); 8321 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") 8322 8323; 8324; Block xor (XC) patterns with src == dest. 8325; 8326 8327(define_insn "*xc_zero" 8328 [(set (match_operand:BLK 0 "memory_operand" "=Q") 8329 (const_int 0)) 8330 (use (match_operand 1 "const_int_operand" "n")) 8331 (clobber (reg:CC CC_REGNUM))] 8332 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" 8333 "xc\t%O0(%1,%R0),%S0" 8334 [(set_attr "op_type" "SS") 8335 (set_attr "z196prop" "z196_cracked")]) 8336 8337(define_peephole2 8338 [(parallel 8339 [(set (match_operand:BLK 0 "memory_operand" "") 8340 (const_int 0)) 8341 (use (match_operand 1 "const_int_operand" "")) 8342 (clobber (reg:CC CC_REGNUM))]) 8343 (parallel 8344 [(set (match_operand:BLK 2 "memory_operand" "") 8345 (const_int 0)) 8346 (use (match_operand 3 "const_int_operand" "")) 8347 (clobber (reg:CC CC_REGNUM))])] 8348 "s390_offset_p (operands[0], operands[2], operands[1]) 8349 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" 8350 [(parallel 8351 [(set (match_dup 4) (const_int 0)) 8352 (use (match_dup 5)) 8353 (clobber (reg:CC CC_REGNUM))])] 8354 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); 8355 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") 8356 8357 8358;; 8359;;- Negate instructions. 8360;; 8361 8362; 8363; neg(di|si)2 instruction pattern(s). 8364; 8365 8366(define_expand "neg<mode>2" 8367 [(parallel 8368 [(set (match_operand:DSI 0 "register_operand" "=d") 8369 (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) 8370 (clobber (reg:CC CC_REGNUM))])] 8371 "" 8372 "") 8373 8374(define_insn "*negdi2_sign_cc" 8375 [(set (reg CC_REGNUM) 8376 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI 8377 (match_operand:SI 1 "register_operand" "d") 0) 8378 (const_int 32)) (const_int 32))) 8379 (const_int 0))) 8380 (set (match_operand:DI 0 "register_operand" "=d") 8381 (neg:DI (sign_extend:DI (match_dup 1))))] 8382 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" 8383 "lcgfr\t%0,%1" 8384 [(set_attr "op_type" "RRE") 8385 (set_attr "z10prop" "z10_c")]) 8386 8387(define_insn "*negdi2_sign" 8388 [(set (match_operand:DI 0 "register_operand" "=d") 8389 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) 8390 (clobber (reg:CC CC_REGNUM))] 8391 "TARGET_ZARCH" 8392 "lcgfr\t%0,%1" 8393 [(set_attr "op_type" "RRE") 8394 (set_attr "z10prop" "z10_c")]) 8395 8396; lcr, lcgr 8397(define_insn "*neg<mode>2_cc" 8398 [(set (reg CC_REGNUM) 8399 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) 8400 (const_int 0))) 8401 (set (match_operand:GPR 0 "register_operand" "=d") 8402 (neg:GPR (match_dup 1)))] 8403 "s390_match_ccmode (insn, CCAmode)" 8404 "lc<g>r\t%0,%1" 8405 [(set_attr "op_type" "RR<E>") 8406 (set_attr "z10prop" "z10_super_c_E1")]) 8407 8408; lcr, lcgr 8409(define_insn "*neg<mode>2_cconly" 8410 [(set (reg CC_REGNUM) 8411 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) 8412 (const_int 0))) 8413 (clobber (match_scratch:GPR 0 "=d"))] 8414 "s390_match_ccmode (insn, CCAmode)" 8415 "lc<g>r\t%0,%1" 8416 [(set_attr "op_type" "RR<E>") 8417 (set_attr "z10prop" "z10_super_c_E1")]) 8418 8419; lcr, lcgr 8420(define_insn "*neg<mode>2" 8421 [(set (match_operand:GPR 0 "register_operand" "=d") 8422 (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) 8423 (clobber (reg:CC CC_REGNUM))] 8424 "" 8425 "lc<g>r\t%0,%1" 8426 [(set_attr "op_type" "RR<E>") 8427 (set_attr "z10prop" "z10_super_c_E1")]) 8428 8429(define_insn "*negdi2_31" 8430 [(set (match_operand:DI 0 "register_operand" "=d") 8431 (neg:DI (match_operand:DI 1 "register_operand" "d"))) 8432 (clobber (reg:CC CC_REGNUM))] 8433 "!TARGET_ZARCH" 8434 "#") 8435 8436; Split a DImode NEG on 31bit into 2 SImode NEGs 8437 8438; Doing the twos complement separately on the SImode parts does an 8439; unwanted +1 on the high part which needs to be subtracted afterwards 8440; ... unless the +1 on the low part created an overflow. 8441 8442(define_split 8443 [(set (match_operand:DI 0 "register_operand" "") 8444 (neg:DI (match_operand:DI 1 "register_operand" ""))) 8445 (clobber (reg:CC CC_REGNUM))] 8446 "!TARGET_ZARCH 8447 && (REGNO (operands[0]) == REGNO (operands[1]) 8448 || s390_split_ok_p (operands[0], operands[1], DImode, 0)) 8449 && reload_completed" 8450 [(parallel 8451 [(set (match_dup 2) (neg:SI (match_dup 3))) 8452 (clobber (reg:CC CC_REGNUM))]) 8453 (parallel 8454 [(set (reg:CCAP CC_REGNUM) 8455 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) 8456 (set (match_dup 4) (neg:SI (match_dup 5)))]) 8457 (set (pc) 8458 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) 8459 (pc) 8460 (label_ref (match_dup 6)))) 8461 (parallel 8462 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) 8463 (clobber (reg:CC CC_REGNUM))]) 8464 (match_dup 6)] 8465 "operands[2] = operand_subword (operands[0], 0, 0, DImode); 8466 operands[3] = operand_subword (operands[1], 0, 0, DImode); 8467 operands[4] = operand_subword (operands[0], 1, 0, DImode); 8468 operands[5] = operand_subword (operands[1], 1, 0, DImode); 8469 operands[6] = gen_label_rtx ();") 8470 8471; Like above but first make a copy of the low part of the src operand 8472; since it might overlap with the high part of the destination. 8473 8474(define_split 8475 [(set (match_operand:DI 0 "register_operand" "") 8476 (neg:DI (match_operand:DI 1 "register_operand" ""))) 8477 (clobber (reg:CC CC_REGNUM))] 8478 "!TARGET_ZARCH 8479 && s390_split_ok_p (operands[0], operands[1], DImode, 1) 8480 && reload_completed" 8481 [; Make a backup of op5 first 8482 (set (match_dup 4) (match_dup 5)) 8483 ; Setting op2 here might clobber op5 8484 (parallel 8485 [(set (match_dup 2) (neg:SI (match_dup 3))) 8486 (clobber (reg:CC CC_REGNUM))]) 8487 (parallel 8488 [(set (reg:CCAP CC_REGNUM) 8489 (compare:CCAP (neg:SI (match_dup 4)) (const_int 0))) 8490 (set (match_dup 4) (neg:SI (match_dup 4)))]) 8491 (set (pc) 8492 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) 8493 (pc) 8494 (label_ref (match_dup 6)))) 8495 (parallel 8496 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) 8497 (clobber (reg:CC CC_REGNUM))]) 8498 (match_dup 6)] 8499 "operands[2] = operand_subword (operands[0], 0, 0, DImode); 8500 operands[3] = operand_subword (operands[1], 0, 0, DImode); 8501 operands[4] = operand_subword (operands[0], 1, 0, DImode); 8502 operands[5] = operand_subword (operands[1], 1, 0, DImode); 8503 operands[6] = gen_label_rtx ();") 8504 8505; 8506; neg(df|sf)2 instruction pattern(s). 8507; 8508 8509(define_expand "neg<mode>2" 8510 [(parallel 8511 [(set (match_operand:BFP 0 "register_operand") 8512 (neg:BFP (match_operand:BFP 1 "register_operand"))) 8513 (clobber (reg:CC CC_REGNUM))])] 8514 "TARGET_HARD_FLOAT") 8515 8516; lcxbr, lcdbr, lcebr 8517(define_insn "*neg<mode>2_cc" 8518 [(set (reg CC_REGNUM) 8519 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) 8520 (match_operand:BFP 2 "const0_operand" ""))) 8521 (set (match_operand:BFP 0 "register_operand" "=f") 8522 (neg:BFP (match_dup 1)))] 8523 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 8524 "lc<xde>br\t%0,%1" 8525 [(set_attr "op_type" "RRE") 8526 (set_attr "type" "fsimp<mode>")]) 8527 8528; lcxbr, lcdbr, lcebr 8529(define_insn "*neg<mode>2_cconly" 8530 [(set (reg CC_REGNUM) 8531 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) 8532 (match_operand:BFP 2 "const0_operand" ""))) 8533 (clobber (match_scratch:BFP 0 "=f"))] 8534 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 8535 "lc<xde>br\t%0,%1" 8536 [(set_attr "op_type" "RRE") 8537 (set_attr "type" "fsimp<mode>")]) 8538 8539; lcdfr 8540(define_insn "*neg<mode>2_nocc" 8541 [(set (match_operand:FP 0 "register_operand" "=f") 8542 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))] 8543 "TARGET_DFP" 8544 "lcdfr\t%0,%1" 8545 [(set_attr "op_type" "RRE") 8546 (set_attr "type" "fsimp<mode>")]) 8547 8548; lcxbr, lcdbr, lcebr 8549; FIXME: wflcdb does not clobber cc 8550; FIXME: Does wflcdb ever match here? 8551(define_insn "*neg<mode>2" 8552 [(set (match_operand:BFP 0 "register_operand" "=f,v,v") 8553 (neg:BFP (match_operand:BFP 1 "register_operand" "f,v,v"))) 8554 (clobber (reg:CC CC_REGNUM))] 8555 "TARGET_HARD_FLOAT" 8556 "@ 8557 lc<xde>br\t%0,%1 8558 wflcdb\t%0,%1 8559 wflcsb\t%0,%1" 8560 [(set_attr "op_type" "RRE,VRR,VRR") 8561 (set_attr "cpu_facility" "*,vx,vxe") 8562 (set_attr "type" "fsimp<mode>,*,*") 8563 (set_attr "enabled" "*,<DF>,<SF>")]) 8564 8565 8566;; 8567;;- Absolute value instructions. 8568;; 8569 8570; 8571; abs(di|si)2 instruction pattern(s). 8572; 8573 8574(define_insn "*absdi2_sign_cc" 8575 [(set (reg CC_REGNUM) 8576 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI 8577 (match_operand:SI 1 "register_operand" "d") 0) 8578 (const_int 32)) (const_int 32))) 8579 (const_int 0))) 8580 (set (match_operand:DI 0 "register_operand" "=d") 8581 (abs:DI (sign_extend:DI (match_dup 1))))] 8582 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" 8583 "lpgfr\t%0,%1" 8584 [(set_attr "op_type" "RRE") 8585 (set_attr "z10prop" "z10_c")]) 8586 8587(define_insn "*absdi2_sign" 8588 [(set (match_operand:DI 0 "register_operand" "=d") 8589 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) 8590 (clobber (reg:CC CC_REGNUM))] 8591 "TARGET_ZARCH" 8592 "lpgfr\t%0,%1" 8593 [(set_attr "op_type" "RRE") 8594 (set_attr "z10prop" "z10_c")]) 8595 8596; lpr, lpgr 8597(define_insn "*abs<mode>2_cc" 8598 [(set (reg CC_REGNUM) 8599 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) 8600 (const_int 0))) 8601 (set (match_operand:GPR 0 "register_operand" "=d") 8602 (abs:GPR (match_dup 1)))] 8603 "s390_match_ccmode (insn, CCAmode)" 8604 "lp<g>r\t%0,%1" 8605 [(set_attr "op_type" "RR<E>") 8606 (set_attr "z10prop" "z10_c")]) 8607 8608; lpr, lpgr 8609(define_insn "*abs<mode>2_cconly" 8610 [(set (reg CC_REGNUM) 8611 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) 8612 (const_int 0))) 8613 (clobber (match_scratch:GPR 0 "=d"))] 8614 "s390_match_ccmode (insn, CCAmode)" 8615 "lp<g>r\t%0,%1" 8616 [(set_attr "op_type" "RR<E>") 8617 (set_attr "z10prop" "z10_c")]) 8618 8619; lpr, lpgr 8620(define_insn "abs<mode>2" 8621 [(set (match_operand:GPR 0 "register_operand" "=d") 8622 (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) 8623 (clobber (reg:CC CC_REGNUM))] 8624 "" 8625 "lp<g>r\t%0,%1" 8626 [(set_attr "op_type" "RR<E>") 8627 (set_attr "z10prop" "z10_c")]) 8628 8629; 8630; abs(df|sf)2 instruction pattern(s). 8631; 8632 8633(define_expand "abs<mode>2" 8634 [(parallel 8635 [(set (match_operand:BFP 0 "register_operand" "=f") 8636 (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) 8637 (clobber (reg:CC CC_REGNUM))])] 8638 "TARGET_HARD_FLOAT" 8639 "") 8640 8641; lpxbr, lpdbr, lpebr 8642(define_insn "*abs<mode>2_cc" 8643 [(set (reg CC_REGNUM) 8644 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) 8645 (match_operand:BFP 2 "const0_operand" ""))) 8646 (set (match_operand:BFP 0 "register_operand" "=f") 8647 (abs:BFP (match_dup 1)))] 8648 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 8649 "lp<xde>br\t%0,%1" 8650 [(set_attr "op_type" "RRE") 8651 (set_attr "type" "fsimp<mode>")]) 8652 8653; lpxbr, lpdbr, lpebr 8654(define_insn "*abs<mode>2_cconly" 8655 [(set (reg CC_REGNUM) 8656 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) 8657 (match_operand:BFP 2 "const0_operand" ""))) 8658 (clobber (match_scratch:BFP 0 "=f"))] 8659 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 8660 "lp<xde>br\t%0,%1" 8661 [(set_attr "op_type" "RRE") 8662 (set_attr "type" "fsimp<mode>")]) 8663 8664; lpdfr 8665(define_insn "*abs<mode>2_nocc" 8666 [(set (match_operand:FP 0 "register_operand" "=f") 8667 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))] 8668 "TARGET_DFP" 8669 "lpdfr\t%0,%1" 8670 [(set_attr "op_type" "RRE") 8671 (set_attr "type" "fsimp<mode>")]) 8672 8673; lpxbr, lpdbr, lpebr 8674; FIXME: wflpdb does not clobber cc 8675(define_insn "*abs<mode>2" 8676 [(set (match_operand:BFP 0 "register_operand" "=f,v") 8677 (abs:BFP (match_operand:BFP 1 "register_operand" "f,v"))) 8678 (clobber (reg:CC CC_REGNUM))] 8679 "TARGET_HARD_FLOAT" 8680 "@ 8681 lp<xde>br\t%0,%1 8682 wflpdb\t%0,%1" 8683 [(set_attr "op_type" "RRE,VRR") 8684 (set_attr "cpu_facility" "*,vx") 8685 (set_attr "type" "fsimp<mode>,*") 8686 (set_attr "enabled" "*,<DFDI>")]) 8687 8688 8689;; 8690;;- Negated absolute value instructions 8691;; 8692 8693; 8694; Integer 8695; 8696 8697(define_insn "*negabsdi2_sign_cc" 8698 [(set (reg CC_REGNUM) 8699 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI 8700 (match_operand:SI 1 "register_operand" "d") 0) 8701 (const_int 32)) (const_int 32)))) 8702 (const_int 0))) 8703 (set (match_operand:DI 0 "register_operand" "=d") 8704 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] 8705 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" 8706 "lngfr\t%0,%1" 8707 [(set_attr "op_type" "RRE") 8708 (set_attr "z10prop" "z10_c")]) 8709 8710(define_insn "*negabsdi2_sign" 8711 [(set (match_operand:DI 0 "register_operand" "=d") 8712 (neg:DI (abs:DI (sign_extend:DI 8713 (match_operand:SI 1 "register_operand" "d"))))) 8714 (clobber (reg:CC CC_REGNUM))] 8715 "TARGET_ZARCH" 8716 "lngfr\t%0,%1" 8717 [(set_attr "op_type" "RRE") 8718 (set_attr "z10prop" "z10_c")]) 8719 8720; lnr, lngr 8721(define_insn "*negabs<mode>2_cc" 8722 [(set (reg CC_REGNUM) 8723 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) 8724 (const_int 0))) 8725 (set (match_operand:GPR 0 "register_operand" "=d") 8726 (neg:GPR (abs:GPR (match_dup 1))))] 8727 "s390_match_ccmode (insn, CCAmode)" 8728 "ln<g>r\t%0,%1" 8729 [(set_attr "op_type" "RR<E>") 8730 (set_attr "z10prop" "z10_c")]) 8731 8732; lnr, lngr 8733(define_insn "*negabs<mode>2_cconly" 8734 [(set (reg CC_REGNUM) 8735 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) 8736 (const_int 0))) 8737 (clobber (match_scratch:GPR 0 "=d"))] 8738 "s390_match_ccmode (insn, CCAmode)" 8739 "ln<g>r\t%0,%1" 8740 [(set_attr "op_type" "RR<E>") 8741 (set_attr "z10prop" "z10_c")]) 8742 8743; lnr, lngr 8744(define_insn "*negabs<mode>2" 8745 [(set (match_operand:GPR 0 "register_operand" "=d") 8746 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) 8747 (clobber (reg:CC CC_REGNUM))] 8748 "" 8749 "ln<g>r\t%0,%1" 8750 [(set_attr "op_type" "RR<E>") 8751 (set_attr "z10prop" "z10_c")]) 8752 8753; 8754; Floating point 8755; 8756 8757; lnxbr, lndbr, lnebr 8758(define_insn "*negabs<mode>2_cc" 8759 [(set (reg CC_REGNUM) 8760 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) 8761 (match_operand:BFP 2 "const0_operand" ""))) 8762 (set (match_operand:BFP 0 "register_operand" "=f") 8763 (neg:BFP (abs:BFP (match_dup 1))))] 8764 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 8765 "ln<xde>br\t%0,%1" 8766 [(set_attr "op_type" "RRE") 8767 (set_attr "type" "fsimp<mode>")]) 8768 8769; lnxbr, lndbr, lnebr 8770(define_insn "*negabs<mode>2_cconly" 8771 [(set (reg CC_REGNUM) 8772 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) 8773 (match_operand:BFP 2 "const0_operand" ""))) 8774 (clobber (match_scratch:BFP 0 "=f"))] 8775 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 8776 "ln<xde>br\t%0,%1" 8777 [(set_attr "op_type" "RRE") 8778 (set_attr "type" "fsimp<mode>")]) 8779 8780; lndfr 8781(define_insn "*negabs<mode>2_nocc" 8782 [(set (match_operand:FP 0 "register_operand" "=f") 8783 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))] 8784 "TARGET_DFP" 8785 "lndfr\t%0,%1" 8786 [(set_attr "op_type" "RRE") 8787 (set_attr "type" "fsimp<mode>")]) 8788 8789; lnxbr, lndbr, lnebr 8790; FIXME: wflndb does not clobber cc 8791(define_insn "*negabs<mode>2" 8792 [(set (match_operand:BFP 0 "register_operand" "=f,v") 8793 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f,v")))) 8794 (clobber (reg:CC CC_REGNUM))] 8795 "TARGET_HARD_FLOAT" 8796 "@ 8797 ln<xde>br\t%0,%1 8798 wflndb\t%0,%1" 8799 [(set_attr "op_type" "RRE,VRR") 8800 (set_attr "cpu_facility" "*,vx") 8801 (set_attr "type" "fsimp<mode>,*") 8802 (set_attr "enabled" "*,<DFDI>")]) 8803 8804;; 8805;;- Square root instructions. 8806;; 8807 8808; 8809; sqrt(df|sf)2 instruction pattern(s). 8810; 8811 8812; sqxbr, sqdbr, sqebr, sqdb, sqeb 8813(define_insn "sqrt<mode>2" 8814 [(set (match_operand:BFP 0 "register_operand" "=f,f,v") 8815 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,R,v")))] 8816 "TARGET_HARD_FLOAT" 8817 "@ 8818 sq<xde>br\t%0,%1 8819 sq<xde>b\t%0,%1 8820 wfsqdb\t%v0,%v1" 8821 [(set_attr "op_type" "RRE,RXE,VRR") 8822 (set_attr "type" "fsqrt<mode>") 8823 (set_attr "cpu_facility" "*,*,vx") 8824 (set_attr "enabled" "*,<DSF>,<DFDI>")]) 8825 8826 8827;; 8828;;- One complement instructions. 8829;; 8830 8831; 8832; one_cmpl(di|si|hi|qi)2 instruction pattern(s). 8833; 8834 8835(define_expand "one_cmpl<mode>2" 8836 [(parallel 8837 [(set (match_operand:INT 0 "register_operand" "") 8838 (xor:INT (match_operand:INT 1 "register_operand" "") 8839 (const_int -1))) 8840 (clobber (reg:CC CC_REGNUM))])] 8841 "" 8842 "") 8843 8844 8845;; 8846;; Find leftmost bit instructions. 8847;; 8848 8849(define_expand "clzdi2" 8850 [(set (match_operand:DI 0 "register_operand" "=d") 8851 (clz:DI (match_operand:DI 1 "register_operand" "d")))] 8852 "TARGET_EXTIMM && TARGET_ZARCH" 8853{ 8854 rtx_insn *insn; 8855 rtx clz_equal; 8856 rtx wide_reg = gen_reg_rtx (TImode); 8857 rtx msb = gen_rtx_CONST_INT (DImode, HOST_WIDE_INT_1U << 63); 8858 8859 clz_equal = gen_rtx_CLZ (DImode, operands[1]); 8860 8861 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); 8862 8863 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); 8864 set_unique_reg_note (insn, REG_EQUAL, clz_equal); 8865 8866 DONE; 8867}) 8868 8869; CLZ result is in hard reg op0 - this is the high part of the target operand 8870; The source with the left-most one bit cleared is in hard reg op0 + 1 - the low part 8871(define_insn "clztidi2" 8872 [(set (match_operand:TI 0 "register_operand" "=d") 8873 (ior:TI 8874 (ashift:TI (zero_extend:TI (clz:DI (match_operand:DI 1 "register_operand" "d"))) 8875 (const_int 64)) 8876 (zero_extend:TI 8877 (xor:DI (match_dup 1) 8878 (lshiftrt (match_operand:DI 2 "const_int_operand" "") 8879 (subreg:SI (clz:DI (match_dup 1)) 4)))))) 8880 (clobber (reg:CC CC_REGNUM))] 8881 "UINTVAL (operands[2]) == HOST_WIDE_INT_1U << 63 8882 && TARGET_EXTIMM && TARGET_ZARCH" 8883 "flogr\t%0,%1" 8884 [(set_attr "op_type" "RRE")]) 8885 8886 8887;; 8888;;- Rotate instructions. 8889;; 8890 8891; 8892; rotl(di|si)3 instruction pattern(s). 8893; 8894 8895(define_expand "rotl<mode>3" 8896 [(set (match_operand:GPR 0 "register_operand" "") 8897 (rotate:GPR (match_operand:GPR 1 "register_operand" "") 8898 (match_operand:SI 2 "nonmemory_operand" "")))] 8899 "TARGET_CPU_ZARCH" 8900 "") 8901 8902; rll, rllg 8903(define_insn "*rotl<mode>3<addr_style_op><masked_op>" 8904 [(set (match_operand:GPR 0 "register_operand" "=d") 8905 (rotate:GPR (match_operand:GPR 1 "register_operand" "d") 8906 (match_operand:SI 2 "nonmemory_operand" "an")))] 8907 "TARGET_CPU_ZARCH" 8908 "rll<g>\t%0,%1,<addr_style_op_ops>" 8909 [(set_attr "op_type" "RSE") 8910 (set_attr "atype" "reg") 8911 (set_attr "z10prop" "z10_super_E1")]) 8912 8913 8914;; 8915;;- Shift instructions. 8916;; 8917 8918; 8919; (ashl|lshr)(di|si)3 instruction pattern(s). 8920; Left shifts and logical right shifts 8921 8922(define_expand "<shift><mode>3" 8923 [(set (match_operand:DSI 0 "register_operand" "") 8924 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "") 8925 (match_operand:SI 2 "nonmemory_operand" "")))] 8926 "" 8927 "") 8928 8929; ESA 64 bit register pair shift with reg or imm shift count 8930; sldl, srdl 8931(define_insn "*<shift>di3_31<addr_style_op><masked_op>" 8932 [(set (match_operand:DI 0 "register_operand" "=d") 8933 (SHIFT:DI (match_operand:DI 1 "register_operand" "0") 8934 (match_operand:SI 2 "nonmemory_operand" "an")))] 8935 "!TARGET_ZARCH" 8936 "s<lr>dl\t%0,<addr_style_op_ops>" 8937 [(set_attr "op_type" "RS") 8938 (set_attr "atype" "reg") 8939 (set_attr "z196prop" "z196_cracked")]) 8940 8941 8942; 64 bit register shift with reg or imm shift count 8943; sll, srl, sllg, srlg, sllk, srlk 8944(define_insn "*<shift><mode>3<addr_style_op><masked_op>" 8945 [(set (match_operand:GPR 0 "register_operand" "=d, d") 8946 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>, d") 8947 (match_operand:SI 2 "nonmemory_operand" "an,an")))] 8948 "" 8949 "@ 8950 s<lr>l<g>\t%0,<1><addr_style_op_ops> 8951 s<lr>l<gk>\t%0,%1,<addr_style_op_ops>" 8952 [(set_attr "op_type" "RS<E>,RSY") 8953 (set_attr "atype" "reg,reg") 8954 (set_attr "cpu_facility" "*,z196") 8955 (set_attr "z10prop" "z10_super_E1,*")]) 8956 8957; 8958; ashr(di|si)3 instruction pattern(s). 8959; Arithmetic right shifts 8960 8961(define_expand "ashr<mode>3" 8962 [(parallel 8963 [(set (match_operand:DSI 0 "register_operand" "") 8964 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "") 8965 (match_operand:SI 2 "nonmemory_operand" ""))) 8966 (clobber (reg:CC CC_REGNUM))])] 8967 "" 8968 "") 8969 8970; FIXME: The number of alternatives is doubled here to match the fix 8971; number of 2 in the subst pattern for the (clobber (match_scratch... 8972; The right fix should be to support match_scratch in the output 8973; pattern of a define_subst. 8974(define_insn "*ashrdi3_31<addr_style_op_cc><masked_op_cc><setcc><cconly>" 8975 [(set (match_operand:DI 0 "register_operand" "=d, d") 8976 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0, 0") 8977 (match_operand:SI 2 "nonmemory_operand" "an,an"))) 8978 (clobber (reg:CC CC_REGNUM))] 8979 "!TARGET_ZARCH" 8980 "@ 8981 srda\t%0,<addr_style_op_cc_ops> 8982 srda\t%0,<addr_style_op_cc_ops>" 8983 [(set_attr "op_type" "RS") 8984 (set_attr "atype" "reg")]) 8985 8986 8987; sra, srag 8988(define_insn "*ashr<mode>3<addr_style_op_cc><masked_op_cc><setcc><cconly>" 8989 [(set (match_operand:GPR 0 "register_operand" "=d, d") 8990 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>, d") 8991 (match_operand:SI 2 "nonmemory_operand" "an,an"))) 8992 (clobber (reg:CC CC_REGNUM))] 8993 "" 8994 "@ 8995 sra<g>\t%0,<1><addr_style_op_cc_ops> 8996 sra<gk>\t%0,%1,<addr_style_op_cc_ops>" 8997 [(set_attr "op_type" "RS<E>,RSY") 8998 (set_attr "atype" "reg") 8999 (set_attr "cpu_facility" "*,z196") 9000 (set_attr "z10prop" "z10_super_E1,*")]) 9001 9002 9003;; 9004;; Branch instruction patterns. 9005;; 9006 9007(define_expand "cbranch<mode>4" 9008 [(set (pc) 9009 (if_then_else (match_operator 0 "comparison_operator" 9010 [(match_operand:GPR 1 "register_operand" "") 9011 (match_operand:GPR 2 "general_operand" "")]) 9012 (label_ref (match_operand 3 "" "")) 9013 (pc)))] 9014 "" 9015 "s390_emit_jump (operands[3], 9016 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); 9017 DONE;") 9018 9019(define_expand "cbranch<mode>4" 9020 [(set (pc) 9021 (if_then_else (match_operator 0 "comparison_operator" 9022 [(match_operand:FP 1 "register_operand" "") 9023 (match_operand:FP 2 "general_operand" "")]) 9024 (label_ref (match_operand 3 "" "")) 9025 (pc)))] 9026 "TARGET_HARD_FLOAT" 9027 "s390_emit_jump (operands[3], 9028 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); 9029 DONE;") 9030 9031(define_expand "cbranchcc4" 9032 [(set (pc) 9033 (if_then_else (match_operator 0 "s390_comparison" 9034 [(match_operand 1 "cc_reg_operand" "") 9035 (match_operand 2 "const_int_operand" "")]) 9036 (label_ref (match_operand 3 "" "")) 9037 (pc)))] 9038 "" 9039 "") 9040 9041 9042;; 9043;;- Conditional jump instructions. 9044;; 9045 9046(define_insn "*cjump_64" 9047 [(set (pc) 9048 (if_then_else 9049 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) 9050 (match_operand 2 "const_int_operand" "")]) 9051 (label_ref (match_operand 0 "" "")) 9052 (pc)))] 9053 "TARGET_CPU_ZARCH" 9054{ 9055 if (get_attr_length (insn) == 4) 9056 return "j%C1\t%l0"; 9057 else 9058 return "jg%C1\t%l0"; 9059} 9060 [(set_attr "op_type" "RI") 9061 (set_attr "type" "branch") 9062 (set (attr "length") 9063 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9064 (const_int 4) (const_int 6)))]) 9065 9066(define_insn "*cjump_31" 9067 [(set (pc) 9068 (if_then_else 9069 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) 9070 (match_operand 2 "const_int_operand" "")]) 9071 (label_ref (match_operand 0 "" "")) 9072 (pc)))] 9073 "!TARGET_CPU_ZARCH" 9074{ 9075 gcc_assert (get_attr_length (insn) == 4); 9076 return "j%C1\t%l0"; 9077} 9078 [(set_attr "op_type" "RI") 9079 (set_attr "type" "branch") 9080 (set (attr "length") 9081 (if_then_else (not (match_test "flag_pic")) 9082 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9083 (const_int 4) (const_int 6)) 9084 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9085 (const_int 4) (const_int 8))))]) 9086 9087(define_insn "*cjump_long" 9088 [(set (pc) 9089 (if_then_else 9090 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) 9091 (match_operand 0 "address_operand" "ZQZR") 9092 (pc)))] 9093 "!TARGET_INDIRECT_BRANCH_NOBP_JUMP" 9094{ 9095 if (get_attr_op_type (insn) == OP_TYPE_RR) 9096 return "b%C1r\t%0"; 9097 else 9098 return "b%C1\t%a0"; 9099} 9100 [(set (attr "op_type") 9101 (if_then_else (match_operand 0 "register_operand" "") 9102 (const_string "RR") (const_string "RX"))) 9103 (set (attr "mnemonic") 9104 (if_then_else (match_operand 0 "register_operand" "") 9105 (const_string "bcr") (const_string "bc"))) 9106 (set_attr "type" "branch") 9107 (set_attr "atype" "agen")]) 9108 9109;; A conditional return instruction. 9110(define_insn "*c<code>" 9111 [(set (pc) 9112 (if_then_else 9113 (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) 9114 (ANY_RETURN) 9115 (pc)))] 9116 "s390_can_use_<code>_insn ()" 9117{ 9118 if (TARGET_INDIRECT_BRANCH_NOBP_RET) 9119 { 9120 s390_indirect_branch_via_thunk (RETURN_REGNUM, 9121 INVALID_REGNUM, 9122 operands[0], 9123 s390_indirect_branch_type_return); 9124 return ""; 9125 } 9126 else 9127 return "b%C0r\t%%r14"; 9128} 9129 [(set (attr "op_type") 9130 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") 9131 (const_string "RIL") 9132 (const_string "RR"))) 9133 (set (attr "mnemonic") 9134 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") 9135 (const_string "brcl") 9136 (const_string "bcr"))) 9137 (set_attr "type" "jsr") 9138 (set_attr "atype" "agen")]) 9139 9140;; 9141;;- Negated conditional jump instructions. 9142;; 9143 9144(define_insn "*icjump_64" 9145 [(set (pc) 9146 (if_then_else 9147 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) 9148 (pc) 9149 (label_ref (match_operand 0 "" ""))))] 9150 "TARGET_CPU_ZARCH" 9151{ 9152 if (get_attr_length (insn) == 4) 9153 return "j%D1\t%l0"; 9154 else 9155 return "jg%D1\t%l0"; 9156} 9157 [(set_attr "op_type" "RI") 9158 (set_attr "type" "branch") 9159 (set (attr "length") 9160 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9161 (const_int 4) (const_int 6)))]) 9162 9163(define_insn "*icjump_31" 9164 [(set (pc) 9165 (if_then_else 9166 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) 9167 (pc) 9168 (label_ref (match_operand 0 "" ""))))] 9169 "!TARGET_CPU_ZARCH" 9170{ 9171 gcc_assert (get_attr_length (insn) == 4); 9172 return "j%D1\t%l0"; 9173} 9174 [(set_attr "op_type" "RI") 9175 (set_attr "type" "branch") 9176 (set (attr "length") 9177 (if_then_else (not (match_test "flag_pic")) 9178 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9179 (const_int 4) (const_int 6)) 9180 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9181 (const_int 4) (const_int 8))))]) 9182 9183(define_insn "*icjump_long" 9184 [(set (pc) 9185 (if_then_else 9186 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) 9187 (pc) 9188 (match_operand 0 "address_operand" "ZQZR")))] 9189 "!TARGET_INDIRECT_BRANCH_NOBP_JUMP" 9190{ 9191 if (get_attr_op_type (insn) == OP_TYPE_RR) 9192 return "b%D1r\t%0"; 9193 else 9194 return "b%D1\t%a0"; 9195} 9196 [(set (attr "op_type") 9197 (if_then_else (match_operand 0 "register_operand" "") 9198 (const_string "RR") (const_string "RX"))) 9199 (set (attr "mnemonic") 9200 (if_then_else (match_operand 0 "register_operand" "") 9201 (const_string "bcr") (const_string "bc"))) 9202 (set_attr "type" "branch") 9203 (set_attr "atype" "agen")]) 9204 9205;; 9206;;- Trap instructions. 9207;; 9208 9209(define_insn "trap" 9210 [(trap_if (const_int 1) (const_int 0))] 9211 "" 9212 "j\t.+2" 9213 [(set_attr "op_type" "RI") 9214 (set_attr "type" "branch")]) 9215 9216(define_expand "ctrap<mode>4" 9217 [(trap_if (match_operator 0 "comparison_operator" 9218 [(match_operand:GPR 1 "register_operand" "") 9219 (match_operand:GPR 2 "general_operand" "")]) 9220 (match_operand 3 "const0_operand" ""))] 9221 "" 9222 { 9223 rtx cond = s390_emit_compare (GET_CODE (operands[0]), 9224 operands[1], operands[2]); 9225 emit_insn (gen_condtrap (cond, XEXP (cond, 0))); 9226 DONE; 9227 }) 9228 9229(define_expand "ctrap<mode>4" 9230 [(trap_if (match_operator 0 "comparison_operator" 9231 [(match_operand:FP 1 "register_operand" "") 9232 (match_operand:FP 2 "general_operand" "")]) 9233 (match_operand 3 "const0_operand" ""))] 9234 "" 9235 { 9236 rtx cond = s390_emit_compare (GET_CODE (operands[0]), 9237 operands[1], operands[2]); 9238 emit_insn (gen_condtrap (cond, XEXP (cond, 0))); 9239 DONE; 9240 }) 9241 9242(define_insn "condtrap" 9243 [(trap_if (match_operator 0 "s390_comparison" 9244 [(match_operand 1 "cc_reg_operand" "c") 9245 (const_int 0)]) 9246 (const_int 0))] 9247 "" 9248 "j%C0\t.+2"; 9249 [(set_attr "op_type" "RI") 9250 (set_attr "type" "branch")]) 9251 9252; crt, cgrt, cit, cgit 9253(define_insn "*cmp_and_trap_signed_int<mode>" 9254 [(trap_if (match_operator 0 "s390_signed_integer_comparison" 9255 [(match_operand:GPR 1 "register_operand" "d,d") 9256 (match_operand:GPR 2 "nonmemory_operand" "d,K")]) 9257 (const_int 0))] 9258 "TARGET_Z10" 9259 "@ 9260 c<g>rt%C0\t%1,%2 9261 c<g>it%C0\t%1,%h2" 9262 [(set_attr "op_type" "RRF,RIE") 9263 (set_attr "type" "branch") 9264 (set_attr "z10prop" "z10_super_c,z10_super")]) 9265 9266; clrt, clgrt, clfit, clgit, clt, clgt 9267(define_insn "*cmp_and_trap_unsigned_int<mode>" 9268 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison" 9269 [(match_operand:GPR 1 "register_operand" "d,d,d") 9270 (match_operand:GPR 2 "general_operand" "d,D,T")]) 9271 (const_int 0))] 9272 "TARGET_Z10" 9273 "@ 9274 cl<g>rt%C0\t%1,%2 9275 cl<gf>it%C0\t%1,%x2 9276 cl<g>t%C0\t%1,%2" 9277 [(set_attr "op_type" "RRF,RIE,RSY") 9278 (set_attr "type" "branch") 9279 (set_attr "z10prop" "z10_super_c,z10_super,*") 9280 (set_attr "cpu_facility" "z10,z10,zEC12")]) 9281 9282; lat, lgat 9283(define_insn "*load_and_trap<mode>" 9284 [(trap_if (eq (match_operand:GPR 0 "memory_operand" "T") 9285 (const_int 0)) 9286 (const_int 0)) 9287 (set (match_operand:GPR 1 "register_operand" "=d") 9288 (match_dup 0))] 9289 "TARGET_ZEC12" 9290 "l<g>at\t%1,%0" 9291 [(set_attr "op_type" "RXY")]) 9292 9293 9294;; 9295;;- Loop instructions. 9296;; 9297;; This is all complicated by the fact that since this is a jump insn 9298;; we must handle our own output reloads. 9299 9300;; branch on index 9301 9302; This splitter will be matched by combine and has to add the 2 moves 9303; necessary to load the compare and the increment values into a 9304; register pair as needed by brxle. 9305 9306(define_insn_and_split "*brx_stage1_<GPR:mode>" 9307 [(set (pc) 9308 (if_then_else 9309 (match_operator 6 "s390_brx_operator" 9310 [(plus:GPR (match_operand:GPR 1 "register_operand" "") 9311 (match_operand:GPR 2 "general_operand" "")) 9312 (match_operand:GPR 3 "register_operand" "")]) 9313 (label_ref (match_operand 0 "" "")) 9314 (pc))) 9315 (set (match_operand:GPR 4 "nonimmediate_operand" "") 9316 (plus:GPR (match_dup 1) (match_dup 2))) 9317 (clobber (match_scratch:GPR 5 ""))] 9318 "TARGET_CPU_ZARCH" 9319 "#" 9320 "!reload_completed && !reload_in_progress" 9321 [(set (match_dup 7) (match_dup 2)) ; the increment 9322 (set (match_dup 8) (match_dup 3)) ; the comparison value 9323 (parallel [(set (pc) 9324 (if_then_else 9325 (match_op_dup 6 9326 [(plus:GPR (match_dup 1) (match_dup 7)) 9327 (match_dup 8)]) 9328 (label_ref (match_dup 0)) 9329 (pc))) 9330 (set (match_dup 4) 9331 (plus:GPR (match_dup 1) (match_dup 7))) 9332 (clobber (match_dup 5)) 9333 (clobber (reg:CC CC_REGNUM))])] 9334 { 9335 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode); 9336 operands[7] = gen_lowpart (<GPR:MODE>mode, 9337 gen_highpart (word_mode, dreg)); 9338 operands[8] = gen_lowpart (<GPR:MODE>mode, 9339 gen_lowpart (word_mode, dreg)); 9340 }) 9341 9342; brxlg, brxhg 9343 9344(define_insn_and_split "*brxg_64bit" 9345 [(set (pc) 9346 (if_then_else 9347 (match_operator 5 "s390_brx_operator" 9348 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d") 9349 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0)) 9350 (subreg:DI (match_dup 2) 8)]) 9351 (label_ref (match_operand 0 "" "")) 9352 (pc))) 9353 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X") 9354 (plus:DI (match_dup 1) 9355 (subreg:DI (match_dup 2) 0))) 9356 (clobber (match_scratch:DI 4 "=X,&1,&?d")) 9357 (clobber (reg:CC CC_REGNUM))] 9358 "TARGET_ZARCH" 9359{ 9360 if (which_alternative != 0) 9361 return "#"; 9362 else if (get_attr_length (insn) == 6) 9363 return "brx%E5g\t%1,%2,%l0"; 9364 else 9365 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0"; 9366} 9367 "&& reload_completed 9368 && (!REG_P (operands[3]) 9369 || !rtx_equal_p (operands[1], operands[3]))" 9370 [(set (match_dup 4) (match_dup 1)) 9371 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0))) 9372 (clobber (reg:CC CC_REGNUM))]) 9373 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8))) 9374 (set (match_dup 3) (match_dup 4)) 9375 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) 9376 (label_ref (match_dup 0)) 9377 (pc)))] 9378 "" 9379 [(set_attr "op_type" "RIE") 9380 (set_attr "type" "branch") 9381 (set (attr "length") 9382 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9383 (const_int 6) (const_int 16)))]) 9384 9385; brxle, brxh 9386 9387(define_insn_and_split "*brx_64bit" 9388 [(set (pc) 9389 (if_then_else 9390 (match_operator 5 "s390_brx_operator" 9391 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") 9392 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4)) 9393 (subreg:SI (match_dup 2) 12)]) 9394 (label_ref (match_operand 0 "" "")) 9395 (pc))) 9396 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") 9397 (plus:SI (match_dup 1) 9398 (subreg:SI (match_dup 2) 4))) 9399 (clobber (match_scratch:SI 4 "=X,&1,&?d")) 9400 (clobber (reg:CC CC_REGNUM))] 9401 "TARGET_ZARCH" 9402{ 9403 if (which_alternative != 0) 9404 return "#"; 9405 else if (get_attr_length (insn) == 6) 9406 return "brx%C5\t%1,%2,%l0"; 9407 else 9408 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; 9409} 9410 "&& reload_completed 9411 && (!REG_P (operands[3]) 9412 || !rtx_equal_p (operands[1], operands[3]))" 9413 [(set (match_dup 4) (match_dup 1)) 9414 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4))) 9415 (clobber (reg:CC CC_REGNUM))]) 9416 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12))) 9417 (set (match_dup 3) (match_dup 4)) 9418 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) 9419 (label_ref (match_dup 0)) 9420 (pc)))] 9421 "" 9422 [(set_attr "op_type" "RSI") 9423 (set_attr "type" "branch") 9424 (set (attr "length") 9425 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9426 (const_int 6) (const_int 14)))]) 9427 9428; brxle, brxh 9429 9430(define_insn_and_split "*brx_31bit" 9431 [(set (pc) 9432 (if_then_else 9433 (match_operator 5 "s390_brx_operator" 9434 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") 9435 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0)) 9436 (subreg:SI (match_dup 2) 4)]) 9437 (label_ref (match_operand 0 "" "")) 9438 (pc))) 9439 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") 9440 (plus:SI (match_dup 1) 9441 (subreg:SI (match_dup 2) 0))) 9442 (clobber (match_scratch:SI 4 "=X,&1,&?d")) 9443 (clobber (reg:CC CC_REGNUM))] 9444 "!TARGET_ZARCH && TARGET_CPU_ZARCH" 9445{ 9446 if (which_alternative != 0) 9447 return "#"; 9448 else if (get_attr_length (insn) == 6) 9449 return "brx%C5\t%1,%2,%l0"; 9450 else 9451 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; 9452} 9453 "&& reload_completed 9454 && (!REG_P (operands[3]) 9455 || !rtx_equal_p (operands[1], operands[3]))" 9456 [(set (match_dup 4) (match_dup 1)) 9457 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0))) 9458 (clobber (reg:CC CC_REGNUM))]) 9459 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4))) 9460 (set (match_dup 3) (match_dup 4)) 9461 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) 9462 (label_ref (match_dup 0)) 9463 (pc)))] 9464 "" 9465 [(set_attr "op_type" "RSI") 9466 (set_attr "type" "branch") 9467 (set (attr "length") 9468 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9469 (const_int 6) (const_int 14)))]) 9470 9471 9472;; branch on count 9473 9474(define_expand "doloop_end" 9475 [(use (match_operand 0 "" "")) ; loop pseudo 9476 (use (match_operand 1 "" ""))] ; label 9477 "" 9478{ 9479 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH) 9480 emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0])); 9481 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) 9482 emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0])); 9483 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH) 9484 emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0])); 9485 else 9486 FAIL; 9487 9488 DONE; 9489}) 9490 9491(define_insn_and_split "doloop_si64" 9492 [(set (pc) 9493 (if_then_else 9494 (ne (match_operand:SI 1 "register_operand" "d,d,d") 9495 (const_int 1)) 9496 (label_ref (match_operand 0 "" "")) 9497 (pc))) 9498 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") 9499 (plus:SI (match_dup 1) (const_int -1))) 9500 (clobber (match_scratch:SI 3 "=X,&1,&?d")) 9501 (clobber (reg:CC CC_REGNUM))] 9502 "TARGET_CPU_ZARCH" 9503{ 9504 if (which_alternative != 0) 9505 return "#"; 9506 else if (get_attr_length (insn) == 4) 9507 return "brct\t%1,%l0"; 9508 else 9509 return "ahi\t%1,-1\;jgne\t%l0"; 9510} 9511 "&& reload_completed 9512 && (! REG_P (operands[2]) 9513 || ! rtx_equal_p (operands[1], operands[2]))" 9514 [(set (match_dup 3) (match_dup 1)) 9515 (parallel [(set (reg:CCAN CC_REGNUM) 9516 (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) 9517 (const_int 0))) 9518 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) 9519 (set (match_dup 2) (match_dup 3)) 9520 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) 9521 (label_ref (match_dup 0)) 9522 (pc)))] 9523 "" 9524 [(set_attr "op_type" "RI") 9525 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not 9526 ; hurt us in the (rare) case of ahi. 9527 (set_attr "z10prop" "z10_super_E1") 9528 (set_attr "type" "branch") 9529 (set (attr "length") 9530 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9531 (const_int 4) (const_int 10)))]) 9532 9533(define_insn_and_split "doloop_si31" 9534 [(set (pc) 9535 (if_then_else 9536 (ne (match_operand:SI 1 "register_operand" "d,d,d") 9537 (const_int 1)) 9538 (label_ref (match_operand 0 "" "")) 9539 (pc))) 9540 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") 9541 (plus:SI (match_dup 1) (const_int -1))) 9542 (clobber (match_scratch:SI 3 "=X,&1,&?d")) 9543 (clobber (reg:CC CC_REGNUM))] 9544 "!TARGET_CPU_ZARCH" 9545{ 9546 if (which_alternative != 0) 9547 return "#"; 9548 else if (get_attr_length (insn) == 4) 9549 return "brct\t%1,%l0"; 9550 else 9551 gcc_unreachable (); 9552} 9553 "&& reload_completed 9554 && (! REG_P (operands[2]) 9555 || ! rtx_equal_p (operands[1], operands[2]))" 9556 [(set (match_dup 3) (match_dup 1)) 9557 (parallel [(set (reg:CCAN CC_REGNUM) 9558 (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) 9559 (const_int 0))) 9560 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) 9561 (set (match_dup 2) (match_dup 3)) 9562 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) 9563 (label_ref (match_dup 0)) 9564 (pc)))] 9565 "" 9566 [(set_attr "op_type" "RI") 9567 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not 9568 ; hurt us in the (rare) case of ahi. 9569 (set_attr "z10prop" "z10_super_E1") 9570 (set_attr "type" "branch") 9571 (set (attr "length") 9572 (if_then_else (not (match_test "flag_pic")) 9573 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9574 (const_int 4) (const_int 6)) 9575 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9576 (const_int 4) (const_int 8))))]) 9577 9578(define_insn "*doloop_si_long" 9579 [(set (pc) 9580 (if_then_else 9581 (ne (match_operand:SI 1 "register_operand" "d") 9582 (const_int 1)) 9583 (match_operand 0 "address_operand" "ZR") 9584 (pc))) 9585 (set (match_operand:SI 2 "register_operand" "=1") 9586 (plus:SI (match_dup 1) (const_int -1))) 9587 (clobber (match_scratch:SI 3 "=X")) 9588 (clobber (reg:CC CC_REGNUM))] 9589 "!TARGET_CPU_ZARCH" 9590{ 9591 if (get_attr_op_type (insn) == OP_TYPE_RR) 9592 return "bctr\t%1,%0"; 9593 else 9594 return "bct\t%1,%a0"; 9595} 9596 [(set (attr "op_type") 9597 (if_then_else (match_operand 0 "register_operand" "") 9598 (const_string "RR") (const_string "RX"))) 9599 (set_attr "type" "branch") 9600 (set_attr "atype" "agen") 9601 (set_attr "z10prop" "z10_c") 9602 (set_attr "z196prop" "z196_cracked")]) 9603 9604(define_insn_and_split "doloop_di" 9605 [(set (pc) 9606 (if_then_else 9607 (ne (match_operand:DI 1 "register_operand" "d,d,d") 9608 (const_int 1)) 9609 (label_ref (match_operand 0 "" "")) 9610 (pc))) 9611 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X") 9612 (plus:DI (match_dup 1) (const_int -1))) 9613 (clobber (match_scratch:DI 3 "=X,&1,&?d")) 9614 (clobber (reg:CC CC_REGNUM))] 9615 "TARGET_ZARCH" 9616{ 9617 if (which_alternative != 0) 9618 return "#"; 9619 else if (get_attr_length (insn) == 4) 9620 return "brctg\t%1,%l0"; 9621 else 9622 return "aghi\t%1,-1\;jgne\t%l0"; 9623} 9624 "&& reload_completed 9625 && (! REG_P (operands[2]) 9626 || ! rtx_equal_p (operands[1], operands[2]))" 9627 [(set (match_dup 3) (match_dup 1)) 9628 (parallel [(set (reg:CCAN CC_REGNUM) 9629 (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) 9630 (const_int 0))) 9631 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) 9632 (set (match_dup 2) (match_dup 3)) 9633 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) 9634 (label_ref (match_dup 0)) 9635 (pc)))] 9636 "" 9637 [(set_attr "op_type" "RI") 9638 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not 9639 ; hurt us in the (rare) case of ahi. 9640 (set_attr "z10prop" "z10_super_E1") 9641 (set_attr "type" "branch") 9642 (set (attr "length") 9643 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9644 (const_int 4) (const_int 10)))]) 9645 9646;; 9647;;- Unconditional jump instructions. 9648;; 9649 9650; 9651; jump instruction pattern(s). 9652; 9653 9654(define_expand "jump" 9655 [(match_operand 0 "" "")] 9656 "" 9657 "s390_emit_jump (operands[0], NULL_RTX); DONE;") 9658 9659(define_insn "*jump64" 9660 [(set (pc) (label_ref (match_operand 0 "" "")))] 9661 "TARGET_CPU_ZARCH" 9662{ 9663 if (get_attr_length (insn) == 4) 9664 return "j\t%l0"; 9665 else 9666 return "jg\t%l0"; 9667} 9668 [(set_attr "op_type" "RI") 9669 (set_attr "type" "branch") 9670 (set (attr "length") 9671 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9672 (const_int 4) (const_int 6)))]) 9673 9674(define_insn "*jump31" 9675 [(set (pc) (label_ref (match_operand 0 "" "")))] 9676 "!TARGET_CPU_ZARCH" 9677{ 9678 gcc_assert (get_attr_length (insn) == 4); 9679 return "j\t%l0"; 9680} 9681 [(set_attr "op_type" "RI") 9682 (set_attr "type" "branch") 9683 (set (attr "length") 9684 (if_then_else (not (match_test "flag_pic")) 9685 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9686 (const_int 4) (const_int 6)) 9687 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9688 (const_int 4) (const_int 8))))]) 9689 9690; 9691; indirect-jump instruction pattern(s). 9692; 9693 9694(define_expand "indirect_jump" 9695 [(set (pc) (match_operand 0 "nonimmediate_operand" ""))] 9696 "" 9697{ 9698 if (address_operand (operands[0], GET_MODE (operands[0]))) 9699 ; 9700 else if (TARGET_ARCH12 9701 && GET_MODE (operands[0]) == Pmode 9702 && memory_operand (operands[0], Pmode)) 9703 ; 9704 else 9705 operands[0] = force_reg (Pmode, operands[0]); 9706 9707 if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK) 9708 { 9709 operands[0] = force_reg (Pmode, operands[0]); 9710 if (TARGET_CPU_Z10) 9711 { 9712 if (TARGET_64BIT) 9713 emit_jump_insn (gen_indirect_jump_via_thunkdi_z10 (operands[0])); 9714 else 9715 emit_jump_insn (gen_indirect_jump_via_thunksi_z10 (operands[0])); 9716 } 9717 else 9718 { 9719 if (TARGET_64BIT) 9720 emit_jump_insn (gen_indirect_jump_via_thunkdi (operands[0])); 9721 else 9722 emit_jump_insn (gen_indirect_jump_via_thunksi (operands[0])); 9723 } 9724 DONE; 9725 } 9726 9727 if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK) 9728 { 9729 operands[0] = force_reg (Pmode, operands[0]); 9730 rtx label_ref = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); 9731 if (TARGET_CPU_Z10) 9732 { 9733 if (TARGET_64BIT) 9734 emit_jump_insn (gen_indirect_jump_via_inlinethunkdi_z10 (operands[0], 9735 label_ref)); 9736 else 9737 emit_jump_insn (gen_indirect_jump_via_inlinethunksi_z10 (operands[0], 9738 label_ref)); 9739 } 9740 else 9741 { 9742 if (TARGET_64BIT) 9743 emit_jump_insn (gen_indirect_jump_via_inlinethunkdi (operands[0], 9744 label_ref, 9745 force_reg (Pmode, label_ref))); 9746 else 9747 emit_jump_insn (gen_indirect_jump_via_inlinethunksi (operands[0], 9748 label_ref, 9749 force_reg (Pmode, label_ref))); 9750 } 9751 DONE; 9752 } 9753}) 9754 9755(define_insn "*indirect_jump" 9756 [(set (pc) 9757 (match_operand 0 "address_operand" "ZR"))] 9758 "!TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK" 9759{ 9760 if (get_attr_op_type (insn) == OP_TYPE_RR) 9761 return "br\t%0"; 9762 else 9763 return "b\t%a0"; 9764} 9765 [(set (attr "op_type") 9766 (if_then_else (match_operand 0 "register_operand" "") 9767 (const_string "RR") (const_string "RX"))) 9768 (set (attr "mnemonic") 9769 (if_then_else (match_operand 0 "register_operand" "") 9770 (const_string "br") (const_string "b"))) 9771 (set_attr "type" "branch") 9772 (set_attr "atype" "agen")]) 9773 9774(define_insn "indirect_jump_via_thunk<mode>_z10" 9775 [(set (pc) 9776 (match_operand:P 0 "register_operand" "a"))] 9777 "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK 9778 && TARGET_CPU_Z10" 9779{ 9780 s390_indirect_branch_via_thunk (REGNO (operands[0]), 9781 INVALID_REGNUM, 9782 NULL_RTX, 9783 s390_indirect_branch_type_jump); 9784 return ""; 9785} 9786 [(set_attr "op_type" "RIL") 9787 (set_attr "mnemonic" "jg") 9788 (set_attr "type" "branch") 9789 (set_attr "atype" "agen")]) 9790 9791(define_insn "indirect_jump_via_thunk<mode>" 9792 [(set (pc) 9793 (match_operand:P 0 "register_operand" " a")) 9794 (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] 9795 "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK 9796 && !TARGET_CPU_Z10" 9797{ 9798 s390_indirect_branch_via_thunk (REGNO (operands[0]), 9799 INVALID_REGNUM, 9800 NULL_RTX, 9801 s390_indirect_branch_type_jump); 9802 return ""; 9803} 9804 [(set_attr "op_type" "RIL") 9805 (set_attr "mnemonic" "jg") 9806 (set_attr "type" "branch") 9807 (set_attr "atype" "agen")]) 9808 9809 9810; The label_ref is wrapped into an if_then_else in order to hide it 9811; from mark_jump_label. Without this the label_ref would become the 9812; ONLY jump target of that jump breaking the control flow graph. 9813(define_insn "indirect_jump_via_inlinethunk<mode>_z10" 9814 [(unspec [(if_then_else (match_operand:P 1 "larl_operand" "X") 9815 (const_int 0) 9816 (const_int 0)) 9817 (const_int 0)] UNSPEC_EXECUTE_JUMP) 9818 (set (pc) (match_operand:P 0 "register_operand" "a"))] 9819 "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK 9820 && TARGET_CPU_Z10" 9821{ 9822 s390_indirect_branch_via_inline_thunk (operands[1]); 9823 return ""; 9824} 9825 [(set_attr "op_type" "RIL") 9826 (set_attr "type" "branch") 9827 (set_attr "length" "10")]) 9828 9829(define_insn "indirect_jump_via_inlinethunk<mode>" 9830 [(unspec [(if_then_else (match_operand:P 1 "larl_operand" "X") 9831 (const_int 0) 9832 (const_int 0)) 9833 (match_operand:P 2 "register_operand" "a")] UNSPEC_EXECUTE_JUMP) 9834 (set (pc) (match_operand:P 0 "register_operand" "a"))] 9835 "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK 9836 && !TARGET_CPU_Z10" 9837{ 9838 s390_indirect_branch_via_inline_thunk (operands[2]); 9839 return ""; 9840} 9841 [(set_attr "op_type" "RX") 9842 (set_attr "type" "branch") 9843 (set_attr "length" "8")]) 9844 9845; FIXME: LRA does not appear to be able to deal with MEMs being 9846; checked against address constraints like ZR above. So make this a 9847; separate pattern for now. 9848(define_insn "*indirect2_jump" 9849 [(set (pc) 9850 (match_operand 0 "nonimmediate_operand" "a,T"))] 9851 "!TARGET_INDIRECT_BRANCH_NOBP_JUMP" 9852 "@ 9853 br\t%0 9854 bi\t%0" 9855 [(set_attr "op_type" "RR,RXY") 9856 (set_attr "type" "branch") 9857 (set_attr "atype" "agen") 9858 (set_attr "cpu_facility" "*,arch12")]) 9859 9860; 9861; casesi instruction pattern(s). 9862; 9863 9864(define_expand "casesi_jump" 9865 [(parallel 9866 [(set (pc) (match_operand 0 "address_operand")) 9867 (use (label_ref (match_operand 1 "")))])] 9868 "" 9869{ 9870 if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK) 9871 { 9872 operands[0] = force_reg (GET_MODE (operands[0]), operands[0]); 9873 9874 if (TARGET_CPU_Z10) 9875 { 9876 if (TARGET_64BIT) 9877 emit_jump_insn (gen_casesi_jump_via_thunkdi_z10 (operands[0], 9878 operands[1])); 9879 else 9880 emit_jump_insn (gen_casesi_jump_via_thunksi_z10 (operands[0], 9881 operands[1])); 9882 } 9883 else 9884 { 9885 if (TARGET_64BIT) 9886 emit_jump_insn (gen_casesi_jump_via_thunkdi (operands[0], 9887 operands[1])); 9888 else 9889 emit_jump_insn (gen_casesi_jump_via_thunksi (operands[0], 9890 operands[1])); 9891 } 9892 DONE; 9893 } 9894 9895 if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK) 9896 { 9897 operands[0] = force_reg (Pmode, operands[0]); 9898 rtx label_ref = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); 9899 if (TARGET_CPU_Z10) 9900 { 9901 if (TARGET_64BIT) 9902 emit_jump_insn (gen_casesi_jump_via_inlinethunkdi_z10 (operands[0], 9903 operands[1], 9904 label_ref)); 9905 else 9906 emit_jump_insn (gen_casesi_jump_via_inlinethunksi_z10 (operands[0], 9907 operands[1], 9908 label_ref)); 9909 } 9910 else 9911 { 9912 if (TARGET_64BIT) 9913 emit_jump_insn (gen_casesi_jump_via_inlinethunkdi (operands[0], 9914 operands[1], 9915 label_ref, 9916 force_reg (Pmode, label_ref))); 9917 else 9918 emit_jump_insn (gen_casesi_jump_via_inlinethunksi (operands[0], 9919 operands[1], 9920 label_ref, 9921 force_reg (Pmode, label_ref))); 9922 } 9923 DONE; 9924 } 9925}) 9926 9927(define_insn "*casesi_jump" 9928 [(set (pc) (match_operand 0 "address_operand" "ZR")) 9929 (use (label_ref (match_operand 1 "" "")))] 9930 "!TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK" 9931{ 9932 if (get_attr_op_type (insn) == OP_TYPE_RR) 9933 return "br\t%0"; 9934 else 9935 return "b\t%a0"; 9936} 9937 [(set (attr "op_type") 9938 (if_then_else (match_operand 0 "register_operand" "") 9939 (const_string "RR") (const_string "RX"))) 9940 (set (attr "mnemonic") 9941 (if_then_else (match_operand 0 "register_operand" "") 9942 (const_string "br") (const_string "b"))) 9943 (set_attr "type" "branch") 9944 (set_attr "atype" "agen")]) 9945 9946(define_insn "casesi_jump_via_thunk<mode>_z10" 9947 [(set (pc) (match_operand:P 0 "register_operand" "a")) 9948 (use (label_ref (match_operand 1 "" "")))] 9949 "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK 9950 && TARGET_CPU_Z10" 9951{ 9952 s390_indirect_branch_via_thunk (REGNO (operands[0]), 9953 INVALID_REGNUM, 9954 NULL_RTX, 9955 s390_indirect_branch_type_jump); 9956 return ""; 9957} 9958 [(set_attr "op_type" "RIL") 9959 (set_attr "mnemonic" "jg") 9960 (set_attr "type" "branch") 9961 (set_attr "atype" "agen")]) 9962 9963(define_insn "casesi_jump_via_thunk<mode>" 9964 [(set (pc) (match_operand:P 0 "register_operand" "a")) 9965 (use (label_ref (match_operand 1 "" ""))) 9966 (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] 9967 "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK 9968 && !TARGET_CPU_Z10" 9969{ 9970 s390_indirect_branch_via_thunk (REGNO (operands[0]), 9971 INVALID_REGNUM, 9972 NULL_RTX, 9973 s390_indirect_branch_type_jump); 9974 return ""; 9975} 9976 [(set_attr "op_type" "RIL") 9977 (set_attr "mnemonic" "jg") 9978 (set_attr "type" "branch") 9979 (set_attr "atype" "agen")]) 9980 9981 9982; The label_ref is wrapped into an if_then_else in order to hide it 9983; from mark_jump_label. Without this the label_ref would become the 9984; ONLY jump target of that jump breaking the control flow graph. 9985(define_insn "casesi_jump_via_inlinethunk<mode>_z10" 9986 [(unspec [(if_then_else (match_operand:P 2 "larl_operand" "X") 9987 (const_int 0) 9988 (const_int 0)) 9989 (const_int 0)] UNSPEC_EXECUTE_JUMP) 9990 (set (pc) (match_operand:P 0 "register_operand" "a")) 9991 (use (label_ref (match_operand 1 "" "")))] 9992 "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK 9993 && TARGET_CPU_Z10" 9994{ 9995 s390_indirect_branch_via_inline_thunk (operands[2]); 9996 return ""; 9997} 9998 [(set_attr "op_type" "RIL") 9999 (set_attr "type" "cs") 10000 (set_attr "length" "10")]) 10001 10002(define_insn "casesi_jump_via_inlinethunk<mode>" 10003 [(unspec [(if_then_else (match_operand:P 2 "larl_operand" "X") 10004 (const_int 0) 10005 (const_int 0)) 10006 (match_operand:P 3 "register_operand" "a")] UNSPEC_EXECUTE_JUMP) 10007 (set (pc) (match_operand:P 0 "register_operand" "a")) 10008 (use (label_ref (match_operand 1 "" "")))] 10009 "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK 10010 && !TARGET_CPU_Z10" 10011{ 10012 s390_indirect_branch_via_inline_thunk (operands[3]); 10013 return ""; 10014} 10015 [(set_attr "op_type" "RX") 10016 (set_attr "type" "cs") 10017 (set_attr "length" "8")]) 10018 10019(define_expand "casesi" 10020 [(match_operand:SI 0 "general_operand" "") 10021 (match_operand:SI 1 "general_operand" "") 10022 (match_operand:SI 2 "general_operand" "") 10023 (label_ref (match_operand 3 "" "")) 10024 (label_ref (match_operand 4 "" ""))] 10025 "" 10026{ 10027 rtx index = gen_reg_rtx (SImode); 10028 rtx base = gen_reg_rtx (Pmode); 10029 rtx target = gen_reg_rtx (Pmode); 10030 10031 emit_move_insn (index, operands[0]); 10032 emit_insn (gen_subsi3 (index, index, operands[1])); 10033 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, 10034 operands[4]); 10035 10036 if (Pmode != SImode) 10037 index = convert_to_mode (Pmode, index, 1); 10038 if (GET_CODE (index) != REG) 10039 index = copy_to_mode_reg (Pmode, index); 10040 10041 if (TARGET_64BIT) 10042 emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); 10043 else 10044 emit_insn (gen_ashlsi3 (index, index, const2_rtx)); 10045 10046 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); 10047 10048 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); 10049 emit_move_insn (target, index); 10050 10051 if (flag_pic) 10052 target = gen_rtx_PLUS (Pmode, base, target); 10053 emit_jump_insn (gen_casesi_jump (target, operands[3])); 10054 10055 DONE; 10056}) 10057 10058 10059;; 10060;;- Jump to subroutine. 10061;; 10062;; 10063 10064; 10065; untyped call instruction pattern(s). 10066; 10067 10068;; Call subroutine returning any type. 10069(define_expand "untyped_call" 10070 [(parallel [(call (match_operand 0 "" "") 10071 (const_int 0)) 10072 (match_operand 1 "" "") 10073 (match_operand 2 "" "")])] 10074 "" 10075{ 10076 int i; 10077 10078 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); 10079 10080 for (i = 0; i < XVECLEN (operands[2], 0); i++) 10081 { 10082 rtx set = XVECEXP (operands[2], 0, i); 10083 emit_move_insn (SET_DEST (set), SET_SRC (set)); 10084 } 10085 10086 /* The optimizer does not know that the call sets the function value 10087 registers we stored in the result block. We avoid problems by 10088 claiming that all hard registers are used and clobbered at this 10089 point. */ 10090 emit_insn (gen_blockage ()); 10091 10092 DONE; 10093}) 10094 10095;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 10096;; all of memory. This blocks insns from being moved across this point. 10097 10098(define_insn "blockage" 10099 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] 10100 "" 10101 "" 10102 [(set_attr "type" "none") 10103 (set_attr "length" "0")]) 10104 10105; 10106; sibcall patterns 10107; 10108 10109(define_expand "sibcall" 10110 [(call (match_operand 0 "" "") 10111 (match_operand 1 "" ""))] 10112 "" 10113{ 10114 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); 10115 DONE; 10116}) 10117 10118(define_insn "*sibcall_br" 10119 [(call (mem:QI (reg SIBCALL_REGNUM)) 10120 (match_operand 0 "const_int_operand" "n"))] 10121 "SIBLING_CALL_P (insn) 10122 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" 10123{ 10124 if (TARGET_INDIRECT_BRANCH_NOBP_CALL) 10125 { 10126 gcc_assert (TARGET_CPU_Z10); 10127 s390_indirect_branch_via_thunk (SIBCALL_REGNUM, 10128 INVALID_REGNUM, 10129 NULL_RTX, 10130 s390_indirect_branch_type_call); 10131 return ""; 10132 } 10133 else 10134 return "br\t%%r1"; 10135} 10136 [(set (attr "op_type") 10137 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") 10138 (const_string "RIL") 10139 (const_string "RR"))) 10140 (set (attr "mnemonic") 10141 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") 10142 (const_string "jg") 10143 (const_string "br"))) 10144 (set_attr "type" "branch") 10145 (set_attr "atype" "agen")]) 10146 10147(define_insn "*sibcall_brc" 10148 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) 10149 (match_operand 1 "const_int_operand" "n"))] 10150 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" 10151 "j\t%0" 10152 [(set_attr "op_type" "RI") 10153 (set_attr "type" "branch")]) 10154 10155(define_insn "*sibcall_brcl" 10156 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) 10157 (match_operand 1 "const_int_operand" "n"))] 10158 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" 10159 "jg\t%0" 10160 [(set_attr "op_type" "RIL") 10161 (set_attr "type" "branch")]) 10162 10163; 10164; sibcall_value patterns 10165; 10166 10167(define_expand "sibcall_value" 10168 [(set (match_operand 0 "" "") 10169 (call (match_operand 1 "" "") 10170 (match_operand 2 "" "")))] 10171 "" 10172{ 10173 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); 10174 DONE; 10175}) 10176 10177(define_insn "*sibcall_value_br" 10178 [(set (match_operand 0 "" "") 10179 (call (mem:QI (reg SIBCALL_REGNUM)) 10180 (match_operand 1 "const_int_operand" "n")))] 10181 "SIBLING_CALL_P (insn) 10182 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" 10183{ 10184 if (TARGET_INDIRECT_BRANCH_NOBP_CALL) 10185 { 10186 gcc_assert (TARGET_CPU_Z10); 10187 s390_indirect_branch_via_thunk (SIBCALL_REGNUM, 10188 INVALID_REGNUM, 10189 NULL_RTX, 10190 s390_indirect_branch_type_call); 10191 return ""; 10192 } 10193 else 10194 return "br\t%%r1"; 10195} 10196 [(set (attr "op_type") 10197 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") 10198 (const_string "RIL") 10199 (const_string "RR"))) 10200 (set (attr "mnemonic") 10201 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") 10202 (const_string "jg") 10203 (const_string "br"))) 10204 (set_attr "type" "branch") 10205 (set_attr "atype" "agen")]) 10206 10207(define_insn "*sibcall_value_brc" 10208 [(set (match_operand 0 "" "") 10209 (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) 10210 (match_operand 2 "const_int_operand" "n")))] 10211 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" 10212 "j\t%1" 10213 [(set_attr "op_type" "RI") 10214 (set_attr "type" "branch")]) 10215 10216(define_insn "*sibcall_value_brcl" 10217 [(set (match_operand 0 "" "") 10218 (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) 10219 (match_operand 2 "const_int_operand" "n")))] 10220 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" 10221 "jg\t%1" 10222 [(set_attr "op_type" "RIL") 10223 (set_attr "type" "branch")]) 10224 10225 10226; 10227; call instruction pattern(s). 10228; 10229 10230(define_expand "call" 10231 [(call (match_operand 0 "" "") 10232 (match_operand 1 "" "")) 10233 (use (match_operand 2 "" ""))] 10234 "" 10235{ 10236 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, 10237 gen_rtx_REG (Pmode, RETURN_REGNUM)); 10238 DONE; 10239}) 10240 10241(define_insn "*bras" 10242 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) 10243 (match_operand 1 "const_int_operand" "n")) 10244 (clobber (match_operand 2 "register_operand" "=r"))] 10245 "!SIBLING_CALL_P (insn) 10246 && TARGET_SMALL_EXEC 10247 && GET_MODE (operands[2]) == Pmode" 10248 "bras\t%2,%0" 10249 [(set_attr "op_type" "RI") 10250 (set_attr "type" "jsr") 10251 (set_attr "z196prop" "z196_cracked")]) 10252 10253(define_insn "*brasl" 10254 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) 10255 (match_operand 1 "const_int_operand" "n")) 10256 (clobber (match_operand 2 "register_operand" "=r"))] 10257 "!SIBLING_CALL_P (insn) 10258 && TARGET_CPU_ZARCH 10259 && GET_MODE (operands[2]) == Pmode" 10260 "brasl\t%2,%0" 10261 [(set_attr "op_type" "RIL") 10262 (set_attr "type" "jsr") 10263 (set_attr "z196prop" "z196_cracked")]) 10264 10265(define_insn "*basr" 10266 [(call (mem:QI (match_operand 0 "address_operand" "ZR")) 10267 (match_operand 1 "const_int_operand" "n")) 10268 (clobber (match_operand 2 "register_operand" "=r"))] 10269 "!TARGET_INDIRECT_BRANCH_NOBP_CALL 10270 && !SIBLING_CALL_P (insn) 10271 && GET_MODE (operands[2]) == Pmode" 10272{ 10273 if (get_attr_op_type (insn) == OP_TYPE_RR) 10274 return "basr\t%2,%0"; 10275 else 10276 return "bas\t%2,%a0"; 10277} 10278 [(set (attr "op_type") 10279 (if_then_else (match_operand 0 "register_operand" "") 10280 (const_string "RR") (const_string "RX"))) 10281 (set (attr "mnemonic") 10282 (if_then_else (match_operand 0 "register_operand" "") 10283 (const_string "basr") (const_string "bas"))) 10284 (set_attr "type" "jsr") 10285 (set_attr "atype" "agen") 10286 (set_attr "z196prop" "z196_cracked")]) 10287 10288(define_insn "*basr_via_thunk<mode>_z10" 10289 [(call (mem:QI (match_operand:P 0 "register_operand" "a")) 10290 (match_operand 1 "const_int_operand" "n")) 10291 (clobber (match_operand:P 2 "register_operand" "=&r"))] 10292 "TARGET_INDIRECT_BRANCH_NOBP_CALL 10293 && TARGET_CPU_Z10 10294 && !SIBLING_CALL_P (insn)" 10295{ 10296 s390_indirect_branch_via_thunk (REGNO (operands[0]), 10297 REGNO (operands[2]), 10298 NULL_RTX, 10299 s390_indirect_branch_type_call); 10300 return ""; 10301} 10302 [(set_attr "op_type" "RIL") 10303 (set_attr "mnemonic" "brasl") 10304 (set_attr "type" "jsr") 10305 (set_attr "atype" "agen") 10306 (set_attr "z196prop" "z196_cracked")]) 10307 10308(define_insn "*basr_via_thunk<mode>" 10309 [(call (mem:QI (match_operand:P 0 "register_operand" "a")) 10310 (match_operand 1 "const_int_operand" "n")) 10311 (clobber (match_operand:P 2 "register_operand" "=&r")) 10312 (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] 10313 "TARGET_INDIRECT_BRANCH_NOBP_CALL 10314 && !TARGET_CPU_Z10 10315 && !SIBLING_CALL_P (insn)" 10316{ 10317 s390_indirect_branch_via_thunk (REGNO (operands[0]), 10318 REGNO (operands[2]), 10319 NULL_RTX, 10320 s390_indirect_branch_type_call); 10321 return ""; 10322} 10323 [(set_attr "op_type" "RIL") 10324 (set_attr "mnemonic" "brasl") 10325 (set_attr "type" "jsr") 10326 (set_attr "atype" "agen") 10327 (set_attr "z196prop" "z196_cracked")]) 10328 10329; 10330; call_value instruction pattern(s). 10331; 10332 10333(define_expand "call_value" 10334 [(set (match_operand 0 "" "") 10335 (call (match_operand 1 "" "") 10336 (match_operand 2 "" ""))) 10337 (use (match_operand 3 "" ""))] 10338 "" 10339{ 10340 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], 10341 gen_rtx_REG (Pmode, RETURN_REGNUM)); 10342 DONE; 10343}) 10344 10345(define_insn "*bras_r" 10346 [(set (match_operand 0 "" "") 10347 (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) 10348 (match_operand:SI 2 "const_int_operand" "n"))) 10349 (clobber (match_operand 3 "register_operand" "=r"))] 10350 "!SIBLING_CALL_P (insn) 10351 && TARGET_SMALL_EXEC 10352 && GET_MODE (operands[3]) == Pmode" 10353 "bras\t%3,%1" 10354 [(set_attr "op_type" "RI") 10355 (set_attr "type" "jsr") 10356 (set_attr "z196prop" "z196_cracked")]) 10357 10358(define_insn "*brasl_r" 10359 [(set (match_operand 0 "" "") 10360 (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) 10361 (match_operand 2 "const_int_operand" "n"))) 10362 (clobber (match_operand 3 "register_operand" "=r"))] 10363 "!SIBLING_CALL_P (insn) 10364 && TARGET_CPU_ZARCH 10365 && GET_MODE (operands[3]) == Pmode" 10366 "brasl\t%3,%1" 10367 [(set_attr "op_type" "RIL") 10368 (set_attr "type" "jsr") 10369 (set_attr "z196prop" "z196_cracked")]) 10370 10371(define_insn "*basr_r" 10372 [(set (match_operand 0 "" "") 10373 (call (mem:QI (match_operand 1 "address_operand" "ZR")) 10374 (match_operand 2 "const_int_operand" "n"))) 10375 (clobber (match_operand 3 "register_operand" "=r"))] 10376 "!TARGET_INDIRECT_BRANCH_NOBP_CALL 10377 && !SIBLING_CALL_P (insn) 10378 && GET_MODE (operands[3]) == Pmode" 10379{ 10380 if (get_attr_op_type (insn) == OP_TYPE_RR) 10381 return "basr\t%3,%1"; 10382 else 10383 return "bas\t%3,%a1"; 10384} 10385 [(set (attr "op_type") 10386 (if_then_else (match_operand 1 "register_operand" "") 10387 (const_string "RR") (const_string "RX"))) 10388 (set (attr "mnemonic") 10389 (if_then_else (match_operand 1 "register_operand" "") 10390 (const_string "basr") (const_string "bas"))) 10391 (set_attr "type" "jsr") 10392 (set_attr "atype" "agen") 10393 (set_attr "z196prop" "z196_cracked")]) 10394 10395(define_insn "*basr_r_via_thunk_z10" 10396 [(set (match_operand 0 "" "") 10397 (call (mem:QI (match_operand 1 "register_operand" "a")) 10398 (match_operand 2 "const_int_operand" "n"))) 10399 (clobber (match_operand 3 "register_operand" "=&r"))] 10400 "TARGET_INDIRECT_BRANCH_NOBP_CALL 10401 && TARGET_CPU_Z10 10402 && !SIBLING_CALL_P (insn) 10403 && GET_MODE (operands[3]) == Pmode" 10404{ 10405 s390_indirect_branch_via_thunk (REGNO (operands[1]), 10406 REGNO (operands[3]), 10407 NULL_RTX, 10408 s390_indirect_branch_type_call); 10409 return ""; 10410} 10411 [(set_attr "op_type" "RIL") 10412 (set_attr "mnemonic" "brasl") 10413 (set_attr "type" "jsr") 10414 (set_attr "atype" "agen") 10415 (set_attr "z196prop" "z196_cracked")]) 10416 10417(define_insn "*basr_r_via_thunk" 10418 [(set (match_operand 0 "" "") 10419 (call (mem:QI (match_operand 1 "register_operand" "a")) 10420 (match_operand 2 "const_int_operand" "n"))) 10421 (clobber (match_operand 3 "register_operand" "=&r")) 10422 (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] 10423 "TARGET_INDIRECT_BRANCH_NOBP_CALL 10424 && !TARGET_CPU_Z10 10425 && !SIBLING_CALL_P (insn) 10426 && GET_MODE (operands[3]) == Pmode" 10427{ 10428 s390_indirect_branch_via_thunk (REGNO (operands[1]), 10429 REGNO (operands[3]), 10430 NULL_RTX, 10431 s390_indirect_branch_type_call); 10432 return ""; 10433} 10434 [(set_attr "op_type" "RIL") 10435 (set_attr "mnemonic" "brasl") 10436 (set_attr "type" "jsr") 10437 (set_attr "atype" "agen") 10438 (set_attr "z196prop" "z196_cracked")]) 10439 10440;; 10441;;- Thread-local storage support. 10442;; 10443 10444(define_expand "get_thread_pointer<mode>" 10445 [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))] 10446 "" 10447 "") 10448 10449(define_expand "set_thread_pointer<mode>" 10450 [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" "")) 10451 (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))] 10452 "" 10453 "") 10454 10455(define_insn "*set_tp" 10456 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] 10457 "" 10458 "" 10459 [(set_attr "type" "none") 10460 (set_attr "length" "0")]) 10461 10462(define_insn "*tls_load_64" 10463 [(set (match_operand:DI 0 "register_operand" "=d") 10464 (unspec:DI [(match_operand:DI 1 "memory_operand" "T") 10465 (match_operand:DI 2 "" "")] 10466 UNSPEC_TLS_LOAD))] 10467 "TARGET_64BIT" 10468 "lg\t%0,%1%J2" 10469 [(set_attr "op_type" "RXE") 10470 (set_attr "z10prop" "z10_fwd_A3")]) 10471 10472(define_insn "*tls_load_31" 10473 [(set (match_operand:SI 0 "register_operand" "=d,d") 10474 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") 10475 (match_operand:SI 2 "" "")] 10476 UNSPEC_TLS_LOAD))] 10477 "!TARGET_64BIT" 10478 "@ 10479 l\t%0,%1%J2 10480 ly\t%0,%1%J2" 10481 [(set_attr "op_type" "RX,RXY") 10482 (set_attr "type" "load") 10483 (set_attr "cpu_facility" "*,longdisp") 10484 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) 10485 10486(define_insn "*bras_tls" 10487 [(set (match_operand 0 "" "") 10488 (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) 10489 (match_operand 2 "const_int_operand" "n"))) 10490 (clobber (match_operand 3 "register_operand" "=r")) 10491 (use (match_operand 4 "" ""))] 10492 "!SIBLING_CALL_P (insn) 10493 && TARGET_SMALL_EXEC 10494 && GET_MODE (operands[3]) == Pmode" 10495 "bras\t%3,%1%J4" 10496 [(set_attr "op_type" "RI") 10497 (set_attr "type" "jsr") 10498 (set_attr "z196prop" "z196_cracked")]) 10499 10500(define_insn "*brasl_tls" 10501 [(set (match_operand 0 "" "") 10502 (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) 10503 (match_operand 2 "const_int_operand" "n"))) 10504 (clobber (match_operand 3 "register_operand" "=r")) 10505 (use (match_operand 4 "" ""))] 10506 "!SIBLING_CALL_P (insn) 10507 && TARGET_CPU_ZARCH 10508 && GET_MODE (operands[3]) == Pmode" 10509 "brasl\t%3,%1%J4" 10510 [(set_attr "op_type" "RIL") 10511 (set_attr "type" "jsr") 10512 (set_attr "z196prop" "z196_cracked")]) 10513 10514(define_insn "*basr_tls" 10515 [(set (match_operand 0 "" "") 10516 (call (mem:QI (match_operand 1 "address_operand" "ZR")) 10517 (match_operand 2 "const_int_operand" "n"))) 10518 (clobber (match_operand 3 "register_operand" "=r")) 10519 (use (match_operand 4 "" ""))] 10520 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" 10521{ 10522 if (get_attr_op_type (insn) == OP_TYPE_RR) 10523 return "basr\t%3,%1%J4"; 10524 else 10525 return "bas\t%3,%a1%J4"; 10526} 10527 [(set (attr "op_type") 10528 (if_then_else (match_operand 1 "register_operand" "") 10529 (const_string "RR") (const_string "RX"))) 10530 (set_attr "type" "jsr") 10531 (set_attr "atype" "agen") 10532 (set_attr "z196prop" "z196_cracked")]) 10533 10534;; 10535;;- Atomic operations 10536;; 10537 10538; 10539; memory barrier patterns. 10540; 10541 10542(define_expand "mem_thread_fence" 10543 [(match_operand:SI 0 "const_int_operand")] ;; model 10544 "" 10545{ 10546 /* Unless this is a SEQ_CST fence, the s390 memory model is strong 10547 enough not to require barriers of any kind. */ 10548 if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0])))) 10549 { 10550 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); 10551 MEM_VOLATILE_P (mem) = 1; 10552 emit_insn (gen_mem_thread_fence_1 (mem)); 10553 } 10554 DONE; 10555}) 10556 10557; Although bcr is superscalar on Z10, this variant will never 10558; become part of an execution group. 10559; With z196 we can make use of the fast-BCR-serialization facility. 10560; This allows for a slightly faster sync which is sufficient for our 10561; purposes. 10562(define_insn "mem_thread_fence_1" 10563 [(set (match_operand:BLK 0 "" "") 10564 (unspec:BLK [(match_dup 0)] UNSPEC_MB))] 10565 "" 10566{ 10567 if (TARGET_Z196) 10568 return "bcr\t14,0"; 10569 else 10570 return "bcr\t15,0"; 10571} 10572 [(set_attr "op_type" "RR") 10573 (set_attr "mnemonic" "bcr_flush") 10574 (set_attr "z196prop" "z196_alone")]) 10575 10576; 10577; atomic load/store operations 10578; 10579 10580; Atomic loads need not examine the memory model at all. 10581(define_expand "atomic_load<mode>" 10582 [(match_operand:DINT 0 "register_operand") ;; output 10583 (match_operand:DINT 1 "memory_operand") ;; memory 10584 (match_operand:SI 2 "const_int_operand")] ;; model 10585 "" 10586{ 10587 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) 10588 FAIL; 10589 10590 if (<MODE>mode == TImode) 10591 emit_insn (gen_atomic_loadti_1 (operands[0], operands[1])); 10592 else if (<MODE>mode == DImode && !TARGET_ZARCH) 10593 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1])); 10594 else 10595 emit_move_insn (operands[0], operands[1]); 10596 DONE; 10597}) 10598 10599; Different from movdi_31 in that we want no splitters. 10600(define_insn "atomic_loaddi_1" 10601 [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f") 10602 (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")] 10603 UNSPEC_MOVA))] 10604 "!TARGET_ZARCH" 10605 "@ 10606 lm\t%0,%M0,%S1 10607 lmy\t%0,%M0,%S1 10608 ld\t%0,%1 10609 ldy\t%0,%1" 10610 [(set_attr "op_type" "RS,RSY,RS,RSY") 10611 (set_attr "cpu_facility" "*,longdisp,*,longdisp") 10612 (set_attr "type" "lm,lm,floaddf,floaddf")]) 10613 10614(define_insn "atomic_loadti_1" 10615 [(set (match_operand:TI 0 "register_operand" "=r") 10616 (unspec:TI [(match_operand:TI 1 "memory_operand" "T")] 10617 UNSPEC_MOVA))] 10618 "TARGET_ZARCH" 10619 "lpq\t%0,%1" 10620 [(set_attr "op_type" "RXY") 10621 (set_attr "type" "other")]) 10622 10623; Atomic stores must(?) enforce sequential consistency. 10624(define_expand "atomic_store<mode>" 10625 [(match_operand:DINT 0 "memory_operand") ;; memory 10626 (match_operand:DINT 1 "register_operand") ;; input 10627 (match_operand:SI 2 "const_int_operand")] ;; model 10628 "" 10629{ 10630 enum memmodel model = memmodel_from_int (INTVAL (operands[2])); 10631 10632 if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0]))) 10633 FAIL; 10634 10635 if (<MODE>mode == TImode) 10636 emit_insn (gen_atomic_storeti_1 (operands[0], operands[1])); 10637 else if (<MODE>mode == DImode && !TARGET_ZARCH) 10638 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1])); 10639 else 10640 emit_move_insn (operands[0], operands[1]); 10641 if (is_mm_seq_cst (model)) 10642 emit_insn (gen_mem_thread_fence (operands[2])); 10643 DONE; 10644}) 10645 10646; Different from movdi_31 in that we want no splitters. 10647(define_insn "atomic_storedi_1" 10648 [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T") 10649 (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")] 10650 UNSPEC_MOVA))] 10651 "!TARGET_ZARCH" 10652 "@ 10653 stm\t%1,%N1,%S0 10654 stmy\t%1,%N1,%S0 10655 std %1,%0 10656 stdy %1,%0" 10657 [(set_attr "op_type" "RS,RSY,RS,RSY") 10658 (set_attr "cpu_facility" "*,longdisp,*,longdisp") 10659 (set_attr "type" "stm,stm,fstoredf,fstoredf")]) 10660 10661(define_insn "atomic_storeti_1" 10662 [(set (match_operand:TI 0 "memory_operand" "=T") 10663 (unspec:TI [(match_operand:TI 1 "register_operand" "r")] 10664 UNSPEC_MOVA))] 10665 "TARGET_ZARCH" 10666 "stpq\t%1,%0" 10667 [(set_attr "op_type" "RXY") 10668 (set_attr "type" "other")]) 10669 10670; 10671; compare and swap patterns. 10672; 10673 10674(define_expand "atomic_compare_and_swap<mode>" 10675 [(match_operand:SI 0 "register_operand") ;; bool success output 10676 (match_operand:DINT 1 "nonimmediate_operand");; oldval output 10677 (match_operand:DINT 2 "s_operand") ;; memory 10678 (match_operand:DINT 3 "general_operand") ;; expected intput 10679 (match_operand:DINT 4 "general_operand") ;; newval intput 10680 (match_operand:SI 5 "const_int_operand") ;; is_weak 10681 (match_operand:SI 6 "const_int_operand") ;; success model 10682 (match_operand:SI 7 "const_int_operand")] ;; failure model 10683 "" 10684{ 10685 if (GET_MODE_BITSIZE (<MODE>mode) >= 16 10686 && GET_MODE_BITSIZE (<MODE>mode) > MEM_ALIGN (operands[2])) 10687 FAIL; 10688 10689 s390_expand_cs (<MODE>mode, operands[0], operands[1], operands[2], 10690 operands[3], operands[4], INTVAL (operands[5])); 10691 DONE;}) 10692 10693(define_expand "atomic_compare_and_swap<mode>_internal" 10694 [(parallel 10695 [(set (match_operand:DGPR 0 "register_operand") 10696 (match_operand:DGPR 1 "s_operand")) 10697 (set (match_dup 1) 10698 (unspec_volatile:DGPR 10699 [(match_dup 1) 10700 (match_operand:DGPR 2 "register_operand") 10701 (match_operand:DGPR 3 "register_operand")] 10702 UNSPECV_CAS)) 10703 (set (match_operand 4 "cc_reg_operand") 10704 (match_dup 5))])] 10705 "GET_MODE (operands[4]) == CCZmode 10706 || GET_MODE (operands[4]) == CCZ1mode" 10707{ 10708 operands[5] 10709 = gen_rtx_COMPARE (GET_MODE (operands[4]), operands[1], operands[2]); 10710}) 10711 10712; cdsg, csg 10713(define_insn "*atomic_compare_and_swap<mode>_1" 10714 [(set (match_operand:TDI 0 "register_operand" "=r") 10715 (match_operand:TDI 1 "memory_operand" "+S")) 10716 (set (match_dup 1) 10717 (unspec_volatile:TDI 10718 [(match_dup 1) 10719 (match_operand:TDI 2 "register_operand" "0") 10720 (match_operand:TDI 3 "register_operand" "r")] 10721 UNSPECV_CAS)) 10722 (set (reg CC_REGNUM) 10723 (compare (match_dup 1) (match_dup 2)))] 10724 "TARGET_ZARCH 10725 && s390_match_ccmode (insn, CCZ1mode)" 10726 "c<td>sg\t%0,%3,%S1" 10727 [(set_attr "op_type" "RSY") 10728 (set_attr "type" "sem")]) 10729 10730; cds, cdsy 10731(define_insn "*atomic_compare_and_swapdi_2" 10732 [(set (match_operand:DI 0 "register_operand" "=r,r") 10733 (match_operand:DI 1 "memory_operand" "+Q,S")) 10734 (set (match_dup 1) 10735 (unspec_volatile:DI 10736 [(match_dup 1) 10737 (match_operand:DI 2 "register_operand" "0,0") 10738 (match_operand:DI 3 "register_operand" "r,r")] 10739 UNSPECV_CAS)) 10740 (set (reg CC_REGNUM) 10741 (compare (match_dup 1) (match_dup 2)))] 10742 "!TARGET_ZARCH 10743 && s390_match_ccmode (insn, CCZ1mode)" 10744 "@ 10745 cds\t%0,%3,%S1 10746 cdsy\t%0,%3,%S1" 10747 [(set_attr "op_type" "RS,RSY") 10748 (set_attr "cpu_facility" "*,longdisp") 10749 (set_attr "type" "sem")]) 10750 10751; cs, csy 10752(define_insn "*atomic_compare_and_swapsi_3" 10753 [(set (match_operand:SI 0 "register_operand" "=r,r") 10754 (match_operand:SI 1 "memory_operand" "+Q,S")) 10755 (set (match_dup 1) 10756 (unspec_volatile:SI 10757 [(match_dup 1) 10758 (match_operand:SI 2 "register_operand" "0,0") 10759 (match_operand:SI 3 "register_operand" "r,r")] 10760 UNSPECV_CAS)) 10761 (set (reg CC_REGNUM) 10762 (compare (match_dup 1) (match_dup 2)))] 10763 "s390_match_ccmode (insn, CCZ1mode)" 10764 "@ 10765 cs\t%0,%3,%S1 10766 csy\t%0,%3,%S1" 10767 [(set_attr "op_type" "RS,RSY") 10768 (set_attr "cpu_facility" "*,longdisp") 10769 (set_attr "type" "sem")]) 10770 10771; 10772; Other atomic instruction patterns. 10773; 10774 10775; z196 load and add, xor, or and and instructions 10776 10777(define_expand "atomic_fetch_<atomic><mode>" 10778 [(match_operand:GPR 0 "register_operand") ;; val out 10779 (ATOMIC_Z196:GPR 10780 (match_operand:GPR 1 "memory_operand") ;; memory 10781 (match_operand:GPR 2 "register_operand")) ;; val in 10782 (match_operand:SI 3 "const_int_operand")] ;; model 10783 "TARGET_Z196" 10784{ 10785 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) 10786 FAIL; 10787 10788 emit_insn (gen_atomic_fetch_<atomic><mode>_iaf 10789 (operands[0], operands[1], operands[2])); 10790 DONE; 10791}) 10792 10793; lan, lang, lao, laog, lax, laxg, laa, laag 10794(define_insn "atomic_fetch_<atomic><mode>_iaf" 10795 [(set (match_operand:GPR 0 "register_operand" "=d") 10796 (match_operand:GPR 1 "memory_operand" "+S")) 10797 (set (match_dup 1) 10798 (unspec_volatile:GPR 10799 [(ATOMIC_Z196:GPR (match_dup 1) 10800 (match_operand:GPR 2 "general_operand" "d"))] 10801 UNSPECV_ATOMIC_OP)) 10802 (clobber (reg:CC CC_REGNUM))] 10803 "TARGET_Z196" 10804 "la<noxa><g>\t%0,%2,%1" 10805 [(set_attr "op_type" "RSY") 10806 (set_attr "type" "sem")]) 10807 10808;; For SImode and larger, the optabs.c code will do just fine in 10809;; expanding a compare-and-swap loop. For QI/HImode, we can do 10810;; better by expanding our own loop. 10811 10812(define_expand "atomic_<atomic><mode>" 10813 [(ATOMIC:HQI 10814 (match_operand:HQI 0 "memory_operand") ;; memory 10815 (match_operand:HQI 1 "general_operand")) ;; val in 10816 (match_operand:SI 2 "const_int_operand")] ;; model 10817 "" 10818{ 10819 s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], 10820 operands[1], false); 10821 DONE; 10822}) 10823 10824(define_expand "atomic_fetch_<atomic><mode>" 10825 [(match_operand:HQI 0 "register_operand") ;; val out 10826 (ATOMIC:HQI 10827 (match_operand:HQI 1 "memory_operand") ;; memory 10828 (match_operand:HQI 2 "general_operand")) ;; val in 10829 (match_operand:SI 3 "const_int_operand")] ;; model 10830 "" 10831{ 10832 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], 10833 operands[2], false); 10834 DONE; 10835}) 10836 10837(define_expand "atomic_<atomic>_fetch<mode>" 10838 [(match_operand:HQI 0 "register_operand") ;; val out 10839 (ATOMIC:HQI 10840 (match_operand:HQI 1 "memory_operand") ;; memory 10841 (match_operand:HQI 2 "general_operand")) ;; val in 10842 (match_operand:SI 3 "const_int_operand")] ;; model 10843 "" 10844{ 10845 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], 10846 operands[2], true); 10847 DONE; 10848}) 10849 10850;; Pattern to implement atomic_exchange with a compare-and-swap loop. The code 10851;; generated by the middleend is not good. 10852(define_expand "atomic_exchange<mode>" 10853 [(match_operand:DINT 0 "register_operand") ;; val out 10854 (match_operand:DINT 1 "s_operand") ;; memory 10855 (match_operand:DINT 2 "general_operand") ;; val in 10856 (match_operand:SI 3 "const_int_operand")] ;; model 10857 "" 10858{ 10859 if (<MODE>mode != QImode 10860 && MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (<MODE>mode)) 10861 FAIL; 10862 if (<MODE>mode == HImode || <MODE>mode == QImode) 10863 s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], operands[2], 10864 false); 10865 else if (<MODE>mode == SImode || TARGET_ZARCH) 10866 s390_expand_atomic_exchange_tdsi (operands[0], operands[1], operands[2]); 10867 else 10868 FAIL; 10869 DONE; 10870}) 10871 10872;; 10873;;- Miscellaneous instructions. 10874;; 10875 10876; 10877; allocate stack instruction pattern(s). 10878; 10879 10880(define_expand "allocate_stack" 10881 [(match_operand 0 "general_operand" "") 10882 (match_operand 1 "general_operand" "")] 10883 "TARGET_BACKCHAIN" 10884{ 10885 rtx temp = gen_reg_rtx (Pmode); 10886 10887 emit_move_insn (temp, s390_back_chain_rtx ()); 10888 anti_adjust_stack (operands[1]); 10889 emit_move_insn (s390_back_chain_rtx (), temp); 10890 10891 emit_move_insn (operands[0], virtual_stack_dynamic_rtx); 10892 DONE; 10893}) 10894 10895 10896; 10897; setjmp instruction pattern. 10898; 10899 10900(define_expand "builtin_setjmp_receiver" 10901 [(match_operand 0 "" "")] 10902 "flag_pic" 10903{ 10904 emit_insn (s390_load_got ()); 10905 emit_use (pic_offset_table_rtx); 10906 DONE; 10907}) 10908 10909;; These patterns say how to save and restore the stack pointer. We need not 10910;; save the stack pointer at function level since we are careful to 10911;; preserve the backchain. At block level, we have to restore the backchain 10912;; when we restore the stack pointer. 10913;; 10914;; For nonlocal gotos, we must save both the stack pointer and its 10915;; backchain and restore both. Note that in the nonlocal case, the 10916;; save area is a memory location. 10917 10918(define_expand "save_stack_function" 10919 [(match_operand 0 "general_operand" "") 10920 (match_operand 1 "general_operand" "")] 10921 "" 10922 "DONE;") 10923 10924(define_expand "restore_stack_function" 10925 [(match_operand 0 "general_operand" "") 10926 (match_operand 1 "general_operand" "")] 10927 "" 10928 "DONE;") 10929 10930(define_expand "restore_stack_block" 10931 [(match_operand 0 "register_operand" "") 10932 (match_operand 1 "register_operand" "")] 10933 "TARGET_BACKCHAIN" 10934{ 10935 rtx temp = gen_reg_rtx (Pmode); 10936 10937 emit_move_insn (temp, s390_back_chain_rtx ()); 10938 emit_move_insn (operands[0], operands[1]); 10939 emit_move_insn (s390_back_chain_rtx (), temp); 10940 10941 DONE; 10942}) 10943 10944(define_expand "save_stack_nonlocal" 10945 [(match_operand 0 "memory_operand" "") 10946 (match_operand 1 "register_operand" "")] 10947 "" 10948{ 10949 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); 10950 10951 /* Copy the backchain to the first word, sp to the second and the 10952 literal pool base to the third. */ 10953 10954 rtx save_bc = adjust_address (operands[0], Pmode, 0); 10955 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode)); 10956 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode)); 10957 10958 if (TARGET_BACKCHAIN) 10959 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ())); 10960 10961 emit_move_insn (save_sp, operands[1]); 10962 emit_move_insn (save_bp, base); 10963 10964 DONE; 10965}) 10966 10967(define_expand "restore_stack_nonlocal" 10968 [(match_operand 0 "register_operand" "") 10969 (match_operand 1 "memory_operand" "")] 10970 "" 10971{ 10972 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); 10973 rtx temp = NULL_RTX; 10974 10975 /* Restore the backchain from the first word, sp from the second and the 10976 literal pool base from the third. */ 10977 10978 rtx save_bc = adjust_address (operands[1], Pmode, 0); 10979 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode)); 10980 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode)); 10981 10982 if (TARGET_BACKCHAIN) 10983 temp = force_reg (Pmode, save_bc); 10984 10985 emit_move_insn (base, save_bp); 10986 emit_move_insn (operands[0], save_sp); 10987 10988 if (temp) 10989 emit_move_insn (s390_back_chain_rtx (), temp); 10990 10991 emit_use (base); 10992 DONE; 10993}) 10994 10995(define_expand "exception_receiver" 10996 [(const_int 0)] 10997 "" 10998{ 10999 s390_set_has_landing_pad_p (true); 11000 DONE; 11001}) 11002 11003; 11004; nop instruction pattern(s). 11005; 11006 11007(define_insn "nop" 11008 [(const_int 0)] 11009 "" 11010 "nopr\t%%r0" 11011 [(set_attr "op_type" "RR")]) 11012 11013; non-branch NOPs required for optimizing compare-and-branch patterns 11014; on z10 11015 11016(define_insn "nop_lr0" 11017 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_LR_0)] 11018 "" 11019 "lr\t0,0" 11020 [(set_attr "op_type" "RR") 11021 (set_attr "z10prop" "z10_fr_E1")]) 11022 11023(define_insn "nop_lr1" 11024 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_LR_1)] 11025 "" 11026 "lr\t1,1" 11027 [(set_attr "op_type" "RR")]) 11028 11029;;- Undeletable nops (used for hotpatching) 11030 11031(define_insn "nop_2_byte" 11032 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)] 11033 "" 11034 "nopr\t%%r0" 11035 [(set_attr "op_type" "RR")]) 11036 11037(define_insn "nop_4_byte" 11038 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)] 11039 "" 11040 "nop\t0" 11041 [(set_attr "op_type" "RX")]) 11042 11043(define_insn "nop_6_byte" 11044 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)] 11045 "TARGET_CPU_ZARCH" 11046 "brcl\t0, 0" 11047 [(set_attr "op_type" "RIL")]) 11048 11049 11050; 11051; Special literal pool access instruction pattern(s). 11052; 11053 11054(define_insn "*pool_entry" 11055 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] 11056 UNSPECV_POOL_ENTRY)] 11057 "" 11058{ 11059 machine_mode mode = GET_MODE (PATTERN (insn)); 11060 unsigned int align = GET_MODE_BITSIZE (mode); 11061 s390_output_pool_entry (operands[0], mode, align); 11062 return ""; 11063} 11064 [(set (attr "length") 11065 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) 11066 11067(define_insn "pool_align" 11068 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] 11069 UNSPECV_POOL_ALIGN)] 11070 "" 11071 ".align\t%0" 11072 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) 11073 11074(define_insn "pool_section_start" 11075 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] 11076 "" 11077{ 11078 switch_to_section (targetm.asm_out.function_rodata_section 11079 (current_function_decl)); 11080 return ""; 11081} 11082 [(set_attr "length" "0")]) 11083 11084(define_insn "pool_section_end" 11085 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] 11086 "" 11087{ 11088 switch_to_section (current_function_section ()); 11089 return ""; 11090} 11091 [(set_attr "length" "0")]) 11092 11093(define_insn "main_base_31_small" 11094 [(set (match_operand 0 "register_operand" "=a") 11095 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] 11096 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" 11097 "basr\t%0,0" 11098 [(set_attr "op_type" "RR") 11099 (set_attr "type" "la") 11100 (set_attr "z196prop" "z196_cracked")]) 11101 11102(define_insn "main_base_31_large" 11103 [(set (match_operand 0 "register_operand" "=a") 11104 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) 11105 (set (pc) (label_ref (match_operand 2 "" "")))] 11106 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" 11107 "bras\t%0,%2" 11108 [(set_attr "op_type" "RI") 11109 (set_attr "z196prop" "z196_cracked")]) 11110 11111(define_insn "main_base_64" 11112 [(set (match_operand 0 "register_operand" "=a") 11113 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] 11114 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" 11115 "larl\t%0,%1" 11116 [(set_attr "op_type" "RIL") 11117 (set_attr "type" "larl") 11118 (set_attr "z10prop" "z10_fwd_A1")]) 11119 11120(define_insn "main_pool" 11121 [(set (match_operand 0 "register_operand" "=a") 11122 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] 11123 "GET_MODE (operands[0]) == Pmode" 11124{ 11125 gcc_unreachable (); 11126} 11127 [(set (attr "type") 11128 (if_then_else (match_test "TARGET_CPU_ZARCH") 11129 (const_string "larl") (const_string "la")))]) 11130 11131(define_insn "reload_base_31" 11132 [(set (match_operand 0 "register_operand" "=a") 11133 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] 11134 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" 11135 "basr\t%0,0\;la\t%0,%1-.(%0)" 11136 [(set_attr "length" "6") 11137 (set_attr "type" "la") 11138 (set_attr "z196prop" "z196_cracked")]) 11139 11140(define_insn "reload_base_64" 11141 [(set (match_operand 0 "register_operand" "=a") 11142 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] 11143 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" 11144 "larl\t%0,%1" 11145 [(set_attr "op_type" "RIL") 11146 (set_attr "type" "larl") 11147 (set_attr "z10prop" "z10_fwd_A1")]) 11148 11149(define_insn "pool" 11150 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] 11151 "" 11152{ 11153 gcc_unreachable (); 11154} 11155 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) 11156 11157;; 11158;; Insns related to generating the function prologue and epilogue. 11159;; 11160 11161 11162(define_expand "prologue" 11163 [(use (const_int 0))] 11164 "" 11165 "s390_emit_prologue (); DONE;") 11166 11167(define_expand "epilogue" 11168 [(use (const_int 1))] 11169 "" 11170 "s390_emit_epilogue (false); DONE;") 11171 11172(define_expand "sibcall_epilogue" 11173 [(use (const_int 0))] 11174 "" 11175 "s390_emit_epilogue (true); DONE;") 11176 11177;; A direct return instruction, without using an epilogue. 11178(define_insn "<code>" 11179 [(ANY_RETURN)] 11180 "s390_can_use_<code>_insn ()" 11181{ 11182 if (TARGET_INDIRECT_BRANCH_NOBP_RET) 11183 { 11184 /* The target is always r14 so there is no clobber 11185 of r1 needed for pre z10 targets. */ 11186 s390_indirect_branch_via_thunk (RETURN_REGNUM, 11187 INVALID_REGNUM, 11188 NULL_RTX, 11189 s390_indirect_branch_type_return); 11190 return ""; 11191 } 11192 else 11193 return "br\t%%r14"; 11194} 11195 [(set (attr "op_type") 11196 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") 11197 (const_string "RIL") 11198 (const_string "RR"))) 11199 (set (attr "mnemonic") 11200 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") 11201 (const_string "jg") 11202 (const_string "br"))) 11203 (set_attr "type" "jsr") 11204 (set_attr "atype" "agen")]) 11205 11206 11207(define_expand "return_use" 11208 [(parallel 11209 [(return) 11210 (use (match_operand 0 "register_operand" "a"))])] 11211 "" 11212{ 11213 if (!TARGET_CPU_Z10 11214 && TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION) 11215 { 11216 if (TARGET_64BIT) 11217 emit_jump_insn (gen_returndi_prez10 (operands[0])); 11218 else 11219 emit_jump_insn (gen_returnsi_prez10 (operands[0])); 11220 DONE; 11221 } 11222}) 11223 11224(define_insn "*return<mode>" 11225 [(return) 11226 (use (match_operand:P 0 "register_operand" "a"))] 11227 "TARGET_CPU_Z10 || !TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION" 11228{ 11229 if (TARGET_INDIRECT_BRANCH_NOBP_RET) 11230 { 11231 s390_indirect_branch_via_thunk (REGNO (operands[0]), 11232 INVALID_REGNUM, 11233 NULL_RTX, 11234 s390_indirect_branch_type_return); 11235 return ""; 11236 } 11237 else 11238 return "br\t%0"; 11239} 11240 [(set (attr "op_type") 11241 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") 11242 (const_string "RIL") 11243 (const_string "RR"))) 11244 (set (attr "mnemonic") 11245 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") 11246 (const_string "jg") 11247 (const_string "br"))) 11248 (set_attr "type" "jsr") 11249 (set_attr "atype" "agen")]) 11250 11251(define_insn "return<mode>_prez10" 11252 [(return) 11253 (use (match_operand:P 0 "register_operand" "a")) 11254 (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] 11255 "!TARGET_CPU_Z10 && TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION" 11256{ 11257 if (TARGET_INDIRECT_BRANCH_NOBP_RET) 11258 { 11259 s390_indirect_branch_via_thunk (REGNO (operands[0]), 11260 INVALID_REGNUM, 11261 NULL_RTX, 11262 s390_indirect_branch_type_return); 11263 return ""; 11264 } 11265 else 11266 return "br\t%0"; 11267} 11268 [(set (attr "op_type") 11269 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") 11270 (const_string "RIL") 11271 (const_string "RR"))) 11272 (set (attr "mnemonic") 11273 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") 11274 (const_string "jg") 11275 (const_string "br"))) 11276 (set_attr "type" "jsr") 11277 (set_attr "atype" "agen")]) 11278 11279 11280;; Instruction definition to extend a 31-bit pointer into a 64-bit 11281;; pointer. This is used for compatibility. 11282 11283(define_expand "ptr_extend" 11284 [(set (match_operand:DI 0 "register_operand" "=r") 11285 (match_operand:SI 1 "register_operand" "r"))] 11286 "TARGET_64BIT" 11287{ 11288 emit_insn (gen_anddi3 (operands[0], 11289 gen_lowpart (DImode, operands[1]), 11290 GEN_INT (0x7fffffff))); 11291 DONE; 11292}) 11293 11294;; Instruction definition to expand eh_return macro to support 11295;; swapping in special linkage return addresses. 11296 11297(define_expand "eh_return" 11298 [(use (match_operand 0 "register_operand" ""))] 11299 "TARGET_TPF" 11300{ 11301 s390_emit_tpf_eh_return (operands[0]); 11302 DONE; 11303}) 11304 11305; 11306; Stack Protector Patterns 11307; 11308 11309(define_expand "stack_protect_set" 11310 [(set (match_operand 0 "memory_operand" "") 11311 (match_operand 1 "memory_operand" ""))] 11312 "" 11313{ 11314#ifdef TARGET_THREAD_SSP_OFFSET 11315 operands[1] 11316 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), 11317 GEN_INT (TARGET_THREAD_SSP_OFFSET))); 11318#endif 11319 if (TARGET_64BIT) 11320 emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); 11321 else 11322 emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); 11323 11324 DONE; 11325}) 11326 11327(define_insn "stack_protect_set<mode>" 11328 [(set (match_operand:DSI 0 "memory_operand" "=Q") 11329 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] 11330 "" 11331 "mvc\t%O0(%G0,%R0),%S1" 11332 [(set_attr "op_type" "SS")]) 11333 11334(define_expand "stack_protect_test" 11335 [(set (reg:CC CC_REGNUM) 11336 (compare (match_operand 0 "memory_operand" "") 11337 (match_operand 1 "memory_operand" ""))) 11338 (match_operand 2 "" "")] 11339 "" 11340{ 11341 rtx cc_reg, test; 11342#ifdef TARGET_THREAD_SSP_OFFSET 11343 operands[1] 11344 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), 11345 GEN_INT (TARGET_THREAD_SSP_OFFSET))); 11346#endif 11347 if (TARGET_64BIT) 11348 emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); 11349 else 11350 emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); 11351 11352 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM); 11353 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx); 11354 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2])); 11355 DONE; 11356}) 11357 11358(define_insn "stack_protect_test<mode>" 11359 [(set (reg:CCZ CC_REGNUM) 11360 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q") 11361 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] 11362 "" 11363 "clc\t%O0(%G0,%R0),%S1" 11364 [(set_attr "op_type" "SS")]) 11365 11366; This is used in s390_emit_prologue in order to prevent insns 11367; adjusting the stack pointer to be moved over insns writing stack 11368; slots using a copy of the stack pointer in a different register. 11369(define_insn "stack_tie" 11370 [(set (match_operand:BLK 0 "memory_operand" "+m") 11371 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] 11372 "" 11373 "" 11374 [(set_attr "length" "0")]) 11375 11376 11377(define_insn "stack_restore_from_fpr" 11378 [(set (reg:DI STACK_REGNUM) 11379 (match_operand:DI 0 "register_operand" "f")) 11380 (clobber (mem:BLK (scratch)))] 11381 "TARGET_Z10" 11382 "lgdr\t%%r15,%0" 11383 [(set_attr "op_type" "RRE")]) 11384 11385; 11386; Data prefetch patterns 11387; 11388 11389(define_insn "prefetch" 11390 [(prefetch (match_operand 0 "address_operand" "ZT,X") 11391 (match_operand:SI 1 "const_int_operand" " n,n") 11392 (match_operand:SI 2 "const_int_operand" " n,n"))] 11393 "TARGET_Z10" 11394{ 11395 switch (which_alternative) 11396 { 11397 case 0: 11398 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0"; 11399 case 1: 11400 if (larl_operand (operands[0], Pmode)) 11401 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0"; 11402 /* fallthrough */ 11403 default: 11404 11405 /* This might be reached for symbolic operands with an odd 11406 addend. We simply omit the prefetch for such rare cases. */ 11407 11408 return ""; 11409 } 11410} 11411 [(set_attr "type" "load,larl") 11412 (set_attr "op_type" "RXY,RIL") 11413 (set_attr "z10prop" "z10_super") 11414 (set_attr "z196prop" "z196_alone")]) 11415 11416 11417; 11418; Byte swap instructions 11419; 11420 11421; FIXME: There is also mvcin but we cannot use it since src and target 11422; may overlap. 11423; lrvr, lrv, strv, lrvgr, lrvg, strvg 11424(define_insn "bswap<mode>2" 11425 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,T") 11426 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,T,d")))] 11427 "TARGET_CPU_ZARCH" 11428 "@ 11429 lrv<g>r\t%0,%1 11430 lrv<g>\t%0,%1 11431 strv<g>\t%1,%0" 11432 [(set_attr "type" "*,load,store") 11433 (set_attr "op_type" "RRE,RXY,RXY") 11434 (set_attr "z10prop" "z10_super")]) 11435 11436(define_insn "bswaphi2" 11437 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,T") 11438 (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,T,d")))] 11439 "TARGET_CPU_ZARCH" 11440 "@ 11441 # 11442 lrvh\t%0,%1 11443 strvh\t%1,%0" 11444 [(set_attr "type" "*,load,store") 11445 (set_attr "op_type" "RRE,RXY,RXY") 11446 (set_attr "z10prop" "z10_super")]) 11447 11448(define_split 11449 [(set (match_operand:HI 0 "register_operand" "") 11450 (bswap:HI (match_operand:HI 1 "register_operand" "")))] 11451 "TARGET_CPU_ZARCH" 11452 [(set (match_dup 2) (bswap:SI (match_dup 3))) 11453 (set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 16)))] 11454{ 11455 operands[2] = simplify_gen_subreg (SImode, operands[0], HImode, 0); 11456 operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0); 11457}) 11458 11459 11460; 11461; Population count instruction 11462; 11463 11464; The S/390 popcount instruction counts the bits of op1 in 8 byte 11465; portions and stores the result in the corresponding bytes in op0. 11466(define_insn "*popcount<mode>" 11467 [(set (match_operand:INT 0 "register_operand" "=d") 11468 (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT)) 11469 (clobber (reg:CC CC_REGNUM))] 11470 "TARGET_Z196" 11471 "popcnt\t%0,%1" 11472 [(set_attr "op_type" "RRE")]) 11473 11474(define_expand "popcountdi2" 11475 [; popcnt op0, op1 11476 (parallel [(set (match_operand:DI 0 "register_operand" "") 11477 (unspec:DI [(match_operand:DI 1 "register_operand")] 11478 UNSPEC_POPCNT)) 11479 (clobber (reg:CC CC_REGNUM))]) 11480 ; sllg op2, op0, 32 11481 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32))) 11482 ; agr op0, op2 11483 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) 11484 (clobber (reg:CC CC_REGNUM))]) 11485 ; sllg op2, op0, 16 11486 (set (match_dup 2) 11487 (ashift:DI (match_dup 0) (const_int 16))) 11488 ; agr op0, op2 11489 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) 11490 (clobber (reg:CC CC_REGNUM))]) 11491 ; sllg op2, op0, 8 11492 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8))) 11493 ; agr op0, op2 11494 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) 11495 (clobber (reg:CC CC_REGNUM))]) 11496 ; srlg op0, op0, 56 11497 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))] 11498 "TARGET_Z196 && TARGET_64BIT" 11499 "operands[2] = gen_reg_rtx (DImode);") 11500 11501(define_expand "popcountsi2" 11502 [; popcnt op0, op1 11503 (parallel [(set (match_operand:SI 0 "register_operand" "") 11504 (unspec:SI [(match_operand:SI 1 "register_operand")] 11505 UNSPEC_POPCNT)) 11506 (clobber (reg:CC CC_REGNUM))]) 11507 ; sllk op2, op0, 16 11508 (set (match_dup 2) 11509 (ashift:SI (match_dup 0) (const_int 16))) 11510 ; ar op0, op2 11511 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) 11512 (clobber (reg:CC CC_REGNUM))]) 11513 ; sllk op2, op0, 8 11514 (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8))) 11515 ; ar op0, op2 11516 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) 11517 (clobber (reg:CC CC_REGNUM))]) 11518 ; srl op0, op0, 24 11519 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))] 11520 "TARGET_Z196" 11521 "operands[2] = gen_reg_rtx (SImode);") 11522 11523(define_expand "popcounthi2" 11524 [; popcnt op0, op1 11525 (parallel [(set (match_operand:HI 0 "register_operand" "") 11526 (unspec:HI [(match_operand:HI 1 "register_operand")] 11527 UNSPEC_POPCNT)) 11528 (clobber (reg:CC CC_REGNUM))]) 11529 ; sllk op2, op0, 8 11530 (set (match_dup 2) 11531 (ashift:SI (match_dup 0) (const_int 8))) 11532 ; ar op0, op2 11533 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) 11534 (clobber (reg:CC CC_REGNUM))]) 11535 ; srl op0, op0, 8 11536 (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))] 11537 "TARGET_Z196" 11538 "operands[2] = gen_reg_rtx (SImode);") 11539 11540(define_expand "popcountqi2" 11541 [; popcnt op0, op1 11542 (parallel [(set (match_operand:QI 0 "register_operand" "") 11543 (unspec:QI [(match_operand:QI 1 "register_operand")] 11544 UNSPEC_POPCNT)) 11545 (clobber (reg:CC CC_REGNUM))])] 11546 "TARGET_Z196" 11547 "") 11548 11549;; 11550;;- Copy sign instructions 11551;; 11552 11553(define_insn "copysign<mode>3" 11554 [(set (match_operand:FP 0 "register_operand" "=f") 11555 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>") 11556 (match_operand:FP 2 "register_operand" "f")] 11557 UNSPEC_COPYSIGN))] 11558 "TARGET_Z196" 11559 "cpsdr\t%0,%2,%1" 11560 [(set_attr "op_type" "RRF") 11561 (set_attr "type" "fsimp<mode>")]) 11562 11563 11564;; 11565;;- Transactional execution instructions 11566;; 11567 11568; This splitter helps combine to make use of CC directly when 11569; comparing the integer result of a tbegin builtin with a constant. 11570; The unspec is already removed by canonicalize_comparison. So this 11571; splitters only job is to turn the PARALLEL into separate insns 11572; again. Unfortunately this only works with the very first cc/int 11573; compare since combine is not able to deal with data flow across 11574; basic block boundaries. 11575 11576; It needs to be an insn pattern as well since combine does not apply 11577; the splitter directly. Combine would only use it if it actually 11578; would reduce the number of instructions. 11579(define_insn_and_split "*ccraw_to_int" 11580 [(set (pc) 11581 (if_then_else 11582 (match_operator 0 "s390_eqne_operator" 11583 [(reg:CCRAW CC_REGNUM) 11584 (match_operand 1 "const_int_operand" "")]) 11585 (label_ref (match_operand 2 "" "")) 11586 (pc))) 11587 (set (match_operand:SI 3 "register_operand" "=d") 11588 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] 11589 "" 11590 "#" 11591 "" 11592 [(set (match_dup 3) 11593 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT)) 11594 (set (pc) 11595 (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)]) 11596 (label_ref (match_dup 2)) 11597 (pc)))] 11598 "") 11599 11600; Non-constrained transaction begin 11601 11602(define_expand "tbegin" 11603 [(match_operand:SI 0 "register_operand" "") 11604 (match_operand:BLK 1 "memory_operand" "")] 11605 "TARGET_HTM" 11606{ 11607 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true); 11608 DONE; 11609}) 11610 11611(define_expand "tbegin_nofloat" 11612 [(match_operand:SI 0 "register_operand" "") 11613 (match_operand:BLK 1 "memory_operand" "")] 11614 "TARGET_HTM" 11615{ 11616 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false); 11617 DONE; 11618}) 11619 11620(define_expand "tbegin_retry" 11621 [(match_operand:SI 0 "register_operand" "") 11622 (match_operand:BLK 1 "memory_operand" "") 11623 (match_operand:SI 2 "general_operand" "")] 11624 "TARGET_HTM" 11625{ 11626 s390_expand_tbegin (operands[0], operands[1], operands[2], true); 11627 DONE; 11628}) 11629 11630(define_expand "tbegin_retry_nofloat" 11631 [(match_operand:SI 0 "register_operand" "") 11632 (match_operand:BLK 1 "memory_operand" "") 11633 (match_operand:SI 2 "general_operand" "")] 11634 "TARGET_HTM" 11635{ 11636 s390_expand_tbegin (operands[0], operands[1], operands[2], false); 11637 DONE; 11638}) 11639 11640; Clobber VRs since they don't get restored 11641(define_insn "tbegin_1_z13" 11642 [(set (reg:CCRAW CC_REGNUM) 11643 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] 11644 UNSPECV_TBEGIN)) 11645 (set (match_operand:BLK 1 "memory_operand" "=Q") 11646 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) 11647 (clobber (reg:TI 16)) (clobber (reg:TI 38)) 11648 (clobber (reg:TI 17)) (clobber (reg:TI 39)) 11649 (clobber (reg:TI 18)) (clobber (reg:TI 40)) 11650 (clobber (reg:TI 19)) (clobber (reg:TI 41)) 11651 (clobber (reg:TI 20)) (clobber (reg:TI 42)) 11652 (clobber (reg:TI 21)) (clobber (reg:TI 43)) 11653 (clobber (reg:TI 22)) (clobber (reg:TI 44)) 11654 (clobber (reg:TI 23)) (clobber (reg:TI 45)) 11655 (clobber (reg:TI 24)) (clobber (reg:TI 46)) 11656 (clobber (reg:TI 25)) (clobber (reg:TI 47)) 11657 (clobber (reg:TI 26)) (clobber (reg:TI 48)) 11658 (clobber (reg:TI 27)) (clobber (reg:TI 49)) 11659 (clobber (reg:TI 28)) (clobber (reg:TI 50)) 11660 (clobber (reg:TI 29)) (clobber (reg:TI 51)) 11661 (clobber (reg:TI 30)) (clobber (reg:TI 52)) 11662 (clobber (reg:TI 31)) (clobber (reg:TI 53))] 11663; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is 11664; not supposed to be used for immediates (see genpreds.c). 11665 "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" 11666 "tbegin\t%1,%x0" 11667 [(set_attr "op_type" "SIL")]) 11668 11669(define_insn "tbegin_1" 11670 [(set (reg:CCRAW CC_REGNUM) 11671 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] 11672 UNSPECV_TBEGIN)) 11673 (set (match_operand:BLK 1 "memory_operand" "=Q") 11674 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) 11675 (clobber (reg:DF 16)) 11676 (clobber (reg:DF 17)) 11677 (clobber (reg:DF 18)) 11678 (clobber (reg:DF 19)) 11679 (clobber (reg:DF 20)) 11680 (clobber (reg:DF 21)) 11681 (clobber (reg:DF 22)) 11682 (clobber (reg:DF 23)) 11683 (clobber (reg:DF 24)) 11684 (clobber (reg:DF 25)) 11685 (clobber (reg:DF 26)) 11686 (clobber (reg:DF 27)) 11687 (clobber (reg:DF 28)) 11688 (clobber (reg:DF 29)) 11689 (clobber (reg:DF 30)) 11690 (clobber (reg:DF 31))] 11691; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is 11692; not supposed to be used for immediates (see genpreds.c). 11693 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" 11694 "tbegin\t%1,%x0" 11695 [(set_attr "op_type" "SIL")]) 11696 11697; Same as above but without the FPR clobbers 11698(define_insn "tbegin_nofloat_1" 11699 [(set (reg:CCRAW CC_REGNUM) 11700 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] 11701 UNSPECV_TBEGIN)) 11702 (set (match_operand:BLK 1 "memory_operand" "=Q") 11703 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))] 11704 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" 11705 "tbegin\t%1,%x0" 11706 [(set_attr "op_type" "SIL")]) 11707 11708 11709; Constrained transaction begin 11710 11711(define_expand "tbeginc" 11712 [(set (reg:CCRAW CC_REGNUM) 11713 (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)] 11714 UNSPECV_TBEGINC))] 11715 "TARGET_HTM" 11716 "") 11717 11718(define_insn "*tbeginc_1" 11719 [(set (reg:CCRAW CC_REGNUM) 11720 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")] 11721 UNSPECV_TBEGINC))] 11722 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" 11723 "tbeginc\t0,%x0" 11724 [(set_attr "op_type" "SIL")]) 11725 11726; Transaction end 11727 11728(define_expand "tend" 11729 [(set (reg:CCRAW CC_REGNUM) 11730 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND)) 11731 (set (match_operand:SI 0 "register_operand" "") 11732 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] 11733 "TARGET_HTM" 11734 "") 11735 11736(define_insn "*tend_1" 11737 [(set (reg:CCRAW CC_REGNUM) 11738 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))] 11739 "TARGET_HTM" 11740 "tend" 11741 [(set_attr "op_type" "S")]) 11742 11743; Transaction abort 11744 11745(define_expand "tabort" 11746 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "")] 11747 UNSPECV_TABORT)] 11748 "TARGET_HTM && operands != NULL" 11749{ 11750 if (CONST_INT_P (operands[0]) 11751 && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255) 11752 { 11753 error ("invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC 11754 ". Values in range 0 through 255 are reserved.", 11755 INTVAL (operands[0])); 11756 FAIL; 11757 } 11758}) 11759 11760(define_insn "*tabort_1" 11761 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "aJ")] 11762 UNSPECV_TABORT)] 11763 "TARGET_HTM && operands != NULL" 11764 "tabort\t%Y0" 11765 [(set_attr "op_type" "S")]) 11766 11767(define_insn "*tabort_1_plus" 11768 [(unspec_volatile [(plus:SI (match_operand:SI 0 "register_operand" "a") 11769 (match_operand:SI 1 "const_int_operand" "J"))] 11770 UNSPECV_TABORT)] 11771 "TARGET_HTM && operands != NULL 11772 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")" 11773 "tabort\t%1(%0)" 11774 [(set_attr "op_type" "S")]) 11775 11776; Transaction extract nesting depth 11777 11778(define_insn "etnd" 11779 [(set (match_operand:SI 0 "register_operand" "=d") 11780 (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))] 11781 "TARGET_HTM" 11782 "etnd\t%0" 11783 [(set_attr "op_type" "RRE")]) 11784 11785; Non-transactional store 11786 11787(define_insn "ntstg" 11788 [(set (match_operand:DI 0 "memory_operand" "=T") 11789 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")] 11790 UNSPECV_NTSTG))] 11791 "TARGET_HTM" 11792 "ntstg\t%1,%0" 11793 [(set_attr "op_type" "RXY")]) 11794 11795; Transaction perform processor assist 11796 11797(define_expand "tx_assist" 11798 [(unspec_volatile [(match_operand:SI 0 "register_operand" "") 11799 (reg:SI GPR0_REGNUM) 11800 (const_int 1)] 11801 UNSPECV_PPA)] 11802 "TARGET_HTM" 11803 "") 11804 11805(define_insn "*ppa" 11806 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d") 11807 (match_operand:SI 1 "register_operand" "d") 11808 (match_operand 2 "const_int_operand" "I")] 11809 UNSPECV_PPA)] 11810 "TARGET_HTM && INTVAL (operands[2]) < 16" 11811 "ppa\t%0,%1,%2" 11812 [(set_attr "op_type" "RRF")]) 11813 11814 11815; Set and get floating point control register 11816 11817(define_insn "sfpc" 11818 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")] 11819 UNSPECV_SFPC)] 11820 "TARGET_HARD_FLOAT" 11821 "sfpc\t%0") 11822 11823(define_insn "efpc" 11824 [(set (match_operand:SI 0 "register_operand" "=d") 11825 (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))] 11826 "TARGET_HARD_FLOAT" 11827 "efpc\t%0") 11828 11829 11830; Load count to block boundary 11831 11832(define_insn "lcbb" 11833 [(set (match_operand:SI 0 "register_operand" "=d") 11834 (unspec:SI [(match_operand 1 "address_operand" "ZR") 11835 (match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB)) 11836 (clobber (reg:CC CC_REGNUM))] 11837 "TARGET_Z13" 11838 "lcbb\t%0,%a1,%b2" 11839 [(set_attr "op_type" "VRX")]) 11840 11841; Handle -fsplit-stack. 11842 11843(define_expand "split_stack_prologue" 11844 [(const_int 0)] 11845 "" 11846{ 11847 s390_expand_split_stack_prologue (); 11848 DONE; 11849}) 11850 11851;; If there are operand 0 bytes available on the stack, jump to 11852;; operand 1. 11853 11854(define_expand "split_stack_space_check" 11855 [(set (pc) (if_then_else 11856 (ltu (minus (reg 15) 11857 (match_operand 0 "register_operand")) 11858 (unspec [(const_int 0)] UNSPEC_STACK_CHECK)) 11859 (label_ref (match_operand 1)) 11860 (pc)))] 11861 "" 11862{ 11863 /* Offset from thread pointer to __private_ss. */ 11864 int psso = TARGET_64BIT ? 0x38 : 0x20; 11865 rtx tp = s390_get_thread_pointer (); 11866 rtx guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, tp, psso)); 11867 rtx reg = gen_reg_rtx (Pmode); 11868 rtx cc; 11869 if (TARGET_64BIT) 11870 emit_insn (gen_subdi3 (reg, stack_pointer_rtx, operands[0])); 11871 else 11872 emit_insn (gen_subsi3 (reg, stack_pointer_rtx, operands[0])); 11873 cc = s390_emit_compare (GT, reg, guard); 11874 s390_emit_jump (operands[1], cc); 11875 11876 DONE; 11877}) 11878 11879;; __morestack parameter block for split stack prologue. Parameters are: 11880;; parameter block label, label to be called by __morestack, frame size, 11881;; stack parameter size. 11882 11883(define_insn "split_stack_data" 11884 [(unspec_volatile [(match_operand 0 "" "X") 11885 (match_operand 1 "" "X") 11886 (match_operand 2 "const_int_operand" "X") 11887 (match_operand 3 "const_int_operand" "X")] 11888 UNSPECV_SPLIT_STACK_DATA)] 11889 "TARGET_CPU_ZARCH" 11890{ 11891 switch_to_section (targetm.asm_out.function_rodata_section 11892 (current_function_decl)); 11893 11894 if (TARGET_64BIT) 11895 output_asm_insn (".align\t8", operands); 11896 else 11897 output_asm_insn (".align\t4", operands); 11898 (*targetm.asm_out.internal_label) (asm_out_file, "L", 11899 CODE_LABEL_NUMBER (operands[0])); 11900 if (TARGET_64BIT) 11901 { 11902 output_asm_insn (".quad\t%2", operands); 11903 output_asm_insn (".quad\t%3", operands); 11904 output_asm_insn (".quad\t%1-%0", operands); 11905 } 11906 else 11907 { 11908 output_asm_insn (".long\t%2", operands); 11909 output_asm_insn (".long\t%3", operands); 11910 output_asm_insn (".long\t%1-%0", operands); 11911 } 11912 11913 switch_to_section (current_function_section ()); 11914 return ""; 11915} 11916 [(set_attr "length" "0")]) 11917 11918 11919;; A jg with minimal fuss for use in split stack prologue. 11920 11921(define_expand "split_stack_call" 11922 [(match_operand 0 "bras_sym_operand" "X") 11923 (match_operand 1 "" "")] 11924 "TARGET_CPU_ZARCH" 11925{ 11926 if (TARGET_64BIT) 11927 emit_jump_insn (gen_split_stack_call_di (operands[0], operands[1])); 11928 else 11929 emit_jump_insn (gen_split_stack_call_si (operands[0], operands[1])); 11930 DONE; 11931}) 11932 11933(define_insn "split_stack_call_<mode>" 11934 [(set (pc) (label_ref (match_operand 1 "" ""))) 11935 (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") 11936 (reg:P 1)] 11937 UNSPECV_SPLIT_STACK_CALL))] 11938 "TARGET_CPU_ZARCH" 11939 "jg\t%0" 11940 [(set_attr "op_type" "RIL") 11941 (set_attr "type" "branch")]) 11942 11943;; Also a conditional one. 11944 11945(define_expand "split_stack_cond_call" 11946 [(match_operand 0 "bras_sym_operand" "X") 11947 (match_operand 1 "" "") 11948 (match_operand 2 "" "")] 11949 "TARGET_CPU_ZARCH" 11950{ 11951 if (TARGET_64BIT) 11952 emit_jump_insn (gen_split_stack_cond_call_di (operands[0], operands[1], operands[2])); 11953 else 11954 emit_jump_insn (gen_split_stack_cond_call_si (operands[0], operands[1], operands[2])); 11955 DONE; 11956}) 11957 11958(define_insn "split_stack_cond_call_<mode>" 11959 [(set (pc) 11960 (if_then_else 11961 (match_operand 1 "" "") 11962 (label_ref (match_operand 2 "" "")) 11963 (pc))) 11964 (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") 11965 (reg:P 1)] 11966 UNSPECV_SPLIT_STACK_CALL))] 11967 "TARGET_CPU_ZARCH" 11968 "jg%C1\t%0" 11969 [(set_attr "op_type" "RIL") 11970 (set_attr "type" "branch")]) 11971 11972(define_insn "osc_break" 11973 [(unspec_volatile [(const_int 0)] UNSPECV_OSC_BREAK)] 11974 "" 11975 "bcr\t7,%%r0" 11976 [(set_attr "op_type" "RR")]) 11977