1#!/usr/bin/python
2#
3# Copyright (C) 2015 The Android Open Source Project
4#
5# Licensed under the Apache License, Version 2.0 (the "License");
6# you may not use this file except in compliance with the License.
7# You may obtain a copy of the License at
8#
9#      http://www.apache.org/licenses/LICENSE-2.0
10#
11# Unless required by applicable law or agreed to in writing, software
12# distributed under the License is distributed on an "AS IS" BASIS,
13# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14# See the License for the specific language governing permissions and
15# limitations under the License.
16#
17
18
19def gen_event_type_entry_str(event_type_name, event_type, event_config, description='',
20                             limited_arch=''):
21  """
22  return string as below:
23  EVENT_TYPE_TABLE_ENTRY(event_type_name, event_type, event_config, description, limited_arch)
24  """
25  return 'EVENT_TYPE_TABLE_ENTRY("%s", %s, %s, "%s", "%s")\n' % (
26            event_type_name, event_type, event_config, description, limited_arch)
27
28def gen_arm_event_type_entry_str(event_type_name, event_type, event_config, description):
29  return gen_event_type_entry_str(event_type_name, event_type, event_config, description,
30                                  "arm")
31
32
33def gen_hardware_events():
34  hardware_configs = ["cpu-cycles",
35                      "instructions",
36                      "cache-references",
37                      "cache-misses",
38                      "branch-instructions",
39                      "branch-misses",
40                      "bus-cycles",
41                      "stalled-cycles-frontend",
42                      "stalled-cycles-backend",
43                      ]
44  generated_str = ""
45  for config in hardware_configs:
46    event_type_name = config
47    event_config = "PERF_COUNT_HW_" + config.replace('-', '_').upper()
48
49    generated_str += gen_event_type_entry_str(
50        event_type_name, "PERF_TYPE_HARDWARE", event_config)
51
52  return generated_str
53
54
55def gen_software_events():
56  software_configs = ["cpu-clock",
57                      "task-clock",
58                      "page-faults",
59                      "context-switches",
60                      "cpu-migrations",
61                      ["minor-faults", "PERF_COUNT_SW_PAGE_FAULTS_MIN"],
62                      ["major-faults", "PERF_COUNT_SW_PAGE_FAULTS_MAJ"],
63                      "alignment-faults",
64                      "emulation-faults",
65                      ]
66  generated_str = ""
67  for config in software_configs:
68    if isinstance(config, list):
69      event_type_name = config[0]
70      event_config = config[1]
71    else:
72      event_type_name = config
73      event_config = "PERF_COUNT_SW_" + config.replace('-', '_').upper()
74
75    generated_str += gen_event_type_entry_str(
76        event_type_name, "PERF_TYPE_SOFTWARE", event_config)
77
78  return generated_str
79
80
81def gen_hw_cache_events():
82  hw_cache_types = [["L1-dcache", "PERF_COUNT_HW_CACHE_L1D"],
83                    ["L1-icache", "PERF_COUNT_HW_CACHE_L1I"],
84                    ["LLC", "PERF_COUNT_HW_CACHE_LL"],
85                    ["dTLB", "PERF_COUNT_HW_CACHE_DTLB"],
86                    ["iTLB", "PERF_COUNT_HW_CACHE_ITLB"],
87                    ["branch", "PERF_COUNT_HW_CACHE_BPU"],
88                    ["node", "PERF_COUNT_HW_CACHE_NODE"],
89                    ]
90  hw_cache_ops = [["loads", "load", "PERF_COUNT_HW_CACHE_OP_READ"],
91                  ["stores", "store", "PERF_COUNT_HW_CACHE_OP_WRITE"],
92                  ["prefetches", "prefetch",
93                   "PERF_COUNT_HW_CACHE_OP_PREFETCH"],
94                  ]
95  hw_cache_op_results = [["accesses", "PERF_COUNT_HW_CACHE_RESULT_ACCESS"],
96                         ["misses", "PERF_COUNT_HW_CACHE_RESULT_MISS"],
97                         ]
98  generated_str = ""
99  for (type_name, type_config) in hw_cache_types:
100    for (op_name_access, op_name_miss, op_config) in hw_cache_ops:
101      for (result_name, result_config) in hw_cache_op_results:
102        if result_name == "accesses":
103          event_type_name = type_name + '-' + op_name_access
104        else:
105          event_type_name = type_name + '-' + \
106              op_name_miss + '-' + result_name
107        event_config = "((%s) | (%s << 8) | (%s << 16))" % (
108            type_config, op_config, result_config)
109        generated_str += gen_event_type_entry_str(
110            event_type_name, "PERF_TYPE_HW_CACHE", event_config)
111
112  return generated_str
113
114def gen_user_space_events():
115  generated_str = gen_event_type_entry_str("inplace-sampler",
116                                           "SIMPLEPERF_TYPE_USER_SPACE_SAMPLERS",
117                                           "SIMPLEPERF_CONFIG_INPLACE_SAMPLER")
118  return generated_str
119
120def gen_arm_raw_events():
121  raw_types = [
122               # Refer to "Table D6-7 PMU common architectural and microarchitectural event numbers" in ARMv8 specification.
123               [0x0000, "sw-incr", "Instruction architecturally executed, Condition code check pass, software increment"],
124               [0x0001, "l1i-cache-refill", "Level 1 instruction cache refill"],
125               [0x0002, "l1i-tlb-refill", "Attributable Level 1 instruction TLB refill"],
126               [0x0003, "l1d-cache-refill", "Level 1 data cache refill"],
127               [0x0004, "l1d-cache", "Level 1 data cache access"],
128               [0x0005, "l1d-tlb-refill", "Attributable Level 1 data TLB refill"],
129               [0x0006, "ld-retired", "Instruction architecturally executed, Condition code check pass, load"],
130               [0x0007, "st-retired", "Instruction architecturally executed, Condition code check pass, store"],
131               [0x0008, "inst-retired", "Instruction architecturally executed"],
132               [0x0009, "exc-taken", "Exception taken"],
133               [0x000A, "exc-return", "Instruction architecturally executed, Condition code check pass, exception return"],
134               [0x000B, "cid-write-retired", "Instruction architecturally executed, Condition code check pass, write to CONTEXTIDR"],
135               [0x000C, "pc-write-retired", "Instruction architecturally executed, Condition code check pass, software change of the PC"],
136               [0x000D, "br-immed-retired", "Instruction architecturally executed, immediate branch"],
137               [0x000E, "br-return-retired", "Instruction architecturally executed, Condition code check pass, procedure return"],
138               [0x000F, "unaligned-ldst-retired", "Instruction architecturally executed, Condition code check pass, unaligned load or store"],
139               [0x0010, "br-mis-pred", "Mispredicted or not predicted branch Speculatively executed"],
140               [0x0011, "cpu-cycles", "Cycle"],
141               [0x0012, "br-pred", "Predictable branch Speculatively executed"],
142               [0x0013, "mem-access", "Data memory access"],
143               [0x0014, "l1i-cache", "Attributable Level 1 instruction cache access"],
144               [0x0015, "l1d-cache-wb", "Attributable Level 1 data cache write-back"],
145               [0x0016, "l2d-cache", "Level 2 data cache access"],
146               [0x0017, "l2d-cache-refill", "Level 2 data cache refill"],
147               [0x0018, "l2d-cache-wb", "Attributable Level 2 data cache write-back"],
148               [0x0019, "bus-access", "Bus access"],
149               [0x001A, "memory-error", "Local memory error"],
150               [0x001B, "inst-spec", "Operation Speculatively executed"],
151               [0x001C, "ttbr-write-retired", "Instruction architecturally executed, Condition code check pass, write to TTBR"],
152               [0x001D, "bus-cycles", "Bus cycle"],
153               [0x001E, "chain", "For odd-numbered counters, increments the count by one for each overflow of the preceding even-numbered counter. For even-numbered counters, there is no increment."],
154               [0x001F, "l1d-cache-allocate", "Attributable Level 1 data cache allocation without refill"],
155               [0x0020, "l2d-cache-allocate", "Attributable Level 2 data cache allocation without refill"],
156               [0x0021, "br-retired", "Instruction architecturally executed, branch"],
157               [0x0022, "br-mis-pred-retired", "Instruction architecturally executed, mispredicted branch"],
158               [0x0023, "stall-frontend", "No operation issued due to the frontend"],
159               [0x0024, "stall-backend", "No operation issued due to backend"],
160               [0x0025, "l1d-tlb", "Attributable Level 1 data or unified TLB access"],
161               [0x0026, "l1i-tlb", "Attributable Level 1 instruction TLB access"],
162               [0x0027, "l2i-cache", "Attributable Level 2 instruction cache access"],
163               [0x0028, "l2i-cache-refill", "Attributable Level 2 instruction cache refill"],
164               [0x0029, "l3d-cache-allocate", "Attributable Level 3 data or unified cache allocation without refill"],
165               [0x002A, "l3d-cache-refill", "Attributable Level 3 data cache refill"],
166               [0x002B, "l3d-cache", "Attributable Level 3 data cache access"],
167               [0x002C, "l3d-cache-wb", "Attributable Level 3 data or unified cache write-back"],
168               [0x002D, "l2d-tlb-refill", "Attributable Level 2 data or unified TLB refill"],
169               [0x002E, "l2i-tlb-refill", "Attributable Level 2 instruction TLB refill"],
170               [0x002F, "l2d-tlb", "Attributable Level 2 data or unified TLB access"],
171               [0x0030, "l2i-tlb", "Attributable Level 2 instruction TLB access"],
172               [0x0031, "remote-access", "Attributable access to another socket in a multi-socket system"],
173               [0x0032, "ll-cache", "Attributable Last Level data cache access"],
174               [0x0033, "ll-cache-miss", "Attributable Last level data or unified cache miss"],
175               [0x0034, "dtlb-walk", "Attributable data or unified TLB access with at least one translation table walk"],
176               [0x0035, "itlb-walk", "Attributable instruction TLB access with at least one translation table walk"],
177               [0x0036, "ll-cache-rd", "Attributable Last Level cache memory read"],
178               [0x0037, "ll-cache-miss-rd", "Attributable Last Level cache memory read miss"],
179               [0x0038, "remote-access-rd", "Attributable memory read access to another socket in a multi-socket system"],
180               [0x0039, "l1d-cache-lmiss-rd", "Level 1 data cache long-latency read miss"],
181               [0x003A, "op-retired", "Micro-operation architecturally executed"],
182               [0x003B, "op-spec", "Micro-operation Speculatively executed"],
183               [0x003C, "stall", "No operation sent for execution"],
184               [0x003D, "stall-slot-backend", "No operation sent for execution on a Slot due to the backend"],
185               [0x003E, "stall-slot-frontend", "No operation send for execution on a Slot due to the frontend"],
186               [0x003F, "stall-slot", "No operation sent for execution on a Slot"],
187               [0x0040, "l1d-cache-rd", "Level 1 data cache read"],
188               [0x4000, "sample-pop", "Sample Population"],
189               [0x4001, "sample-feed", "Sample Taken"],
190               [0x4002, "sample-filtrate", "Sample Taken and not removed by filtering"],
191               [0x4003, "sample-collision", "Sample collided with previous sample"],
192               [0x4004, "cnt-cycles", "Constant frequency cycles"],
193               [0x4005, "stall-backend-mem", "Memory stall cycles"],
194               [0x4006, "l1i-cache-lmiss", "Level 1 instruction cache long-latency miss"],
195               [0x4009, "l2d-cache-lmiss-rd", "Level 2 data cache long-latency read miss"],
196               [0x400A, "l2i-cache-lmiss", "Level 2 instruction cache long-latency miss"],
197               [0x400B, "l3d-cache-lmiss-rd", "Level 3 data cache long-latency read miss"],
198               [0x8002, "sve-inst-retired", "SVE Instructions architecturally executed"],
199               [0x8006, "sve-inst-spec", "SVE Instructions speculatively executed"],
200
201               # Refer to "Table K3.1 ARM recommendations for IMPLEMENTATION DEFINED event numbers" in ARMv8 specification.
202               #[0x0040, "l1d-cache-rd", "Attributable Level 1 data cache access, read"],
203               [0x0041, "l1d-cache-wr", "Attributable Level 1 data cache access, write"],
204               [0x0042, "l1d-cache-refill-rd", "Attributable Level 1 data cache refill, read"],
205               [0x0043, "l1d-cache-refill-wr", "Attributable Level 1 data cache refill, write"],
206               [0x0044, "l1d-cache-refill-inner", "Attributable Level 1 data cache refill, inner"],
207               [0x0045, "l1d-cache-refill-outer", "Attributable Level 1 data cache refill, outer"],
208               [0x0046, "l1d-cache-wb-victim", "Attributable Level 1 data cache Write-Back, victim"],
209               [0x0047, "l1d-cache-wb-clean", "Level 1 data cache Write-Back, cleaning and coherency"],
210               [0x0048, "l1d-cache-inval", "Attributable Level 1 data cache invalidate"],
211               # 0x0049-0x004B - Reserved
212               [0x004C, "l1d-tlb-refill-rd", "Attributable Level 1 data TLB refill, read"],
213               [0x004D, "l1d-tlb-refill-wr", "Attributable Level 1 data TLB refill, write"],
214               [0x004E, "l1d-tlb-rd", "Attributable Level 1 data or unified TLB access, read"],
215               [0x004F, "l1d-tlb-wr", "Attributable Level 1 data or unified TLB access, write"],
216               [0x0050, "l2d-cache-rd", "Attributable Level 2 data cache access, read"],
217               [0x0051, "l2d-cache-wr", "Attributable Level 2 data cache access, write"],
218               [0x0052, "l2d-cache-refill-rd", "Attributable Level 2 data cache refill, read"],
219               [0x0053, "l2d-cache-refill-wr", "Attributable Level 2 data cache refill, write"],
220               # 0x0054-0x0055 - Reserved
221               [0x0056, "l2d-cache-wb-victim", "Attributable Level 2 data cache Write-Back, victim"],
222               [0x0057, "l2d-cache-wb-clean", "Level 2 data cache Write-Back, cleaning and coherency"],
223               [0x0058, "l2d-cache-inval", "Attributable Level 2 data cache invalidate"],
224               # 0x0059-0x005B - Reserved
225               [0x005C, "l2d-tlb-refill-rd", "Attributable Level 2 data or unified TLB refill, read"],
226               [0x005D, "l2d-tlb-refill-wr", "Attributable Level 2 data or unified TLB refill, write"],
227               [0x005E, "l2d-tlb-rd", "Attributable Level 2 data or unified TLB access, read"],
228               [0x005F, "l2d-tlb-wr", "Attributable Level 2 data or unified TLB access, write"],
229               [0x0060, "bus-access-rd", "Bus access, read"],
230               [0x0061, "bus-access-wr", "Bus access, write"],
231               [0x0062, "bus-access-shared", "Bus access, Normal, Cacheable, Shareable"],
232               [0x0063, "bus-access-not-shared", "Bus access, not Normal, Cacheable, Shareable"],
233               [0x0064, "bus-access-normal", "Bus access, normal"],
234               [0x0065, "bus-access-periph", "Bus access, peripheral"],
235               [0x0066, "mem-access-rd", "Data memory access, read"],
236               [0x0067, "mem-access-wr", "Data memory access, write"],
237               [0x0068, "unaligned-ld-spec", "Unaligned access, read"],
238               [0x0069, "unaligned-st-spec", "Unaligned access, write"],
239               [0x006A, "unaligned-ldst-spec", "Unaligned access"],
240               # 0x006B - Reserved
241               [0x006C, "ldrex-spec", "Exclusive operation speculatively executed, LDREX or LDX"],
242               [0x006D, "strex-pass-spec", "Exclusive operation speculatively executed, STREX or STX pass"],
243               [0x006E, "strex-fail-spec", "Exclusive operation speculatively executed, STREX or STX fail"],
244               [0x006F, "strex-spec", "Exclusive operation speculatively executed, STREX or STX"],
245               [0x0070, "ld-spec", "Operation speculatively executed, load"],
246               [0x0071, "st-spec", "Operation speculatively executed, store"],
247               [0x0072, "ldst-spec", "Operation speculatively executed, load or store"],
248               [0x0073, "dp-spec", "Operation speculatively executed, integer data processing"],
249               [0x0074, "ase-spec", "Operation speculatively executed, Advanced SIMD instruction"],
250               [0x0075, "vfp-spec", "Operation speculatively executed, floating-point instruction"],
251               [0x0076, "pc-write-spec", "Operation speculatively executed, software change of the PC"],
252               [0x0077, "crypto-spec", "Operation speculatively executed, Cryptographic instruction"],
253               [0x0078, "br-immed-spec", "Branch speculatively executed, immediate branch"],
254               [0x0079, "br-return-spec", "Branch speculatively executed, procedure return"],
255               [0x007A, "br-indirect-spec", "Branch speculatively executed, indirect branch"],
256               # 0x007B - Reserved
257               [0x007C, "isb-spec", "Barrier speculatively executed, ISB"],
258               [0x007D, "dsb-spec", "Barrier speculatively executed, DSB"],
259               [0x007E, "dmb-spec", "Barrier speculatively executed, DMB"],
260               # 0x007F-0x0080 - Reserved
261               [0x0081, "exc-undef", "Exception taken, Other synchronous"],
262               [0x0082, "exc-svc", "Exception taken, Supervisor Call"],
263               [0x0083, "exc-pabort", "Exception taken, Instruction Abort"],
264               [0x0084, "exc-dabort", "Exception taken, Data Abort and SError"],
265               # 0x0085 - Reserved
266               [0x0086, "exc-irq", "Exception taken, IRQ"],
267               [0x0087, "exc-fiq", "Exception taken, FIQ"],
268               [0x0088, "exc-smc", "Exception taken, Secure Monitor Call"],
269               # 0x0089 - Reserved
270               [0x008A, "exc-hvc", "Exception taken, Hypervisor Call"],
271               [0x008B, "exc-trap-pabort", "Exception taken, Instruction Abort not Taken locallyb"],
272               [0x008C, "exc-trap-dabort", "Exception taken, Data Abort or SError not Taken locallyb"],
273               [0x008D, "exc-trap-other", "Exception taken, Other traps not Taken locallyb"],
274               [0x008E, "exc-trap-irq", "Exception taken, IRQ not Taken locallyb"],
275               [0x008F, "exc-trap-fiq", "Exception taken, FIQ not Taken locallyb"],
276               [0x0090, "rc-ld-spec", "Release consistency operation speculatively executed, Load-Acquire"],
277               [0x0091, "rc-st-spec", "Release consistency operation speculatively executed, Store-Release"],
278               # 0x0092-0x009F - Reserved
279               [0x00A0, "l3d-cache-rd", "Attributable Level 3 data or unified cache access, read"],
280               [0x00A1, "l3d-cache-wr", "Attributable Level 3 data or unified cache access, write"],
281               [0x00A2, "l3d-cache-refill-rd", "Attributable Level 3 data or unified cache refill, read"],
282               [0x00A3, "l3d-cache-refill-wr", "Attributable Level 3 data or unified cache refill, write"],
283               # 0x00A4-0x00A5 - Reserved
284               [0x00A6, "l3d-cache-wb-victim", "Attributable Level 3 data or unified cache Write-Back, victim"],
285               [0x00A7, "l3d-cache-wb-clean", "Attributable Level 3 data or unified cache Write-Back, cache clean"],
286               [0x00A8, "l3d-cache-inval", "Attributable Level 3 data or unified cache access, invalidate"],
287               ]
288  generated_str = ""
289  for item in raw_types:
290    event_type = 'PERF_TYPE_RAW'
291    event_type_name = "raw-" + item[1]
292    event_config = '0x%x' % item[0]
293    description = item[2]
294    generated_str += gen_arm_event_type_entry_str(event_type_name, event_type, event_config,
295                                              description)
296  return generated_str
297
298
299def gen_events():
300  generated_str = "// This file is auto-generated by generate-event_table.py.\n\n"
301  generated_str += gen_hardware_events() + '\n'
302  generated_str += gen_software_events() + '\n'
303  generated_str += gen_hw_cache_events() + '\n'
304  generated_str += gen_user_space_events() + '\n'
305  generated_str += gen_arm_raw_events() + '\n'
306  return generated_str
307
308generated_str = gen_events()
309fh = open('event_type_table.h', 'w')
310fh.write(generated_str)
311fh.close()
312