1 /* Definitions for opcode table for the sparc. 2 Copyright (C) 1989-2021 Free Software Foundation, Inc. 3 4 This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and 5 the GNU Binutils. 6 7 GAS/GDB is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GAS/GDB is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GAS or GDB; see the file COPYING3. If not, write to 19 the Free Software Foundation, 51 Franklin Street - Fifth Floor, 20 Boston, MA 02110-1301, USA. */ 21 22 #include "ansidecl.h" 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* The SPARC opcode table (and other related data) is defined in 29 the opcodes library in sparc-opc.c. If you change anything here, make 30 sure you fix up that file, and vice versa. */ 31 32 /* FIXME-someday: perhaps the ,a's and such should be embedded in the 33 instruction's name rather than the args. This would make gas faster, pinsn 34 slower, but would mess up some macros a bit. xoxorich. */ 35 36 /* List of instruction sets variations. 37 These values are such that each element is either a superset of a 38 preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P 39 returns non-zero. 40 The values are indices into `sparc_opcode_archs' defined in sparc-opc.c. 41 Don't change this without updating sparc-opc.c. */ 42 43 enum sparc_opcode_arch_val 44 { 45 SPARC_OPCODE_ARCH_V6 = 0, 46 SPARC_OPCODE_ARCH_V7, 47 SPARC_OPCODE_ARCH_V8, 48 SPARC_OPCODE_ARCH_LEON, 49 SPARC_OPCODE_ARCH_SPARCLET, 50 SPARC_OPCODE_ARCH_SPARCLITE, 51 /* V9 variants must appear last. */ 52 SPARC_OPCODE_ARCH_V9, 53 SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions. */ 54 SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions. */ 55 SPARC_OPCODE_ARCH_V9C, /* V9 with UA2005 and T1 additions. */ 56 SPARC_OPCODE_ARCH_V9D, /* V9 with UA2007 and T3 additions. */ 57 SPARC_OPCODE_ARCH_V9E, /* V9 with OSA2011 and T4 additions modulus integer multiply-add. */ 58 SPARC_OPCODE_ARCH_V9V, /* V9 with OSA2011 and T4 additions, integer 59 multiply and Fujitsu fp multiply-add. */ 60 SPARC_OPCODE_ARCH_V9M, /* V9 with OSA2015 and M7 additions. */ 61 SPARC_OPCODE_ARCH_M8, /* V9 with OSA2017 and M8 additions. */ 62 SPARC_OPCODE_ARCH_MAX = SPARC_OPCODE_ARCH_M8, 63 SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */ 64 }; 65 66 67 /* Given an enum sparc_opcode_arch_val, return the bitmask to use in 68 insn encoding/decoding. */ 69 #define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch)) 70 71 /* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */ 72 #define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9) 73 74 /* Table of cpu variants. */ 75 76 typedef struct sparc_opcode_arch 77 { 78 const char *name; 79 /* Mask of sparc_opcode_arch_val's supported. 80 EG: For v7 this would be 81 (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)). 82 These are short's because sparc_opcode.architecture is. */ 83 short supported; 84 /* Bitmaps describing the set of hardware capabilities implemented 85 by the opcode arch. */ 86 int hwcaps; 87 int hwcaps2; 88 } sparc_opcode_arch; 89 90 extern const struct sparc_opcode_arch sparc_opcode_archs[]; 91 92 /* Given architecture name, look up it's sparc_opcode_arch_val value. */ 93 extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch (const char *); 94 95 /* Return the bitmask of supported architectures for ARCH. */ 96 #define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported) 97 98 /* Non-zero if ARCH1 conflicts with ARCH2. 99 IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */ 100 #define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \ 101 (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ 102 != SPARC_OPCODE_SUPPORTED (ARCH1)) \ 103 && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ 104 != SPARC_OPCODE_SUPPORTED (ARCH2))) 105 106 /* Structure of an opcode table entry. */ 107 108 typedef struct sparc_opcode 109 { 110 const char *name; 111 unsigned long match; /* Bits that must be set. */ 112 unsigned long lose; /* Bits that must not be set. */ 113 const char *args; 114 /* This was called "delayed" in versions before the flags. */ 115 unsigned int flags; 116 unsigned int hwcaps; 117 unsigned int hwcaps2; 118 short architecture; /* Bitmask of sparc_opcode_arch_val's. */ 119 } sparc_opcode; 120 121 /* Struct for ASIs - to handle ASIs introduced in a specific architecture */ 122 typedef struct 123 { 124 int value; 125 const char *name; 126 short architecture; 127 } sparc_asi; 128 129 /* FIXME: Add F_ANACHRONISTIC flag for v9. */ 130 #define F_DELAYED 0x00000001 /* Delayed branch. */ 131 #define F_ALIAS 0x00000002 /* Alias for a "real" instruction. */ 132 #define F_UNBR 0x00000004 /* Unconditional branch. */ 133 #define F_CONDBR 0x00000008 /* Conditional branch. */ 134 #define F_JSR 0x00000010 /* Subroutine call. */ 135 #define F_FLOAT 0x00000020 /* Floating point instruction (not a branch). */ 136 #define F_FBR 0x00000040 /* Floating point branch. */ 137 #define F_PREFERRED 0x00000080 /* A preferred alias. */ 138 139 #define F_PREF_ALIAS (F_ALIAS|F_PREFERRED) 140 141 /* These must match the ELF_SPARC_HWCAP_* and ELF_SPARC_HWCAP2_* 142 values precisely. See include/elf/sparc.h. */ 143 #define HWCAP_MUL32 0x00000001 /* umul/umulcc/smul/smulcc insns */ 144 #define HWCAP_DIV32 0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */ 145 #define HWCAP_FSMULD 0x00000004 /* 'fsmuld' insn */ 146 #define HWCAP_V8PLUS 0x00000008 /* v9 insns available to 32bit */ 147 #define HWCAP_POPC 0x00000010 /* 'popc' insn */ 148 #define HWCAP_VIS 0x00000020 /* VIS insns */ 149 #define HWCAP_VIS2 0x00000040 /* VIS2 insns */ 150 #define HWCAP_ASI_BLK_INIT \ 151 0x00000080 /* block init ASIs */ 152 #define HWCAP_FMAF 0x00000100 /* fused multiply-add */ 153 #define HWCAP_VIS3 0x00000400 /* VIS3 insns */ 154 #define HWCAP_HPC 0x00000800 /* HPC insns */ 155 #define HWCAP_RANDOM 0x00001000 /* 'random' insn */ 156 #define HWCAP_TRANS 0x00002000 /* transaction insns */ 157 #define HWCAP_FJFMAU 0x00004000 /* unfused multiply-add */ 158 #define HWCAP_IMA 0x00008000 /* integer multiply-add */ 159 #define HWCAP_ASI_CACHE_SPARING \ 160 0x00010000 /* cache sparing ASIs */ 161 #define HWCAP_AES 0x00020000 /* AES crypto insns */ 162 #define HWCAP_DES 0x00040000 /* DES crypto insns */ 163 #define HWCAP_KASUMI 0x00080000 /* KASUMI crypto insns */ 164 #define HWCAP_CAMELLIA 0x00100000 /* CAMELLIA crypto insns */ 165 #define HWCAP_MD5 0x00200000 /* MD5 hashing insns */ 166 #define HWCAP_SHA1 0x00400000 /* SHA1 hashing insns */ 167 #define HWCAP_SHA256 0x00800000 /* SHA256 hashing insns */ 168 #define HWCAP_SHA512 0x01000000 /* SHA512 hashing insns */ 169 #define HWCAP_MPMUL 0x02000000 /* Multiple Precision Multiply */ 170 #define HWCAP_MONT 0x04000000 /* Montgomery Mult/Sqrt */ 171 #define HWCAP_PAUSE 0x08000000 /* Pause insn */ 172 #define HWCAP_CBCOND 0x10000000 /* Compare and Branch insns */ 173 #define HWCAP_CRC32C 0x20000000 /* CRC32C insn */ 174 175 #define HWCAP2_FJATHPLUS 0x00000001 /* Fujitsu Athena+ */ 176 #define HWCAP2_VIS3B 0x00000002 /* Subset of VIS3 present on sparc64 X+. */ 177 #define HWCAP2_ADP 0x00000004 /* Application Data Protection */ 178 #define HWCAP2_SPARC5 0x00000008 /* The 29 new fp and sub instructions */ 179 #define HWCAP2_MWAIT 0x00000010 /* mwait instruction and load/monitor ASIs */ 180 #define HWCAP2_XMPMUL 0x00000020 /* XOR multiple precision multiply */ 181 #define HWCAP2_XMONT 0x00000040 /* XOR Montgomery mult/sqr instructions */ 182 #define HWCAP2_NSEC \ 183 0x00000080 /* pause insn with support for nsec timings */ 184 #define HWCAP2_FJATHHPC 0x00001000 /* Fujitsu HPC instrs */ 185 #define HWCAP2_FJDES 0x00002000 /* Fujitsu DES instrs */ 186 #define HWCAP2_FJAES 0x00010000 /* Fujitsu AES instrs */ 187 188 #define HWCAP2_SPARC6 0x00020000 /* OSA2017 new instructions */ 189 #define HWCAP2_ONADDSUB 0x00040000 /* Oracle Number add/subtract */ 190 #define HWCAP2_ONMUL 0x00080000 /* Oracle Number multiply */ 191 #define HWCAP2_ONDIV 0x00100000 /* Oracle Number divide */ 192 #define HWCAP2_DICTUNP 0x00200000 /* Dictionary unpack instruction */ 193 #define HWCAP2_FPCMPSHL 0x00400000 /* Partition compare with shifted result */ 194 #define HWCAP2_RLE 0x00800000 /* Run-length encoded burst and length */ 195 #define HWCAP2_SHA3 0x01000000 /* SHA3 instruction */ 196 197 198 /* All sparc opcodes are 32 bits, except for the `set' instruction (really a 199 macro), which is 64 bits. It is handled as a special case. 200 201 The match component is a mask saying which bits must match a particular 202 opcode in order for an instruction to be an instance of that opcode. 203 204 The args component is a string containing one character for each operand of the 205 instruction. 206 207 Kinds of operands: 208 # Number used by optimizer. It is ignored. 209 1 rs1 register. 210 2 rs2 register. 211 d rd register. 212 e frs1 floating point register. 213 v frs1 floating point register (double/even). 214 V frs1 floating point register (quad/multiple of 4). 215 ; frs1 floating piont register (multiple of 8). 216 f frs2 floating point register. 217 B frs2 floating point register (double/even). 218 R frs2 floating point register (quad/multiple of 4). 219 : frs2 floating point register (multiple of 8). 220 ' rs2m floating point register (double/even) in FPCMPSHL. (m8) 221 4 frs3 floating point register. 222 5 frs3 floating point register (doube/even). 223 g frsd floating point register. 224 H frsd floating point register (double/even). 225 J frsd floating point register (quad/multiple of 4). 226 } frsd floating point register (double/even) that is == frs2 227 ^ frsd floating piont register in ON instructions. 228 b crs1 coprocessor register 229 c crs2 coprocessor register 230 D crsd coprocessor register 231 m alternate space register (asr) in rd 232 M alternate space register (asr) in rs1 233 h 22 high bits. 234 X 5 bit unsigned immediate 235 Y 6 bit unsigned immediate 236 3 SIAM mode (3 bits). (v9b) 237 K MEMBAR mask (7 bits). (v9) 238 j 10 bit Immediate. (v9) 239 I 11 bit Immediate. (v9) 240 i 13 bit Immediate. 241 n 22 bit immediate. 242 k 2+14 bit PC relative immediate. (v9) 243 G 19 bit PC relative immediate. (v9) 244 l 22 bit PC relative immediate. 245 L 30 bit PC relative immediate. 246 a Annul. The annul bit is set. 247 A Alternate address space. Stored as 8 bits. 248 C Coprocessor state register. 249 F floating point state register. 250 p Processor state register. 251 N Branch predict clear ",pn" (v9) 252 T Branch predict set ",pt" (v9) 253 z %icc. (v9) 254 Z %xcc. (v9) 255 q Floating point queue. 256 r Single register that is both rs1 and rd. 257 O Single register that is both rs2 and rd. 258 Q Coprocessor queue. 259 S Special case. 260 t Trap base register. 261 w Window invalid mask register. 262 y Y register. 263 u sparclet coprocessor registers in rd position 264 U sparclet coprocessor registers in rs1 position 265 E %ccr. (v9) 266 s %fprs. (v9) 267 P %pc. (v9) 268 W %tick. (v9) 269 { %mcdper. (v9b) 270 & %entropy. (m8) 271 o %asi. (v9) 272 6 %fcc0. (v9) 273 7 %fcc1. (v9) 274 8 %fcc2. (v9) 275 9 %fcc3. (v9) 276 ! Privileged Register in rd (v9) 277 ? Privileged Register in rs1 (v9) 278 % Hyperprivileged Register in rd (v9b) 279 $ Hyperprivileged Register in rs1 (v9b) 280 * Prefetch function constant. (v9) 281 x OPF field (v9 impdep). 282 0 32/64 bit immediate for set or setx (v9) insns 283 _ Ancillary state register in rd (v9a) 284 / Ancillary state register in rs1 (v9a) 285 ( entire floating point state register (%efsr) 286 ) 5 bit immediate placed in RS3 field 287 = 2+8 bit PC relative immediate. (v9) 288 | FPCMPSHL 2 bit immediate. (m8) */ 289 290 #define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */ 291 #define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */ 292 #define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */ 293 #define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */ 294 #define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */ 295 #define OPF_LOW4(x) OPF ((x) & 0xf) /* V9. */ 296 #define OPM(x) (((x) & 0x7) << 10) /* opm field of misaligned load/store insns. */ 297 #define OPMI(x) (((x) & 0x1) << 9) /* opm i field of misaligned load/store insns. */ 298 #define ONFCN(x) (((x) & 0x3) << 26) /* fcn field of Oracle Number insns. */ 299 #define REVFCN(x) (((x) & 0x3) << 0) /* fcn field of REV* insns. */ 300 #define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */ 301 #define F3F4(x, y, z) (OP (x) | OP3 (y) | OPF_LOW4 (z)) 302 #define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */ 303 #define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */ 304 #define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */ 305 #define F1(x) (OP (x)) 306 #define DISP30(x) ((x) & 0x3fffffff) 307 #define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */ 308 #define RS2(x) ((x) & 0x1f) /* Rs2 field. */ 309 #define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */ 310 #define SIMM10(x) ((x) & 0x3ff) /* Simm10 field. */ 311 #define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */ 312 #define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */ 313 #define RS3(x) (((x) & 0x1f) << 9) /* Rs3 field. */ 314 #define ASI_RS2(x) (SIMM13 (x)) 315 #define MEMBAR(x) ((x) & 0x7f) 316 #define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */ 317 318 #define ANNUL (1 << 29) 319 #define BPRED (1 << 19) /* V9. */ 320 #define IMMED F3I (1) 321 #define RD_G0 RD (~0) 322 #define RS1_G0 RS1 (~0) 323 #define RS2_G0 RS2 (~0) 324 325 extern const struct sparc_opcode sparc_opcodes[]; 326 extern const int sparc_num_opcodes; 327 328 extern const sparc_asi *sparc_encode_asi (const char *); 329 extern const char *sparc_decode_asi (int); 330 extern int sparc_encode_membar (const char *); 331 extern const char *sparc_decode_membar (int); 332 extern int sparc_encode_prefetch (const char *); 333 extern const char *sparc_decode_prefetch (int); 334 extern int sparc_encode_sparclet_cpreg (const char *); 335 extern const char *sparc_decode_sparclet_cpreg (int); 336 337 /* Local Variables: 338 fill-column: 131 339 comment-column: 0 340 End: */ 341 342 #ifdef __cplusplus 343 } 344 #endif 345