1 /* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
2 /* CPU data for bpf.
3
4 THIS FILE IS MACHINE GENERATED WITH CGEN.
5
6 Copyright (C) 1996-2021 Free Software Foundation, Inc.
7
8 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
9
10 This file is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 It is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
19
20 You should have received a copy of the GNU General Public License along
21 with this program; if not, write to the Free Software Foundation, Inc.,
22 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
23
24 */
25
26 #include "sysdep.h"
27 #include <stdio.h>
28 #include <stdarg.h>
29 #include "ansidecl.h"
30 #include "bfd.h"
31 #include "symcat.h"
32 #include "bpf-desc.h"
33 #include "bpf-opc.h"
34 #include "opintl.h"
35 #include "libiberty.h"
36 #include "xregex.h"
37
38 /* Attributes. */
39
40 static const CGEN_ATTR_ENTRY bool_attr[] =
41 {
42 { "#f", 0 },
43 { "#t", 1 },
44 { 0, 0 }
45 };
46
47 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
48 {
49 { "base", MACH_BASE },
50 { "bpf", MACH_BPF },
51 { "xbpf", MACH_XBPF },
52 { "max", MACH_MAX },
53 { 0, 0 }
54 };
55
56 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
57 {
58 { "ebpfle", ISA_EBPFLE },
59 { "ebpfbe", ISA_EBPFBE },
60 { "xbpfle", ISA_XBPFLE },
61 { "xbpfbe", ISA_XBPFBE },
62 { "max", ISA_MAX },
63 { 0, 0 }
64 };
65
66 const CGEN_ATTR_TABLE bpf_cgen_ifield_attr_table[] =
67 {
68 { "MACH", & MACH_attr[0], & MACH_attr[0] },
69 { "ISA", & ISA_attr[0], & ISA_attr[0] },
70 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
71 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
72 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
73 { "RESERVED", &bool_attr[0], &bool_attr[0] },
74 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
75 { "SIGNED", &bool_attr[0], &bool_attr[0] },
76 { 0, 0, 0 }
77 };
78
79 const CGEN_ATTR_TABLE bpf_cgen_hardware_attr_table[] =
80 {
81 { "MACH", & MACH_attr[0], & MACH_attr[0] },
82 { "ISA", & ISA_attr[0], & ISA_attr[0] },
83 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
84 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
85 { "PC", &bool_attr[0], &bool_attr[0] },
86 { "PROFILE", &bool_attr[0], &bool_attr[0] },
87 { 0, 0, 0 }
88 };
89
90 const CGEN_ATTR_TABLE bpf_cgen_operand_attr_table[] =
91 {
92 { "MACH", & MACH_attr[0], & MACH_attr[0] },
93 { "ISA", & ISA_attr[0], & ISA_attr[0] },
94 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
95 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
96 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
97 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
98 { "SIGNED", &bool_attr[0], &bool_attr[0] },
99 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
100 { "RELAX", &bool_attr[0], &bool_attr[0] },
101 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
102 { 0, 0, 0 }
103 };
104
105 const CGEN_ATTR_TABLE bpf_cgen_insn_attr_table[] =
106 {
107 { "MACH", & MACH_attr[0], & MACH_attr[0] },
108 { "ISA", & ISA_attr[0], & ISA_attr[0] },
109 { "ALIAS", &bool_attr[0], &bool_attr[0] },
110 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
111 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
112 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
113 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
114 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
115 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
116 { "RELAXED", &bool_attr[0], &bool_attr[0] },
117 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
118 { "PBB", &bool_attr[0], &bool_attr[0] },
119 { 0, 0, 0 }
120 };
121
122 /* Instruction set variants. */
123
124 static const CGEN_ISA bpf_cgen_isa_table[] = {
125 { "ebpfle", 64, 64, 64, 128 },
126 { "ebpfbe", 64, 64, 64, 128 },
127 { "xbpfle", 64, 64, 64, 128 },
128 { "xbpfbe", 64, 64, 64, 128 },
129 { 0, 0, 0, 0, 0 }
130 };
131
132 /* Machine variants. */
133
134 static const CGEN_MACH bpf_cgen_mach_table[] = {
135 { "bpf", "bpf", MACH_BPF, 0 },
136 { "xbpf", "xbpf", MACH_XBPF, 0 },
137 { 0, 0, 0, 0 }
138 };
139
140 static CGEN_KEYWORD_ENTRY bpf_cgen_opval_h_gpr_entries[] =
141 {
142 { "%r0", 0, {0, {{{0, 0}}}}, 0, 0 },
143 { "%r1", 1, {0, {{{0, 0}}}}, 0, 0 },
144 { "%r2", 2, {0, {{{0, 0}}}}, 0, 0 },
145 { "%r3", 3, {0, {{{0, 0}}}}, 0, 0 },
146 { "%r4", 4, {0, {{{0, 0}}}}, 0, 0 },
147 { "%r5", 5, {0, {{{0, 0}}}}, 0, 0 },
148 { "%r6", 6, {0, {{{0, 0}}}}, 0, 0 },
149 { "%r7", 7, {0, {{{0, 0}}}}, 0, 0 },
150 { "%r8", 8, {0, {{{0, 0}}}}, 0, 0 },
151 { "%r9", 9, {0, {{{0, 0}}}}, 0, 0 },
152 { "%fp", 10, {0, {{{0, 0}}}}, 0, 0 },
153 { "%r0", 0, {0, {{{0, 0}}}}, 0, 0 },
154 { "%r6", 6, {0, {{{0, 0}}}}, 0, 0 },
155 { "%r10", 10, {0, {{{0, 0}}}}, 0, 0 }
156 };
157
158 CGEN_KEYWORD bpf_cgen_opval_h_gpr =
159 {
160 & bpf_cgen_opval_h_gpr_entries[0],
161 14,
162 0, 0, 0, 0, ""
163 };
164
165
166 /* The hardware table. */
167
168 #define A(a) (1 << CGEN_HW_##a)
169
170 const CGEN_HW_ENTRY bpf_cgen_hw_table[] =
171 {
172 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
173 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
174 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
175 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
176 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
177 { "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, (PTR) & bpf_cgen_opval_h_gpr, { 0, { { { (1<<MACH_BPF)|(1<<MACH_XBPF), 0 } }, { { 1, "\xf0" } } } } },
178 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
179 { "h-sint64", HW_H_SINT64, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
180 { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
181 };
182
183 #undef A
184
185
186 /* The instruction field table. */
187
188 #define A(a) (1 << CGEN_IFLD_##a)
189
190 const CGEN_IFLD bpf_cgen_ifld_table[] =
191 {
192 { BPF_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
193 { BPF_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
194 { BPF_F_OP_CODE, "f-op-code", 0, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
195 { BPF_F_OP_SRC, "f-op-src", 0, 8, 3, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
196 { BPF_F_OP_CLASS, "f-op-class", 0, 8, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
197 { BPF_F_OP_MODE, "f-op-mode", 0, 8, 7, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
198 { BPF_F_OP_SIZE, "f-op-size", 0, 8, 4, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
199 { BPF_F_DSTLE, "f-dstle", 8, 8, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } },
200 { BPF_F_SRCLE, "f-srcle", 8, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } },
201 { BPF_F_DSTBE, "f-dstbe", 8, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } },
202 { BPF_F_SRCBE, "f-srcbe", 8, 8, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } },
203 { BPF_F_REGS, "f-regs", 8, 8, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
204 { BPF_F_OFFSET16, "f-offset16", 16, 16, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
205 { BPF_F_IMM32, "f-imm32", 32, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
206 { BPF_F_IMM64_A, "f-imm64-a", 32, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
207 { BPF_F_IMM64_B, "f-imm64-b", 64, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
208 { BPF_F_IMM64_C, "f-imm64-c", 96, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
209 { BPF_F_IMM64, "f-imm64", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
210 { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
211 };
212
213 #undef A
214
215
216
217 /* multi ifield declarations */
218
219 const CGEN_MAYBE_MULTI_IFLD BPF_F_IMM64_MULTI_IFIELD [];
220
221
222 /* multi ifield definitions */
223
224 const CGEN_MAYBE_MULTI_IFLD BPF_F_IMM64_MULTI_IFIELD [] =
225 {
226 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM64_A] } },
227 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM64_B] } },
228 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM64_C] } },
229 { 0, { (const PTR) 0 } }
230 };
231
232 /* The operand table. */
233
234 #define A(a) (1 << CGEN_OPERAND_##a)
235 #define OPERAND(op) BPF_OPERAND_##op
236
237 const CGEN_OPERAND bpf_cgen_operand_table[] =
238 {
239 /* pc: program counter */
240 { "pc", BPF_OPERAND_PC, HW_H_PC, 0, 0,
241 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_NIL] } },
242 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
243 /* dstle: destination register */
244 { "dstle", BPF_OPERAND_DSTLE, HW_H_GPR, 3, 4,
245 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_DSTLE] } },
246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } },
247 /* srcle: source register */
248 { "srcle", BPF_OPERAND_SRCLE, HW_H_GPR, 7, 4,
249 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_SRCLE] } },
250 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } },
251 /* dstbe: destination register */
252 { "dstbe", BPF_OPERAND_DSTBE, HW_H_GPR, 7, 4,
253 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_DSTBE] } },
254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } },
255 /* srcbe: source register */
256 { "srcbe", BPF_OPERAND_SRCBE, HW_H_GPR, 3, 4,
257 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_SRCBE] } },
258 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } },
259 /* disp16: 16-bit PC-relative address */
260 { "disp16", BPF_OPERAND_DISP16, HW_H_SINT, 15, 16,
261 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_OFFSET16] } },
262 { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
263 /* disp32: 32-bit PC-relative address */
264 { "disp32", BPF_OPERAND_DISP32, HW_H_SINT, 31, 32,
265 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM32] } },
266 { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
267 /* imm32: 32-bit immediate */
268 { "imm32", BPF_OPERAND_IMM32, HW_H_SINT, 31, 32,
269 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM32] } },
270 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
271 /* offset16: 16-bit offset */
272 { "offset16", BPF_OPERAND_OFFSET16, HW_H_SINT, 15, 16,
273 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_OFFSET16] } },
274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
275 /* imm64: 64-bit immediate */
276 { "imm64", BPF_OPERAND_IMM64, HW_H_SINT64, 31, 96,
277 { 3, { (const PTR) &BPF_F_IMM64_MULTI_IFIELD[0] } },
278 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
279 /* endsize: endianness size immediate: 16, 32 or 64 */
280 { "endsize", BPF_OPERAND_ENDSIZE, HW_H_UINT, 31, 32,
281 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM32] } },
282 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
283 /* sentinel */
284 { 0, 0, 0, 0, 0,
285 { 0, { (const PTR) 0 } },
286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
287 };
288
289 #undef A
290
291
292 /* The instruction table. */
293
294 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
295 #define A(a) (1 << CGEN_INSN_##a)
296
297 static const CGEN_IBASE bpf_cgen_insn_table[MAX_INSNS] =
298 {
299 /* Special null first entry.
300 A `num' value of zero is thus invalid.
301 Also, the special `invalid' insn resides here. */
302 { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
303 /* add $dstle,$imm32 */
304 {
305 BPF_INSN_ADDILE, "addile", "add", 64,
306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
307 },
308 /* add $dstle,$srcle */
309 {
310 BPF_INSN_ADDRLE, "addrle", "add", 64,
311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
312 },
313 /* add32 $dstle,$imm32 */
314 {
315 BPF_INSN_ADD32ILE, "add32ile", "add32", 64,
316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
317 },
318 /* add32 $dstle,$srcle */
319 {
320 BPF_INSN_ADD32RLE, "add32rle", "add32", 64,
321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
322 },
323 /* sub $dstle,$imm32 */
324 {
325 BPF_INSN_SUBILE, "subile", "sub", 64,
326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
327 },
328 /* sub $dstle,$srcle */
329 {
330 BPF_INSN_SUBRLE, "subrle", "sub", 64,
331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
332 },
333 /* sub32 $dstle,$imm32 */
334 {
335 BPF_INSN_SUB32ILE, "sub32ile", "sub32", 64,
336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
337 },
338 /* sub32 $dstle,$srcle */
339 {
340 BPF_INSN_SUB32RLE, "sub32rle", "sub32", 64,
341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
342 },
343 /* mul $dstle,$imm32 */
344 {
345 BPF_INSN_MULILE, "mulile", "mul", 64,
346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
347 },
348 /* mul $dstle,$srcle */
349 {
350 BPF_INSN_MULRLE, "mulrle", "mul", 64,
351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
352 },
353 /* mul32 $dstle,$imm32 */
354 {
355 BPF_INSN_MUL32ILE, "mul32ile", "mul32", 64,
356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
357 },
358 /* mul32 $dstle,$srcle */
359 {
360 BPF_INSN_MUL32RLE, "mul32rle", "mul32", 64,
361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
362 },
363 /* div $dstle,$imm32 */
364 {
365 BPF_INSN_DIVILE, "divile", "div", 64,
366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
367 },
368 /* div $dstle,$srcle */
369 {
370 BPF_INSN_DIVRLE, "divrle", "div", 64,
371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
372 },
373 /* div32 $dstle,$imm32 */
374 {
375 BPF_INSN_DIV32ILE, "div32ile", "div32", 64,
376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
377 },
378 /* div32 $dstle,$srcle */
379 {
380 BPF_INSN_DIV32RLE, "div32rle", "div32", 64,
381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
382 },
383 /* or $dstle,$imm32 */
384 {
385 BPF_INSN_ORILE, "orile", "or", 64,
386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
387 },
388 /* or $dstle,$srcle */
389 {
390 BPF_INSN_ORRLE, "orrle", "or", 64,
391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
392 },
393 /* or32 $dstle,$imm32 */
394 {
395 BPF_INSN_OR32ILE, "or32ile", "or32", 64,
396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
397 },
398 /* or32 $dstle,$srcle */
399 {
400 BPF_INSN_OR32RLE, "or32rle", "or32", 64,
401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
402 },
403 /* and $dstle,$imm32 */
404 {
405 BPF_INSN_ANDILE, "andile", "and", 64,
406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
407 },
408 /* and $dstle,$srcle */
409 {
410 BPF_INSN_ANDRLE, "andrle", "and", 64,
411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
412 },
413 /* and32 $dstle,$imm32 */
414 {
415 BPF_INSN_AND32ILE, "and32ile", "and32", 64,
416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
417 },
418 /* and32 $dstle,$srcle */
419 {
420 BPF_INSN_AND32RLE, "and32rle", "and32", 64,
421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
422 },
423 /* lsh $dstle,$imm32 */
424 {
425 BPF_INSN_LSHILE, "lshile", "lsh", 64,
426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
427 },
428 /* lsh $dstle,$srcle */
429 {
430 BPF_INSN_LSHRLE, "lshrle", "lsh", 64,
431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
432 },
433 /* lsh32 $dstle,$imm32 */
434 {
435 BPF_INSN_LSH32ILE, "lsh32ile", "lsh32", 64,
436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
437 },
438 /* lsh32 $dstle,$srcle */
439 {
440 BPF_INSN_LSH32RLE, "lsh32rle", "lsh32", 64,
441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
442 },
443 /* rsh $dstle,$imm32 */
444 {
445 BPF_INSN_RSHILE, "rshile", "rsh", 64,
446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
447 },
448 /* rsh $dstle,$srcle */
449 {
450 BPF_INSN_RSHRLE, "rshrle", "rsh", 64,
451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
452 },
453 /* rsh32 $dstle,$imm32 */
454 {
455 BPF_INSN_RSH32ILE, "rsh32ile", "rsh32", 64,
456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
457 },
458 /* rsh32 $dstle,$srcle */
459 {
460 BPF_INSN_RSH32RLE, "rsh32rle", "rsh32", 64,
461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
462 },
463 /* mod $dstle,$imm32 */
464 {
465 BPF_INSN_MODILE, "modile", "mod", 64,
466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
467 },
468 /* mod $dstle,$srcle */
469 {
470 BPF_INSN_MODRLE, "modrle", "mod", 64,
471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
472 },
473 /* mod32 $dstle,$imm32 */
474 {
475 BPF_INSN_MOD32ILE, "mod32ile", "mod32", 64,
476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
477 },
478 /* mod32 $dstle,$srcle */
479 {
480 BPF_INSN_MOD32RLE, "mod32rle", "mod32", 64,
481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
482 },
483 /* xor $dstle,$imm32 */
484 {
485 BPF_INSN_XORILE, "xorile", "xor", 64,
486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
487 },
488 /* xor $dstle,$srcle */
489 {
490 BPF_INSN_XORRLE, "xorrle", "xor", 64,
491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
492 },
493 /* xor32 $dstle,$imm32 */
494 {
495 BPF_INSN_XOR32ILE, "xor32ile", "xor32", 64,
496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
497 },
498 /* xor32 $dstle,$srcle */
499 {
500 BPF_INSN_XOR32RLE, "xor32rle", "xor32", 64,
501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
502 },
503 /* arsh $dstle,$imm32 */
504 {
505 BPF_INSN_ARSHILE, "arshile", "arsh", 64,
506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
507 },
508 /* arsh $dstle,$srcle */
509 {
510 BPF_INSN_ARSHRLE, "arshrle", "arsh", 64,
511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
512 },
513 /* arsh32 $dstle,$imm32 */
514 {
515 BPF_INSN_ARSH32ILE, "arsh32ile", "arsh32", 64,
516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
517 },
518 /* arsh32 $dstle,$srcle */
519 {
520 BPF_INSN_ARSH32RLE, "arsh32rle", "arsh32", 64,
521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
522 },
523 /* sdiv $dstle,$imm32 */
524 {
525 BPF_INSN_SDIVILE, "sdivile", "sdiv", 64,
526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
527 },
528 /* sdiv $dstle,$srcle */
529 {
530 BPF_INSN_SDIVRLE, "sdivrle", "sdiv", 64,
531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
532 },
533 /* sdiv32 $dstle,$imm32 */
534 {
535 BPF_INSN_SDIV32ILE, "sdiv32ile", "sdiv32", 64,
536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
537 },
538 /* sdiv32 $dstle,$srcle */
539 {
540 BPF_INSN_SDIV32RLE, "sdiv32rle", "sdiv32", 64,
541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
542 },
543 /* smod $dstle,$imm32 */
544 {
545 BPF_INSN_SMODILE, "smodile", "smod", 64,
546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
547 },
548 /* smod $dstle,$srcle */
549 {
550 BPF_INSN_SMODRLE, "smodrle", "smod", 64,
551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
552 },
553 /* smod32 $dstle,$imm32 */
554 {
555 BPF_INSN_SMOD32ILE, "smod32ile", "smod32", 64,
556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
557 },
558 /* smod32 $dstle,$srcle */
559 {
560 BPF_INSN_SMOD32RLE, "smod32rle", "smod32", 64,
561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
562 },
563 /* neg $dstle */
564 {
565 BPF_INSN_NEGLE, "negle", "neg", 64,
566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
567 },
568 /* neg32 $dstle */
569 {
570 BPF_INSN_NEG32LE, "neg32le", "neg32", 64,
571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
572 },
573 /* mov $dstle,$imm32 */
574 {
575 BPF_INSN_MOVILE, "movile", "mov", 64,
576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
577 },
578 /* mov $dstle,$srcle */
579 {
580 BPF_INSN_MOVRLE, "movrle", "mov", 64,
581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
582 },
583 /* mov32 $dstle,$imm32 */
584 {
585 BPF_INSN_MOV32ILE, "mov32ile", "mov32", 64,
586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
587 },
588 /* mov32 $dstle,$srcle */
589 {
590 BPF_INSN_MOV32RLE, "mov32rle", "mov32", 64,
591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
592 },
593 /* add $dstbe,$imm32 */
594 {
595 BPF_INSN_ADDIBE, "addibe", "add", 64,
596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
597 },
598 /* add $dstbe,$srcbe */
599 {
600 BPF_INSN_ADDRBE, "addrbe", "add", 64,
601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
602 },
603 /* add32 $dstbe,$imm32 */
604 {
605 BPF_INSN_ADD32IBE, "add32ibe", "add32", 64,
606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
607 },
608 /* add32 $dstbe,$srcbe */
609 {
610 BPF_INSN_ADD32RBE, "add32rbe", "add32", 64,
611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
612 },
613 /* sub $dstbe,$imm32 */
614 {
615 BPF_INSN_SUBIBE, "subibe", "sub", 64,
616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
617 },
618 /* sub $dstbe,$srcbe */
619 {
620 BPF_INSN_SUBRBE, "subrbe", "sub", 64,
621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
622 },
623 /* sub32 $dstbe,$imm32 */
624 {
625 BPF_INSN_SUB32IBE, "sub32ibe", "sub32", 64,
626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
627 },
628 /* sub32 $dstbe,$srcbe */
629 {
630 BPF_INSN_SUB32RBE, "sub32rbe", "sub32", 64,
631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
632 },
633 /* mul $dstbe,$imm32 */
634 {
635 BPF_INSN_MULIBE, "mulibe", "mul", 64,
636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
637 },
638 /* mul $dstbe,$srcbe */
639 {
640 BPF_INSN_MULRBE, "mulrbe", "mul", 64,
641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
642 },
643 /* mul32 $dstbe,$imm32 */
644 {
645 BPF_INSN_MUL32IBE, "mul32ibe", "mul32", 64,
646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
647 },
648 /* mul32 $dstbe,$srcbe */
649 {
650 BPF_INSN_MUL32RBE, "mul32rbe", "mul32", 64,
651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
652 },
653 /* div $dstbe,$imm32 */
654 {
655 BPF_INSN_DIVIBE, "divibe", "div", 64,
656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
657 },
658 /* div $dstbe,$srcbe */
659 {
660 BPF_INSN_DIVRBE, "divrbe", "div", 64,
661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
662 },
663 /* div32 $dstbe,$imm32 */
664 {
665 BPF_INSN_DIV32IBE, "div32ibe", "div32", 64,
666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
667 },
668 /* div32 $dstbe,$srcbe */
669 {
670 BPF_INSN_DIV32RBE, "div32rbe", "div32", 64,
671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
672 },
673 /* or $dstbe,$imm32 */
674 {
675 BPF_INSN_ORIBE, "oribe", "or", 64,
676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
677 },
678 /* or $dstbe,$srcbe */
679 {
680 BPF_INSN_ORRBE, "orrbe", "or", 64,
681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
682 },
683 /* or32 $dstbe,$imm32 */
684 {
685 BPF_INSN_OR32IBE, "or32ibe", "or32", 64,
686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
687 },
688 /* or32 $dstbe,$srcbe */
689 {
690 BPF_INSN_OR32RBE, "or32rbe", "or32", 64,
691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
692 },
693 /* and $dstbe,$imm32 */
694 {
695 BPF_INSN_ANDIBE, "andibe", "and", 64,
696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
697 },
698 /* and $dstbe,$srcbe */
699 {
700 BPF_INSN_ANDRBE, "andrbe", "and", 64,
701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
702 },
703 /* and32 $dstbe,$imm32 */
704 {
705 BPF_INSN_AND32IBE, "and32ibe", "and32", 64,
706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
707 },
708 /* and32 $dstbe,$srcbe */
709 {
710 BPF_INSN_AND32RBE, "and32rbe", "and32", 64,
711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
712 },
713 /* lsh $dstbe,$imm32 */
714 {
715 BPF_INSN_LSHIBE, "lshibe", "lsh", 64,
716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
717 },
718 /* lsh $dstbe,$srcbe */
719 {
720 BPF_INSN_LSHRBE, "lshrbe", "lsh", 64,
721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
722 },
723 /* lsh32 $dstbe,$imm32 */
724 {
725 BPF_INSN_LSH32IBE, "lsh32ibe", "lsh32", 64,
726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
727 },
728 /* lsh32 $dstbe,$srcbe */
729 {
730 BPF_INSN_LSH32RBE, "lsh32rbe", "lsh32", 64,
731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
732 },
733 /* rsh $dstbe,$imm32 */
734 {
735 BPF_INSN_RSHIBE, "rshibe", "rsh", 64,
736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
737 },
738 /* rsh $dstbe,$srcbe */
739 {
740 BPF_INSN_RSHRBE, "rshrbe", "rsh", 64,
741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
742 },
743 /* rsh32 $dstbe,$imm32 */
744 {
745 BPF_INSN_RSH32IBE, "rsh32ibe", "rsh32", 64,
746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
747 },
748 /* rsh32 $dstbe,$srcbe */
749 {
750 BPF_INSN_RSH32RBE, "rsh32rbe", "rsh32", 64,
751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
752 },
753 /* mod $dstbe,$imm32 */
754 {
755 BPF_INSN_MODIBE, "modibe", "mod", 64,
756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
757 },
758 /* mod $dstbe,$srcbe */
759 {
760 BPF_INSN_MODRBE, "modrbe", "mod", 64,
761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
762 },
763 /* mod32 $dstbe,$imm32 */
764 {
765 BPF_INSN_MOD32IBE, "mod32ibe", "mod32", 64,
766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
767 },
768 /* mod32 $dstbe,$srcbe */
769 {
770 BPF_INSN_MOD32RBE, "mod32rbe", "mod32", 64,
771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
772 },
773 /* xor $dstbe,$imm32 */
774 {
775 BPF_INSN_XORIBE, "xoribe", "xor", 64,
776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
777 },
778 /* xor $dstbe,$srcbe */
779 {
780 BPF_INSN_XORRBE, "xorrbe", "xor", 64,
781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
782 },
783 /* xor32 $dstbe,$imm32 */
784 {
785 BPF_INSN_XOR32IBE, "xor32ibe", "xor32", 64,
786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
787 },
788 /* xor32 $dstbe,$srcbe */
789 {
790 BPF_INSN_XOR32RBE, "xor32rbe", "xor32", 64,
791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
792 },
793 /* arsh $dstbe,$imm32 */
794 {
795 BPF_INSN_ARSHIBE, "arshibe", "arsh", 64,
796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
797 },
798 /* arsh $dstbe,$srcbe */
799 {
800 BPF_INSN_ARSHRBE, "arshrbe", "arsh", 64,
801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
802 },
803 /* arsh32 $dstbe,$imm32 */
804 {
805 BPF_INSN_ARSH32IBE, "arsh32ibe", "arsh32", 64,
806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
807 },
808 /* arsh32 $dstbe,$srcbe */
809 {
810 BPF_INSN_ARSH32RBE, "arsh32rbe", "arsh32", 64,
811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
812 },
813 /* sdiv $dstbe,$imm32 */
814 {
815 BPF_INSN_SDIVIBE, "sdivibe", "sdiv", 64,
816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
817 },
818 /* sdiv $dstbe,$srcbe */
819 {
820 BPF_INSN_SDIVRBE, "sdivrbe", "sdiv", 64,
821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
822 },
823 /* sdiv32 $dstbe,$imm32 */
824 {
825 BPF_INSN_SDIV32IBE, "sdiv32ibe", "sdiv32", 64,
826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
827 },
828 /* sdiv32 $dstbe,$srcbe */
829 {
830 BPF_INSN_SDIV32RBE, "sdiv32rbe", "sdiv32", 64,
831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
832 },
833 /* smod $dstbe,$imm32 */
834 {
835 BPF_INSN_SMODIBE, "smodibe", "smod", 64,
836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
837 },
838 /* smod $dstbe,$srcbe */
839 {
840 BPF_INSN_SMODRBE, "smodrbe", "smod", 64,
841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
842 },
843 /* smod32 $dstbe,$imm32 */
844 {
845 BPF_INSN_SMOD32IBE, "smod32ibe", "smod32", 64,
846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
847 },
848 /* smod32 $dstbe,$srcbe */
849 {
850 BPF_INSN_SMOD32RBE, "smod32rbe", "smod32", 64,
851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
852 },
853 /* neg $dstbe */
854 {
855 BPF_INSN_NEGBE, "negbe", "neg", 64,
856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
857 },
858 /* neg32 $dstbe */
859 {
860 BPF_INSN_NEG32BE, "neg32be", "neg32", 64,
861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
862 },
863 /* mov $dstbe,$imm32 */
864 {
865 BPF_INSN_MOVIBE, "movibe", "mov", 64,
866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
867 },
868 /* mov $dstbe,$srcbe */
869 {
870 BPF_INSN_MOVRBE, "movrbe", "mov", 64,
871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
872 },
873 /* mov32 $dstbe,$imm32 */
874 {
875 BPF_INSN_MOV32IBE, "mov32ibe", "mov32", 64,
876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
877 },
878 /* mov32 $dstbe,$srcbe */
879 {
880 BPF_INSN_MOV32RBE, "mov32rbe", "mov32", 64,
881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
882 },
883 /* endle $dstle,$endsize */
884 {
885 BPF_INSN_ENDLELE, "endlele", "endle", 64,
886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
887 },
888 /* endbe $dstle,$endsize */
889 {
890 BPF_INSN_ENDBELE, "endbele", "endbe", 64,
891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
892 },
893 /* endle $dstbe,$endsize */
894 {
895 BPF_INSN_ENDLEBE, "endlebe", "endle", 64,
896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
897 },
898 /* endbe $dstbe,$endsize */
899 {
900 BPF_INSN_ENDBEBE, "endbebe", "endbe", 64,
901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
902 },
903 /* lddw $dstle,$imm64 */
904 {
905 BPF_INSN_LDDWLE, "lddwle", "lddw", 128,
906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
907 },
908 /* lddw $dstbe,$imm64 */
909 {
910 BPF_INSN_LDDWBE, "lddwbe", "lddw", 128,
911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
912 },
913 /* ldabsw $imm32 */
914 {
915 BPF_INSN_LDABSW, "ldabsw", "ldabsw", 64,
916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }
917 },
918 /* ldabsh $imm32 */
919 {
920 BPF_INSN_LDABSH, "ldabsh", "ldabsh", 64,
921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }
922 },
923 /* ldabsb $imm32 */
924 {
925 BPF_INSN_LDABSB, "ldabsb", "ldabsb", 64,
926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }
927 },
928 /* ldabsdw $imm32 */
929 {
930 BPF_INSN_LDABSDW, "ldabsdw", "ldabsdw", 64,
931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }
932 },
933 /* ldindw $srcle,$imm32 */
934 {
935 BPF_INSN_LDINDWLE, "ldindwle", "ldindw", 64,
936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
937 },
938 /* ldindh $srcle,$imm32 */
939 {
940 BPF_INSN_LDINDHLE, "ldindhle", "ldindh", 64,
941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
942 },
943 /* ldindb $srcle,$imm32 */
944 {
945 BPF_INSN_LDINDBLE, "ldindble", "ldindb", 64,
946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
947 },
948 /* ldinddw $srcle,$imm32 */
949 {
950 BPF_INSN_LDINDDWLE, "ldinddwle", "ldinddw", 64,
951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
952 },
953 /* ldindw $srcbe,$imm32 */
954 {
955 BPF_INSN_LDINDWBE, "ldindwbe", "ldindw", 64,
956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
957 },
958 /* ldindh $srcbe,$imm32 */
959 {
960 BPF_INSN_LDINDHBE, "ldindhbe", "ldindh", 64,
961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
962 },
963 /* ldindb $srcbe,$imm32 */
964 {
965 BPF_INSN_LDINDBBE, "ldindbbe", "ldindb", 64,
966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
967 },
968 /* ldinddw $srcbe,$imm32 */
969 {
970 BPF_INSN_LDINDDWBE, "ldinddwbe", "ldinddw", 64,
971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
972 },
973 /* ldxw $dstle,[$srcle+$offset16] */
974 {
975 BPF_INSN_LDXWLE, "ldxwle", "ldxw", 64,
976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
977 },
978 /* ldxh $dstle,[$srcle+$offset16] */
979 {
980 BPF_INSN_LDXHLE, "ldxhle", "ldxh", 64,
981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
982 },
983 /* ldxb $dstle,[$srcle+$offset16] */
984 {
985 BPF_INSN_LDXBLE, "ldxble", "ldxb", 64,
986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
987 },
988 /* ldxdw $dstle,[$srcle+$offset16] */
989 {
990 BPF_INSN_LDXDWLE, "ldxdwle", "ldxdw", 64,
991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
992 },
993 /* stxw [$dstle+$offset16],$srcle */
994 {
995 BPF_INSN_STXWLE, "stxwle", "stxw", 64,
996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
997 },
998 /* stxh [$dstle+$offset16],$srcle */
999 {
1000 BPF_INSN_STXHLE, "stxhle", "stxh", 64,
1001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1002 },
1003 /* stxb [$dstle+$offset16],$srcle */
1004 {
1005 BPF_INSN_STXBLE, "stxble", "stxb", 64,
1006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1007 },
1008 /* stxdw [$dstle+$offset16],$srcle */
1009 {
1010 BPF_INSN_STXDWLE, "stxdwle", "stxdw", 64,
1011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1012 },
1013 /* ldxw $dstbe,[$srcbe+$offset16] */
1014 {
1015 BPF_INSN_LDXWBE, "ldxwbe", "ldxw", 64,
1016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1017 },
1018 /* ldxh $dstbe,[$srcbe+$offset16] */
1019 {
1020 BPF_INSN_LDXHBE, "ldxhbe", "ldxh", 64,
1021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1022 },
1023 /* ldxb $dstbe,[$srcbe+$offset16] */
1024 {
1025 BPF_INSN_LDXBBE, "ldxbbe", "ldxb", 64,
1026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1027 },
1028 /* ldxdw $dstbe,[$srcbe+$offset16] */
1029 {
1030 BPF_INSN_LDXDWBE, "ldxdwbe", "ldxdw", 64,
1031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1032 },
1033 /* stxw [$dstbe+$offset16],$srcbe */
1034 {
1035 BPF_INSN_STXWBE, "stxwbe", "stxw", 64,
1036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1037 },
1038 /* stxh [$dstbe+$offset16],$srcbe */
1039 {
1040 BPF_INSN_STXHBE, "stxhbe", "stxh", 64,
1041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1042 },
1043 /* stxb [$dstbe+$offset16],$srcbe */
1044 {
1045 BPF_INSN_STXBBE, "stxbbe", "stxb", 64,
1046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1047 },
1048 /* stxdw [$dstbe+$offset16],$srcbe */
1049 {
1050 BPF_INSN_STXDWBE, "stxdwbe", "stxdw", 64,
1051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1052 },
1053 /* stb [$dstle+$offset16],$imm32 */
1054 {
1055 BPF_INSN_STBLE, "stble", "stb", 64,
1056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1057 },
1058 /* sth [$dstle+$offset16],$imm32 */
1059 {
1060 BPF_INSN_STHLE, "sthle", "sth", 64,
1061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1062 },
1063 /* stw [$dstle+$offset16],$imm32 */
1064 {
1065 BPF_INSN_STWLE, "stwle", "stw", 64,
1066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1067 },
1068 /* stdw [$dstle+$offset16],$imm32 */
1069 {
1070 BPF_INSN_STDWLE, "stdwle", "stdw", 64,
1071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1072 },
1073 /* stb [$dstbe+$offset16],$imm32 */
1074 {
1075 BPF_INSN_STBBE, "stbbe", "stb", 64,
1076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1077 },
1078 /* sth [$dstbe+$offset16],$imm32 */
1079 {
1080 BPF_INSN_STHBE, "sthbe", "sth", 64,
1081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1082 },
1083 /* stw [$dstbe+$offset16],$imm32 */
1084 {
1085 BPF_INSN_STWBE, "stwbe", "stw", 64,
1086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1087 },
1088 /* stdw [$dstbe+$offset16],$imm32 */
1089 {
1090 BPF_INSN_STDWBE, "stdwbe", "stdw", 64,
1091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1092 },
1093 /* jeq $dstle,$imm32,$disp16 */
1094 {
1095 BPF_INSN_JEQILE, "jeqile", "jeq", 64,
1096 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1097 },
1098 /* jeq $dstle,$srcle,$disp16 */
1099 {
1100 BPF_INSN_JEQRLE, "jeqrle", "jeq", 64,
1101 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1102 },
1103 /* jeq32 $dstle,$imm32,$disp16 */
1104 {
1105 BPF_INSN_JEQ32ILE, "jeq32ile", "jeq32", 64,
1106 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1107 },
1108 /* jeq32 $dstle,$srcle,$disp16 */
1109 {
1110 BPF_INSN_JEQ32RLE, "jeq32rle", "jeq32", 64,
1111 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1112 },
1113 /* jgt $dstle,$imm32,$disp16 */
1114 {
1115 BPF_INSN_JGTILE, "jgtile", "jgt", 64,
1116 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1117 },
1118 /* jgt $dstle,$srcle,$disp16 */
1119 {
1120 BPF_INSN_JGTRLE, "jgtrle", "jgt", 64,
1121 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1122 },
1123 /* jgt32 $dstle,$imm32,$disp16 */
1124 {
1125 BPF_INSN_JGT32ILE, "jgt32ile", "jgt32", 64,
1126 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1127 },
1128 /* jgt32 $dstle,$srcle,$disp16 */
1129 {
1130 BPF_INSN_JGT32RLE, "jgt32rle", "jgt32", 64,
1131 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1132 },
1133 /* jge $dstle,$imm32,$disp16 */
1134 {
1135 BPF_INSN_JGEILE, "jgeile", "jge", 64,
1136 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1137 },
1138 /* jge $dstle,$srcle,$disp16 */
1139 {
1140 BPF_INSN_JGERLE, "jgerle", "jge", 64,
1141 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1142 },
1143 /* jge32 $dstle,$imm32,$disp16 */
1144 {
1145 BPF_INSN_JGE32ILE, "jge32ile", "jge32", 64,
1146 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1147 },
1148 /* jge32 $dstle,$srcle,$disp16 */
1149 {
1150 BPF_INSN_JGE32RLE, "jge32rle", "jge32", 64,
1151 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1152 },
1153 /* jlt $dstle,$imm32,$disp16 */
1154 {
1155 BPF_INSN_JLTILE, "jltile", "jlt", 64,
1156 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1157 },
1158 /* jlt $dstle,$srcle,$disp16 */
1159 {
1160 BPF_INSN_JLTRLE, "jltrle", "jlt", 64,
1161 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1162 },
1163 /* jlt32 $dstle,$imm32,$disp16 */
1164 {
1165 BPF_INSN_JLT32ILE, "jlt32ile", "jlt32", 64,
1166 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1167 },
1168 /* jlt32 $dstle,$srcle,$disp16 */
1169 {
1170 BPF_INSN_JLT32RLE, "jlt32rle", "jlt32", 64,
1171 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1172 },
1173 /* jle $dstle,$imm32,$disp16 */
1174 {
1175 BPF_INSN_JLEILE, "jleile", "jle", 64,
1176 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1177 },
1178 /* jle $dstle,$srcle,$disp16 */
1179 {
1180 BPF_INSN_JLERLE, "jlerle", "jle", 64,
1181 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1182 },
1183 /* jle32 $dstle,$imm32,$disp16 */
1184 {
1185 BPF_INSN_JLE32ILE, "jle32ile", "jle32", 64,
1186 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1187 },
1188 /* jle32 $dstle,$srcle,$disp16 */
1189 {
1190 BPF_INSN_JLE32RLE, "jle32rle", "jle32", 64,
1191 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1192 },
1193 /* jset $dstle,$imm32,$disp16 */
1194 {
1195 BPF_INSN_JSETILE, "jsetile", "jset", 64,
1196 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1197 },
1198 /* jset $dstle,$srcle,$disp16 */
1199 {
1200 BPF_INSN_JSETRLE, "jsetrle", "jset", 64,
1201 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1202 },
1203 /* jset32 $dstle,$imm32,$disp16 */
1204 {
1205 BPF_INSN_JSET32ILE, "jset32ile", "jset32", 64,
1206 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1207 },
1208 /* jset32 $dstle,$srcle,$disp16 */
1209 {
1210 BPF_INSN_JSET32RLE, "jset32rle", "jset32", 64,
1211 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1212 },
1213 /* jne $dstle,$imm32,$disp16 */
1214 {
1215 BPF_INSN_JNEILE, "jneile", "jne", 64,
1216 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1217 },
1218 /* jne $dstle,$srcle,$disp16 */
1219 {
1220 BPF_INSN_JNERLE, "jnerle", "jne", 64,
1221 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1222 },
1223 /* jne32 $dstle,$imm32,$disp16 */
1224 {
1225 BPF_INSN_JNE32ILE, "jne32ile", "jne32", 64,
1226 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1227 },
1228 /* jne32 $dstle,$srcle,$disp16 */
1229 {
1230 BPF_INSN_JNE32RLE, "jne32rle", "jne32", 64,
1231 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1232 },
1233 /* jsgt $dstle,$imm32,$disp16 */
1234 {
1235 BPF_INSN_JSGTILE, "jsgtile", "jsgt", 64,
1236 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1237 },
1238 /* jsgt $dstle,$srcle,$disp16 */
1239 {
1240 BPF_INSN_JSGTRLE, "jsgtrle", "jsgt", 64,
1241 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1242 },
1243 /* jsgt32 $dstle,$imm32,$disp16 */
1244 {
1245 BPF_INSN_JSGT32ILE, "jsgt32ile", "jsgt32", 64,
1246 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1247 },
1248 /* jsgt32 $dstle,$srcle,$disp16 */
1249 {
1250 BPF_INSN_JSGT32RLE, "jsgt32rle", "jsgt32", 64,
1251 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1252 },
1253 /* jsge $dstle,$imm32,$disp16 */
1254 {
1255 BPF_INSN_JSGEILE, "jsgeile", "jsge", 64,
1256 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1257 },
1258 /* jsge $dstle,$srcle,$disp16 */
1259 {
1260 BPF_INSN_JSGERLE, "jsgerle", "jsge", 64,
1261 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1262 },
1263 /* jsge32 $dstle,$imm32,$disp16 */
1264 {
1265 BPF_INSN_JSGE32ILE, "jsge32ile", "jsge32", 64,
1266 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1267 },
1268 /* jsge32 $dstle,$srcle,$disp16 */
1269 {
1270 BPF_INSN_JSGE32RLE, "jsge32rle", "jsge32", 64,
1271 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1272 },
1273 /* jslt $dstle,$imm32,$disp16 */
1274 {
1275 BPF_INSN_JSLTILE, "jsltile", "jslt", 64,
1276 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1277 },
1278 /* jslt $dstle,$srcle,$disp16 */
1279 {
1280 BPF_INSN_JSLTRLE, "jsltrle", "jslt", 64,
1281 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1282 },
1283 /* jslt32 $dstle,$imm32,$disp16 */
1284 {
1285 BPF_INSN_JSLT32ILE, "jslt32ile", "jslt32", 64,
1286 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1287 },
1288 /* jslt32 $dstle,$srcle,$disp16 */
1289 {
1290 BPF_INSN_JSLT32RLE, "jslt32rle", "jslt32", 64,
1291 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1292 },
1293 /* jsle $dstle,$imm32,$disp16 */
1294 {
1295 BPF_INSN_JSLEILE, "jsleile", "jsle", 64,
1296 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1297 },
1298 /* jsle $dstle,$srcle,$disp16 */
1299 {
1300 BPF_INSN_JSLERLE, "jslerle", "jsle", 64,
1301 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1302 },
1303 /* jsle32 $dstle,$imm32,$disp16 */
1304 {
1305 BPF_INSN_JSLE32ILE, "jsle32ile", "jsle32", 64,
1306 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1307 },
1308 /* jsle32 $dstle,$srcle,$disp16 */
1309 {
1310 BPF_INSN_JSLE32RLE, "jsle32rle", "jsle32", 64,
1311 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1312 },
1313 /* jeq $dstbe,$imm32,$disp16 */
1314 {
1315 BPF_INSN_JEQIBE, "jeqibe", "jeq", 64,
1316 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1317 },
1318 /* jeq $dstbe,$srcbe,$disp16 */
1319 {
1320 BPF_INSN_JEQRBE, "jeqrbe", "jeq", 64,
1321 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1322 },
1323 /* jeq32 $dstbe,$imm32,$disp16 */
1324 {
1325 BPF_INSN_JEQ32IBE, "jeq32ibe", "jeq32", 64,
1326 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1327 },
1328 /* jeq32 $dstbe,$srcbe,$disp16 */
1329 {
1330 BPF_INSN_JEQ32RBE, "jeq32rbe", "jeq32", 64,
1331 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1332 },
1333 /* jgt $dstbe,$imm32,$disp16 */
1334 {
1335 BPF_INSN_JGTIBE, "jgtibe", "jgt", 64,
1336 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1337 },
1338 /* jgt $dstbe,$srcbe,$disp16 */
1339 {
1340 BPF_INSN_JGTRBE, "jgtrbe", "jgt", 64,
1341 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1342 },
1343 /* jgt32 $dstbe,$imm32,$disp16 */
1344 {
1345 BPF_INSN_JGT32IBE, "jgt32ibe", "jgt32", 64,
1346 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1347 },
1348 /* jgt32 $dstbe,$srcbe,$disp16 */
1349 {
1350 BPF_INSN_JGT32RBE, "jgt32rbe", "jgt32", 64,
1351 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1352 },
1353 /* jge $dstbe,$imm32,$disp16 */
1354 {
1355 BPF_INSN_JGEIBE, "jgeibe", "jge", 64,
1356 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1357 },
1358 /* jge $dstbe,$srcbe,$disp16 */
1359 {
1360 BPF_INSN_JGERBE, "jgerbe", "jge", 64,
1361 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1362 },
1363 /* jge32 $dstbe,$imm32,$disp16 */
1364 {
1365 BPF_INSN_JGE32IBE, "jge32ibe", "jge32", 64,
1366 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1367 },
1368 /* jge32 $dstbe,$srcbe,$disp16 */
1369 {
1370 BPF_INSN_JGE32RBE, "jge32rbe", "jge32", 64,
1371 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1372 },
1373 /* jlt $dstbe,$imm32,$disp16 */
1374 {
1375 BPF_INSN_JLTIBE, "jltibe", "jlt", 64,
1376 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1377 },
1378 /* jlt $dstbe,$srcbe,$disp16 */
1379 {
1380 BPF_INSN_JLTRBE, "jltrbe", "jlt", 64,
1381 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1382 },
1383 /* jlt32 $dstbe,$imm32,$disp16 */
1384 {
1385 BPF_INSN_JLT32IBE, "jlt32ibe", "jlt32", 64,
1386 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1387 },
1388 /* jlt32 $dstbe,$srcbe,$disp16 */
1389 {
1390 BPF_INSN_JLT32RBE, "jlt32rbe", "jlt32", 64,
1391 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1392 },
1393 /* jle $dstbe,$imm32,$disp16 */
1394 {
1395 BPF_INSN_JLEIBE, "jleibe", "jle", 64,
1396 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1397 },
1398 /* jle $dstbe,$srcbe,$disp16 */
1399 {
1400 BPF_INSN_JLERBE, "jlerbe", "jle", 64,
1401 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1402 },
1403 /* jle32 $dstbe,$imm32,$disp16 */
1404 {
1405 BPF_INSN_JLE32IBE, "jle32ibe", "jle32", 64,
1406 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1407 },
1408 /* jle32 $dstbe,$srcbe,$disp16 */
1409 {
1410 BPF_INSN_JLE32RBE, "jle32rbe", "jle32", 64,
1411 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1412 },
1413 /* jset $dstbe,$imm32,$disp16 */
1414 {
1415 BPF_INSN_JSETIBE, "jsetibe", "jset", 64,
1416 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1417 },
1418 /* jset $dstbe,$srcbe,$disp16 */
1419 {
1420 BPF_INSN_JSETRBE, "jsetrbe", "jset", 64,
1421 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1422 },
1423 /* jset32 $dstbe,$imm32,$disp16 */
1424 {
1425 BPF_INSN_JSET32IBE, "jset32ibe", "jset32", 64,
1426 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1427 },
1428 /* jset32 $dstbe,$srcbe,$disp16 */
1429 {
1430 BPF_INSN_JSET32RBE, "jset32rbe", "jset32", 64,
1431 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1432 },
1433 /* jne $dstbe,$imm32,$disp16 */
1434 {
1435 BPF_INSN_JNEIBE, "jneibe", "jne", 64,
1436 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1437 },
1438 /* jne $dstbe,$srcbe,$disp16 */
1439 {
1440 BPF_INSN_JNERBE, "jnerbe", "jne", 64,
1441 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1442 },
1443 /* jne32 $dstbe,$imm32,$disp16 */
1444 {
1445 BPF_INSN_JNE32IBE, "jne32ibe", "jne32", 64,
1446 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1447 },
1448 /* jne32 $dstbe,$srcbe,$disp16 */
1449 {
1450 BPF_INSN_JNE32RBE, "jne32rbe", "jne32", 64,
1451 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1452 },
1453 /* jsgt $dstbe,$imm32,$disp16 */
1454 {
1455 BPF_INSN_JSGTIBE, "jsgtibe", "jsgt", 64,
1456 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1457 },
1458 /* jsgt $dstbe,$srcbe,$disp16 */
1459 {
1460 BPF_INSN_JSGTRBE, "jsgtrbe", "jsgt", 64,
1461 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1462 },
1463 /* jsgt32 $dstbe,$imm32,$disp16 */
1464 {
1465 BPF_INSN_JSGT32IBE, "jsgt32ibe", "jsgt32", 64,
1466 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1467 },
1468 /* jsgt32 $dstbe,$srcbe,$disp16 */
1469 {
1470 BPF_INSN_JSGT32RBE, "jsgt32rbe", "jsgt32", 64,
1471 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1472 },
1473 /* jsge $dstbe,$imm32,$disp16 */
1474 {
1475 BPF_INSN_JSGEIBE, "jsgeibe", "jsge", 64,
1476 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1477 },
1478 /* jsge $dstbe,$srcbe,$disp16 */
1479 {
1480 BPF_INSN_JSGERBE, "jsgerbe", "jsge", 64,
1481 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1482 },
1483 /* jsge32 $dstbe,$imm32,$disp16 */
1484 {
1485 BPF_INSN_JSGE32IBE, "jsge32ibe", "jsge32", 64,
1486 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1487 },
1488 /* jsge32 $dstbe,$srcbe,$disp16 */
1489 {
1490 BPF_INSN_JSGE32RBE, "jsge32rbe", "jsge32", 64,
1491 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1492 },
1493 /* jslt $dstbe,$imm32,$disp16 */
1494 {
1495 BPF_INSN_JSLTIBE, "jsltibe", "jslt", 64,
1496 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1497 },
1498 /* jslt $dstbe,$srcbe,$disp16 */
1499 {
1500 BPF_INSN_JSLTRBE, "jsltrbe", "jslt", 64,
1501 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1502 },
1503 /* jslt32 $dstbe,$imm32,$disp16 */
1504 {
1505 BPF_INSN_JSLT32IBE, "jslt32ibe", "jslt32", 64,
1506 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1507 },
1508 /* jslt32 $dstbe,$srcbe,$disp16 */
1509 {
1510 BPF_INSN_JSLT32RBE, "jslt32rbe", "jslt32", 64,
1511 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1512 },
1513 /* jsle $dstbe,$imm32,$disp16 */
1514 {
1515 BPF_INSN_JSLEIBE, "jsleibe", "jsle", 64,
1516 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1517 },
1518 /* jsle $dstbe,$srcbe,$disp16 */
1519 {
1520 BPF_INSN_JSLERBE, "jslerbe", "jsle", 64,
1521 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1522 },
1523 /* jsle32 $dstbe,$imm32,$disp16 */
1524 {
1525 BPF_INSN_JSLE32IBE, "jsle32ibe", "jsle32", 64,
1526 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1527 },
1528 /* jsle32 $dstbe,$srcbe,$disp16 */
1529 {
1530 BPF_INSN_JSLE32RBE, "jsle32rbe", "jsle32", 64,
1531 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1532 },
1533 /* call $disp32 */
1534 {
1535 BPF_INSN_CALLLE, "callle", "call", 64,
1536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1537 },
1538 /* call $disp32 */
1539 {
1540 BPF_INSN_CALLBE, "callbe", "call", 64,
1541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1542 },
1543 /* call $dstle */
1544 {
1545 BPF_INSN_CALLRLE, "callrle", "call", 64,
1546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
1547 },
1548 /* call $dstbe */
1549 {
1550 BPF_INSN_CALLRBE, "callrbe", "call", 64,
1551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
1552 },
1553 /* ja $disp16 */
1554 {
1555 BPF_INSN_JA, "ja", "ja", 64,
1556 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }
1557 },
1558 /* exit */
1559 {
1560 BPF_INSN_EXIT, "exit", "exit", 64,
1561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }
1562 },
1563 /* xadddw [$dstle+$offset16],$srcle */
1564 {
1565 BPF_INSN_XADDDWLE, "xadddwle", "xadddw", 64,
1566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1567 },
1568 /* xaddw [$dstle+$offset16],$srcle */
1569 {
1570 BPF_INSN_XADDWLE, "xaddwle", "xaddw", 64,
1571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1572 },
1573 /* xadddw [$dstbe+$offset16],$srcbe */
1574 {
1575 BPF_INSN_XADDDWBE, "xadddwbe", "xadddw", 64,
1576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1577 },
1578 /* xaddw [$dstbe+$offset16],$srcbe */
1579 {
1580 BPF_INSN_XADDWBE, "xaddwbe", "xaddw", 64,
1581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1582 },
1583 /* brkpt */
1584 {
1585 BPF_INSN_BRKPT, "brkpt", "brkpt", 64,
1586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }
1587 },
1588 };
1589
1590 #undef OP
1591 #undef A
1592
1593 /* Initialize anything needed to be done once, before any cpu_open call. */
1594
1595 static void
init_tables(void)1596 init_tables (void)
1597 {
1598 }
1599
1600 #ifndef opcodes_error_handler
1601 #define opcodes_error_handler(...) \
1602 fprintf (stderr, __VA_ARGS__); fputc ('\n', stderr)
1603 #endif
1604
1605 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
1606 static void build_hw_table (CGEN_CPU_TABLE *);
1607 static void build_ifield_table (CGEN_CPU_TABLE *);
1608 static void build_operand_table (CGEN_CPU_TABLE *);
1609 static void build_insn_table (CGEN_CPU_TABLE *);
1610 static void bpf_cgen_rebuild_tables (CGEN_CPU_TABLE *);
1611
1612 /* Subroutine of bpf_cgen_cpu_open to look up a mach via its bfd name. */
1613
1614 static const CGEN_MACH *
lookup_mach_via_bfd_name(const CGEN_MACH * table,const char * name)1615 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
1616 {
1617 while (table->name)
1618 {
1619 if (strcmp (name, table->bfd_name) == 0)
1620 return table;
1621 ++table;
1622 }
1623 return NULL;
1624 }
1625
1626 /* Subroutine of bpf_cgen_cpu_open to build the hardware table. */
1627
1628 static void
build_hw_table(CGEN_CPU_TABLE * cd)1629 build_hw_table (CGEN_CPU_TABLE *cd)
1630 {
1631 int i;
1632 int machs = cd->machs;
1633 const CGEN_HW_ENTRY *init = & bpf_cgen_hw_table[0];
1634 /* MAX_HW is only an upper bound on the number of selected entries.
1635 However each entry is indexed by it's enum so there can be holes in
1636 the table. */
1637 const CGEN_HW_ENTRY **selected =
1638 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1639
1640 cd->hw_table.init_entries = init;
1641 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1642 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1643 /* ??? For now we just use machs to determine which ones we want. */
1644 for (i = 0; init[i].name != NULL; ++i)
1645 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1646 & machs)
1647 selected[init[i].type] = &init[i];
1648 cd->hw_table.entries = selected;
1649 cd->hw_table.num_entries = MAX_HW;
1650 }
1651
1652 /* Subroutine of bpf_cgen_cpu_open to build the hardware table. */
1653
1654 static void
build_ifield_table(CGEN_CPU_TABLE * cd)1655 build_ifield_table (CGEN_CPU_TABLE *cd)
1656 {
1657 cd->ifld_table = & bpf_cgen_ifld_table[0];
1658 }
1659
1660 /* Subroutine of bpf_cgen_cpu_open to build the hardware table. */
1661
1662 static void
build_operand_table(CGEN_CPU_TABLE * cd)1663 build_operand_table (CGEN_CPU_TABLE *cd)
1664 {
1665 int i;
1666 int machs = cd->machs;
1667 const CGEN_OPERAND *init = & bpf_cgen_operand_table[0];
1668 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1669 However each entry is indexed by it's enum so there can be holes in
1670 the table. */
1671 const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
1672
1673 cd->operand_table.init_entries = init;
1674 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1675 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1676 /* ??? For now we just use mach to determine which ones we want. */
1677 for (i = 0; init[i].name != NULL; ++i)
1678 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1679 & machs)
1680 selected[init[i].type] = &init[i];
1681 cd->operand_table.entries = selected;
1682 cd->operand_table.num_entries = MAX_OPERANDS;
1683 }
1684
1685 /* Subroutine of bpf_cgen_cpu_open to build the hardware table.
1686 ??? This could leave out insns not supported by the specified mach/isa,
1687 but that would cause errors like "foo only supported by bar" to become
1688 "unknown insn", so for now we include all insns and require the app to
1689 do the checking later.
1690 ??? On the other hand, parsing of such insns may require their hardware or
1691 operand elements to be in the table [which they mightn't be]. */
1692
1693 static void
build_insn_table(CGEN_CPU_TABLE * cd)1694 build_insn_table (CGEN_CPU_TABLE *cd)
1695 {
1696 int i;
1697 const CGEN_IBASE *ib = & bpf_cgen_insn_table[0];
1698 CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1699
1700 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1701 for (i = 0; i < MAX_INSNS; ++i)
1702 insns[i].base = &ib[i];
1703 cd->insn_table.init_entries = insns;
1704 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1705 cd->insn_table.num_init_entries = MAX_INSNS;
1706 }
1707
1708 /* Subroutine of bpf_cgen_cpu_open to rebuild the tables. */
1709
1710 static void
bpf_cgen_rebuild_tables(CGEN_CPU_TABLE * cd)1711 bpf_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
1712 {
1713 int i;
1714 CGEN_BITSET *isas = cd->isas;
1715 unsigned int machs = cd->machs;
1716
1717 cd->int_insn_p = CGEN_INT_INSN_P;
1718
1719 /* Data derived from the isa spec. */
1720 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
1721 cd->default_insn_bitsize = UNSET;
1722 cd->base_insn_bitsize = UNSET;
1723 cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
1724 cd->max_insn_bitsize = 0;
1725 for (i = 0; i < MAX_ISAS; ++i)
1726 if (cgen_bitset_contains (isas, i))
1727 {
1728 const CGEN_ISA *isa = & bpf_cgen_isa_table[i];
1729
1730 /* Default insn sizes of all selected isas must be
1731 equal or we set the result to 0, meaning "unknown". */
1732 if (cd->default_insn_bitsize == UNSET)
1733 cd->default_insn_bitsize = isa->default_insn_bitsize;
1734 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1735 ; /* This is ok. */
1736 else
1737 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1738
1739 /* Base insn sizes of all selected isas must be equal
1740 or we set the result to 0, meaning "unknown". */
1741 if (cd->base_insn_bitsize == UNSET)
1742 cd->base_insn_bitsize = isa->base_insn_bitsize;
1743 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1744 ; /* This is ok. */
1745 else
1746 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1747
1748 /* Set min,max insn sizes. */
1749 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1750 cd->min_insn_bitsize = isa->min_insn_bitsize;
1751 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1752 cd->max_insn_bitsize = isa->max_insn_bitsize;
1753 }
1754
1755 /* Data derived from the mach spec. */
1756 for (i = 0; i < MAX_MACHS; ++i)
1757 if (((1 << i) & machs) != 0)
1758 {
1759 const CGEN_MACH *mach = & bpf_cgen_mach_table[i];
1760
1761 if (mach->insn_chunk_bitsize != 0)
1762 {
1763 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
1764 {
1765 opcodes_error_handler
1766 (/* xgettext:c-format */
1767 _("internal error: bpf_cgen_rebuild_tables: "
1768 "conflicting insn-chunk-bitsize values: `%d' vs. `%d'"),
1769 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
1770 abort ();
1771 }
1772
1773 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
1774 }
1775 }
1776
1777 /* Determine which hw elements are used by MACH. */
1778 build_hw_table (cd);
1779
1780 /* Build the ifield table. */
1781 build_ifield_table (cd);
1782
1783 /* Determine which operands are used by MACH/ISA. */
1784 build_operand_table (cd);
1785
1786 /* Build the instruction table. */
1787 build_insn_table (cd);
1788 }
1789
1790 /* Initialize a cpu table and return a descriptor.
1791 It's much like opening a file, and must be the first function called.
1792 The arguments are a set of (type/value) pairs, terminated with
1793 CGEN_CPU_OPEN_END.
1794
1795 Currently supported values:
1796 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
1797 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
1798 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1799 CGEN_CPU_OPEN_ENDIAN: specify endian choice
1800 CGEN_CPU_OPEN_INSN_ENDIAN: specify instruction endian choice
1801 CGEN_CPU_OPEN_END: terminates arguments
1802
1803 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1804 precluded. */
1805
1806 CGEN_CPU_DESC
bpf_cgen_cpu_open(enum cgen_cpu_open_arg arg_type,...)1807 bpf_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1808 {
1809 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1810 static int init_p;
1811 CGEN_BITSET *isas = 0; /* 0 = "unspecified" */
1812 unsigned int machs = 0; /* 0 = "unspecified" */
1813 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1814 enum cgen_endian insn_endian = CGEN_ENDIAN_UNKNOWN;
1815 va_list ap;
1816
1817 if (! init_p)
1818 {
1819 init_tables ();
1820 init_p = 1;
1821 }
1822
1823 memset (cd, 0, sizeof (*cd));
1824
1825 va_start (ap, arg_type);
1826 while (arg_type != CGEN_CPU_OPEN_END)
1827 {
1828 switch (arg_type)
1829 {
1830 case CGEN_CPU_OPEN_ISAS :
1831 isas = va_arg (ap, CGEN_BITSET *);
1832 break;
1833 case CGEN_CPU_OPEN_MACHS :
1834 machs = va_arg (ap, unsigned int);
1835 break;
1836 case CGEN_CPU_OPEN_BFDMACH :
1837 {
1838 const char *name = va_arg (ap, const char *);
1839 const CGEN_MACH *mach =
1840 lookup_mach_via_bfd_name (bpf_cgen_mach_table, name);
1841
1842 if (mach != NULL)
1843 machs |= 1 << mach->num;
1844 break;
1845 }
1846 case CGEN_CPU_OPEN_ENDIAN :
1847 endian = va_arg (ap, enum cgen_endian);
1848 break;
1849 case CGEN_CPU_OPEN_INSN_ENDIAN :
1850 insn_endian = va_arg (ap, enum cgen_endian);
1851 break;
1852 default :
1853 opcodes_error_handler
1854 (/* xgettext:c-format */
1855 _("internal error: bpf_cgen_cpu_open: "
1856 "unsupported argument `%d'"),
1857 arg_type);
1858 abort (); /* ??? return NULL? */
1859 }
1860 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1861 }
1862 va_end (ap);
1863
1864 /* Mach unspecified means "all". */
1865 if (machs == 0)
1866 machs = (1 << MAX_MACHS) - 1;
1867 /* Base mach is always selected. */
1868 machs |= 1;
1869 if (endian == CGEN_ENDIAN_UNKNOWN)
1870 {
1871 /* ??? If target has only one, could have a default. */
1872 opcodes_error_handler
1873 (/* xgettext:c-format */
1874 _("internal error: bpf_cgen_cpu_open: no endianness specified"));
1875 abort ();
1876 }
1877
1878 cd->isas = cgen_bitset_copy (isas);
1879 cd->machs = machs;
1880 cd->endian = endian;
1881 cd->insn_endian
1882 = (insn_endian == CGEN_ENDIAN_UNKNOWN ? endian : insn_endian);
1883
1884 /* Table (re)builder. */
1885 cd->rebuild_tables = bpf_cgen_rebuild_tables;
1886 bpf_cgen_rebuild_tables (cd);
1887
1888 /* Default to not allowing signed overflow. */
1889 cd->signed_overflow_ok_p = 0;
1890
1891 return (CGEN_CPU_DESC) cd;
1892 }
1893
1894 /* Cover fn to bpf_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1895 MACH_NAME is the bfd name of the mach. */
1896
1897 CGEN_CPU_DESC
bpf_cgen_cpu_open_1(const char * mach_name,enum cgen_endian endian)1898 bpf_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
1899 {
1900 return bpf_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1901 CGEN_CPU_OPEN_ENDIAN, endian,
1902 CGEN_CPU_OPEN_END);
1903 }
1904
1905 /* Close a cpu table.
1906 ??? This can live in a machine independent file, but there's currently
1907 no place to put this file (there's no libcgen). libopcodes is the wrong
1908 place as some simulator ports use this but they don't use libopcodes. */
1909
1910 void
bpf_cgen_cpu_close(CGEN_CPU_DESC cd)1911 bpf_cgen_cpu_close (CGEN_CPU_DESC cd)
1912 {
1913 unsigned int i;
1914 const CGEN_INSN *insns;
1915
1916 if (cd->macro_insn_table.init_entries)
1917 {
1918 insns = cd->macro_insn_table.init_entries;
1919 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
1920 if (CGEN_INSN_RX ((insns)))
1921 regfree (CGEN_INSN_RX (insns));
1922 }
1923
1924 if (cd->insn_table.init_entries)
1925 {
1926 insns = cd->insn_table.init_entries;
1927 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
1928 if (CGEN_INSN_RX (insns))
1929 regfree (CGEN_INSN_RX (insns));
1930 }
1931
1932 free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
1933 free ((CGEN_INSN *) cd->insn_table.init_entries);
1934 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1935 free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
1936 free (cd);
1937 }
1938
1939