1 /* Definitions of target machine GNU compiler. IA-64 version. 2 Copyright (C) 1999-2018 Free Software Foundation, Inc. 3 Contributed by James E. Wilson <wilson@cygnus.com> and 4 David Mosberger <davidm@hpl.hp.com>. 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 GCC is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING3. If not see 20 <http://www.gnu.org/licenses/>. */ 21 22 /* ??? Look at ABI group documents for list of preprocessor macros and 23 other features required for ABI compliance. */ 24 25 /* ??? Functions containing a non-local goto target save many registers. Why? 26 See for instance execute/920428-2.c. */ 27 28 29 /* Run-time target specifications */ 30 31 /* Target CPU builtins. */ 32 #define TARGET_CPU_CPP_BUILTINS() \ 33 do { \ 34 builtin_assert("cpu=ia64"); \ 35 builtin_assert("machine=ia64"); \ 36 builtin_define("__ia64"); \ 37 builtin_define("__ia64__"); \ 38 builtin_define("__itanium__"); \ 39 if (TARGET_BIG_ENDIAN) \ 40 builtin_define("__BIG_ENDIAN__"); \ 41 builtin_define("__SIZEOF_FPREG__=16"); \ 42 builtin_define("__SIZEOF_FLOAT80__=16");\ 43 builtin_define("__SIZEOF_FLOAT128__=16");\ 44 } while (0) 45 46 #ifndef SUBTARGET_EXTRA_SPECS 47 #define SUBTARGET_EXTRA_SPECS 48 #endif 49 50 #define EXTRA_SPECS \ 51 { "asm_extra", ASM_EXTRA_SPEC }, \ 52 SUBTARGET_EXTRA_SPECS 53 54 #define CC1_SPEC "%(cc1_cpu) " 55 56 #define ASM_EXTRA_SPEC "" 57 58 /* Variables which are this size or smaller are put in the sdata/sbss 59 sections. */ 60 extern unsigned int ia64_section_threshold; 61 62 /* If the assembler supports thread-local storage, assume that the 63 system does as well. If a particular target system has an 64 assembler that supports TLS -- but the rest of the system does not 65 support TLS -- that system should explicit define TARGET_HAVE_TLS 66 to false in its own configuration file. */ 67 #if !defined(TARGET_HAVE_TLS) && defined(HAVE_AS_TLS) 68 #define TARGET_HAVE_TLS true 69 #endif 70 71 #define TARGET_TLS14 (ia64_tls_size == 14) 72 #define TARGET_TLS22 (ia64_tls_size == 22) 73 #define TARGET_TLS64 (ia64_tls_size == 64) 74 75 #define TARGET_HPUX 0 76 #define TARGET_HPUX_LD 0 77 78 #define TARGET_ABI_OPEN_VMS 0 79 80 #ifndef TARGET_ILP32 81 #define TARGET_ILP32 0 82 #endif 83 84 #ifndef HAVE_AS_LTOFFX_LDXMOV_RELOCS 85 #define HAVE_AS_LTOFFX_LDXMOV_RELOCS 0 86 #endif 87 88 /* Values for TARGET_INLINE_FLOAT_DIV, TARGET_INLINE_INT_DIV, and 89 TARGET_INLINE_SQRT. */ 90 91 enum ia64_inline_type 92 { 93 INL_NO = 0, 94 INL_MIN_LAT = 1, 95 INL_MAX_THR = 2 96 }; 97 98 /* Default target_flags if no switches are specified */ 99 100 #ifndef TARGET_DEFAULT 101 #define TARGET_DEFAULT (MASK_DWARF2_ASM) 102 #endif 103 104 #ifndef TARGET_CPU_DEFAULT 105 #define TARGET_CPU_DEFAULT 0 106 #endif 107 108 /* Driver configuration */ 109 110 /* A C string constant that tells the GCC driver program options to pass to 111 `cc1'. It can also specify how to translate options you give to GCC into 112 options for GCC to pass to the `cc1'. */ 113 114 #undef CC1_SPEC 115 #define CC1_SPEC "%{G*}" 116 117 /* A C string constant that tells the GCC driver program options to pass to 118 `cc1plus'. It can also specify how to translate options you give to GCC 119 into options for GCC to pass to the `cc1plus'. */ 120 121 /* #define CC1PLUS_SPEC "" */ 122 123 /* Storage Layout */ 124 125 /* Define this macro to have the value 1 if the most significant bit in a byte 126 has the lowest number; otherwise define it to have the value zero. */ 127 128 #define BITS_BIG_ENDIAN 0 129 130 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 131 132 /* Define this macro to have the value 1 if, in a multiword object, the most 133 significant word has the lowest number. */ 134 135 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 136 137 #define UNITS_PER_WORD 8 138 139 #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64) 140 141 /* A C expression whose value is zero if pointers that need to be extended 142 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and one if 143 they are zero-extended and negative one if there is a ptr_extend operation. 144 145 You need not define this macro if the `POINTER_SIZE' is equal to the width 146 of `Pmode'. */ 147 /* Need this for 32-bit pointers, see hpux.h for setting it. */ 148 /* #define POINTERS_EXTEND_UNSIGNED */ 149 150 /* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and 151 which has the specified mode and signedness is to be stored in a register. 152 This macro is only called when TYPE is a scalar type. */ 153 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 154 do \ 155 { \ 156 if (GET_MODE_CLASS (MODE) == MODE_INT \ 157 && GET_MODE_SIZE (MODE) < 4) \ 158 (MODE) = SImode; \ 159 } \ 160 while (0) 161 162 #define PARM_BOUNDARY 64 163 164 /* Define this macro if you wish to preserve a certain alignment for the stack 165 pointer. The definition is a C expression for the desired alignment 166 (measured in bits). */ 167 168 #define STACK_BOUNDARY 128 169 170 /* Align frames on double word boundaries */ 171 #ifndef IA64_STACK_ALIGN 172 #define IA64_STACK_ALIGN(LOC) (((LOC) + 15) & ~15) 173 #endif 174 175 #define FUNCTION_BOUNDARY 128 176 177 /* Optional x86 80-bit float, quad-precision 128-bit float, and quad-word 178 128-bit integers all require 128-bit alignment. */ 179 #define BIGGEST_ALIGNMENT 128 180 181 /* If defined, a C expression to compute the alignment for a static variable. 182 TYPE is the data type, and ALIGN is the alignment that the object 183 would ordinarily have. The value of this macro is used instead of that 184 alignment to align the object. */ 185 186 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 187 (TREE_CODE (TYPE) == ARRAY_TYPE \ 188 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 189 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 190 191 #define STRICT_ALIGNMENT 1 192 193 /* Define this if you wish to imitate the way many other C compilers handle 194 alignment of bitfields and the structures that contain them. 195 The behavior is that the type written for a bit-field (`int', `short', or 196 other integer type) imposes an alignment for the entire structure, as if the 197 structure really did contain an ordinary field of that type. In addition, 198 the bit-field is placed within the structure so that it would fit within such 199 a field, not crossing a boundary for it. */ 200 #define PCC_BITFIELD_TYPE_MATTERS 1 201 202 /* An integer expression for the size in bits of the largest integer machine 203 mode that should actually be used. */ 204 205 /* Allow pairs of registers to be used, which is the intent of the default. */ 206 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) 207 208 /* By default, the C++ compiler will use function addresses in the 209 vtable entries. Setting this nonzero tells the compiler to use 210 function descriptors instead. The value of this macro says how 211 many words wide the descriptor is (normally 2). It is assumed 212 that the address of a function descriptor may be treated as a 213 pointer to a function. 214 215 For reasons known only to HP, the vtable entries (as opposed to 216 normal function descriptors) are 16 bytes wide in 32-bit mode as 217 well, even though the 3rd and 4th words are unused. */ 218 #define TARGET_VTABLE_USES_DESCRIPTORS (TARGET_ILP32 ? 4 : 2) 219 220 /* Due to silliness in the HPUX linker, vtable entries must be 221 8-byte aligned even in 32-bit mode. Rather than create multiple 222 ABIs, force this restriction on everyone else too. */ 223 #define TARGET_VTABLE_ENTRY_ALIGN 64 224 225 /* Due to the above, we need extra padding for the data entries below 0 226 to retain the alignment of the descriptors. */ 227 #define TARGET_VTABLE_DATA_ENTRY_DISTANCE (TARGET_ILP32 ? 2 : 1) 228 229 /* Layout of Source Language Data Types */ 230 231 #define INT_TYPE_SIZE 32 232 233 #define SHORT_TYPE_SIZE 16 234 235 #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64) 236 237 #define LONG_LONG_TYPE_SIZE 64 238 239 #define FLOAT_TYPE_SIZE 32 240 241 #define DOUBLE_TYPE_SIZE 64 242 243 /* long double is XFmode normally, and TFmode for HPUX. It should be 244 TFmode for VMS as well but we only support up to DFmode now. */ 245 #define LONG_DOUBLE_TYPE_SIZE \ 246 (TARGET_HPUX ? 128 \ 247 : TARGET_ABI_OPEN_VMS ? 64 \ 248 : 80) 249 250 251 #define DEFAULT_SIGNED_CHAR 1 252 253 /* A C expression for a string describing the name of the data type to use for 254 size values. The typedef name `size_t' is defined using the contents of the 255 string. */ 256 /* ??? Needs to be defined for P64 code. */ 257 /* #define SIZE_TYPE */ 258 259 /* A C expression for a string describing the name of the data type to use for 260 the result of subtracting two pointers. The typedef name `ptrdiff_t' is 261 defined using the contents of the string. See `SIZE_TYPE' above for more 262 information. */ 263 /* ??? Needs to be defined for P64 code. */ 264 /* #define PTRDIFF_TYPE */ 265 266 /* A C expression for a string describing the name of the data type to use for 267 wide characters. The typedef name `wchar_t' is defined using the contents 268 of the string. See `SIZE_TYPE' above for more information. */ 269 /* #define WCHAR_TYPE */ 270 271 /* A C expression for the size in bits of the data type for wide characters. 272 This is used in `cpp', which cannot make use of `WCHAR_TYPE'. */ 273 /* #define WCHAR_TYPE_SIZE */ 274 275 276 /* Register Basics */ 277 278 /* Number of hardware registers known to the compiler. 279 We have 128 general registers, 128 floating point registers, 280 64 predicate registers, 8 branch registers, one frame pointer, 281 and several "application" registers. */ 282 283 #define FIRST_PSEUDO_REGISTER 334 284 285 /* Ranges for the various kinds of registers. */ 286 #define ADDL_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 3) 287 #define GR_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 127) 288 #define FR_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 255) 289 #define FP_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 254 && (REGNO) != 159) 290 #define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319) 291 #define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327) 292 #define GENERAL_REGNO_P(REGNO) \ 293 (GR_REGNO_P (REGNO) || (REGNO) == FRAME_POINTER_REGNUM) 294 295 #define GR_REG(REGNO) ((REGNO) + 0) 296 #define FR_REG(REGNO) ((REGNO) + 128) 297 #define PR_REG(REGNO) ((REGNO) + 256) 298 #define BR_REG(REGNO) ((REGNO) + 320) 299 #define OUT_REG(REGNO) ((REGNO) + 120) 300 #define IN_REG(REGNO) ((REGNO) + 112) 301 #define LOC_REG(REGNO) ((REGNO) + 32) 302 303 #define AR_CCV_REGNUM 329 304 #define AR_UNAT_REGNUM 330 305 #define AR_PFS_REGNUM 331 306 #define AR_LC_REGNUM 332 307 #define AR_EC_REGNUM 333 308 309 #define IN_REGNO_P(REGNO) ((REGNO) >= IN_REG (0) && (REGNO) <= IN_REG (7)) 310 #define LOC_REGNO_P(REGNO) ((REGNO) >= LOC_REG (0) && (REGNO) <= LOC_REG (79)) 311 #define OUT_REGNO_P(REGNO) ((REGNO) >= OUT_REG (0) && (REGNO) <= OUT_REG (7)) 312 313 #define AR_M_REGNO_P(REGNO) ((REGNO) == AR_CCV_REGNUM \ 314 || (REGNO) == AR_UNAT_REGNUM) 315 #define AR_I_REGNO_P(REGNO) ((REGNO) >= AR_PFS_REGNUM \ 316 && (REGNO) < FIRST_PSEUDO_REGISTER) 317 #define AR_REGNO_P(REGNO) ((REGNO) >= AR_CCV_REGNUM \ 318 && (REGNO) < FIRST_PSEUDO_REGISTER) 319 320 321 /* ??? Don't really need two sets of macros. I like this one better because 322 it is less typing. */ 323 #define R_GR(REGNO) GR_REG (REGNO) 324 #define R_FR(REGNO) FR_REG (REGNO) 325 #define R_PR(REGNO) PR_REG (REGNO) 326 #define R_BR(REGNO) BR_REG (REGNO) 327 328 /* An initializer that says which registers are used for fixed purposes all 329 throughout the compiled code and are therefore not available for general 330 allocation. 331 332 r0: constant 0 333 r1: global pointer (gp) 334 r12: stack pointer (sp) 335 r13: thread pointer (tp) 336 f0: constant 0.0 337 f1: constant 1.0 338 p0: constant true 339 fp: eliminable frame pointer */ 340 341 /* The last 16 stacked regs are reserved for the 8 input and 8 output 342 registers. */ 343 344 #define FIXED_REGISTERS \ 345 { /* General registers. */ \ 346 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \ 347 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 348 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 349 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 350 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 351 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 352 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 353 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 354 /* Floating-point registers. */ \ 355 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 356 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 357 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 358 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 359 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 360 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 361 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 362 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 363 /* Predicate registers. */ \ 364 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 365 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 366 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 367 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 368 /* Branch registers. */ \ 369 0, 0, 0, 0, 0, 0, 0, 0, \ 370 /*FP CCV UNAT PFS LC EC */ \ 371 1, 1, 1, 1, 1, 1 \ 372 } 373 374 /* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered 375 (in general) by function calls as well as for fixed registers. This 376 macro therefore identifies the registers that are not available for 377 general allocation of values that must live across function calls. */ 378 379 #define CALL_USED_REGISTERS \ 380 { /* General registers. */ \ 381 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \ 382 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 383 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 384 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 385 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 386 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 387 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 388 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \ 389 /* Floating-point registers. */ \ 390 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 391 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 392 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 393 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 394 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 395 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 396 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 397 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 398 /* Predicate registers. */ \ 399 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 400 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 401 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 402 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 403 /* Branch registers. */ \ 404 1, 0, 0, 0, 0, 0, 1, 1, \ 405 /*FP CCV UNAT PFS LC EC */ \ 406 1, 1, 1, 1, 1, 1 \ 407 } 408 409 /* Like `CALL_USED_REGISTERS' but used to overcome a historical 410 problem which makes CALL_USED_REGISTERS *always* include 411 all the FIXED_REGISTERS. Until this problem has been 412 resolved this macro can be used to overcome this situation. 413 In particular, block_propagate() requires this list 414 be accurate, or we can remove registers which should be live. 415 This macro is used in regs_invalidated_by_call. */ 416 417 #define CALL_REALLY_USED_REGISTERS \ 418 { /* General registers. */ \ 419 0, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, \ 420 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 421 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 422 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 423 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 424 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 425 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 426 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \ 427 /* Floating-point registers. */ \ 428 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 429 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 430 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 431 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 432 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 433 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 434 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 435 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 436 /* Predicate registers. */ \ 437 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 438 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 439 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 440 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 441 /* Branch registers. */ \ 442 1, 0, 0, 0, 0, 0, 1, 1, \ 443 /*FP CCV UNAT PFS LC EC */ \ 444 0, 1, 0, 1, 0, 0 \ 445 } 446 447 448 /* Define this macro if the target machine has register windows. This C 449 expression returns the register number as seen by the called function 450 corresponding to the register number OUT as seen by the calling function. 451 Return OUT if register number OUT is not an outbound register. */ 452 453 #define INCOMING_REGNO(OUT) \ 454 ((unsigned) ((OUT) - OUT_REG (0)) < 8 ? IN_REG ((OUT) - OUT_REG (0)) : (OUT)) 455 456 /* Define this macro if the target machine has register windows. This C 457 expression returns the register number as seen by the calling function 458 corresponding to the register number IN as seen by the called function. 459 Return IN if register number IN is not an inbound register. */ 460 461 #define OUTGOING_REGNO(IN) \ 462 ((unsigned) ((IN) - IN_REG (0)) < 8 ? OUT_REG ((IN) - IN_REG (0)) : (IN)) 463 464 /* Define this macro if the target machine has register windows. This 465 C expression returns true if the register is call-saved but is in the 466 register window. */ 467 468 #define LOCAL_REGNO(REGNO) \ 469 (IN_REGNO_P (REGNO) || LOC_REGNO_P (REGNO)) 470 471 /* We define CCImode in ia64-modes.def so we need a selector. */ 472 473 #define SELECT_CC_MODE(OP,X,Y) CCmode 474 475 /* Order of allocation of registers */ 476 477 /* If defined, an initializer for a vector of integers, containing the numbers 478 of hard registers in the order in which GCC should prefer to use them 479 (from most preferred to least). 480 481 If this macro is not defined, registers are used lowest numbered first (all 482 else being equal). 483 484 One use of this macro is on machines where the highest numbered registers 485 must always be saved and the save-multiple-registers instruction supports 486 only sequences of consecutive registers. On such machines, define 487 `REG_ALLOC_ORDER' to be an initializer that lists the highest numbered 488 allocatable register first. */ 489 490 /* ??? Should the GR return value registers come before or after the rest 491 of the caller-save GRs? */ 492 493 #define REG_ALLOC_ORDER \ 494 { \ 495 /* Caller-saved general registers. */ \ 496 R_GR (14), R_GR (15), R_GR (16), R_GR (17), \ 497 R_GR (18), R_GR (19), R_GR (20), R_GR (21), R_GR (22), R_GR (23), \ 498 R_GR (24), R_GR (25), R_GR (26), R_GR (27), R_GR (28), R_GR (29), \ 499 R_GR (30), R_GR (31), \ 500 /* Output registers. */ \ 501 R_GR (120), R_GR (121), R_GR (122), R_GR (123), R_GR (124), R_GR (125), \ 502 R_GR (126), R_GR (127), \ 503 /* Caller-saved general registers, also used for return values. */ \ 504 R_GR (8), R_GR (9), R_GR (10), R_GR (11), \ 505 /* addl caller-saved general registers. */ \ 506 R_GR (2), R_GR (3), \ 507 /* Caller-saved FP registers. */ \ 508 R_FR (6), R_FR (7), \ 509 /* Caller-saved FP registers, used for parameters and return values. */ \ 510 R_FR (8), R_FR (9), R_FR (10), R_FR (11), \ 511 R_FR (12), R_FR (13), R_FR (14), R_FR (15), \ 512 /* Rotating caller-saved FP registers. */ \ 513 R_FR (32), R_FR (33), R_FR (34), R_FR (35), \ 514 R_FR (36), R_FR (37), R_FR (38), R_FR (39), R_FR (40), R_FR (41), \ 515 R_FR (42), R_FR (43), R_FR (44), R_FR (45), R_FR (46), R_FR (47), \ 516 R_FR (48), R_FR (49), R_FR (50), R_FR (51), R_FR (52), R_FR (53), \ 517 R_FR (54), R_FR (55), R_FR (56), R_FR (57), R_FR (58), R_FR (59), \ 518 R_FR (60), R_FR (61), R_FR (62), R_FR (63), R_FR (64), R_FR (65), \ 519 R_FR (66), R_FR (67), R_FR (68), R_FR (69), R_FR (70), R_FR (71), \ 520 R_FR (72), R_FR (73), R_FR (74), R_FR (75), R_FR (76), R_FR (77), \ 521 R_FR (78), R_FR (79), R_FR (80), R_FR (81), R_FR (82), R_FR (83), \ 522 R_FR (84), R_FR (85), R_FR (86), R_FR (87), R_FR (88), R_FR (89), \ 523 R_FR (90), R_FR (91), R_FR (92), R_FR (93), R_FR (94), R_FR (95), \ 524 R_FR (96), R_FR (97), R_FR (98), R_FR (99), R_FR (100), R_FR (101), \ 525 R_FR (102), R_FR (103), R_FR (104), R_FR (105), R_FR (106), R_FR (107), \ 526 R_FR (108), R_FR (109), R_FR (110), R_FR (111), R_FR (112), R_FR (113), \ 527 R_FR (114), R_FR (115), R_FR (116), R_FR (117), R_FR (118), R_FR (119), \ 528 R_FR (120), R_FR (121), R_FR (122), R_FR (123), R_FR (124), R_FR (125), \ 529 R_FR (126), R_FR (127), \ 530 /* Caller-saved predicate registers. */ \ 531 R_PR (6), R_PR (7), R_PR (8), R_PR (9), R_PR (10), R_PR (11), \ 532 R_PR (12), R_PR (13), R_PR (14), R_PR (15), \ 533 /* Rotating caller-saved predicate registers. */ \ 534 R_PR (16), R_PR (17), \ 535 R_PR (18), R_PR (19), R_PR (20), R_PR (21), R_PR (22), R_PR (23), \ 536 R_PR (24), R_PR (25), R_PR (26), R_PR (27), R_PR (28), R_PR (29), \ 537 R_PR (30), R_PR (31), R_PR (32), R_PR (33), R_PR (34), R_PR (35), \ 538 R_PR (36), R_PR (37), R_PR (38), R_PR (39), R_PR (40), R_PR (41), \ 539 R_PR (42), R_PR (43), R_PR (44), R_PR (45), R_PR (46), R_PR (47), \ 540 R_PR (48), R_PR (49), R_PR (50), R_PR (51), R_PR (52), R_PR (53), \ 541 R_PR (54), R_PR (55), R_PR (56), R_PR (57), R_PR (58), R_PR (59), \ 542 R_PR (60), R_PR (61), R_PR (62), R_PR (63), \ 543 /* Caller-saved branch registers. */ \ 544 R_BR (6), R_BR (7), \ 545 \ 546 /* Stacked callee-saved general registers. */ \ 547 R_GR (32), R_GR (33), R_GR (34), R_GR (35), \ 548 R_GR (36), R_GR (37), R_GR (38), R_GR (39), R_GR (40), R_GR (41), \ 549 R_GR (42), R_GR (43), R_GR (44), R_GR (45), R_GR (46), R_GR (47), \ 550 R_GR (48), R_GR (49), R_GR (50), R_GR (51), R_GR (52), R_GR (53), \ 551 R_GR (54), R_GR (55), R_GR (56), R_GR (57), R_GR (58), R_GR (59), \ 552 R_GR (60), R_GR (61), R_GR (62), R_GR (63), R_GR (64), R_GR (65), \ 553 R_GR (66), R_GR (67), R_GR (68), R_GR (69), R_GR (70), R_GR (71), \ 554 R_GR (72), R_GR (73), R_GR (74), R_GR (75), R_GR (76), R_GR (77), \ 555 R_GR (78), R_GR (79), R_GR (80), R_GR (81), R_GR (82), R_GR (83), \ 556 R_GR (84), R_GR (85), R_GR (86), R_GR (87), R_GR (88), R_GR (89), \ 557 R_GR (90), R_GR (91), R_GR (92), R_GR (93), R_GR (94), R_GR (95), \ 558 R_GR (96), R_GR (97), R_GR (98), R_GR (99), R_GR (100), R_GR (101), \ 559 R_GR (102), R_GR (103), R_GR (104), R_GR (105), R_GR (106), R_GR (107), \ 560 R_GR (108), \ 561 /* Input registers. */ \ 562 R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (116), R_GR (117), \ 563 R_GR (118), R_GR (119), \ 564 /* Callee-saved general registers. */ \ 565 R_GR (4), R_GR (5), R_GR (6), R_GR (7), \ 566 /* Callee-saved FP registers. */ \ 567 R_FR (2), R_FR (3), R_FR (4), R_FR (5), R_FR (16), R_FR (17), \ 568 R_FR (18), R_FR (19), R_FR (20), R_FR (21), R_FR (22), R_FR (23), \ 569 R_FR (24), R_FR (25), R_FR (26), R_FR (27), R_FR (28), R_FR (29), \ 570 R_FR (30), R_FR (31), \ 571 /* Callee-saved predicate registers. */ \ 572 R_PR (1), R_PR (2), R_PR (3), R_PR (4), R_PR (5), \ 573 /* Callee-saved branch registers. */ \ 574 R_BR (1), R_BR (2), R_BR (3), R_BR (4), R_BR (5), \ 575 \ 576 /* ??? Stacked registers reserved for fp, rp, and ar.pfs. */ \ 577 R_GR (109), R_GR (110), R_GR (111), \ 578 \ 579 /* Special general registers. */ \ 580 R_GR (0), R_GR (1), R_GR (12), R_GR (13), \ 581 /* Special FP registers. */ \ 582 R_FR (0), R_FR (1), \ 583 /* Special predicate registers. */ \ 584 R_PR (0), \ 585 /* Special branch registers. */ \ 586 R_BR (0), \ 587 /* Other fixed registers. */ \ 588 FRAME_POINTER_REGNUM, \ 589 AR_CCV_REGNUM, AR_UNAT_REGNUM, AR_PFS_REGNUM, AR_LC_REGNUM, \ 590 AR_EC_REGNUM \ 591 } 592 593 /* How Values Fit in Registers */ 594 595 /* Specify the modes required to caller save a given hard regno. 596 We need to ensure floating pt regs are not saved as DImode. */ 597 598 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 599 ((FR_REGNO_P (REGNO) && (NREGS) == 1) ? RFmode \ 600 : choose_hard_reg_mode ((REGNO), (NREGS), false)) 601 602 /* Handling Leaf Functions */ 603 604 /* A C initializer for a vector, indexed by hard register number, which 605 contains 1 for a register that is allowable in a candidate for leaf function 606 treatment. */ 607 /* ??? This might be useful. */ 608 /* #define LEAF_REGISTERS */ 609 610 /* A C expression whose value is the register number to which REGNO should be 611 renumbered, when a function is treated as a leaf function. */ 612 /* ??? This might be useful. */ 613 /* #define LEAF_REG_REMAP(REGNO) */ 614 615 616 /* Register Classes */ 617 618 /* An enumeral type that must be defined with all the register class names as 619 enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last 620 register class, followed by one more enumeral value, `LIM_REG_CLASSES', 621 which is not a register class but rather tells how many classes there 622 are. */ 623 /* ??? When compiling without optimization, it is possible for the only use of 624 a pseudo to be a parameter load from the stack with a REG_EQUIV note. 625 Regclass handles this case specially and does not assign any costs to the 626 pseudo. The pseudo then ends up using the last class before ALL_REGS. 627 Thus we must not let either PR_REGS or BR_REGS be the last class. The 628 testcase for this is gcc.c-torture/execute/va-arg-7.c. */ 629 enum reg_class 630 { 631 NO_REGS, 632 PR_REGS, 633 BR_REGS, 634 AR_M_REGS, 635 AR_I_REGS, 636 ADDL_REGS, 637 GR_REGS, 638 FP_REGS, 639 FR_REGS, 640 GR_AND_BR_REGS, 641 GR_AND_FR_REGS, 642 ALL_REGS, 643 LIM_REG_CLASSES 644 }; 645 646 #define GENERAL_REGS GR_REGS 647 648 /* The number of distinct register classes. */ 649 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) 650 651 /* An initializer containing the names of the register classes as C string 652 constants. These names are used in writing some of the debugging dumps. */ 653 #define REG_CLASS_NAMES \ 654 { "NO_REGS", "PR_REGS", "BR_REGS", "AR_M_REGS", "AR_I_REGS", \ 655 "ADDL_REGS", "GR_REGS", "FP_REGS", "FR_REGS", \ 656 "GR_AND_BR_REGS", "GR_AND_FR_REGS", "ALL_REGS" } 657 658 /* An initializer containing the contents of the register classes, as integers 659 which are bit masks. The Nth integer specifies the contents of class N. 660 The way the integer MASK is interpreted is that register R is in the class 661 if `MASK & (1 << R)' is 1. */ 662 #define REG_CLASS_CONTENTS \ 663 { \ 664 /* NO_REGS. */ \ 665 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 666 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 667 0x00000000, 0x00000000, 0x0000 }, \ 668 /* PR_REGS. */ \ 669 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 670 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 671 0xFFFFFFFF, 0xFFFFFFFF, 0x0000 }, \ 672 /* BR_REGS. */ \ 673 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 674 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 675 0x00000000, 0x00000000, 0x00FF }, \ 676 /* AR_M_REGS. */ \ 677 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 678 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 679 0x00000000, 0x00000000, 0x0600 }, \ 680 /* AR_I_REGS. */ \ 681 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 682 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 683 0x00000000, 0x00000000, 0x3800 }, \ 684 /* ADDL_REGS. */ \ 685 { 0x0000000F, 0x00000000, 0x00000000, 0x00000000, \ 686 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 687 0x00000000, 0x00000000, 0x0000 }, \ 688 /* GR_REGS. */ \ 689 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 690 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 691 0x00000000, 0x00000000, 0x0100 }, \ 692 /* FP_REGS. */ \ 693 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 694 0x7FFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF, \ 695 0x00000000, 0x00000000, 0x0000 }, \ 696 /* FR_REGS. */ \ 697 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 698 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 699 0x00000000, 0x00000000, 0x0000 }, \ 700 /* GR_AND_BR_REGS. */ \ 701 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 702 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 703 0x00000000, 0x00000000, 0x01FF }, \ 704 /* GR_AND_FR_REGS. */ \ 705 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 706 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 707 0x00000000, 0x00000000, 0x0100 }, \ 708 /* ALL_REGS. */ \ 709 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 710 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 711 0xFFFFFFFF, 0xFFFFFFFF, 0x3FFF }, \ 712 } 713 714 /* A C expression whose value is a register class containing hard register 715 REGNO. In general there is more than one such class; choose a class which 716 is "minimal", meaning that no smaller class also contains the register. */ 717 /* The NO_REGS case is primarily for the benefit of rws_access_reg, which 718 may call here with private (invalid) register numbers, such as 719 REG_VOLATILE. */ 720 #define REGNO_REG_CLASS(REGNO) \ 721 (ADDL_REGNO_P (REGNO) ? ADDL_REGS \ 722 : GENERAL_REGNO_P (REGNO) ? GR_REGS \ 723 : FR_REGNO_P (REGNO) ? (REGNO) != R_FR (31) \ 724 && (REGNO) != R_FR(127) ? FP_REGS : FR_REGS \ 725 : PR_REGNO_P (REGNO) ? PR_REGS \ 726 : BR_REGNO_P (REGNO) ? BR_REGS \ 727 : AR_M_REGNO_P (REGNO) ? AR_M_REGS \ 728 : AR_I_REGNO_P (REGNO) ? AR_I_REGS \ 729 : NO_REGS) 730 731 /* A macro whose definition is the name of the class to which a valid base 732 register must belong. A base register is one used in an address which is 733 the register value plus a displacement. */ 734 #define BASE_REG_CLASS GENERAL_REGS 735 736 /* A macro whose definition is the name of the class to which a valid index 737 register must belong. An index register is one used in an address where its 738 value is either multiplied by a scale factor or added to another register 739 (as well as added to a displacement). This is needed for POST_MODIFY. */ 740 #define INDEX_REG_CLASS GENERAL_REGS 741 742 /* A C expression which is nonzero if register number NUM is suitable for use 743 as a base register in operand addresses. It may be either a suitable hard 744 register or a pseudo register that has been allocated such a hard reg. */ 745 #define REGNO_OK_FOR_BASE_P(REGNO) \ 746 (GENERAL_REGNO_P (REGNO) || GENERAL_REGNO_P (reg_renumber[REGNO])) 747 748 /* A C expression which is nonzero if register number NUM is suitable for use 749 as an index register in operand addresses. It may be either a suitable hard 750 register or a pseudo register that has been allocated such a hard reg. 751 This is needed for POST_MODIFY. */ 752 #define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM) 753 754 /* You should define this macro to indicate to the reload phase that it may 755 need to allocate at least one register for a reload in addition to the 756 register to contain the data. Specifically, if copying X to a register 757 CLASS in MODE requires an intermediate register, you should define this 758 to return the largest register class all of whose registers can be used 759 as intermediate registers or scratch registers. */ 760 761 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \ 762 ia64_secondary_reload_class (CLASS, MODE, X) 763 764 /* A C expression for the maximum number of consecutive registers of 765 class CLASS needed to hold a value of mode MODE. 766 This is closely related to TARGET_HARD_REGNO_NREGS. */ 767 768 #define CLASS_MAX_NREGS(CLASS, MODE) \ 769 ((MODE) == BImode && (CLASS) == PR_REGS ? 2 \ 770 : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XFmode) ? 1 \ 771 : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == RFmode) ? 1 \ 772 : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XCmode) ? 2 \ 773 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 774 775 /* Basic Stack Layout */ 776 777 /* Define this macro if pushing a word onto the stack moves the stack pointer 778 to a smaller address. */ 779 #define STACK_GROWS_DOWNWARD 1 780 781 /* Define this macro to nonzero if the addresses of local variable slots 782 are at negative offsets from the frame pointer. */ 783 #define FRAME_GROWS_DOWNWARD 0 784 785 /* Offset from the stack pointer register to the first location at which 786 outgoing arguments are placed. If not specified, the default value of zero 787 is used. This is the proper value for most machines. */ 788 /* IA64 has a 16 byte scratch area that is at the bottom of the stack. */ 789 #define STACK_POINTER_OFFSET 16 790 791 /* Offset from the argument pointer register to the first argument's address. 792 On some machines it may depend on the data type of the function. */ 793 #define FIRST_PARM_OFFSET(FUNDECL) 0 794 795 /* A C expression whose value is RTL representing the value of the return 796 address for the frame COUNT steps up from the current frame, after the 797 prologue. */ 798 799 /* ??? Frames other than zero would likely require interpreting the frame 800 unwind info, so we don't try to support them. We would also need to define 801 DYNAMIC_CHAIN_ADDRESS and SETUP_FRAME_ADDRESS (for the reg stack flush). */ 802 803 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 804 ia64_return_addr_rtx (COUNT, FRAME) 805 806 /* A C expression whose value is RTL representing the location of the incoming 807 return address at the beginning of any function, before the prologue. This 808 RTL is either a `REG', indicating that the return value is saved in `REG', 809 or a `MEM' representing a location in the stack. This enables DWARF2 810 unwind info for C++ EH. */ 811 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, BR_REG (0)) 812 813 /* A C expression whose value is an integer giving the offset, in bytes, from 814 the value of the stack pointer register to the top of the stack frame at the 815 beginning of any function, before the prologue. The top of the frame is 816 defined to be the value of the stack pointer in the previous frame, just 817 before the call instruction. */ 818 /* The CFA is past the red zone, not at the entry-point stack 819 pointer. */ 820 #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET 821 822 /* We shorten debug info by using CFA-16 as DW_AT_frame_base. */ 823 #define CFA_FRAME_BASE_OFFSET(FUNDECL) (-INCOMING_FRAME_SP_OFFSET) 824 825 826 /* Register That Address the Stack Frame. */ 827 828 /* The register number of the stack pointer register, which must also be a 829 fixed register according to `FIXED_REGISTERS'. On most machines, the 830 hardware determines which register this is. */ 831 832 #define STACK_POINTER_REGNUM 12 833 834 /* The register number of the frame pointer register, which is used to access 835 automatic variables in the stack frame. On some machines, the hardware 836 determines which register this is. On other machines, you can choose any 837 register you wish for this purpose. */ 838 839 #define FRAME_POINTER_REGNUM 328 840 841 /* Base register for access to local variables of the function. */ 842 #define HARD_FRAME_POINTER_REGNUM LOC_REG (79) 843 844 /* The register number of the arg pointer register, which is used to access the 845 function's argument list. */ 846 /* r0 won't otherwise be used, so put the always eliminated argument pointer 847 in it. */ 848 #define ARG_POINTER_REGNUM R_GR(0) 849 850 /* Due to the way varargs and argument spilling happens, the argument 851 pointer is not 16-byte aligned like the stack pointer. */ 852 #define INIT_EXPANDERS \ 853 do { \ 854 ia64_init_expanders (); \ 855 if (crtl->emit.regno_pointer_align) \ 856 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = 64; \ 857 } while (0) 858 859 /* Register numbers used for passing a function's static chain pointer. */ 860 /* ??? The ABI sez the static chain should be passed as a normal parameter. */ 861 #define STATIC_CHAIN_REGNUM 15 862 863 /* Eliminating the Frame Pointer and the Arg Pointer */ 864 865 /* If defined, this macro specifies a table of register pairs used to eliminate 866 unneeded registers that point into the stack frame. */ 867 868 #define ELIMINABLE_REGS \ 869 { \ 870 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 871 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 872 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 873 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 874 } 875 876 /* This macro returns the initial difference between the specified pair 877 of registers. */ 878 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 879 ((OFFSET) = ia64_initial_elimination_offset ((FROM), (TO))) 880 881 /* Passing Function Arguments on the Stack */ 882 883 /* If defined, the maximum amount of space required for outgoing arguments will 884 be computed and placed into the variable 885 `crtl->outgoing_args_size'. */ 886 887 #define ACCUMULATE_OUTGOING_ARGS 1 888 889 890 /* Function Arguments in Registers */ 891 892 #define MAX_ARGUMENT_SLOTS 8 893 #define MAX_INT_RETURN_SLOTS 4 894 #define GR_ARG_FIRST IN_REG (0) 895 #define GR_RET_FIRST GR_REG (8) 896 #define GR_RET_LAST GR_REG (11) 897 #define FR_ARG_FIRST FR_REG (8) 898 #define FR_RET_FIRST FR_REG (8) 899 #define FR_RET_LAST FR_REG (15) 900 #define AR_ARG_FIRST OUT_REG (0) 901 902 /* A C type for declaring a variable that is used as the first argument of 903 `FUNCTION_ARG' and other related values. For some target machines, the type 904 `int' suffices and can hold the number of bytes of argument so far. */ 905 906 enum ivms_arg_type {I64, FF, FD, FG, FS, FT}; 907 /* VMS floating point formats VAX F, VAX D, VAX G, IEEE S, IEEE T. */ 908 909 typedef struct ia64_args 910 { 911 int words; /* # words of arguments so far */ 912 int int_regs; /* # GR registers used so far */ 913 int fp_regs; /* # FR registers used so far */ 914 int prototype; /* whether function prototyped */ 915 enum ivms_arg_type atypes[8]; /* which VMS float type or if not float */ 916 } CUMULATIVE_ARGS; 917 918 /* A C statement (sans semicolon) for initializing the variable CUM for the 919 state at the beginning of the argument list. */ 920 921 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 922 do { \ 923 (CUM).words = 0; \ 924 (CUM).int_regs = 0; \ 925 (CUM).fp_regs = 0; \ 926 (CUM).prototype = ((FNTYPE) && prototype_p (FNTYPE)) || (LIBNAME); \ 927 (CUM).atypes[0] = (CUM).atypes[1] = (CUM).atypes[2] = I64; \ 928 (CUM).atypes[3] = (CUM).atypes[4] = (CUM).atypes[5] = I64; \ 929 (CUM).atypes[6] = (CUM).atypes[7] = I64; \ 930 } while (0) 931 932 /* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the 933 arguments for the function being compiled. If this macro is undefined, 934 `INIT_CUMULATIVE_ARGS' is used instead. */ 935 936 /* We set prototype to true so that we never try to return a PARALLEL from 937 function_arg. */ 938 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ 939 do { \ 940 (CUM).words = 0; \ 941 (CUM).int_regs = 0; \ 942 (CUM).fp_regs = 0; \ 943 (CUM).prototype = 1; \ 944 (CUM).atypes[0] = (CUM).atypes[1] = (CUM).atypes[2] = I64; \ 945 (CUM).atypes[3] = (CUM).atypes[4] = (CUM).atypes[5] = I64; \ 946 (CUM).atypes[6] = (CUM).atypes[7] = I64; \ 947 } while (0) 948 949 /* A C expression that is nonzero if REGNO is the number of a hard register in 950 which function arguments are sometimes passed. This does *not* include 951 implicit arguments such as the static chain and the structure-value address. 952 On many machines, no registers can be used for this purpose since all 953 function arguments are pushed on the stack. */ 954 #define FUNCTION_ARG_REGNO_P(REGNO) \ 955 (((REGNO) >= AR_ARG_FIRST && (REGNO) < (AR_ARG_FIRST + MAX_ARGUMENT_SLOTS)) \ 956 || ((REGNO) >= FR_ARG_FIRST && (REGNO) < (FR_ARG_FIRST + MAX_ARGUMENT_SLOTS))) 957 958 959 /* How Large Values are Returned */ 960 961 #define DEFAULT_PCC_STRUCT_RETURN 0 962 963 964 /* Caller-Saves Register Allocation */ 965 966 /* A C expression to determine whether it is worthwhile to consider placing a 967 pseudo-register in a call-clobbered hard register and saving and restoring 968 it around each function call. The expression should be 1 when this is worth 969 doing, and 0 otherwise. 970 971 If you don't define this macro, a default is used which is good on most 972 machines: `4 * CALLS < REFS'. */ 973 /* ??? Investigate. */ 974 /* #define CALLER_SAVE_PROFITABLE(REFS, CALLS) */ 975 976 977 /* Function Entry and Exit */ 978 979 /* Define this macro as a C expression that is nonzero if the return 980 instruction or the function epilogue ignores the value of the stack pointer; 981 in other words, if it is safe to delete an instruction to adjust the stack 982 pointer before a return from the function. */ 983 984 #define EXIT_IGNORE_STACK 1 985 986 /* Define this macro as a C expression that is nonzero for registers 987 used by the epilogue or the `return' pattern. */ 988 989 #define EPILOGUE_USES(REGNO) ia64_epilogue_uses (REGNO) 990 991 /* Nonzero for registers used by the exception handling mechanism. */ 992 993 #define EH_USES(REGNO) ia64_eh_uses (REGNO) 994 995 /* Output part N of a function descriptor for DECL. For ia64, both 996 words are emitted with a single relocation, so ignore N > 0. */ 997 #define ASM_OUTPUT_FDESC(FILE, DECL, PART) \ 998 do { \ 999 if ((PART) == 0) \ 1000 { \ 1001 if (TARGET_ILP32) \ 1002 fputs ("\tdata8.ua @iplt(", FILE); \ 1003 else \ 1004 fputs ("\tdata16.ua @iplt(", FILE); \ 1005 mark_decl_referenced (DECL); \ 1006 assemble_name (FILE, XSTR (XEXP (DECL_RTL (DECL), 0), 0)); \ 1007 fputs (")\n", FILE); \ 1008 if (TARGET_ILP32) \ 1009 fputs ("\tdata8.ua 0\n", FILE); \ 1010 } \ 1011 } while (0) 1012 1013 /* Generating Code for Profiling. */ 1014 1015 /* A C statement or compound statement to output to FILE some assembler code to 1016 call the profiling subroutine `mcount'. */ 1017 1018 #undef FUNCTION_PROFILER 1019 #define FUNCTION_PROFILER(FILE, LABELNO) \ 1020 ia64_output_function_profiler(FILE, LABELNO) 1021 1022 /* Neither hpux nor linux use profile counters. */ 1023 #define NO_PROFILE_COUNTERS 1 1024 1025 /* Trampolines for Nested Functions. */ 1026 1027 /* We need 32 bytes, so we can save the sp, ar.rnat, ar.bsp, and ar.pfs of 1028 the function containing a non-local goto target. */ 1029 1030 #define STACK_SAVEAREA_MODE(LEVEL) \ 1031 ((LEVEL) == SAVE_NONLOCAL ? OImode : Pmode) 1032 1033 /* A C expression for the size in bytes of the trampoline, as an integer. */ 1034 1035 #define TRAMPOLINE_SIZE 32 1036 1037 /* Alignment required for trampolines, in bits. */ 1038 1039 #define TRAMPOLINE_ALIGNMENT 64 1040 1041 /* Addressing Modes */ 1042 1043 /* Define this macro if the machine supports post-increment addressing. */ 1044 1045 #define HAVE_POST_INCREMENT 1 1046 #define HAVE_POST_DECREMENT 1 1047 #define HAVE_POST_MODIFY_DISP 1 1048 #define HAVE_POST_MODIFY_REG 1 1049 1050 /* A C expression that is 1 if the RTX X is a constant which is a valid 1051 address. */ 1052 1053 #define CONSTANT_ADDRESS_P(X) 0 1054 1055 /* The max number of registers that can appear in a valid memory address. */ 1056 1057 #define MAX_REGS_PER_ADDRESS 2 1058 1059 1060 /* Condition Code Status */ 1061 1062 /* One some machines not all possible comparisons are defined, but you can 1063 convert an invalid comparison into a valid one. */ 1064 /* ??? Investigate. See the alpha definition. */ 1065 /* #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) */ 1066 1067 1068 /* Describing Relative Costs of Operations */ 1069 1070 /* A C expression for the cost of a branch instruction. A value of 1 is the 1071 default; other values are interpreted relative to that. Used by the 1072 if-conversion code as max instruction count. */ 1073 /* ??? This requires investigation. The primary effect might be how 1074 many additional insn groups we run into, vs how good the dynamic 1075 branch predictor is. */ 1076 1077 #define BRANCH_COST(speed_p, predictable_p) 6 1078 1079 /* Define this macro as a C expression which is nonzero if accessing less than 1080 a word of memory (i.e. a `char' or a `short') is no faster than accessing a 1081 word of memory. */ 1082 1083 #define SLOW_BYTE_ACCESS 1 1084 1085 /* Define this macro if it is as good or better to call a constant function 1086 address than to call an address kept in a register. 1087 1088 Indirect function calls are more expensive that direct function calls, so 1089 don't cse function addresses. */ 1090 1091 #define NO_FUNCTION_CSE 1 1092 1093 1094 /* Dividing the output into sections. */ 1095 1096 /* A C expression whose value is a string containing the assembler operation 1097 that should precede instructions and read-only data. */ 1098 1099 #define TEXT_SECTION_ASM_OP "\t.text" 1100 1101 /* A C expression whose value is a string containing the assembler operation to 1102 identify the following data as writable initialized data. */ 1103 1104 #define DATA_SECTION_ASM_OP "\t.data" 1105 1106 /* If defined, a C expression whose value is a string containing the assembler 1107 operation to identify the following data as uninitialized global data. */ 1108 1109 #define BSS_SECTION_ASM_OP "\t.bss" 1110 1111 #define IA64_DEFAULT_GVALUE 8 1112 1113 /* Position Independent Code. */ 1114 1115 /* The register number of the register used to address a table of static data 1116 addresses in memory. */ 1117 1118 /* ??? Should modify ia64.md to use pic_offset_table_rtx instead of 1119 gen_rtx_REG (DImode, 1). */ 1120 1121 /* ??? Should we set flag_pic? Probably need to define 1122 LEGITIMIZE_PIC_OPERAND_P to make that work. */ 1123 1124 #define PIC_OFFSET_TABLE_REGNUM GR_REG (1) 1125 1126 /* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' is 1127 clobbered by calls. */ 1128 1129 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 1 1130 1131 1132 /* The Overall Framework of an Assembler File. */ 1133 1134 /* A C string constant describing how to begin a comment in the target 1135 assembler language. The compiler assumes that the comment will end at the 1136 end of the line. */ 1137 1138 #define ASM_COMMENT_START "//" 1139 1140 /* A C string constant for text to be output before each `asm' statement or 1141 group of consecutive ones. */ 1142 1143 #define ASM_APP_ON (TARGET_GNU_AS ? "#APP\n" : "//APP\n") 1144 1145 /* A C string constant for text to be output after each `asm' statement or 1146 group of consecutive ones. */ 1147 1148 #define ASM_APP_OFF (TARGET_GNU_AS ? "#NO_APP\n" : "//NO_APP\n") 1149 1150 /* Output and Generation of Labels. */ 1151 1152 /* A C statement (sans semicolon) to output to the stdio stream STREAM the 1153 assembler definition of a label named NAME. */ 1154 1155 /* See the ASM_OUTPUT_LABELREF definition in sysv4.h for an explanation of 1156 why ia64_asm_output_label exists. */ 1157 1158 extern int ia64_asm_output_label; 1159 #define ASM_OUTPUT_LABEL(STREAM, NAME) \ 1160 do { \ 1161 ia64_asm_output_label = 1; \ 1162 assemble_name (STREAM, NAME); \ 1163 fputs (":\n", STREAM); \ 1164 ia64_asm_output_label = 0; \ 1165 } while (0) 1166 1167 /* Globalizing directive for a label. */ 1168 #define GLOBAL_ASM_OP "\t.global " 1169 1170 /* A C statement (sans semicolon) to output to the stdio stream STREAM any text 1171 necessary for declaring the name of an external symbol named NAME which is 1172 referenced in this compilation but not defined. */ 1173 1174 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \ 1175 ia64_asm_output_external (FILE, DECL, NAME) 1176 1177 /* A C statement to store into the string STRING a label whose name is made 1178 from the string PREFIX and the number NUM. */ 1179 1180 #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \ 1181 do { \ 1182 sprintf (LABEL, "*.%s%d", PREFIX, NUM); \ 1183 } while (0) 1184 1185 /* ??? Not sure if using a ? in the name for Intel as is safe. */ 1186 1187 #define ASM_PN_FORMAT (TARGET_GNU_AS ? "%s.%lu" : "%s?%lu") 1188 1189 /* A C statement to output to the stdio stream STREAM assembler code which 1190 defines (equates) the symbol NAME to have the value VALUE. */ 1191 1192 #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \ 1193 do { \ 1194 assemble_name (STREAM, NAME); \ 1195 fputs (" = ", STREAM); \ 1196 if (ISDIGIT (*VALUE)) \ 1197 ia64_asm_output_label = 1; \ 1198 assemble_name (STREAM, VALUE); \ 1199 fputc ('\n', STREAM); \ 1200 ia64_asm_output_label = 0; \ 1201 } while (0) 1202 1203 1204 /* Macros Controlling Initialization Routines. */ 1205 1206 /* This is handled by sysv4.h. */ 1207 1208 1209 /* Output of Assembler Instructions. */ 1210 1211 /* A C initializer containing the assembler's names for the machine registers, 1212 each one as a C string constant. */ 1213 1214 #define REGISTER_NAMES \ 1215 { \ 1216 /* General registers. */ \ 1217 "ap", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \ 1218 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \ 1219 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \ 1220 "r30", "r31", \ 1221 /* Local registers. */ \ 1222 "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7", \ 1223 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15", \ 1224 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23", \ 1225 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31", \ 1226 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39", \ 1227 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47", \ 1228 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55", \ 1229 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63", \ 1230 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71", \ 1231 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79", \ 1232 /* Input registers. */ \ 1233 "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7", \ 1234 /* Output registers. */ \ 1235 "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7", \ 1236 /* Floating-point registers. */ \ 1237 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", \ 1238 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \ 1239 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \ 1240 "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", \ 1241 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", \ 1242 "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", \ 1243 "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69", \ 1244 "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79", \ 1245 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89", \ 1246 "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99", \ 1247 "f100","f101","f102","f103","f104","f105","f106","f107","f108","f109",\ 1248 "f110","f111","f112","f113","f114","f115","f116","f117","f118","f119",\ 1249 "f120","f121","f122","f123","f124","f125","f126","f127", \ 1250 /* Predicate registers. */ \ 1251 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", \ 1252 "p10", "p11", "p12", "p13", "p14", "p15", "p16", "p17", "p18", "p19", \ 1253 "p20", "p21", "p22", "p23", "p24", "p25", "p26", "p27", "p28", "p29", \ 1254 "p30", "p31", "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39", \ 1255 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47", "p48", "p49", \ 1256 "p50", "p51", "p52", "p53", "p54", "p55", "p56", "p57", "p58", "p59", \ 1257 "p60", "p61", "p62", "p63", \ 1258 /* Branch registers. */ \ 1259 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", \ 1260 /* Frame pointer. Application registers. */ \ 1261 "sfp", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec", \ 1262 } 1263 1264 /* If defined, a C initializer for an array of structures containing a name and 1265 a register number. This macro defines additional names for hard registers, 1266 thus allowing the `asm' option in declarations to refer to registers using 1267 alternate names. */ 1268 1269 #define ADDITIONAL_REGISTER_NAMES \ 1270 { \ 1271 { "gp", R_GR (1) }, \ 1272 { "sp", R_GR (12) }, \ 1273 { "in0", IN_REG (0) }, \ 1274 { "in1", IN_REG (1) }, \ 1275 { "in2", IN_REG (2) }, \ 1276 { "in3", IN_REG (3) }, \ 1277 { "in4", IN_REG (4) }, \ 1278 { "in5", IN_REG (5) }, \ 1279 { "in6", IN_REG (6) }, \ 1280 { "in7", IN_REG (7) }, \ 1281 { "out0", OUT_REG (0) }, \ 1282 { "out1", OUT_REG (1) }, \ 1283 { "out2", OUT_REG (2) }, \ 1284 { "out3", OUT_REG (3) }, \ 1285 { "out4", OUT_REG (4) }, \ 1286 { "out5", OUT_REG (5) }, \ 1287 { "out6", OUT_REG (6) }, \ 1288 { "out7", OUT_REG (7) }, \ 1289 { "loc0", LOC_REG (0) }, \ 1290 { "loc1", LOC_REG (1) }, \ 1291 { "loc2", LOC_REG (2) }, \ 1292 { "loc3", LOC_REG (3) }, \ 1293 { "loc4", LOC_REG (4) }, \ 1294 { "loc5", LOC_REG (5) }, \ 1295 { "loc6", LOC_REG (6) }, \ 1296 { "loc7", LOC_REG (7) }, \ 1297 { "loc8", LOC_REG (8) }, \ 1298 { "loc9", LOC_REG (9) }, \ 1299 { "loc10", LOC_REG (10) }, \ 1300 { "loc11", LOC_REG (11) }, \ 1301 { "loc12", LOC_REG (12) }, \ 1302 { "loc13", LOC_REG (13) }, \ 1303 { "loc14", LOC_REG (14) }, \ 1304 { "loc15", LOC_REG (15) }, \ 1305 { "loc16", LOC_REG (16) }, \ 1306 { "loc17", LOC_REG (17) }, \ 1307 { "loc18", LOC_REG (18) }, \ 1308 { "loc19", LOC_REG (19) }, \ 1309 { "loc20", LOC_REG (20) }, \ 1310 { "loc21", LOC_REG (21) }, \ 1311 { "loc22", LOC_REG (22) }, \ 1312 { "loc23", LOC_REG (23) }, \ 1313 { "loc24", LOC_REG (24) }, \ 1314 { "loc25", LOC_REG (25) }, \ 1315 { "loc26", LOC_REG (26) }, \ 1316 { "loc27", LOC_REG (27) }, \ 1317 { "loc28", LOC_REG (28) }, \ 1318 { "loc29", LOC_REG (29) }, \ 1319 { "loc30", LOC_REG (30) }, \ 1320 { "loc31", LOC_REG (31) }, \ 1321 { "loc32", LOC_REG (32) }, \ 1322 { "loc33", LOC_REG (33) }, \ 1323 { "loc34", LOC_REG (34) }, \ 1324 { "loc35", LOC_REG (35) }, \ 1325 { "loc36", LOC_REG (36) }, \ 1326 { "loc37", LOC_REG (37) }, \ 1327 { "loc38", LOC_REG (38) }, \ 1328 { "loc39", LOC_REG (39) }, \ 1329 { "loc40", LOC_REG (40) }, \ 1330 { "loc41", LOC_REG (41) }, \ 1331 { "loc42", LOC_REG (42) }, \ 1332 { "loc43", LOC_REG (43) }, \ 1333 { "loc44", LOC_REG (44) }, \ 1334 { "loc45", LOC_REG (45) }, \ 1335 { "loc46", LOC_REG (46) }, \ 1336 { "loc47", LOC_REG (47) }, \ 1337 { "loc48", LOC_REG (48) }, \ 1338 { "loc49", LOC_REG (49) }, \ 1339 { "loc50", LOC_REG (50) }, \ 1340 { "loc51", LOC_REG (51) }, \ 1341 { "loc52", LOC_REG (52) }, \ 1342 { "loc53", LOC_REG (53) }, \ 1343 { "loc54", LOC_REG (54) }, \ 1344 { "loc55", LOC_REG (55) }, \ 1345 { "loc56", LOC_REG (56) }, \ 1346 { "loc57", LOC_REG (57) }, \ 1347 { "loc58", LOC_REG (58) }, \ 1348 { "loc59", LOC_REG (59) }, \ 1349 { "loc60", LOC_REG (60) }, \ 1350 { "loc61", LOC_REG (61) }, \ 1351 { "loc62", LOC_REG (62) }, \ 1352 { "loc63", LOC_REG (63) }, \ 1353 { "loc64", LOC_REG (64) }, \ 1354 { "loc65", LOC_REG (65) }, \ 1355 { "loc66", LOC_REG (66) }, \ 1356 { "loc67", LOC_REG (67) }, \ 1357 { "loc68", LOC_REG (68) }, \ 1358 { "loc69", LOC_REG (69) }, \ 1359 { "loc70", LOC_REG (70) }, \ 1360 { "loc71", LOC_REG (71) }, \ 1361 { "loc72", LOC_REG (72) }, \ 1362 { "loc73", LOC_REG (73) }, \ 1363 { "loc74", LOC_REG (74) }, \ 1364 { "loc75", LOC_REG (75) }, \ 1365 { "loc76", LOC_REG (76) }, \ 1366 { "loc77", LOC_REG (77) }, \ 1367 { "loc78", LOC_REG (78) }, \ 1368 { "loc79", LOC_REG (79) }, \ 1369 } 1370 1371 /* If defined, C string expressions to be used for the `%R', `%L', `%U', and 1372 `%I' options of `asm_fprintf' (see `final.c'). */ 1373 1374 #define REGISTER_PREFIX "" 1375 #define LOCAL_LABEL_PREFIX "." 1376 #define USER_LABEL_PREFIX "" 1377 #define IMMEDIATE_PREFIX "" 1378 1379 1380 /* Output of dispatch tables. */ 1381 1382 /* This macro should be provided on machines where the addresses in a dispatch 1383 table are relative to the table's own address. */ 1384 1385 /* ??? Depends on the pointer size. */ 1386 1387 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ 1388 do { \ 1389 if (CASE_VECTOR_MODE == SImode) \ 1390 fprintf (STREAM, "\tdata4 @pcrel(.L%d)\n", VALUE); \ 1391 else \ 1392 fprintf (STREAM, "\tdata8 @pcrel(.L%d)\n", VALUE); \ 1393 } while (0) 1394 1395 /* Jump tables only need 4 or 8 byte alignment. */ 1396 1397 #define ADDR_VEC_ALIGN(ADDR_VEC) (CASE_VECTOR_MODE == SImode ? 2 : 3) 1398 1399 1400 /* Assembler Commands for Exception Regions. */ 1401 1402 /* Select a format to encode pointers in exception handling data. CODE 1403 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 1404 true if the symbol may be affected by dynamic relocations. */ 1405 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 1406 (((CODE) == 1 ? DW_EH_PE_textrel : DW_EH_PE_datarel) \ 1407 | ((GLOBAL) ? DW_EH_PE_indirect : 0) \ 1408 | (TARGET_ILP32 ? DW_EH_PE_udata4 : DW_EH_PE_udata8)) 1409 1410 /* Handle special EH pointer encodings. Absolute, pc-relative, and 1411 indirect are handled automatically. */ 1412 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \ 1413 do { \ 1414 const char *reltag = NULL; \ 1415 if (((ENCODING) & 0xF0) == DW_EH_PE_textrel) \ 1416 reltag = "@segrel("; \ 1417 else if (((ENCODING) & 0xF0) == DW_EH_PE_datarel) \ 1418 reltag = "@gprel("; \ 1419 if (reltag) \ 1420 { \ 1421 fputs (integer_asm_op (SIZE, FALSE), FILE); \ 1422 fputs (reltag, FILE); \ 1423 assemble_name (FILE, XSTR (ADDR, 0)); \ 1424 fputc (')', FILE); \ 1425 goto DONE; \ 1426 } \ 1427 } while (0) 1428 1429 1430 /* Assembler Commands for Alignment. */ 1431 1432 /* ??? Investigate. */ 1433 1434 /* The alignment (log base 2) to put in front of LABEL, which follows 1435 a BARRIER. */ 1436 1437 /* #define LABEL_ALIGN_AFTER_BARRIER(LABEL) */ 1438 1439 /* The desired alignment for the location counter at the beginning 1440 of a loop. */ 1441 1442 /* #define LOOP_ALIGN(LABEL) */ 1443 1444 /* Define this macro if `ASM_OUTPUT_SKIP' should not be used in the text 1445 section because it fails put zeros in the bytes that are skipped. */ 1446 1447 #define ASM_NO_SKIP_IN_TEXT 1 1448 1449 /* A C statement to output to the stdio stream STREAM an assembler command to 1450 advance the location counter to a multiple of 2 to the POWER bytes. */ 1451 1452 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \ 1453 fprintf (STREAM, "\t.align %d\n", 1<<(POWER)) 1454 1455 1456 /* Macros Affecting all Debug Formats. */ 1457 1458 /* This is handled in sysv4.h. */ 1459 1460 1461 /* Specific Options for DBX Output. */ 1462 1463 /* This is handled by dbxelf.h. */ 1464 1465 1466 /* Open ended Hooks for DBX Output. */ 1467 1468 /* Likewise. */ 1469 1470 1471 /* File names in DBX format. */ 1472 1473 /* Likewise. */ 1474 1475 1476 /* Macros for Dwarf Output. */ 1477 1478 /* Define this macro if GCC should produce dwarf version 2 format debugging 1479 output in response to the `-g' option. */ 1480 1481 #define DWARF2_DEBUGGING_INFO 1 1482 1483 #define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DWARF2_ASM) 1484 1485 /* Use tags for debug info labels, so that they don't break instruction 1486 bundles. This also avoids getting spurious DV warnings from the 1487 assembler. This is similar to (*targetm.asm_out.internal_label), except that we 1488 add brackets around the label. */ 1489 1490 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \ 1491 fprintf (FILE, TARGET_GNU_AS ? "[.%s%d:]\n" : ".%s%d:\n", PREFIX, NUM) 1492 1493 /* Use section-relative relocations for debugging offsets. Unlike other 1494 targets that fake this by putting the section VMA at 0, IA-64 has 1495 proper relocations for them. */ 1496 #define ASM_OUTPUT_DWARF_OFFSET(FILE, SIZE, LABEL, OFFSET, SECTION) \ 1497 do { \ 1498 fputs (integer_asm_op (SIZE, FALSE), FILE); \ 1499 fputs ("@secrel(", FILE); \ 1500 assemble_name (FILE, LABEL); \ 1501 if ((OFFSET) != 0) \ 1502 fprintf (FILE, "+" HOST_WIDE_INT_PRINT_DEC, \ 1503 (HOST_WIDE_INT) (OFFSET)); \ 1504 fputc (')', FILE); \ 1505 } while (0) 1506 1507 /* Emit a PC-relative relocation. */ 1508 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \ 1509 do { \ 1510 fputs (integer_asm_op (SIZE, FALSE), FILE); \ 1511 fputs ("@pcrel(", FILE); \ 1512 assemble_name (FILE, LABEL); \ 1513 fputc (')', FILE); \ 1514 } while (0) 1515 1516 /* Register Renaming Parameters. */ 1517 1518 /* A C expression that is nonzero if hard register number REGNO2 can be 1519 considered for use as a rename register for REGNO1 */ 1520 1521 #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \ 1522 ia64_hard_regno_rename_ok((REGNO1), (REGNO2)) 1523 1524 1525 /* Miscellaneous Parameters. */ 1526 1527 /* Flag to mark data that is in the small address area (addressable 1528 via "addl", that is, within a 2MByte offset of 0. */ 1529 #define SYMBOL_FLAG_SMALL_ADDR (SYMBOL_FLAG_MACH_DEP << 0) 1530 #define SYMBOL_REF_SMALL_ADDR_P(X) \ 1531 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_SMALL_ADDR) != 0) 1532 1533 /* An alias for a machine mode name. This is the machine mode that elements of 1534 a jump-table should have. */ 1535 1536 #define CASE_VECTOR_MODE ptr_mode 1537 1538 /* Define as C expression which evaluates to nonzero if the tablejump 1539 instruction expects the table to contain offsets from the address of the 1540 table. */ 1541 1542 #define CASE_VECTOR_PC_RELATIVE 1 1543 1544 /* Define this macro if operations between registers with integral mode smaller 1545 than a word are always performed on the entire register. */ 1546 1547 #define WORD_REGISTER_OPERATIONS 1 1548 1549 /* Define this macro to be a C expression indicating when insns that read 1550 memory in MODE, an integral mode narrower than a word, set the bits outside 1551 of MODE to be either the sign-extension or the zero-extension of the data 1552 read. */ 1553 1554 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1555 1556 /* The maximum number of bytes that a single instruction can move quickly from 1557 memory to memory. */ 1558 #define MOVE_MAX 8 1559 1560 /* A C expression describing the value returned by a comparison operator with 1561 an integral mode and stored by a store-flag instruction (`sCOND') when the 1562 condition is true. */ 1563 1564 /* ??? Investigate using STORE_FLAG_VALUE of -1 instead of 1. */ 1565 1566 /* An alias for the machine mode for pointers. */ 1567 1568 /* ??? This would change if we had ILP32 support. */ 1569 1570 #define Pmode DImode 1571 1572 /* An alias for the machine mode used for memory references to functions being 1573 called, in `call' RTL expressions. */ 1574 1575 #define FUNCTION_MODE Pmode 1576 1577 /* A C expression for the maximum number of instructions to execute via 1578 conditional execution instructions instead of a branch. A value of 1579 BRANCH_COST+1 is the default if the machine does not use 1580 cc0, and 1 if it does use cc0. */ 1581 /* ??? Investigate. */ 1582 #define MAX_CONDITIONAL_EXECUTE 12 1583 1584 extern int ia64_final_schedule; 1585 1586 #define TARGET_UNWIND_TABLES_DEFAULT true 1587 1588 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 15 : INVALID_REGNUM) 1589 1590 /* This function contains machine specific function data. */ 1591 struct GTY(()) machine_function 1592 { 1593 /* The new stack pointer when unwinding from EH. */ 1594 rtx ia64_eh_epilogue_sp; 1595 1596 /* The new bsp value when unwinding from EH. */ 1597 rtx ia64_eh_epilogue_bsp; 1598 1599 /* The GP value save register. */ 1600 rtx ia64_gp_save; 1601 1602 /* The number of varargs registers to save. */ 1603 int n_varargs; 1604 1605 /* The number of the next unwind state to copy. */ 1606 int state_num; 1607 }; 1608 1609 #define DONT_USE_BUILTIN_SETJMP 1610 1611 /* Output any profiling code before the prologue. */ 1612 1613 #undef PROFILE_BEFORE_PROLOGUE 1614 #define PROFILE_BEFORE_PROLOGUE 1 1615 1616 /* Initialize library function table. */ 1617 #undef TARGET_INIT_LIBFUNCS 1618 #define TARGET_INIT_LIBFUNCS ia64_init_libfuncs 1619 1620 1621 /* Switch on code for querying unit reservations. */ 1622 #define CPU_UNITS_QUERY 1 1623 1624 /* End of ia64.h */ 1625