1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987-2018 Free Software Foundation, Inc.
3
4 This file is part of GCC.
5
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
19
20 #define IN_TARGET_CODE 1
21
22 #include "config.h"
23 #include "system.h"
24 #include "coretypes.h"
25 #include "backend.h"
26 #include "cfghooks.h"
27 #include "tree.h"
28 #include "stringpool.h"
29 #include "attribs.h"
30 #include "rtl.h"
31 #include "df.h"
32 #include "alias.h"
33 #include "fold-const.h"
34 #include "calls.h"
35 #include "stor-layout.h"
36 #include "varasm.h"
37 #include "regs.h"
38 #include "insn-config.h"
39 #include "conditions.h"
40 #include "output.h"
41 #include "insn-attr.h"
42 #include "recog.h"
43 #include "diagnostic-core.h"
44 #include "flags.h"
45 #include "expmed.h"
46 #include "dojump.h"
47 #include "explow.h"
48 #include "memmodel.h"
49 #include "emit-rtl.h"
50 #include "stmt.h"
51 #include "expr.h"
52 #include "reload.h"
53 #include "tm_p.h"
54 #include "target.h"
55 #include "debug.h"
56 #include "cfgrtl.h"
57 #include "cfganal.h"
58 #include "lcm.h"
59 #include "cfgbuild.h"
60 #include "cfgcleanup.h"
61 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
62 #include "sched-int.h"
63 #include "insn-codes.h"
64 #include "opts.h"
65 #include "optabs.h"
66 #include "builtins.h"
67 #include "rtl-iter.h"
68
69 /* This file should be included last. */
70 #include "target-def.h"
71
72 enum reg_class regno_reg_class[] =
73 {
74 DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS,
75 DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS,
76 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
77 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
78 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
79 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
80 ADDR_REGS
81 };
82
83
84 /* The minimum number of integer registers that we want to save with the
85 movem instruction. Using two movel instructions instead of a single
86 moveml is about 15% faster for the 68020 and 68030 at no expense in
87 code size. */
88 #define MIN_MOVEM_REGS 3
89
90 /* The minimum number of floating point registers that we want to save
91 with the fmovem instruction. */
92 #define MIN_FMOVEM_REGS 1
93
94 /* Structure describing stack frame layout. */
95 struct m68k_frame
96 {
97 /* Stack pointer to frame pointer offset. */
98 HOST_WIDE_INT offset;
99
100 /* Offset of FPU registers. */
101 HOST_WIDE_INT foffset;
102
103 /* Frame size in bytes (rounded up). */
104 HOST_WIDE_INT size;
105
106 /* Data and address register. */
107 int reg_no;
108 unsigned int reg_mask;
109
110 /* FPU registers. */
111 int fpu_no;
112 unsigned int fpu_mask;
113
114 /* Offsets relative to ARG_POINTER. */
115 HOST_WIDE_INT frame_pointer_offset;
116 HOST_WIDE_INT stack_pointer_offset;
117
118 /* Function which the above information refers to. */
119 int funcdef_no;
120 };
121
122 /* Current frame information calculated by m68k_compute_frame_layout(). */
123 static struct m68k_frame current_frame;
124
125 /* Structure describing an m68k address.
126
127 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
128 with null fields evaluating to 0. Here:
129
130 - BASE satisfies m68k_legitimate_base_reg_p
131 - INDEX satisfies m68k_legitimate_index_reg_p
132 - OFFSET satisfies m68k_legitimate_constant_address_p
133
134 INDEX is either HImode or SImode. The other fields are SImode.
135
136 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
137 the address is (BASE)+. */
138 struct m68k_address {
139 enum rtx_code code;
140 rtx base;
141 rtx index;
142 rtx offset;
143 int scale;
144 };
145
146 static int m68k_sched_adjust_cost (rtx_insn *, int, rtx_insn *, int,
147 unsigned int);
148 static int m68k_sched_issue_rate (void);
149 static int m68k_sched_variable_issue (FILE *, int, rtx_insn *, int);
150 static void m68k_sched_md_init_global (FILE *, int, int);
151 static void m68k_sched_md_finish_global (FILE *, int);
152 static void m68k_sched_md_init (FILE *, int, int);
153 static void m68k_sched_dfa_pre_advance_cycle (void);
154 static void m68k_sched_dfa_post_advance_cycle (void);
155 static int m68k_sched_first_cycle_multipass_dfa_lookahead (void);
156
157 static bool m68k_can_eliminate (const int, const int);
158 static void m68k_conditional_register_usage (void);
159 static bool m68k_legitimate_address_p (machine_mode, rtx, bool);
160 static void m68k_option_override (void);
161 static void m68k_override_options_after_change (void);
162 static rtx find_addr_reg (rtx);
163 static const char *singlemove_string (rtx *);
164 static void m68k_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
165 HOST_WIDE_INT, tree);
166 static rtx m68k_struct_value_rtx (tree, int);
167 static tree m68k_handle_fndecl_attribute (tree *node, tree name,
168 tree args, int flags,
169 bool *no_add_attrs);
170 static void m68k_compute_frame_layout (void);
171 static bool m68k_save_reg (unsigned int regno, bool interrupt_handler);
172 static bool m68k_ok_for_sibcall_p (tree, tree);
173 static bool m68k_tls_symbol_p (rtx);
174 static rtx m68k_legitimize_address (rtx, rtx, machine_mode);
175 static bool m68k_rtx_costs (rtx, machine_mode, int, int, int *, bool);
176 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
177 static bool m68k_return_in_memory (const_tree, const_tree);
178 #endif
179 static void m68k_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
180 static void m68k_trampoline_init (rtx, tree, rtx);
181 static poly_int64 m68k_return_pops_args (tree, tree, poly_int64);
182 static rtx m68k_delegitimize_address (rtx);
183 static void m68k_function_arg_advance (cumulative_args_t, machine_mode,
184 const_tree, bool);
185 static rtx m68k_function_arg (cumulative_args_t, machine_mode,
186 const_tree, bool);
187 static bool m68k_cannot_force_const_mem (machine_mode mode, rtx x);
188 static bool m68k_output_addr_const_extra (FILE *, rtx);
189 static void m68k_init_sync_libfuncs (void) ATTRIBUTE_UNUSED;
190 static enum flt_eval_method
191 m68k_excess_precision (enum excess_precision_type);
192 static unsigned int m68k_hard_regno_nregs (unsigned int, machine_mode);
193 static bool m68k_hard_regno_mode_ok (unsigned int, machine_mode);
194 static bool m68k_modes_tieable_p (machine_mode, machine_mode);
195 static machine_mode m68k_promote_function_mode (const_tree, machine_mode,
196 int *, const_tree, int);
197
198 /* Initialize the GCC target structure. */
199
200 #if INT_OP_GROUP == INT_OP_DOT_WORD
201 #undef TARGET_ASM_ALIGNED_HI_OP
202 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
203 #endif
204
205 #if INT_OP_GROUP == INT_OP_NO_DOT
206 #undef TARGET_ASM_BYTE_OP
207 #define TARGET_ASM_BYTE_OP "\tbyte\t"
208 #undef TARGET_ASM_ALIGNED_HI_OP
209 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
210 #undef TARGET_ASM_ALIGNED_SI_OP
211 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
212 #endif
213
214 #if INT_OP_GROUP == INT_OP_DC
215 #undef TARGET_ASM_BYTE_OP
216 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
217 #undef TARGET_ASM_ALIGNED_HI_OP
218 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
219 #undef TARGET_ASM_ALIGNED_SI_OP
220 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
221 #endif
222
223 #undef TARGET_ASM_UNALIGNED_HI_OP
224 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
225 #undef TARGET_ASM_UNALIGNED_SI_OP
226 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
227
228 #undef TARGET_ASM_OUTPUT_MI_THUNK
229 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
230 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
231 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
232
233 #undef TARGET_ASM_FILE_START_APP_OFF
234 #define TARGET_ASM_FILE_START_APP_OFF true
235
236 #undef TARGET_LEGITIMIZE_ADDRESS
237 #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address
238
239 #undef TARGET_SCHED_ADJUST_COST
240 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
241
242 #undef TARGET_SCHED_ISSUE_RATE
243 #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate
244
245 #undef TARGET_SCHED_VARIABLE_ISSUE
246 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
247
248 #undef TARGET_SCHED_INIT_GLOBAL
249 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
250
251 #undef TARGET_SCHED_FINISH_GLOBAL
252 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
253
254 #undef TARGET_SCHED_INIT
255 #define TARGET_SCHED_INIT m68k_sched_md_init
256
257 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
258 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
259
260 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
261 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
262
263 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
264 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
265 m68k_sched_first_cycle_multipass_dfa_lookahead
266
267 #undef TARGET_OPTION_OVERRIDE
268 #define TARGET_OPTION_OVERRIDE m68k_option_override
269
270 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
271 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m68k_override_options_after_change
272
273 #undef TARGET_RTX_COSTS
274 #define TARGET_RTX_COSTS m68k_rtx_costs
275
276 #undef TARGET_ATTRIBUTE_TABLE
277 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
278
279 #undef TARGET_PROMOTE_PROTOTYPES
280 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
281
282 #undef TARGET_STRUCT_VALUE_RTX
283 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
284
285 #undef TARGET_CANNOT_FORCE_CONST_MEM
286 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_cannot_force_const_mem
287
288 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
289 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
290
291 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
292 #undef TARGET_RETURN_IN_MEMORY
293 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
294 #endif
295
296 #ifdef HAVE_AS_TLS
297 #undef TARGET_HAVE_TLS
298 #define TARGET_HAVE_TLS (true)
299
300 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
301 #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel
302 #endif
303
304 #undef TARGET_LRA_P
305 #define TARGET_LRA_P hook_bool_void_false
306
307 #undef TARGET_LEGITIMATE_ADDRESS_P
308 #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p
309
310 #undef TARGET_CAN_ELIMINATE
311 #define TARGET_CAN_ELIMINATE m68k_can_eliminate
312
313 #undef TARGET_CONDITIONAL_REGISTER_USAGE
314 #define TARGET_CONDITIONAL_REGISTER_USAGE m68k_conditional_register_usage
315
316 #undef TARGET_TRAMPOLINE_INIT
317 #define TARGET_TRAMPOLINE_INIT m68k_trampoline_init
318
319 #undef TARGET_RETURN_POPS_ARGS
320 #define TARGET_RETURN_POPS_ARGS m68k_return_pops_args
321
322 #undef TARGET_DELEGITIMIZE_ADDRESS
323 #define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address
324
325 #undef TARGET_FUNCTION_ARG
326 #define TARGET_FUNCTION_ARG m68k_function_arg
327
328 #undef TARGET_FUNCTION_ARG_ADVANCE
329 #define TARGET_FUNCTION_ARG_ADVANCE m68k_function_arg_advance
330
331 #undef TARGET_LEGITIMATE_CONSTANT_P
332 #define TARGET_LEGITIMATE_CONSTANT_P m68k_legitimate_constant_p
333
334 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
335 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA m68k_output_addr_const_extra
336
337 #undef TARGET_C_EXCESS_PRECISION
338 #define TARGET_C_EXCESS_PRECISION m68k_excess_precision
339
340 /* The value stored by TAS. */
341 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
342 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 128
343
344 #undef TARGET_HARD_REGNO_NREGS
345 #define TARGET_HARD_REGNO_NREGS m68k_hard_regno_nregs
346 #undef TARGET_HARD_REGNO_MODE_OK
347 #define TARGET_HARD_REGNO_MODE_OK m68k_hard_regno_mode_ok
348
349 #undef TARGET_MODES_TIEABLE_P
350 #define TARGET_MODES_TIEABLE_P m68k_modes_tieable_p
351
352 #undef TARGET_PROMOTE_FUNCTION_MODE
353 #define TARGET_PROMOTE_FUNCTION_MODE m68k_promote_function_mode
354
355 static const struct attribute_spec m68k_attribute_table[] =
356 {
357 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
358 affects_type_identity, handler, exclude } */
359 { "interrupt", 0, 0, true, false, false, false,
360 m68k_handle_fndecl_attribute, NULL },
361 { "interrupt_handler", 0, 0, true, false, false, false,
362 m68k_handle_fndecl_attribute, NULL },
363 { "interrupt_thread", 0, 0, true, false, false, false,
364 m68k_handle_fndecl_attribute, NULL },
365 { NULL, 0, 0, false, false, false, false, NULL, NULL }
366 };
367
368 struct gcc_target targetm = TARGET_INITIALIZER;
369
370 /* Base flags for 68k ISAs. */
371 #define FL_FOR_isa_00 FL_ISA_68000
372 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
373 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
374 generated 68881 code for 68020 and 68030 targets unless explicitly told
375 not to. */
376 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
377 | FL_BITFIELD | FL_68881 | FL_CAS)
378 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
379 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
380
381 /* Base flags for ColdFire ISAs. */
382 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
383 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
384 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
385 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
386 /* ISA_C is not upwardly compatible with ISA_B. */
387 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
388
389 enum m68k_isa
390 {
391 /* Traditional 68000 instruction sets. */
392 isa_00,
393 isa_10,
394 isa_20,
395 isa_40,
396 isa_cpu32,
397 /* ColdFire instruction set variants. */
398 isa_a,
399 isa_aplus,
400 isa_b,
401 isa_c,
402 isa_max
403 };
404
405 /* Information about one of the -march, -mcpu or -mtune arguments. */
406 struct m68k_target_selection
407 {
408 /* The argument being described. */
409 const char *name;
410
411 /* For -mcpu, this is the device selected by the option.
412 For -mtune and -march, it is a representative device
413 for the microarchitecture or ISA respectively. */
414 enum target_device device;
415
416 /* The M68K_DEVICE fields associated with DEVICE. See the comment
417 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
418 const char *family;
419 enum uarch_type microarch;
420 enum m68k_isa isa;
421 unsigned long flags;
422 };
423
424 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
425 static const struct m68k_target_selection all_devices[] =
426 {
427 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
428 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
429 #include "m68k-devices.def"
430 #undef M68K_DEVICE
431 { NULL, unk_device, NULL, unk_arch, isa_max, 0 }
432 };
433
434 /* A list of all ISAs, mapping each one to a representative device.
435 Used for -march selection. */
436 static const struct m68k_target_selection all_isas[] =
437 {
438 #define M68K_ISA(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
439 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
440 #include "m68k-isas.def"
441 #undef M68K_ISA
442 { NULL, unk_device, NULL, unk_arch, isa_max, 0 }
443 };
444
445 /* A list of all microarchitectures, mapping each one to a representative
446 device. Used for -mtune selection. */
447 static const struct m68k_target_selection all_microarchs[] =
448 {
449 #define M68K_MICROARCH(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
450 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
451 #include "m68k-microarchs.def"
452 #undef M68K_MICROARCH
453 { NULL, unk_device, NULL, unk_arch, isa_max, 0 }
454 };
455
456 /* The entries associated with the -mcpu, -march and -mtune settings,
457 or null for options that have not been used. */
458 const struct m68k_target_selection *m68k_cpu_entry;
459 const struct m68k_target_selection *m68k_arch_entry;
460 const struct m68k_target_selection *m68k_tune_entry;
461
462 /* Which CPU we are generating code for. */
463 enum target_device m68k_cpu;
464
465 /* Which microarchitecture to tune for. */
466 enum uarch_type m68k_tune;
467
468 /* Which FPU to use. */
469 enum fpu_type m68k_fpu;
470
471 /* The set of FL_* flags that apply to the target processor. */
472 unsigned int m68k_cpu_flags;
473
474 /* The set of FL_* flags that apply to the processor to be tuned for. */
475 unsigned int m68k_tune_flags;
476
477 /* Asm templates for calling or jumping to an arbitrary symbolic address,
478 or NULL if such calls or jumps are not supported. The address is held
479 in operand 0. */
480 const char *m68k_symbolic_call;
481 const char *m68k_symbolic_jump;
482
483 /* Enum variable that corresponds to m68k_symbolic_call values. */
484 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var;
485
486
487 /* Implement TARGET_OPTION_OVERRIDE. */
488
489 static void
m68k_option_override(void)490 m68k_option_override (void)
491 {
492 const struct m68k_target_selection *entry;
493 unsigned long target_mask;
494
495 if (global_options_set.x_m68k_arch_option)
496 m68k_arch_entry = &all_isas[m68k_arch_option];
497
498 if (global_options_set.x_m68k_cpu_option)
499 m68k_cpu_entry = &all_devices[(int) m68k_cpu_option];
500
501 if (global_options_set.x_m68k_tune_option)
502 m68k_tune_entry = &all_microarchs[(int) m68k_tune_option];
503
504 /* User can choose:
505
506 -mcpu=
507 -march=
508 -mtune=
509
510 -march=ARCH should generate code that runs any processor
511 implementing architecture ARCH. -mcpu=CPU should override -march
512 and should generate code that runs on processor CPU, making free
513 use of any instructions that CPU understands. -mtune=UARCH applies
514 on top of -mcpu or -march and optimizes the code for UARCH. It does
515 not change the target architecture. */
516 if (m68k_cpu_entry)
517 {
518 /* Complain if the -march setting is for a different microarchitecture,
519 or includes flags that the -mcpu setting doesn't. */
520 if (m68k_arch_entry
521 && (m68k_arch_entry->microarch != m68k_cpu_entry->microarch
522 || (m68k_arch_entry->flags & ~m68k_cpu_entry->flags) != 0))
523 warning (0, "-mcpu=%s conflicts with -march=%s",
524 m68k_cpu_entry->name, m68k_arch_entry->name);
525
526 entry = m68k_cpu_entry;
527 }
528 else
529 entry = m68k_arch_entry;
530
531 if (!entry)
532 entry = all_devices + TARGET_CPU_DEFAULT;
533
534 m68k_cpu_flags = entry->flags;
535
536 /* Use the architecture setting to derive default values for
537 certain flags. */
538 target_mask = 0;
539
540 /* ColdFire is lenient about alignment. */
541 if (!TARGET_COLDFIRE)
542 target_mask |= MASK_STRICT_ALIGNMENT;
543
544 if ((m68k_cpu_flags & FL_BITFIELD) != 0)
545 target_mask |= MASK_BITFIELD;
546 if ((m68k_cpu_flags & FL_CF_HWDIV) != 0)
547 target_mask |= MASK_CF_HWDIV;
548 if ((m68k_cpu_flags & (FL_68881 | FL_CF_FPU)) != 0)
549 target_mask |= MASK_HARD_FLOAT;
550 target_flags |= target_mask & ~target_flags_explicit;
551
552 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
553 m68k_cpu = entry->device;
554 if (m68k_tune_entry)
555 {
556 m68k_tune = m68k_tune_entry->microarch;
557 m68k_tune_flags = m68k_tune_entry->flags;
558 }
559 #ifdef M68K_DEFAULT_TUNE
560 else if (!m68k_cpu_entry && !m68k_arch_entry)
561 {
562 enum target_device dev;
563 dev = all_microarchs[M68K_DEFAULT_TUNE].device;
564 m68k_tune_flags = all_devices[dev].flags;
565 }
566 #endif
567 else
568 {
569 m68k_tune = entry->microarch;
570 m68k_tune_flags = entry->flags;
571 }
572
573 /* Set the type of FPU. */
574 m68k_fpu = (!TARGET_HARD_FLOAT ? FPUTYPE_NONE
575 : (m68k_cpu_flags & FL_COLDFIRE) != 0 ? FPUTYPE_COLDFIRE
576 : FPUTYPE_68881);
577
578 /* Sanity check to ensure that msep-data and mid-sahred-library are not
579 * both specified together. Doing so simply doesn't make sense.
580 */
581 if (TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY)
582 error ("cannot specify both -msep-data and -mid-shared-library");
583
584 /* If we're generating code for a separate A5 relative data segment,
585 * we've got to enable -fPIC as well. This might be relaxable to
586 * -fpic but it hasn't been tested properly.
587 */
588 if (TARGET_SEP_DATA || TARGET_ID_SHARED_LIBRARY)
589 flag_pic = 2;
590
591 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
592 error if the target does not support them. */
593 if (TARGET_PCREL && !TARGET_68020 && flag_pic == 2)
594 error ("-mpcrel -fPIC is not currently supported on selected cpu");
595
596 /* ??? A historic way of turning on pic, or is this intended to
597 be an embedded thing that doesn't have the same name binding
598 significance that it does on hosted ELF systems? */
599 if (TARGET_PCREL && flag_pic == 0)
600 flag_pic = 1;
601
602 if (!flag_pic)
603 {
604 m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_JSR;
605
606 m68k_symbolic_jump = "jra %a0";
607 }
608 else if (TARGET_ID_SHARED_LIBRARY)
609 /* All addresses must be loaded from the GOT. */
610 ;
611 else if (TARGET_68020 || TARGET_ISAB || TARGET_ISAC)
612 {
613 if (TARGET_PCREL)
614 m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_C;
615 else
616 m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_P;
617
618 if (TARGET_ISAC)
619 /* No unconditional long branch */;
620 else if (TARGET_PCREL)
621 m68k_symbolic_jump = "bra%.l %c0";
622 else
623 m68k_symbolic_jump = "bra%.l %p0";
624 /* Turn off function cse if we are doing PIC. We always want
625 function call to be done as `bsr foo@PLTPC'. */
626 /* ??? It's traditional to do this for -mpcrel too, but it isn't
627 clear how intentional that is. */
628 flag_no_function_cse = 1;
629 }
630
631 switch (m68k_symbolic_call_var)
632 {
633 case M68K_SYMBOLIC_CALL_JSR:
634 m68k_symbolic_call = "jsr %a0";
635 break;
636
637 case M68K_SYMBOLIC_CALL_BSR_C:
638 m68k_symbolic_call = "bsr%.l %c0";
639 break;
640
641 case M68K_SYMBOLIC_CALL_BSR_P:
642 m68k_symbolic_call = "bsr%.l %p0";
643 break;
644
645 case M68K_SYMBOLIC_CALL_NONE:
646 gcc_assert (m68k_symbolic_call == NULL);
647 break;
648
649 default:
650 gcc_unreachable ();
651 }
652
653 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
654 if (align_labels > 2)
655 {
656 warning (0, "-falign-labels=%d is not supported", align_labels);
657 align_labels = 0;
658 }
659 if (align_loops > 2)
660 {
661 warning (0, "-falign-loops=%d is not supported", align_loops);
662 align_loops = 0;
663 }
664 #endif
665
666 if ((opt_fstack_limit_symbol_arg != NULL || opt_fstack_limit_register_no >= 0)
667 && !TARGET_68020)
668 {
669 warning (0, "-fstack-limit- options are not supported on this cpu");
670 opt_fstack_limit_symbol_arg = NULL;
671 opt_fstack_limit_register_no = -1;
672 }
673
674 SUBTARGET_OVERRIDE_OPTIONS;
675
676 /* Setup scheduling options. */
677 if (TUNE_CFV1)
678 m68k_sched_cpu = CPU_CFV1;
679 else if (TUNE_CFV2)
680 m68k_sched_cpu = CPU_CFV2;
681 else if (TUNE_CFV3)
682 m68k_sched_cpu = CPU_CFV3;
683 else if (TUNE_CFV4)
684 m68k_sched_cpu = CPU_CFV4;
685 else
686 {
687 m68k_sched_cpu = CPU_UNKNOWN;
688 flag_schedule_insns = 0;
689 flag_schedule_insns_after_reload = 0;
690 flag_modulo_sched = 0;
691 flag_live_range_shrinkage = 0;
692 }
693
694 if (m68k_sched_cpu != CPU_UNKNOWN)
695 {
696 if ((m68k_cpu_flags & (FL_CF_EMAC | FL_CF_EMAC_B)) != 0)
697 m68k_sched_mac = MAC_CF_EMAC;
698 else if ((m68k_cpu_flags & FL_CF_MAC) != 0)
699 m68k_sched_mac = MAC_CF_MAC;
700 else
701 m68k_sched_mac = MAC_NO;
702 }
703 }
704
705 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE. */
706
707 static void
m68k_override_options_after_change(void)708 m68k_override_options_after_change (void)
709 {
710 if (m68k_sched_cpu == CPU_UNKNOWN)
711 {
712 flag_schedule_insns = 0;
713 flag_schedule_insns_after_reload = 0;
714 flag_modulo_sched = 0;
715 flag_live_range_shrinkage = 0;
716 }
717 }
718
719 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
720 given argument and NAME is the argument passed to -mcpu. Return NULL
721 if -mcpu was not passed. */
722
723 const char *
m68k_cpp_cpu_ident(const char * prefix)724 m68k_cpp_cpu_ident (const char *prefix)
725 {
726 if (!m68k_cpu_entry)
727 return NULL;
728 return concat ("__m", prefix, "_cpu_", m68k_cpu_entry->name, NULL);
729 }
730
731 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
732 given argument and NAME is the name of the representative device for
733 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
734
735 const char *
m68k_cpp_cpu_family(const char * prefix)736 m68k_cpp_cpu_family (const char *prefix)
737 {
738 if (!m68k_cpu_entry)
739 return NULL;
740 return concat ("__m", prefix, "_family_", m68k_cpu_entry->family, NULL);
741 }
742
743 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
744 "interrupt_handler" attribute and interrupt_thread if FUNC has an
745 "interrupt_thread" attribute. Otherwise, return
746 m68k_fk_normal_function. */
747
748 enum m68k_function_kind
m68k_get_function_kind(tree func)749 m68k_get_function_kind (tree func)
750 {
751 tree a;
752
753 gcc_assert (TREE_CODE (func) == FUNCTION_DECL);
754
755 a = lookup_attribute ("interrupt", DECL_ATTRIBUTES (func));
756 if (a != NULL_TREE)
757 return m68k_fk_interrupt_handler;
758
759 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
760 if (a != NULL_TREE)
761 return m68k_fk_interrupt_handler;
762
763 a = lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func));
764 if (a != NULL_TREE)
765 return m68k_fk_interrupt_thread;
766
767 return m68k_fk_normal_function;
768 }
769
770 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
771 struct attribute_spec.handler. */
772 static tree
m68k_handle_fndecl_attribute(tree * node,tree name,tree args ATTRIBUTE_UNUSED,int flags ATTRIBUTE_UNUSED,bool * no_add_attrs)773 m68k_handle_fndecl_attribute (tree *node, tree name,
774 tree args ATTRIBUTE_UNUSED,
775 int flags ATTRIBUTE_UNUSED,
776 bool *no_add_attrs)
777 {
778 if (TREE_CODE (*node) != FUNCTION_DECL)
779 {
780 warning (OPT_Wattributes, "%qE attribute only applies to functions",
781 name);
782 *no_add_attrs = true;
783 }
784
785 if (m68k_get_function_kind (*node) != m68k_fk_normal_function)
786 {
787 error ("multiple interrupt attributes not allowed");
788 *no_add_attrs = true;
789 }
790
791 if (!TARGET_FIDOA
792 && !strcmp (IDENTIFIER_POINTER (name), "interrupt_thread"))
793 {
794 error ("interrupt_thread is available only on fido");
795 *no_add_attrs = true;
796 }
797
798 return NULL_TREE;
799 }
800
801 static void
m68k_compute_frame_layout(void)802 m68k_compute_frame_layout (void)
803 {
804 int regno, saved;
805 unsigned int mask;
806 enum m68k_function_kind func_kind =
807 m68k_get_function_kind (current_function_decl);
808 bool interrupt_handler = func_kind == m68k_fk_interrupt_handler;
809 bool interrupt_thread = func_kind == m68k_fk_interrupt_thread;
810
811 /* Only compute the frame once per function.
812 Don't cache information until reload has been completed. */
813 if (current_frame.funcdef_no == current_function_funcdef_no
814 && reload_completed)
815 return;
816
817 current_frame.size = (get_frame_size () + 3) & -4;
818
819 mask = saved = 0;
820
821 /* Interrupt thread does not need to save any register. */
822 if (!interrupt_thread)
823 for (regno = 0; regno < 16; regno++)
824 if (m68k_save_reg (regno, interrupt_handler))
825 {
826 mask |= 1 << (regno - D0_REG);
827 saved++;
828 }
829 current_frame.offset = saved * 4;
830 current_frame.reg_no = saved;
831 current_frame.reg_mask = mask;
832
833 current_frame.foffset = 0;
834 mask = saved = 0;
835 if (TARGET_HARD_FLOAT)
836 {
837 /* Interrupt thread does not need to save any register. */
838 if (!interrupt_thread)
839 for (regno = 16; regno < 24; regno++)
840 if (m68k_save_reg (regno, interrupt_handler))
841 {
842 mask |= 1 << (regno - FP0_REG);
843 saved++;
844 }
845 current_frame.foffset = saved * TARGET_FP_REG_SIZE;
846 current_frame.offset += current_frame.foffset;
847 }
848 current_frame.fpu_no = saved;
849 current_frame.fpu_mask = mask;
850
851 /* Remember what function this frame refers to. */
852 current_frame.funcdef_no = current_function_funcdef_no;
853 }
854
855 /* Worker function for TARGET_CAN_ELIMINATE. */
856
857 bool
m68k_can_eliminate(const int from ATTRIBUTE_UNUSED,const int to)858 m68k_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
859 {
860 return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true);
861 }
862
863 HOST_WIDE_INT
m68k_initial_elimination_offset(int from,int to)864 m68k_initial_elimination_offset (int from, int to)
865 {
866 int argptr_offset;
867 /* The arg pointer points 8 bytes before the start of the arguments,
868 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
869 frame pointer in most frames. */
870 argptr_offset = frame_pointer_needed ? 0 : UNITS_PER_WORD;
871 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
872 return argptr_offset;
873
874 m68k_compute_frame_layout ();
875
876 gcc_assert (to == STACK_POINTER_REGNUM);
877 switch (from)
878 {
879 case ARG_POINTER_REGNUM:
880 return current_frame.offset + current_frame.size - argptr_offset;
881 case FRAME_POINTER_REGNUM:
882 return current_frame.offset + current_frame.size;
883 default:
884 gcc_unreachable ();
885 }
886 }
887
888 /* Refer to the array `regs_ever_live' to determine which registers
889 to save; `regs_ever_live[I]' is nonzero if register number I
890 is ever used in the function. This function is responsible for
891 knowing which registers should not be saved even if used.
892 Return true if we need to save REGNO. */
893
894 static bool
m68k_save_reg(unsigned int regno,bool interrupt_handler)895 m68k_save_reg (unsigned int regno, bool interrupt_handler)
896 {
897 if (flag_pic && regno == PIC_REG)
898 {
899 if (crtl->saves_all_registers)
900 return true;
901 if (crtl->uses_pic_offset_table)
902 return true;
903 /* Reload may introduce constant pool references into a function
904 that thitherto didn't need a PIC register. Note that the test
905 above will not catch that case because we will only set
906 crtl->uses_pic_offset_table when emitting
907 the address reloads. */
908 if (crtl->uses_const_pool)
909 return true;
910 }
911
912 if (crtl->calls_eh_return)
913 {
914 unsigned int i;
915 for (i = 0; ; i++)
916 {
917 unsigned int test = EH_RETURN_DATA_REGNO (i);
918 if (test == INVALID_REGNUM)
919 break;
920 if (test == regno)
921 return true;
922 }
923 }
924
925 /* Fixed regs we never touch. */
926 if (fixed_regs[regno])
927 return false;
928
929 /* The frame pointer (if it is such) is handled specially. */
930 if (regno == FRAME_POINTER_REGNUM && frame_pointer_needed)
931 return false;
932
933 /* Interrupt handlers must also save call_used_regs
934 if they are live or when calling nested functions. */
935 if (interrupt_handler)
936 {
937 if (df_regs_ever_live_p (regno))
938 return true;
939
940 if (!crtl->is_leaf && call_used_regs[regno])
941 return true;
942 }
943
944 /* Never need to save registers that aren't touched. */
945 if (!df_regs_ever_live_p (regno))
946 return false;
947
948 /* Otherwise save everything that isn't call-clobbered. */
949 return !call_used_regs[regno];
950 }
951
952 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
953 the lowest memory address. COUNT is the number of registers to be
954 moved, with register REGNO + I being moved if bit I of MASK is set.
955 STORE_P specifies the direction of the move and ADJUST_STACK_P says
956 whether or not this is pre-decrement (if STORE_P) or post-increment
957 (if !STORE_P) operation. */
958
959 static rtx_insn *
m68k_emit_movem(rtx base,HOST_WIDE_INT offset,unsigned int count,unsigned int regno,unsigned int mask,bool store_p,bool adjust_stack_p)960 m68k_emit_movem (rtx base, HOST_WIDE_INT offset,
961 unsigned int count, unsigned int regno,
962 unsigned int mask, bool store_p, bool adjust_stack_p)
963 {
964 int i;
965 rtx body, addr, src, operands[2];
966 machine_mode mode;
967
968 body = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (adjust_stack_p + count));
969 mode = reg_raw_mode[regno];
970 i = 0;
971
972 if (adjust_stack_p)
973 {
974 src = plus_constant (Pmode, base,
975 (count
976 * GET_MODE_SIZE (mode)
977 * (HOST_WIDE_INT) (store_p ? -1 : 1)));
978 XVECEXP (body, 0, i++) = gen_rtx_SET (base, src);
979 }
980
981 for (; mask != 0; mask >>= 1, regno++)
982 if (mask & 1)
983 {
984 addr = plus_constant (Pmode, base, offset);
985 operands[!store_p] = gen_frame_mem (mode, addr);
986 operands[store_p] = gen_rtx_REG (mode, regno);
987 XVECEXP (body, 0, i++)
988 = gen_rtx_SET (operands[0], operands[1]);
989 offset += GET_MODE_SIZE (mode);
990 }
991 gcc_assert (i == XVECLEN (body, 0));
992
993 return emit_insn (body);
994 }
995
996 /* Make INSN a frame-related instruction. */
997
998 static void
m68k_set_frame_related(rtx_insn * insn)999 m68k_set_frame_related (rtx_insn *insn)
1000 {
1001 rtx body;
1002 int i;
1003
1004 RTX_FRAME_RELATED_P (insn) = 1;
1005 body = PATTERN (insn);
1006 if (GET_CODE (body) == PARALLEL)
1007 for (i = 0; i < XVECLEN (body, 0); i++)
1008 RTX_FRAME_RELATED_P (XVECEXP (body, 0, i)) = 1;
1009 }
1010
1011 /* Emit RTL for the "prologue" define_expand. */
1012
1013 void
m68k_expand_prologue(void)1014 m68k_expand_prologue (void)
1015 {
1016 HOST_WIDE_INT fsize_with_regs;
1017 rtx limit, src, dest;
1018
1019 m68k_compute_frame_layout ();
1020
1021 if (flag_stack_usage_info)
1022 current_function_static_stack_size
1023 = current_frame.size + current_frame.offset;
1024
1025 /* If the stack limit is a symbol, we can check it here,
1026 before actually allocating the space. */
1027 if (crtl->limit_stack
1028 && GET_CODE (stack_limit_rtx) == SYMBOL_REF)
1029 {
1030 limit = plus_constant (Pmode, stack_limit_rtx, current_frame.size + 4);
1031 if (!m68k_legitimate_constant_p (Pmode, limit))
1032 {
1033 emit_move_insn (gen_rtx_REG (Pmode, D0_REG), limit);
1034 limit = gen_rtx_REG (Pmode, D0_REG);
1035 }
1036 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode,
1037 stack_pointer_rtx, limit),
1038 stack_pointer_rtx, limit,
1039 const1_rtx));
1040 }
1041
1042 fsize_with_regs = current_frame.size;
1043 if (TARGET_COLDFIRE)
1044 {
1045 /* ColdFire's move multiple instructions do not allow pre-decrement
1046 addressing. Add the size of movem saves to the initial stack
1047 allocation instead. */
1048 if (current_frame.reg_no >= MIN_MOVEM_REGS)
1049 fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode);
1050 if (current_frame.fpu_no >= MIN_FMOVEM_REGS)
1051 fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode);
1052 }
1053
1054 if (frame_pointer_needed)
1055 {
1056 if (fsize_with_regs == 0 && TUNE_68040)
1057 {
1058 /* On the 68040, two separate moves are faster than link.w 0. */
1059 dest = gen_frame_mem (Pmode,
1060 gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
1061 m68k_set_frame_related (emit_move_insn (dest, frame_pointer_rtx));
1062 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx,
1063 stack_pointer_rtx));
1064 }
1065 else if (fsize_with_regs < 0x8000 || TARGET_68020)
1066 m68k_set_frame_related
1067 (emit_insn (gen_link (frame_pointer_rtx,
1068 GEN_INT (-4 - fsize_with_regs))));
1069 else
1070 {
1071 m68k_set_frame_related
1072 (emit_insn (gen_link (frame_pointer_rtx, GEN_INT (-4))));
1073 m68k_set_frame_related
1074 (emit_insn (gen_addsi3 (stack_pointer_rtx,
1075 stack_pointer_rtx,
1076 GEN_INT (-fsize_with_regs))));
1077 }
1078
1079 /* If the frame pointer is needed, emit a special barrier that
1080 will prevent the scheduler from moving stores to the frame
1081 before the stack adjustment. */
1082 emit_insn (gen_stack_tie (stack_pointer_rtx, frame_pointer_rtx));
1083 }
1084 else if (fsize_with_regs != 0)
1085 m68k_set_frame_related
1086 (emit_insn (gen_addsi3 (stack_pointer_rtx,
1087 stack_pointer_rtx,
1088 GEN_INT (-fsize_with_regs))));
1089
1090 if (current_frame.fpu_mask)
1091 {
1092 gcc_assert (current_frame.fpu_no >= MIN_FMOVEM_REGS);
1093 if (TARGET_68881)
1094 m68k_set_frame_related
1095 (m68k_emit_movem (stack_pointer_rtx,
1096 current_frame.fpu_no * -GET_MODE_SIZE (XFmode),
1097 current_frame.fpu_no, FP0_REG,
1098 current_frame.fpu_mask, true, true));
1099 else
1100 {
1101 int offset;
1102
1103 /* If we're using moveml to save the integer registers,
1104 the stack pointer will point to the bottom of the moveml
1105 save area. Find the stack offset of the first FP register. */
1106 if (current_frame.reg_no < MIN_MOVEM_REGS)
1107 offset = 0;
1108 else
1109 offset = current_frame.reg_no * GET_MODE_SIZE (SImode);
1110 m68k_set_frame_related
1111 (m68k_emit_movem (stack_pointer_rtx, offset,
1112 current_frame.fpu_no, FP0_REG,
1113 current_frame.fpu_mask, true, false));
1114 }
1115 }
1116
1117 /* If the stack limit is not a symbol, check it here.
1118 This has the disadvantage that it may be too late... */
1119 if (crtl->limit_stack)
1120 {
1121 if (REG_P (stack_limit_rtx))
1122 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode, stack_pointer_rtx,
1123 stack_limit_rtx),
1124 stack_pointer_rtx, stack_limit_rtx,
1125 const1_rtx));
1126
1127 else if (GET_CODE (stack_limit_rtx) != SYMBOL_REF)
1128 warning (0, "stack limit expression is not supported");
1129 }
1130
1131 if (current_frame.reg_no < MIN_MOVEM_REGS)
1132 {
1133 /* Store each register separately in the same order moveml does. */
1134 int i;
1135
1136 for (i = 16; i-- > 0; )
1137 if (current_frame.reg_mask & (1 << i))
1138 {
1139 src = gen_rtx_REG (SImode, D0_REG + i);
1140 dest = gen_frame_mem (SImode,
1141 gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
1142 m68k_set_frame_related (emit_insn (gen_movsi (dest, src)));
1143 }
1144 }
1145 else
1146 {
1147 if (TARGET_COLDFIRE)
1148 /* The required register save space has already been allocated.
1149 The first register should be stored at (%sp). */
1150 m68k_set_frame_related
1151 (m68k_emit_movem (stack_pointer_rtx, 0,
1152 current_frame.reg_no, D0_REG,
1153 current_frame.reg_mask, true, false));
1154 else
1155 m68k_set_frame_related
1156 (m68k_emit_movem (stack_pointer_rtx,
1157 current_frame.reg_no * -GET_MODE_SIZE (SImode),
1158 current_frame.reg_no, D0_REG,
1159 current_frame.reg_mask, true, true));
1160 }
1161
1162 if (!TARGET_SEP_DATA
1163 && crtl->uses_pic_offset_table)
1164 emit_insn (gen_load_got (pic_offset_table_rtx));
1165 }
1166
1167 /* Return true if a simple (return) instruction is sufficient for this
1168 instruction (i.e. if no epilogue is needed). */
1169
1170 bool
m68k_use_return_insn(void)1171 m68k_use_return_insn (void)
1172 {
1173 if (!reload_completed || frame_pointer_needed || get_frame_size () != 0)
1174 return false;
1175
1176 m68k_compute_frame_layout ();
1177 return current_frame.offset == 0;
1178 }
1179
1180 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1181 SIBCALL_P says which.
1182
1183 The function epilogue should not depend on the current stack pointer!
1184 It should use the frame pointer only, if there is a frame pointer.
1185 This is mandatory because of alloca; we also take advantage of it to
1186 omit stack adjustments before returning. */
1187
1188 void
m68k_expand_epilogue(bool sibcall_p)1189 m68k_expand_epilogue (bool sibcall_p)
1190 {
1191 HOST_WIDE_INT fsize, fsize_with_regs;
1192 bool big, restore_from_sp;
1193
1194 m68k_compute_frame_layout ();
1195
1196 fsize = current_frame.size;
1197 big = false;
1198 restore_from_sp = false;
1199
1200 /* FIXME : crtl->is_leaf below is too strong.
1201 What we really need to know there is if there could be pending
1202 stack adjustment needed at that point. */
1203 restore_from_sp = (!frame_pointer_needed
1204 || (!cfun->calls_alloca && crtl->is_leaf));
1205
1206 /* fsize_with_regs is the size we need to adjust the sp when
1207 popping the frame. */
1208 fsize_with_regs = fsize;
1209 if (TARGET_COLDFIRE && restore_from_sp)
1210 {
1211 /* ColdFire's move multiple instructions do not allow post-increment
1212 addressing. Add the size of movem loads to the final deallocation
1213 instead. */
1214 if (current_frame.reg_no >= MIN_MOVEM_REGS)
1215 fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode);
1216 if (current_frame.fpu_no >= MIN_FMOVEM_REGS)
1217 fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode);
1218 }
1219
1220 if (current_frame.offset + fsize >= 0x8000
1221 && !restore_from_sp
1222 && (current_frame.reg_mask || current_frame.fpu_mask))
1223 {
1224 if (TARGET_COLDFIRE
1225 && (current_frame.reg_no >= MIN_MOVEM_REGS
1226 || current_frame.fpu_no >= MIN_FMOVEM_REGS))
1227 {
1228 /* ColdFire's move multiple instructions do not support the
1229 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1230 stack-based restore. */
1231 emit_move_insn (gen_rtx_REG (Pmode, A1_REG),
1232 GEN_INT (-(current_frame.offset + fsize)));
1233 emit_insn (gen_blockage ());
1234 emit_insn (gen_addsi3 (stack_pointer_rtx,
1235 gen_rtx_REG (Pmode, A1_REG),
1236 frame_pointer_rtx));
1237 restore_from_sp = true;
1238 }
1239 else
1240 {
1241 emit_move_insn (gen_rtx_REG (Pmode, A1_REG), GEN_INT (-fsize));
1242 fsize = 0;
1243 big = true;
1244 }
1245 }
1246
1247 if (current_frame.reg_no < MIN_MOVEM_REGS)
1248 {
1249 /* Restore each register separately in the same order moveml does. */
1250 int i;
1251 HOST_WIDE_INT offset;
1252
1253 offset = current_frame.offset + fsize;
1254 for (i = 0; i < 16; i++)
1255 if (current_frame.reg_mask & (1 << i))
1256 {
1257 rtx addr;
1258
1259 if (big)
1260 {
1261 /* Generate the address -OFFSET(%fp,%a1.l). */
1262 addr = gen_rtx_REG (Pmode, A1_REG);
1263 addr = gen_rtx_PLUS (Pmode, addr, frame_pointer_rtx);
1264 addr = plus_constant (Pmode, addr, -offset);
1265 }
1266 else if (restore_from_sp)
1267 addr = gen_rtx_POST_INC (Pmode, stack_pointer_rtx);
1268 else
1269 addr = plus_constant (Pmode, frame_pointer_rtx, -offset);
1270 emit_move_insn (gen_rtx_REG (SImode, D0_REG + i),
1271 gen_frame_mem (SImode, addr));
1272 offset -= GET_MODE_SIZE (SImode);
1273 }
1274 }
1275 else if (current_frame.reg_mask)
1276 {
1277 if (big)
1278 m68k_emit_movem (gen_rtx_PLUS (Pmode,
1279 gen_rtx_REG (Pmode, A1_REG),
1280 frame_pointer_rtx),
1281 -(current_frame.offset + fsize),
1282 current_frame.reg_no, D0_REG,
1283 current_frame.reg_mask, false, false);
1284 else if (restore_from_sp)
1285 m68k_emit_movem (stack_pointer_rtx, 0,
1286 current_frame.reg_no, D0_REG,
1287 current_frame.reg_mask, false,
1288 !TARGET_COLDFIRE);
1289 else
1290 m68k_emit_movem (frame_pointer_rtx,
1291 -(current_frame.offset + fsize),
1292 current_frame.reg_no, D0_REG,
1293 current_frame.reg_mask, false, false);
1294 }
1295
1296 if (current_frame.fpu_no > 0)
1297 {
1298 if (big)
1299 m68k_emit_movem (gen_rtx_PLUS (Pmode,
1300 gen_rtx_REG (Pmode, A1_REG),
1301 frame_pointer_rtx),
1302 -(current_frame.foffset + fsize),
1303 current_frame.fpu_no, FP0_REG,
1304 current_frame.fpu_mask, false, false);
1305 else if (restore_from_sp)
1306 {
1307 if (TARGET_COLDFIRE)
1308 {
1309 int offset;
1310
1311 /* If we used moveml to restore the integer registers, the
1312 stack pointer will still point to the bottom of the moveml
1313 save area. Find the stack offset of the first FP
1314 register. */
1315 if (current_frame.reg_no < MIN_MOVEM_REGS)
1316 offset = 0;
1317 else
1318 offset = current_frame.reg_no * GET_MODE_SIZE (SImode);
1319 m68k_emit_movem (stack_pointer_rtx, offset,
1320 current_frame.fpu_no, FP0_REG,
1321 current_frame.fpu_mask, false, false);
1322 }
1323 else
1324 m68k_emit_movem (stack_pointer_rtx, 0,
1325 current_frame.fpu_no, FP0_REG,
1326 current_frame.fpu_mask, false, true);
1327 }
1328 else
1329 m68k_emit_movem (frame_pointer_rtx,
1330 -(current_frame.foffset + fsize),
1331 current_frame.fpu_no, FP0_REG,
1332 current_frame.fpu_mask, false, false);
1333 }
1334
1335 emit_insn (gen_blockage ());
1336 if (frame_pointer_needed)
1337 emit_insn (gen_unlink (frame_pointer_rtx));
1338 else if (fsize_with_regs)
1339 emit_insn (gen_addsi3 (stack_pointer_rtx,
1340 stack_pointer_rtx,
1341 GEN_INT (fsize_with_regs)));
1342
1343 if (crtl->calls_eh_return)
1344 emit_insn (gen_addsi3 (stack_pointer_rtx,
1345 stack_pointer_rtx,
1346 EH_RETURN_STACKADJ_RTX));
1347
1348 if (!sibcall_p)
1349 emit_jump_insn (ret_rtx);
1350 }
1351
1352 /* Return true if X is a valid comparison operator for the dbcc
1353 instruction.
1354
1355 Note it rejects floating point comparison operators.
1356 (In the future we could use Fdbcc).
1357
1358 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1359
1360 int
valid_dbcc_comparison_p_2(rtx x,machine_mode mode ATTRIBUTE_UNUSED)1361 valid_dbcc_comparison_p_2 (rtx x, machine_mode mode ATTRIBUTE_UNUSED)
1362 {
1363 switch (GET_CODE (x))
1364 {
1365 case EQ: case NE: case GTU: case LTU:
1366 case GEU: case LEU:
1367 return 1;
1368
1369 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1370 conservative */
1371 case GT: case LT: case GE: case LE:
1372 return ! (cc_prev_status.flags & CC_NO_OVERFLOW);
1373 default:
1374 return 0;
1375 }
1376 }
1377
1378 /* Return nonzero if flags are currently in the 68881 flag register. */
1379 int
flags_in_68881(void)1380 flags_in_68881 (void)
1381 {
1382 /* We could add support for these in the future */
1383 return cc_status.flags & CC_IN_68881;
1384 }
1385
1386 /* Return true if PARALLEL contains register REGNO. */
1387 static bool
m68k_reg_present_p(const_rtx parallel,unsigned int regno)1388 m68k_reg_present_p (const_rtx parallel, unsigned int regno)
1389 {
1390 int i;
1391
1392 if (REG_P (parallel) && REGNO (parallel) == regno)
1393 return true;
1394
1395 if (GET_CODE (parallel) != PARALLEL)
1396 return false;
1397
1398 for (i = 0; i < XVECLEN (parallel, 0); ++i)
1399 {
1400 const_rtx x;
1401
1402 x = XEXP (XVECEXP (parallel, 0, i), 0);
1403 if (REG_P (x) && REGNO (x) == regno)
1404 return true;
1405 }
1406
1407 return false;
1408 }
1409
1410 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1411
1412 static bool
m68k_ok_for_sibcall_p(tree decl,tree exp)1413 m68k_ok_for_sibcall_p (tree decl, tree exp)
1414 {
1415 enum m68k_function_kind kind;
1416
1417 /* We cannot use sibcalls for nested functions because we use the
1418 static chain register for indirect calls. */
1419 if (CALL_EXPR_STATIC_CHAIN (exp))
1420 return false;
1421
1422 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
1423 {
1424 /* Check that the return value locations are the same. For
1425 example that we aren't returning a value from the sibling in
1426 a D0 register but then need to transfer it to a A0 register. */
1427 rtx cfun_value;
1428 rtx call_value;
1429
1430 cfun_value = FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun->decl)),
1431 cfun->decl);
1432 call_value = FUNCTION_VALUE (TREE_TYPE (exp), decl);
1433
1434 /* Check that the values are equal or that the result the callee
1435 function returns is superset of what the current function returns. */
1436 if (!(rtx_equal_p (cfun_value, call_value)
1437 || (REG_P (cfun_value)
1438 && m68k_reg_present_p (call_value, REGNO (cfun_value)))))
1439 return false;
1440 }
1441
1442 kind = m68k_get_function_kind (current_function_decl);
1443 if (kind == m68k_fk_normal_function)
1444 /* We can always sibcall from a normal function, because it's
1445 undefined if it is calling an interrupt function. */
1446 return true;
1447
1448 /* Otherwise we can only sibcall if the function kind is known to be
1449 the same. */
1450 if (decl && m68k_get_function_kind (decl) == kind)
1451 return true;
1452
1453 return false;
1454 }
1455
1456 /* On the m68k all args are always pushed. */
1457
1458 static rtx
m68k_function_arg(cumulative_args_t cum ATTRIBUTE_UNUSED,machine_mode mode ATTRIBUTE_UNUSED,const_tree type ATTRIBUTE_UNUSED,bool named ATTRIBUTE_UNUSED)1459 m68k_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED,
1460 machine_mode mode ATTRIBUTE_UNUSED,
1461 const_tree type ATTRIBUTE_UNUSED,
1462 bool named ATTRIBUTE_UNUSED)
1463 {
1464 return NULL_RTX;
1465 }
1466
1467 static void
m68k_function_arg_advance(cumulative_args_t cum_v,machine_mode mode,const_tree type,bool named ATTRIBUTE_UNUSED)1468 m68k_function_arg_advance (cumulative_args_t cum_v, machine_mode mode,
1469 const_tree type, bool named ATTRIBUTE_UNUSED)
1470 {
1471 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1472
1473 *cum += (mode != BLKmode
1474 ? (GET_MODE_SIZE (mode) + 3) & ~3
1475 : (int_size_in_bytes (type) + 3) & ~3);
1476 }
1477
1478 /* Convert X to a legitimate function call memory reference and return the
1479 result. */
1480
1481 rtx
m68k_legitimize_call_address(rtx x)1482 m68k_legitimize_call_address (rtx x)
1483 {
1484 gcc_assert (MEM_P (x));
1485 if (call_operand (XEXP (x, 0), VOIDmode))
1486 return x;
1487 return replace_equiv_address (x, force_reg (Pmode, XEXP (x, 0)));
1488 }
1489
1490 /* Likewise for sibling calls. */
1491
1492 rtx
m68k_legitimize_sibcall_address(rtx x)1493 m68k_legitimize_sibcall_address (rtx x)
1494 {
1495 gcc_assert (MEM_P (x));
1496 if (sibcall_operand (XEXP (x, 0), VOIDmode))
1497 return x;
1498
1499 emit_move_insn (gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM), XEXP (x, 0));
1500 return replace_equiv_address (x, gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM));
1501 }
1502
1503 /* Convert X to a legitimate address and return it if successful. Otherwise
1504 return X.
1505
1506 For the 68000, we handle X+REG by loading X into a register R and
1507 using R+REG. R will go in an address reg and indexing will be used.
1508 However, if REG is a broken-out memory address or multiplication,
1509 nothing needs to be done because REG can certainly go in an address reg. */
1510
1511 static rtx
m68k_legitimize_address(rtx x,rtx oldx,machine_mode mode)1512 m68k_legitimize_address (rtx x, rtx oldx, machine_mode mode)
1513 {
1514 if (m68k_tls_symbol_p (x))
1515 return m68k_legitimize_tls_address (x);
1516
1517 if (GET_CODE (x) == PLUS)
1518 {
1519 int ch = (x) != (oldx);
1520 int copied = 0;
1521
1522 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1523
1524 if (GET_CODE (XEXP (x, 0)) == MULT)
1525 {
1526 COPY_ONCE (x);
1527 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
1528 }
1529 if (GET_CODE (XEXP (x, 1)) == MULT)
1530 {
1531 COPY_ONCE (x);
1532 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
1533 }
1534 if (ch)
1535 {
1536 if (GET_CODE (XEXP (x, 1)) == REG
1537 && GET_CODE (XEXP (x, 0)) == REG)
1538 {
1539 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT)
1540 {
1541 COPY_ONCE (x);
1542 x = force_operand (x, 0);
1543 }
1544 return x;
1545 }
1546 if (memory_address_p (mode, x))
1547 return x;
1548 }
1549 if (GET_CODE (XEXP (x, 0)) == REG
1550 || (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
1551 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
1552 && GET_MODE (XEXP (XEXP (x, 0), 0)) == HImode))
1553 {
1554 rtx temp = gen_reg_rtx (Pmode);
1555 rtx val = force_operand (XEXP (x, 1), 0);
1556 emit_move_insn (temp, val);
1557 COPY_ONCE (x);
1558 XEXP (x, 1) = temp;
1559 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT
1560 && GET_CODE (XEXP (x, 0)) == REG)
1561 x = force_operand (x, 0);
1562 }
1563 else if (GET_CODE (XEXP (x, 1)) == REG
1564 || (GET_CODE (XEXP (x, 1)) == SIGN_EXTEND
1565 && GET_CODE (XEXP (XEXP (x, 1), 0)) == REG
1566 && GET_MODE (XEXP (XEXP (x, 1), 0)) == HImode))
1567 {
1568 rtx temp = gen_reg_rtx (Pmode);
1569 rtx val = force_operand (XEXP (x, 0), 0);
1570 emit_move_insn (temp, val);
1571 COPY_ONCE (x);
1572 XEXP (x, 0) = temp;
1573 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT
1574 && GET_CODE (XEXP (x, 1)) == REG)
1575 x = force_operand (x, 0);
1576 }
1577 }
1578
1579 return x;
1580 }
1581
1582
1583 /* Output a dbCC; jCC sequence. Note we do not handle the
1584 floating point version of this sequence (Fdbcc). We also
1585 do not handle alternative conditions when CC_NO_OVERFLOW is
1586 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1587 kick those out before we get here. */
1588
1589 void
output_dbcc_and_branch(rtx * operands)1590 output_dbcc_and_branch (rtx *operands)
1591 {
1592 switch (GET_CODE (operands[3]))
1593 {
1594 case EQ:
1595 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands);
1596 break;
1597
1598 case NE:
1599 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands);
1600 break;
1601
1602 case GT:
1603 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands);
1604 break;
1605
1606 case GTU:
1607 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands);
1608 break;
1609
1610 case LT:
1611 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands);
1612 break;
1613
1614 case LTU:
1615 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands);
1616 break;
1617
1618 case GE:
1619 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands);
1620 break;
1621
1622 case GEU:
1623 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands);
1624 break;
1625
1626 case LE:
1627 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands);
1628 break;
1629
1630 case LEU:
1631 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands);
1632 break;
1633
1634 default:
1635 gcc_unreachable ();
1636 }
1637
1638 /* If the decrement is to be done in SImode, then we have
1639 to compensate for the fact that dbcc decrements in HImode. */
1640 switch (GET_MODE (operands[0]))
1641 {
1642 case E_SImode:
1643 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands);
1644 break;
1645
1646 case E_HImode:
1647 break;
1648
1649 default:
1650 gcc_unreachable ();
1651 }
1652 }
1653
1654 const char *
output_scc_di(rtx op,rtx operand1,rtx operand2,rtx dest)1655 output_scc_di (rtx op, rtx operand1, rtx operand2, rtx dest)
1656 {
1657 rtx loperands[7];
1658 enum rtx_code op_code = GET_CODE (op);
1659
1660 /* This does not produce a useful cc. */
1661 CC_STATUS_INIT;
1662
1663 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1664 below. Swap the operands and change the op if these requirements
1665 are not fulfilled. */
1666 if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG)
1667 {
1668 rtx tmp = operand1;
1669
1670 operand1 = operand2;
1671 operand2 = tmp;
1672 op_code = swap_condition (op_code);
1673 }
1674 loperands[0] = operand1;
1675 if (GET_CODE (operand1) == REG)
1676 loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1);
1677 else
1678 loperands[1] = adjust_address (operand1, SImode, 4);
1679 if (operand2 != const0_rtx)
1680 {
1681 loperands[2] = operand2;
1682 if (GET_CODE (operand2) == REG)
1683 loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1);
1684 else
1685 loperands[3] = adjust_address (operand2, SImode, 4);
1686 }
1687 loperands[4] = gen_label_rtx ();
1688 if (operand2 != const0_rtx)
1689 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands);
1690 else
1691 {
1692 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[0]))
1693 output_asm_insn ("tst%.l %0", loperands);
1694 else
1695 output_asm_insn ("cmp%.w #0,%0", loperands);
1696
1697 output_asm_insn ("jne %l4", loperands);
1698
1699 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[1]))
1700 output_asm_insn ("tst%.l %1", loperands);
1701 else
1702 output_asm_insn ("cmp%.w #0,%1", loperands);
1703 }
1704
1705 loperands[5] = dest;
1706
1707 switch (op_code)
1708 {
1709 case EQ:
1710 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1711 CODE_LABEL_NUMBER (loperands[4]));
1712 output_asm_insn ("seq %5", loperands);
1713 break;
1714
1715 case NE:
1716 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1717 CODE_LABEL_NUMBER (loperands[4]));
1718 output_asm_insn ("sne %5", loperands);
1719 break;
1720
1721 case GT:
1722 loperands[6] = gen_label_rtx ();
1723 output_asm_insn ("shi %5\n\tjra %l6", loperands);
1724 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1725 CODE_LABEL_NUMBER (loperands[4]));
1726 output_asm_insn ("sgt %5", loperands);
1727 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1728 CODE_LABEL_NUMBER (loperands[6]));
1729 break;
1730
1731 case GTU:
1732 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1733 CODE_LABEL_NUMBER (loperands[4]));
1734 output_asm_insn ("shi %5", loperands);
1735 break;
1736
1737 case LT:
1738 loperands[6] = gen_label_rtx ();
1739 output_asm_insn ("scs %5\n\tjra %l6", loperands);
1740 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1741 CODE_LABEL_NUMBER (loperands[4]));
1742 output_asm_insn ("slt %5", loperands);
1743 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1744 CODE_LABEL_NUMBER (loperands[6]));
1745 break;
1746
1747 case LTU:
1748 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1749 CODE_LABEL_NUMBER (loperands[4]));
1750 output_asm_insn ("scs %5", loperands);
1751 break;
1752
1753 case GE:
1754 loperands[6] = gen_label_rtx ();
1755 output_asm_insn ("scc %5\n\tjra %l6", loperands);
1756 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1757 CODE_LABEL_NUMBER (loperands[4]));
1758 output_asm_insn ("sge %5", loperands);
1759 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1760 CODE_LABEL_NUMBER (loperands[6]));
1761 break;
1762
1763 case GEU:
1764 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1765 CODE_LABEL_NUMBER (loperands[4]));
1766 output_asm_insn ("scc %5", loperands);
1767 break;
1768
1769 case LE:
1770 loperands[6] = gen_label_rtx ();
1771 output_asm_insn ("sls %5\n\tjra %l6", loperands);
1772 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1773 CODE_LABEL_NUMBER (loperands[4]));
1774 output_asm_insn ("sle %5", loperands);
1775 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1776 CODE_LABEL_NUMBER (loperands[6]));
1777 break;
1778
1779 case LEU:
1780 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1781 CODE_LABEL_NUMBER (loperands[4]));
1782 output_asm_insn ("sls %5", loperands);
1783 break;
1784
1785 default:
1786 gcc_unreachable ();
1787 }
1788 return "";
1789 }
1790
1791 const char *
output_btst(rtx * operands,rtx countop,rtx dataop,rtx_insn * insn,int signpos)1792 output_btst (rtx *operands, rtx countop, rtx dataop, rtx_insn *insn, int signpos)
1793 {
1794 operands[0] = countop;
1795 operands[1] = dataop;
1796
1797 if (GET_CODE (countop) == CONST_INT)
1798 {
1799 register int count = INTVAL (countop);
1800 /* If COUNT is bigger than size of storage unit in use,
1801 advance to the containing unit of same size. */
1802 if (count > signpos)
1803 {
1804 int offset = (count & ~signpos) / 8;
1805 count = count & signpos;
1806 operands[1] = dataop = adjust_address (dataop, QImode, offset);
1807 }
1808 if (count == signpos)
1809 cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N;
1810 else
1811 cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N;
1812
1813 /* These three statements used to use next_insns_test_no...
1814 but it appears that this should do the same job. */
1815 if (count == 31
1816 && next_insn_tests_no_inequality (insn))
1817 return "tst%.l %1";
1818 if (count == 15
1819 && next_insn_tests_no_inequality (insn))
1820 return "tst%.w %1";
1821 if (count == 7
1822 && next_insn_tests_no_inequality (insn))
1823 return "tst%.b %1";
1824 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1825 On some m68k variants unfortunately that's slower than btst.
1826 On 68000 and higher, that should also work for all HImode operands. */
1827 if (TUNE_CPU32 || TARGET_COLDFIRE || optimize_size)
1828 {
1829 if (count == 3 && DATA_REG_P (operands[1])
1830 && next_insn_tests_no_inequality (insn))
1831 {
1832 cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N | CC_NO_OVERFLOW;
1833 return "move%.w %1,%%ccr";
1834 }
1835 if (count == 2 && DATA_REG_P (operands[1])
1836 && next_insn_tests_no_inequality (insn))
1837 {
1838 cc_status.flags = CC_NOT_NEGATIVE | CC_INVERTED | CC_NO_OVERFLOW;
1839 return "move%.w %1,%%ccr";
1840 }
1841 /* count == 1 followed by bvc/bvs and
1842 count == 0 followed by bcc/bcs are also possible, but need
1843 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1844 }
1845
1846 cc_status.flags = CC_NOT_NEGATIVE;
1847 }
1848 return "btst %0,%1";
1849 }
1850
1851 /* Return true if X is a legitimate base register. STRICT_P says
1852 whether we need strict checking. */
1853
1854 bool
m68k_legitimate_base_reg_p(rtx x,bool strict_p)1855 m68k_legitimate_base_reg_p (rtx x, bool strict_p)
1856 {
1857 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1858 if (!strict_p && GET_CODE (x) == SUBREG)
1859 x = SUBREG_REG (x);
1860
1861 return (REG_P (x)
1862 && (strict_p
1863 ? REGNO_OK_FOR_BASE_P (REGNO (x))
1864 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x))));
1865 }
1866
1867 /* Return true if X is a legitimate index register. STRICT_P says
1868 whether we need strict checking. */
1869
1870 bool
m68k_legitimate_index_reg_p(rtx x,bool strict_p)1871 m68k_legitimate_index_reg_p (rtx x, bool strict_p)
1872 {
1873 if (!strict_p && GET_CODE (x) == SUBREG)
1874 x = SUBREG_REG (x);
1875
1876 return (REG_P (x)
1877 && (strict_p
1878 ? REGNO_OK_FOR_INDEX_P (REGNO (x))
1879 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x))));
1880 }
1881
1882 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1883 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1884 ADDRESS if so. STRICT_P says whether we need strict checking. */
1885
1886 static bool
m68k_decompose_index(rtx x,bool strict_p,struct m68k_address * address)1887 m68k_decompose_index (rtx x, bool strict_p, struct m68k_address *address)
1888 {
1889 int scale;
1890
1891 /* Check for a scale factor. */
1892 scale = 1;
1893 if ((TARGET_68020 || TARGET_COLDFIRE)
1894 && GET_CODE (x) == MULT
1895 && GET_CODE (XEXP (x, 1)) == CONST_INT
1896 && (INTVAL (XEXP (x, 1)) == 2
1897 || INTVAL (XEXP (x, 1)) == 4
1898 || (INTVAL (XEXP (x, 1)) == 8
1899 && (TARGET_COLDFIRE_FPU || !TARGET_COLDFIRE))))
1900 {
1901 scale = INTVAL (XEXP (x, 1));
1902 x = XEXP (x, 0);
1903 }
1904
1905 /* Check for a word extension. */
1906 if (!TARGET_COLDFIRE
1907 && GET_CODE (x) == SIGN_EXTEND
1908 && GET_MODE (XEXP (x, 0)) == HImode)
1909 x = XEXP (x, 0);
1910
1911 if (m68k_legitimate_index_reg_p (x, strict_p))
1912 {
1913 address->scale = scale;
1914 address->index = x;
1915 return true;
1916 }
1917
1918 return false;
1919 }
1920
1921 /* Return true if X is an illegitimate symbolic constant. */
1922
1923 bool
m68k_illegitimate_symbolic_constant_p(rtx x)1924 m68k_illegitimate_symbolic_constant_p (rtx x)
1925 {
1926 rtx base, offset;
1927
1928 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
1929 {
1930 split_const (x, &base, &offset);
1931 if (GET_CODE (base) == SYMBOL_REF
1932 && !offset_within_block_p (base, INTVAL (offset)))
1933 return true;
1934 }
1935 return m68k_tls_reference_p (x, false);
1936 }
1937
1938 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1939
1940 static bool
m68k_cannot_force_const_mem(machine_mode mode ATTRIBUTE_UNUSED,rtx x)1941 m68k_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
1942 {
1943 return m68k_illegitimate_symbolic_constant_p (x);
1944 }
1945
1946 /* Return true if X is a legitimate constant address that can reach
1947 bytes in the range [X, X + REACH). STRICT_P says whether we need
1948 strict checking. */
1949
1950 static bool
m68k_legitimate_constant_address_p(rtx x,unsigned int reach,bool strict_p)1951 m68k_legitimate_constant_address_p (rtx x, unsigned int reach, bool strict_p)
1952 {
1953 rtx base, offset;
1954
1955 if (!CONSTANT_ADDRESS_P (x))
1956 return false;
1957
1958 if (flag_pic
1959 && !(strict_p && TARGET_PCREL)
1960 && symbolic_operand (x, VOIDmode))
1961 return false;
1962
1963 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P && reach > 1)
1964 {
1965 split_const (x, &base, &offset);
1966 if (GET_CODE (base) == SYMBOL_REF
1967 && !offset_within_block_p (base, INTVAL (offset) + reach - 1))
1968 return false;
1969 }
1970
1971 return !m68k_tls_reference_p (x, false);
1972 }
1973
1974 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1975 labels will become jump tables. */
1976
1977 static bool
m68k_jump_table_ref_p(rtx x)1978 m68k_jump_table_ref_p (rtx x)
1979 {
1980 if (GET_CODE (x) != LABEL_REF)
1981 return false;
1982
1983 rtx_insn *insn = as_a <rtx_insn *> (XEXP (x, 0));
1984 if (!NEXT_INSN (insn) && !PREV_INSN (insn))
1985 return true;
1986
1987 insn = next_nonnote_insn (insn);
1988 return insn && JUMP_TABLE_DATA_P (insn);
1989 }
1990
1991 /* Return true if X is a legitimate address for values of mode MODE.
1992 STRICT_P says whether strict checking is needed. If the address
1993 is valid, describe its components in *ADDRESS. */
1994
1995 static bool
m68k_decompose_address(machine_mode mode,rtx x,bool strict_p,struct m68k_address * address)1996 m68k_decompose_address (machine_mode mode, rtx x,
1997 bool strict_p, struct m68k_address *address)
1998 {
1999 unsigned int reach;
2000
2001 memset (address, 0, sizeof (*address));
2002
2003 if (mode == BLKmode)
2004 reach = 1;
2005 else
2006 reach = GET_MODE_SIZE (mode);
2007
2008 /* Check for (An) (mode 2). */
2009 if (m68k_legitimate_base_reg_p (x, strict_p))
2010 {
2011 address->base = x;
2012 return true;
2013 }
2014
2015 /* Check for -(An) and (An)+ (modes 3 and 4). */
2016 if ((GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC)
2017 && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p))
2018 {
2019 address->code = GET_CODE (x);
2020 address->base = XEXP (x, 0);
2021 return true;
2022 }
2023
2024 /* Check for (d16,An) (mode 5). */
2025 if (GET_CODE (x) == PLUS
2026 && GET_CODE (XEXP (x, 1)) == CONST_INT
2027 && IN_RANGE (INTVAL (XEXP (x, 1)), -0x8000, 0x8000 - reach)
2028 && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p))
2029 {
2030 address->base = XEXP (x, 0);
2031 address->offset = XEXP (x, 1);
2032 return true;
2033 }
2034
2035 /* Check for GOT loads. These are (bd,An,Xn) addresses if
2036 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
2037 addresses. */
2038 if (GET_CODE (x) == PLUS
2039 && XEXP (x, 0) == pic_offset_table_rtx)
2040 {
2041 /* As we are processing a PLUS, do not unwrap RELOC32 symbols --
2042 they are invalid in this context. */
2043 if (m68k_unwrap_symbol (XEXP (x, 1), false) != XEXP (x, 1))
2044 {
2045 address->base = XEXP (x, 0);
2046 address->offset = XEXP (x, 1);
2047 return true;
2048 }
2049 }
2050
2051 /* The ColdFire FPU only accepts addressing modes 2-5. */
2052 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT)
2053 return false;
2054
2055 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
2056 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
2057 All these modes are variations of mode 7. */
2058 if (m68k_legitimate_constant_address_p (x, reach, strict_p))
2059 {
2060 address->offset = x;
2061 return true;
2062 }
2063
2064 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
2065 tablejumps.
2066
2067 ??? do_tablejump creates these addresses before placing the target
2068 label, so we have to assume that unplaced labels are jump table
2069 references. It seems unlikely that we would ever generate indexed
2070 accesses to unplaced labels in other cases. */
2071 if (GET_CODE (x) == PLUS
2072 && m68k_jump_table_ref_p (XEXP (x, 1))
2073 && m68k_decompose_index (XEXP (x, 0), strict_p, address))
2074 {
2075 address->offset = XEXP (x, 1);
2076 return true;
2077 }
2078
2079 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
2080 (bd,An,Xn.SIZE*SCALE) addresses. */
2081
2082 if (TARGET_68020)
2083 {
2084 /* Check for a nonzero base displacement. */
2085 if (GET_CODE (x) == PLUS
2086 && m68k_legitimate_constant_address_p (XEXP (x, 1), reach, strict_p))
2087 {
2088 address->offset = XEXP (x, 1);
2089 x = XEXP (x, 0);
2090 }
2091
2092 /* Check for a suppressed index register. */
2093 if (m68k_legitimate_base_reg_p (x, strict_p))
2094 {
2095 address->base = x;
2096 return true;
2097 }
2098
2099 /* Check for a suppressed base register. Do not allow this case
2100 for non-symbolic offsets as it effectively gives gcc freedom
2101 to treat data registers as base registers, which can generate
2102 worse code. */
2103 if (address->offset
2104 && symbolic_operand (address->offset, VOIDmode)
2105 && m68k_decompose_index (x, strict_p, address))
2106 return true;
2107 }
2108 else
2109 {
2110 /* Check for a nonzero base displacement. */
2111 if (GET_CODE (x) == PLUS
2112 && GET_CODE (XEXP (x, 1)) == CONST_INT
2113 && IN_RANGE (INTVAL (XEXP (x, 1)), -0x80, 0x80 - reach))
2114 {
2115 address->offset = XEXP (x, 1);
2116 x = XEXP (x, 0);
2117 }
2118 }
2119
2120 /* We now expect the sum of a base and an index. */
2121 if (GET_CODE (x) == PLUS)
2122 {
2123 if (m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p)
2124 && m68k_decompose_index (XEXP (x, 1), strict_p, address))
2125 {
2126 address->base = XEXP (x, 0);
2127 return true;
2128 }
2129
2130 if (m68k_legitimate_base_reg_p (XEXP (x, 1), strict_p)
2131 && m68k_decompose_index (XEXP (x, 0), strict_p, address))
2132 {
2133 address->base = XEXP (x, 1);
2134 return true;
2135 }
2136 }
2137 return false;
2138 }
2139
2140 /* Return true if X is a legitimate address for values of mode MODE.
2141 STRICT_P says whether strict checking is needed. */
2142
2143 bool
m68k_legitimate_address_p(machine_mode mode,rtx x,bool strict_p)2144 m68k_legitimate_address_p (machine_mode mode, rtx x, bool strict_p)
2145 {
2146 struct m68k_address address;
2147
2148 return m68k_decompose_address (mode, x, strict_p, &address);
2149 }
2150
2151 /* Return true if X is a memory, describing its address in ADDRESS if so.
2152 Apply strict checking if called during or after reload. */
2153
2154 static bool
m68k_legitimate_mem_p(rtx x,struct m68k_address * address)2155 m68k_legitimate_mem_p (rtx x, struct m68k_address *address)
2156 {
2157 return (MEM_P (x)
2158 && m68k_decompose_address (GET_MODE (x), XEXP (x, 0),
2159 reload_in_progress || reload_completed,
2160 address));
2161 }
2162
2163 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
2164
2165 bool
m68k_legitimate_constant_p(machine_mode mode,rtx x)2166 m68k_legitimate_constant_p (machine_mode mode, rtx x)
2167 {
2168 return mode != XFmode && !m68k_illegitimate_symbolic_constant_p (x);
2169 }
2170
2171 /* Return true if X matches the 'Q' constraint. It must be a memory
2172 with a base address and no constant offset or index. */
2173
2174 bool
m68k_matches_q_p(rtx x)2175 m68k_matches_q_p (rtx x)
2176 {
2177 struct m68k_address address;
2178
2179 return (m68k_legitimate_mem_p (x, &address)
2180 && address.code == UNKNOWN
2181 && address.base
2182 && !address.offset
2183 && !address.index);
2184 }
2185
2186 /* Return true if X matches the 'U' constraint. It must be a base address
2187 with a constant offset and no index. */
2188
2189 bool
m68k_matches_u_p(rtx x)2190 m68k_matches_u_p (rtx x)
2191 {
2192 struct m68k_address address;
2193
2194 return (m68k_legitimate_mem_p (x, &address)
2195 && address.code == UNKNOWN
2196 && address.base
2197 && address.offset
2198 && !address.index);
2199 }
2200
2201 /* Return GOT pointer. */
2202
2203 static rtx
m68k_get_gp(void)2204 m68k_get_gp (void)
2205 {
2206 if (pic_offset_table_rtx == NULL_RTX)
2207 pic_offset_table_rtx = gen_rtx_REG (Pmode, PIC_REG);
2208
2209 crtl->uses_pic_offset_table = 1;
2210
2211 return pic_offset_table_rtx;
2212 }
2213
2214 /* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC
2215 wrappers. */
2216 enum m68k_reloc { RELOC_GOT, RELOC_TLSGD, RELOC_TLSLDM, RELOC_TLSLDO,
2217 RELOC_TLSIE, RELOC_TLSLE };
2218
2219 #define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT)
2220
2221 /* Wrap symbol X into unspec representing relocation RELOC.
2222 BASE_REG - register that should be added to the result.
2223 TEMP_REG - if non-null, temporary register. */
2224
2225 static rtx
m68k_wrap_symbol(rtx x,enum m68k_reloc reloc,rtx base_reg,rtx temp_reg)2226 m68k_wrap_symbol (rtx x, enum m68k_reloc reloc, rtx base_reg, rtx temp_reg)
2227 {
2228 bool use_x_p;
2229
2230 use_x_p = (base_reg == pic_offset_table_rtx) ? TARGET_XGOT : TARGET_XTLS;
2231
2232 if (TARGET_COLDFIRE && use_x_p)
2233 /* When compiling with -mx{got, tls} switch the code will look like this:
2234
2235 move.l <X>@<RELOC>,<TEMP_REG>
2236 add.l <BASE_REG>,<TEMP_REG> */
2237 {
2238 /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra
2239 to put @RELOC after reference. */
2240 x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (reloc)),
2241 UNSPEC_RELOC32);
2242 x = gen_rtx_CONST (Pmode, x);
2243
2244 if (temp_reg == NULL)
2245 {
2246 gcc_assert (can_create_pseudo_p ());
2247 temp_reg = gen_reg_rtx (Pmode);
2248 }
2249
2250 emit_move_insn (temp_reg, x);
2251 emit_insn (gen_addsi3 (temp_reg, temp_reg, base_reg));
2252 x = temp_reg;
2253 }
2254 else
2255 {
2256 x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (reloc)),
2257 UNSPEC_RELOC16);
2258 x = gen_rtx_CONST (Pmode, x);
2259
2260 x = gen_rtx_PLUS (Pmode, base_reg, x);
2261 }
2262
2263 return x;
2264 }
2265
2266 /* Helper for m68k_unwrap_symbol.
2267 Also, if unwrapping was successful (that is if (ORIG != <return value>)),
2268 sets *RELOC_PTR to relocation type for the symbol. */
2269
2270 static rtx
m68k_unwrap_symbol_1(rtx orig,bool unwrap_reloc32_p,enum m68k_reloc * reloc_ptr)2271 m68k_unwrap_symbol_1 (rtx orig, bool unwrap_reloc32_p,
2272 enum m68k_reloc *reloc_ptr)
2273 {
2274 if (GET_CODE (orig) == CONST)
2275 {
2276 rtx x;
2277 enum m68k_reloc dummy;
2278
2279 x = XEXP (orig, 0);
2280
2281 if (reloc_ptr == NULL)
2282 reloc_ptr = &dummy;
2283
2284 /* Handle an addend. */
2285 if ((GET_CODE (x) == PLUS || GET_CODE (x) == MINUS)
2286 && CONST_INT_P (XEXP (x, 1)))
2287 x = XEXP (x, 0);
2288
2289 if (GET_CODE (x) == UNSPEC)
2290 {
2291 switch (XINT (x, 1))
2292 {
2293 case UNSPEC_RELOC16:
2294 orig = XVECEXP (x, 0, 0);
2295 *reloc_ptr = (enum m68k_reloc) INTVAL (XVECEXP (x, 0, 1));
2296 break;
2297
2298 case UNSPEC_RELOC32:
2299 if (unwrap_reloc32_p)
2300 {
2301 orig = XVECEXP (x, 0, 0);
2302 *reloc_ptr = (enum m68k_reloc) INTVAL (XVECEXP (x, 0, 1));
2303 }
2304 break;
2305
2306 default:
2307 break;
2308 }
2309 }
2310 }
2311
2312 return orig;
2313 }
2314
2315 /* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p,
2316 UNSPEC_RELOC32 wrappers. */
2317
2318 rtx
m68k_unwrap_symbol(rtx orig,bool unwrap_reloc32_p)2319 m68k_unwrap_symbol (rtx orig, bool unwrap_reloc32_p)
2320 {
2321 return m68k_unwrap_symbol_1 (orig, unwrap_reloc32_p, NULL);
2322 }
2323
2324 /* Prescan insn before outputing assembler for it. */
2325
2326 void
m68k_final_prescan_insn(rtx_insn * insn ATTRIBUTE_UNUSED,rtx * operands,int n_operands)2327 m68k_final_prescan_insn (rtx_insn *insn ATTRIBUTE_UNUSED,
2328 rtx *operands, int n_operands)
2329 {
2330 int i;
2331
2332 /* Combine and, possibly, other optimizations may do good job
2333 converting
2334 (const (unspec [(symbol)]))
2335 into
2336 (const (plus (unspec [(symbol)])
2337 (const_int N))).
2338 The problem with this is emitting @TLS or @GOT decorations.
2339 The decoration is emitted when processing (unspec), so the
2340 result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE".
2341
2342 It seems that the easiest solution to this is to convert such
2343 operands to
2344 (const (unspec [(plus (symbol)
2345 (const_int N))])).
2346 Note, that the top level of operand remains intact, so we don't have
2347 to patch up anything outside of the operand. */
2348
2349 subrtx_var_iterator::array_type array;
2350 for (i = 0; i < n_operands; ++i)
2351 {
2352 rtx op;
2353
2354 op = operands[i];
2355
2356 FOR_EACH_SUBRTX_VAR (iter, array, op, ALL)
2357 {
2358 rtx x = *iter;
2359 if (m68k_unwrap_symbol (x, true) != x)
2360 {
2361 rtx plus;
2362
2363 gcc_assert (GET_CODE (x) == CONST);
2364 plus = XEXP (x, 0);
2365
2366 if (GET_CODE (plus) == PLUS || GET_CODE (plus) == MINUS)
2367 {
2368 rtx unspec;
2369 rtx addend;
2370
2371 unspec = XEXP (plus, 0);
2372 gcc_assert (GET_CODE (unspec) == UNSPEC);
2373 addend = XEXP (plus, 1);
2374 gcc_assert (CONST_INT_P (addend));
2375
2376 /* We now have all the pieces, rearrange them. */
2377
2378 /* Move symbol to plus. */
2379 XEXP (plus, 0) = XVECEXP (unspec, 0, 0);
2380
2381 /* Move plus inside unspec. */
2382 XVECEXP (unspec, 0, 0) = plus;
2383
2384 /* Move unspec to top level of const. */
2385 XEXP (x, 0) = unspec;
2386 }
2387 iter.skip_subrtxes ();
2388 }
2389 }
2390 }
2391 }
2392
2393 /* Move X to a register and add REG_EQUAL note pointing to ORIG.
2394 If REG is non-null, use it; generate new pseudo otherwise. */
2395
2396 static rtx
m68k_move_to_reg(rtx x,rtx orig,rtx reg)2397 m68k_move_to_reg (rtx x, rtx orig, rtx reg)
2398 {
2399 rtx_insn *insn;
2400
2401 if (reg == NULL_RTX)
2402 {
2403 gcc_assert (can_create_pseudo_p ());
2404 reg = gen_reg_rtx (Pmode);
2405 }
2406
2407 insn = emit_move_insn (reg, x);
2408 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2409 by loop. */
2410 set_unique_reg_note (insn, REG_EQUAL, orig);
2411
2412 return reg;
2413 }
2414
2415 /* Does the same as m68k_wrap_symbol, but returns a memory reference to
2416 GOT slot. */
2417
2418 static rtx
m68k_wrap_symbol_into_got_ref(rtx x,enum m68k_reloc reloc,rtx temp_reg)2419 m68k_wrap_symbol_into_got_ref (rtx x, enum m68k_reloc reloc, rtx temp_reg)
2420 {
2421 x = m68k_wrap_symbol (x, reloc, m68k_get_gp (), temp_reg);
2422
2423 x = gen_rtx_MEM (Pmode, x);
2424 MEM_READONLY_P (x) = 1;
2425
2426 return x;
2427 }
2428
2429 /* Legitimize PIC addresses. If the address is already
2430 position-independent, we return ORIG. Newly generated
2431 position-independent addresses go to REG. If we need more
2432 than one register, we lose.
2433
2434 An address is legitimized by making an indirect reference
2435 through the Global Offset Table with the name of the symbol
2436 used as an offset.
2437
2438 The assembler and linker are responsible for placing the
2439 address of the symbol in the GOT. The function prologue
2440 is responsible for initializing a5 to the starting address
2441 of the GOT.
2442
2443 The assembler is also responsible for translating a symbol name
2444 into a constant displacement from the start of the GOT.
2445
2446 A quick example may make things a little clearer:
2447
2448 When not generating PIC code to store the value 12345 into _foo
2449 we would generate the following code:
2450
2451 movel #12345, _foo
2452
2453 When generating PIC two transformations are made. First, the compiler
2454 loads the address of foo into a register. So the first transformation makes:
2455
2456 lea _foo, a0
2457 movel #12345, a0@
2458
2459 The code in movsi will intercept the lea instruction and call this
2460 routine which will transform the instructions into:
2461
2462 movel a5@(_foo:w), a0
2463 movel #12345, a0@
2464
2465
2466 That (in a nutshell) is how *all* symbol and label references are
2467 handled. */
2468
2469 rtx
legitimize_pic_address(rtx orig,machine_mode mode ATTRIBUTE_UNUSED,rtx reg)2470 legitimize_pic_address (rtx orig, machine_mode mode ATTRIBUTE_UNUSED,
2471 rtx reg)
2472 {
2473 rtx pic_ref = orig;
2474
2475 /* First handle a simple SYMBOL_REF or LABEL_REF */
2476 if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
2477 {
2478 gcc_assert (reg);
2479
2480 pic_ref = m68k_wrap_symbol_into_got_ref (orig, RELOC_GOT, reg);
2481 pic_ref = m68k_move_to_reg (pic_ref, orig, reg);
2482 }
2483 else if (GET_CODE (orig) == CONST)
2484 {
2485 rtx base;
2486
2487 /* Make sure this has not already been legitimized. */
2488 if (m68k_unwrap_symbol (orig, true) != orig)
2489 return orig;
2490
2491 gcc_assert (reg);
2492
2493 /* legitimize both operands of the PLUS */
2494 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
2495
2496 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2497 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2498 base == reg ? 0 : reg);
2499
2500 if (GET_CODE (orig) == CONST_INT)
2501 pic_ref = plus_constant (Pmode, base, INTVAL (orig));
2502 else
2503 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
2504 }
2505
2506 return pic_ref;
2507 }
2508
2509 /* The __tls_get_addr symbol. */
2510 static GTY(()) rtx m68k_tls_get_addr;
2511
2512 /* Return SYMBOL_REF for __tls_get_addr. */
2513
2514 static rtx
m68k_get_tls_get_addr(void)2515 m68k_get_tls_get_addr (void)
2516 {
2517 if (m68k_tls_get_addr == NULL_RTX)
2518 m68k_tls_get_addr = init_one_libfunc ("__tls_get_addr");
2519
2520 return m68k_tls_get_addr;
2521 }
2522
2523 /* Return libcall result in A0 instead of usual D0. */
2524 static bool m68k_libcall_value_in_a0_p = false;
2525
2526 /* Emit instruction sequence that calls __tls_get_addr. X is
2527 the TLS symbol we are referencing and RELOC is the symbol type to use
2528 (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence
2529 emitted. A pseudo register with result of __tls_get_addr call is
2530 returned. */
2531
2532 static rtx
m68k_call_tls_get_addr(rtx x,rtx eqv,enum m68k_reloc reloc)2533 m68k_call_tls_get_addr (rtx x, rtx eqv, enum m68k_reloc reloc)
2534 {
2535 rtx a0;
2536 rtx_insn *insns;
2537 rtx dest;
2538
2539 /* Emit the call sequence. */
2540 start_sequence ();
2541
2542 /* FIXME: Unfortunately, emit_library_call_value does not
2543 consider (plus (%a5) (const (unspec))) to be a good enough
2544 operand for push, so it forces it into a register. The bad
2545 thing about this is that combiner, due to copy propagation and other
2546 optimizations, sometimes can not later fix this. As a consequence,
2547 additional register may be allocated resulting in a spill.
2548 For reference, see args processing loops in
2549 calls.c:emit_library_call_value_1.
2550 For testcase, see gcc.target/m68k/tls-{gd, ld}.c */
2551 x = m68k_wrap_symbol (x, reloc, m68k_get_gp (), NULL_RTX);
2552
2553 /* __tls_get_addr() is not a libcall, but emitting a libcall_value
2554 is the simpliest way of generating a call. The difference between
2555 __tls_get_addr() and libcall is that the result is returned in D0
2556 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2557 which temporarily switches returning the result to A0. */
2558
2559 m68k_libcall_value_in_a0_p = true;
2560 a0 = emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX, LCT_PURE,
2561 Pmode, x, Pmode);
2562 m68k_libcall_value_in_a0_p = false;
2563
2564 insns = get_insns ();
2565 end_sequence ();
2566
2567 gcc_assert (can_create_pseudo_p ());
2568 dest = gen_reg_rtx (Pmode);
2569 emit_libcall_block (insns, dest, a0, eqv);
2570
2571 return dest;
2572 }
2573
2574 /* The __tls_get_addr symbol. */
2575 static GTY(()) rtx m68k_read_tp;
2576
2577 /* Return SYMBOL_REF for __m68k_read_tp. */
2578
2579 static rtx
m68k_get_m68k_read_tp(void)2580 m68k_get_m68k_read_tp (void)
2581 {
2582 if (m68k_read_tp == NULL_RTX)
2583 m68k_read_tp = init_one_libfunc ("__m68k_read_tp");
2584
2585 return m68k_read_tp;
2586 }
2587
2588 /* Emit instruction sequence that calls __m68k_read_tp.
2589 A pseudo register with result of __m68k_read_tp call is returned. */
2590
2591 static rtx
m68k_call_m68k_read_tp(void)2592 m68k_call_m68k_read_tp (void)
2593 {
2594 rtx a0;
2595 rtx eqv;
2596 rtx_insn *insns;
2597 rtx dest;
2598
2599 start_sequence ();
2600
2601 /* __m68k_read_tp() is not a libcall, but emitting a libcall_value
2602 is the simpliest way of generating a call. The difference between
2603 __m68k_read_tp() and libcall is that the result is returned in D0
2604 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2605 which temporarily switches returning the result to A0. */
2606
2607 /* Emit the call sequence. */
2608 m68k_libcall_value_in_a0_p = true;
2609 a0 = emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX, LCT_PURE,
2610 Pmode);
2611 m68k_libcall_value_in_a0_p = false;
2612 insns = get_insns ();
2613 end_sequence ();
2614
2615 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2616 share the m68k_read_tp result with other IE/LE model accesses. */
2617 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx), UNSPEC_RELOC32);
2618
2619 gcc_assert (can_create_pseudo_p ());
2620 dest = gen_reg_rtx (Pmode);
2621 emit_libcall_block (insns, dest, a0, eqv);
2622
2623 return dest;
2624 }
2625
2626 /* Return a legitimized address for accessing TLS SYMBOL_REF X.
2627 For explanations on instructions sequences see TLS/NPTL ABI for m68k and
2628 ColdFire. */
2629
2630 rtx
m68k_legitimize_tls_address(rtx orig)2631 m68k_legitimize_tls_address (rtx orig)
2632 {
2633 switch (SYMBOL_REF_TLS_MODEL (orig))
2634 {
2635 case TLS_MODEL_GLOBAL_DYNAMIC:
2636 orig = m68k_call_tls_get_addr (orig, orig, RELOC_TLSGD);
2637 break;
2638
2639 case TLS_MODEL_LOCAL_DYNAMIC:
2640 {
2641 rtx eqv;
2642 rtx a0;
2643 rtx x;
2644
2645 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2646 share the LDM result with other LD model accesses. */
2647 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2648 UNSPEC_RELOC32);
2649
2650 a0 = m68k_call_tls_get_addr (orig, eqv, RELOC_TLSLDM);
2651
2652 x = m68k_wrap_symbol (orig, RELOC_TLSLDO, a0, NULL_RTX);
2653
2654 if (can_create_pseudo_p ())
2655 x = m68k_move_to_reg (x, orig, NULL_RTX);
2656
2657 orig = x;
2658 break;
2659 }
2660
2661 case TLS_MODEL_INITIAL_EXEC:
2662 {
2663 rtx a0;
2664 rtx x;
2665
2666 a0 = m68k_call_m68k_read_tp ();
2667
2668 x = m68k_wrap_symbol_into_got_ref (orig, RELOC_TLSIE, NULL_RTX);
2669 x = gen_rtx_PLUS (Pmode, x, a0);
2670
2671 if (can_create_pseudo_p ())
2672 x = m68k_move_to_reg (x, orig, NULL_RTX);
2673
2674 orig = x;
2675 break;
2676 }
2677
2678 case TLS_MODEL_LOCAL_EXEC:
2679 {
2680 rtx a0;
2681 rtx x;
2682
2683 a0 = m68k_call_m68k_read_tp ();
2684
2685 x = m68k_wrap_symbol (orig, RELOC_TLSLE, a0, NULL_RTX);
2686
2687 if (can_create_pseudo_p ())
2688 x = m68k_move_to_reg (x, orig, NULL_RTX);
2689
2690 orig = x;
2691 break;
2692 }
2693
2694 default:
2695 gcc_unreachable ();
2696 }
2697
2698 return orig;
2699 }
2700
2701 /* Return true if X is a TLS symbol. */
2702
2703 static bool
m68k_tls_symbol_p(rtx x)2704 m68k_tls_symbol_p (rtx x)
2705 {
2706 if (!TARGET_HAVE_TLS)
2707 return false;
2708
2709 if (GET_CODE (x) != SYMBOL_REF)
2710 return false;
2711
2712 return SYMBOL_REF_TLS_MODEL (x) != 0;
2713 }
2714
2715 /* If !LEGITIMATE_P, return true if X is a TLS symbol reference,
2716 though illegitimate one.
2717 If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */
2718
2719 bool
m68k_tls_reference_p(rtx x,bool legitimate_p)2720 m68k_tls_reference_p (rtx x, bool legitimate_p)
2721 {
2722 if (!TARGET_HAVE_TLS)
2723 return false;
2724
2725 if (!legitimate_p)
2726 {
2727 subrtx_var_iterator::array_type array;
2728 FOR_EACH_SUBRTX_VAR (iter, array, x, ALL)
2729 {
2730 rtx x = *iter;
2731
2732 /* Note: this is not the same as m68k_tls_symbol_p. */
2733 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0)
2734 return true;
2735
2736 /* Don't recurse into legitimate TLS references. */
2737 if (m68k_tls_reference_p (x, true))
2738 iter.skip_subrtxes ();
2739 }
2740 return false;
2741 }
2742 else
2743 {
2744 enum m68k_reloc reloc = RELOC_GOT;
2745
2746 return (m68k_unwrap_symbol_1 (x, true, &reloc) != x
2747 && TLS_RELOC_P (reloc));
2748 }
2749 }
2750
2751
2752
2753 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2754
2755 /* Return the type of move that should be used for integer I. */
2756
2757 M68K_CONST_METHOD
m68k_const_method(HOST_WIDE_INT i)2758 m68k_const_method (HOST_WIDE_INT i)
2759 {
2760 unsigned u;
2761
2762 if (USE_MOVQ (i))
2763 return MOVQ;
2764
2765 /* The ColdFire doesn't have byte or word operations. */
2766 /* FIXME: This may not be useful for the m68060 either. */
2767 if (!TARGET_COLDFIRE)
2768 {
2769 /* if -256 < N < 256 but N is not in range for a moveq
2770 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2771 if (USE_MOVQ (i ^ 0xff))
2772 return NOTB;
2773 /* Likewise, try with not.w */
2774 if (USE_MOVQ (i ^ 0xffff))
2775 return NOTW;
2776 /* This is the only value where neg.w is useful */
2777 if (i == -65408)
2778 return NEGW;
2779 }
2780
2781 /* Try also with swap. */
2782 u = i;
2783 if (USE_MOVQ ((u >> 16) | (u << 16)))
2784 return SWAP;
2785
2786 if (TARGET_ISAB)
2787 {
2788 /* Try using MVZ/MVS with an immediate value to load constants. */
2789 if (i >= 0 && i <= 65535)
2790 return MVZ;
2791 if (i >= -32768 && i <= 32767)
2792 return MVS;
2793 }
2794
2795 /* Otherwise, use move.l */
2796 return MOVL;
2797 }
2798
2799 /* Return the cost of moving constant I into a data register. */
2800
2801 static int
const_int_cost(HOST_WIDE_INT i)2802 const_int_cost (HOST_WIDE_INT i)
2803 {
2804 switch (m68k_const_method (i))
2805 {
2806 case MOVQ:
2807 /* Constants between -128 and 127 are cheap due to moveq. */
2808 return 0;
2809 case MVZ:
2810 case MVS:
2811 case NOTB:
2812 case NOTW:
2813 case NEGW:
2814 case SWAP:
2815 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2816 return 1;
2817 case MOVL:
2818 return 2;
2819 default:
2820 gcc_unreachable ();
2821 }
2822 }
2823
2824 static bool
m68k_rtx_costs(rtx x,machine_mode mode,int outer_code,int opno ATTRIBUTE_UNUSED,int * total,bool speed ATTRIBUTE_UNUSED)2825 m68k_rtx_costs (rtx x, machine_mode mode, int outer_code,
2826 int opno ATTRIBUTE_UNUSED,
2827 int *total, bool speed ATTRIBUTE_UNUSED)
2828 {
2829 int code = GET_CODE (x);
2830
2831 switch (code)
2832 {
2833 case CONST_INT:
2834 /* Constant zero is super cheap due to clr instruction. */
2835 if (x == const0_rtx)
2836 *total = 0;
2837 else
2838 *total = const_int_cost (INTVAL (x));
2839 return true;
2840
2841 case CONST:
2842 case LABEL_REF:
2843 case SYMBOL_REF:
2844 *total = 3;
2845 return true;
2846
2847 case CONST_DOUBLE:
2848 /* Make 0.0 cheaper than other floating constants to
2849 encourage creating tstsf and tstdf insns. */
2850 if (outer_code == COMPARE
2851 && (x == CONST0_RTX (SFmode) || x == CONST0_RTX (DFmode)))
2852 *total = 4;
2853 else
2854 *total = 5;
2855 return true;
2856
2857 /* These are vaguely right for a 68020. */
2858 /* The costs for long multiply have been adjusted to work properly
2859 in synth_mult on the 68020, relative to an average of the time
2860 for add and the time for shift, taking away a little more because
2861 sometimes move insns are needed. */
2862 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2863 terms. */
2864 #define MULL_COST \
2865 (TUNE_68060 ? 2 \
2866 : TUNE_68040 ? 5 \
2867 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2868 : (TUNE_CFV2 && TUNE_MAC) ? 4 \
2869 : TUNE_CFV2 ? 8 \
2870 : TARGET_COLDFIRE ? 3 : 13)
2871
2872 #define MULW_COST \
2873 (TUNE_68060 ? 2 \
2874 : TUNE_68040 ? 3 \
2875 : TUNE_68000_10 ? 5 \
2876 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2877 : (TUNE_CFV2 && TUNE_MAC) ? 2 \
2878 : TUNE_CFV2 ? 8 \
2879 : TARGET_COLDFIRE ? 2 : 8)
2880
2881 #define DIVW_COST \
2882 (TARGET_CF_HWDIV ? 11 \
2883 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2884
2885 case PLUS:
2886 /* An lea costs about three times as much as a simple add. */
2887 if (mode == SImode
2888 && GET_CODE (XEXP (x, 1)) == REG
2889 && GET_CODE (XEXP (x, 0)) == MULT
2890 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
2891 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2892 && (INTVAL (XEXP (XEXP (x, 0), 1)) == 2
2893 || INTVAL (XEXP (XEXP (x, 0), 1)) == 4
2894 || INTVAL (XEXP (XEXP (x, 0), 1)) == 8))
2895 {
2896 /* lea an@(dx:l:i),am */
2897 *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 2 : 3);
2898 return true;
2899 }
2900 return false;
2901
2902 case ASHIFT:
2903 case ASHIFTRT:
2904 case LSHIFTRT:
2905 if (TUNE_68060)
2906 {
2907 *total = COSTS_N_INSNS(1);
2908 return true;
2909 }
2910 if (TUNE_68000_10)
2911 {
2912 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2913 {
2914 if (INTVAL (XEXP (x, 1)) < 16)
2915 *total = COSTS_N_INSNS (2) + INTVAL (XEXP (x, 1)) / 2;
2916 else
2917 /* We're using clrw + swap for these cases. */
2918 *total = COSTS_N_INSNS (4) + (INTVAL (XEXP (x, 1)) - 16) / 2;
2919 }
2920 else
2921 *total = COSTS_N_INSNS (10); /* Worst case. */
2922 return true;
2923 }
2924 /* A shift by a big integer takes an extra instruction. */
2925 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2926 && (INTVAL (XEXP (x, 1)) == 16))
2927 {
2928 *total = COSTS_N_INSNS (2); /* clrw;swap */
2929 return true;
2930 }
2931 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2932 && !(INTVAL (XEXP (x, 1)) > 0
2933 && INTVAL (XEXP (x, 1)) <= 8))
2934 {
2935 *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 1 : 3); /* lsr #i,dn */
2936 return true;
2937 }
2938 return false;
2939
2940 case MULT:
2941 if ((GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
2942 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
2943 && mode == SImode)
2944 *total = COSTS_N_INSNS (MULW_COST);
2945 else if (mode == QImode || mode == HImode)
2946 *total = COSTS_N_INSNS (MULW_COST);
2947 else
2948 *total = COSTS_N_INSNS (MULL_COST);
2949 return true;
2950
2951 case DIV:
2952 case UDIV:
2953 case MOD:
2954 case UMOD:
2955 if (mode == QImode || mode == HImode)
2956 *total = COSTS_N_INSNS (DIVW_COST); /* div.w */
2957 else if (TARGET_CF_HWDIV)
2958 *total = COSTS_N_INSNS (18);
2959 else
2960 *total = COSTS_N_INSNS (43); /* div.l */
2961 return true;
2962
2963 case ZERO_EXTRACT:
2964 if (outer_code == COMPARE)
2965 *total = 0;
2966 return false;
2967
2968 default:
2969 return false;
2970 }
2971 }
2972
2973 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2974 OPERANDS[0]. */
2975
2976 static const char *
output_move_const_into_data_reg(rtx * operands)2977 output_move_const_into_data_reg (rtx *operands)
2978 {
2979 HOST_WIDE_INT i;
2980
2981 i = INTVAL (operands[1]);
2982 switch (m68k_const_method (i))
2983 {
2984 case MVZ:
2985 return "mvzw %1,%0";
2986 case MVS:
2987 return "mvsw %1,%0";
2988 case MOVQ:
2989 return "moveq %1,%0";
2990 case NOTB:
2991 CC_STATUS_INIT;
2992 operands[1] = GEN_INT (i ^ 0xff);
2993 return "moveq %1,%0\n\tnot%.b %0";
2994 case NOTW:
2995 CC_STATUS_INIT;
2996 operands[1] = GEN_INT (i ^ 0xffff);
2997 return "moveq %1,%0\n\tnot%.w %0";
2998 case NEGW:
2999 CC_STATUS_INIT;
3000 return "moveq #-128,%0\n\tneg%.w %0";
3001 case SWAP:
3002 {
3003 unsigned u = i;
3004
3005 operands[1] = GEN_INT ((u << 16) | (u >> 16));
3006 return "moveq %1,%0\n\tswap %0";
3007 }
3008 case MOVL:
3009 return "move%.l %1,%0";
3010 default:
3011 gcc_unreachable ();
3012 }
3013 }
3014
3015 /* Return true if I can be handled by ISA B's mov3q instruction. */
3016
3017 bool
valid_mov3q_const(HOST_WIDE_INT i)3018 valid_mov3q_const (HOST_WIDE_INT i)
3019 {
3020 return TARGET_ISAB && (i == -1 || IN_RANGE (i, 1, 7));
3021 }
3022
3023 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
3024 I is the value of OPERANDS[1]. */
3025
3026 static const char *
output_move_simode_const(rtx * operands)3027 output_move_simode_const (rtx *operands)
3028 {
3029 rtx dest;
3030 HOST_WIDE_INT src;
3031
3032 dest = operands[0];
3033 src = INTVAL (operands[1]);
3034 if (src == 0
3035 && (DATA_REG_P (dest) || MEM_P (dest))
3036 /* clr insns on 68000 read before writing. */
3037 && ((TARGET_68010 || TARGET_COLDFIRE)
3038 || !(MEM_P (dest) && MEM_VOLATILE_P (dest))))
3039 return "clr%.l %0";
3040 else if (GET_MODE (dest) == SImode && valid_mov3q_const (src))
3041 return "mov3q%.l %1,%0";
3042 else if (src == 0 && ADDRESS_REG_P (dest))
3043 return "sub%.l %0,%0";
3044 else if (DATA_REG_P (dest))
3045 return output_move_const_into_data_reg (operands);
3046 else if (ADDRESS_REG_P (dest) && IN_RANGE (src, -0x8000, 0x7fff))
3047 {
3048 if (valid_mov3q_const (src))
3049 return "mov3q%.l %1,%0";
3050 return "move%.w %1,%0";
3051 }
3052 else if (MEM_P (dest)
3053 && GET_CODE (XEXP (dest, 0)) == PRE_DEC
3054 && REGNO (XEXP (XEXP (dest, 0), 0)) == STACK_POINTER_REGNUM
3055 && IN_RANGE (src, -0x8000, 0x7fff))
3056 {
3057 if (valid_mov3q_const (src))
3058 return "mov3q%.l %1,%-";
3059 return "pea %a1";
3060 }
3061 return "move%.l %1,%0";
3062 }
3063
3064 const char *
output_move_simode(rtx * operands)3065 output_move_simode (rtx *operands)
3066 {
3067 if (GET_CODE (operands[1]) == CONST_INT)
3068 return output_move_simode_const (operands);
3069 else if ((GET_CODE (operands[1]) == SYMBOL_REF
3070 || GET_CODE (operands[1]) == CONST)
3071 && push_operand (operands[0], SImode))
3072 return "pea %a1";
3073 else if ((GET_CODE (operands[1]) == SYMBOL_REF
3074 || GET_CODE (operands[1]) == CONST)
3075 && ADDRESS_REG_P (operands[0]))
3076 return "lea %a1,%0";
3077 return "move%.l %1,%0";
3078 }
3079
3080 const char *
output_move_himode(rtx * operands)3081 output_move_himode (rtx *operands)
3082 {
3083 if (GET_CODE (operands[1]) == CONST_INT)
3084 {
3085 if (operands[1] == const0_rtx
3086 && (DATA_REG_P (operands[0])
3087 || GET_CODE (operands[0]) == MEM)
3088 /* clr insns on 68000 read before writing. */
3089 && ((TARGET_68010 || TARGET_COLDFIRE)
3090 || !(GET_CODE (operands[0]) == MEM
3091 && MEM_VOLATILE_P (operands[0]))))
3092 return "clr%.w %0";
3093 else if (operands[1] == const0_rtx
3094 && ADDRESS_REG_P (operands[0]))
3095 return "sub%.l %0,%0";
3096 else if (DATA_REG_P (operands[0])
3097 && INTVAL (operands[1]) < 128
3098 && INTVAL (operands[1]) >= -128)
3099 return "moveq %1,%0";
3100 else if (INTVAL (operands[1]) < 0x8000
3101 && INTVAL (operands[1]) >= -0x8000)
3102 return "move%.w %1,%0";
3103 }
3104 else if (CONSTANT_P (operands[1]))
3105 return "move%.l %1,%0";
3106 return "move%.w %1,%0";
3107 }
3108
3109 const char *
output_move_qimode(rtx * operands)3110 output_move_qimode (rtx *operands)
3111 {
3112 /* 68k family always modifies the stack pointer by at least 2, even for
3113 byte pushes. The 5200 (ColdFire) does not do this. */
3114
3115 /* This case is generated by pushqi1 pattern now. */
3116 gcc_assert (!(GET_CODE (operands[0]) == MEM
3117 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
3118 && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx
3119 && ! ADDRESS_REG_P (operands[1])
3120 && ! TARGET_COLDFIRE));
3121
3122 /* clr and st insns on 68000 read before writing. */
3123 if (!ADDRESS_REG_P (operands[0])
3124 && ((TARGET_68010 || TARGET_COLDFIRE)
3125 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
3126 {
3127 if (operands[1] == const0_rtx)
3128 return "clr%.b %0";
3129 if ((!TARGET_COLDFIRE || DATA_REG_P (operands[0]))
3130 && GET_CODE (operands[1]) == CONST_INT
3131 && (INTVAL (operands[1]) & 255) == 255)
3132 {
3133 CC_STATUS_INIT;
3134 return "st %0";
3135 }
3136 }
3137 if (GET_CODE (operands[1]) == CONST_INT
3138 && DATA_REG_P (operands[0])
3139 && INTVAL (operands[1]) < 128
3140 && INTVAL (operands[1]) >= -128)
3141 return "moveq %1,%0";
3142 if (operands[1] == const0_rtx && ADDRESS_REG_P (operands[0]))
3143 return "sub%.l %0,%0";
3144 if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
3145 return "move%.l %1,%0";
3146 /* 68k family (including the 5200 ColdFire) does not support byte moves to
3147 from address registers. */
3148 if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
3149 return "move%.w %1,%0";
3150 return "move%.b %1,%0";
3151 }
3152
3153 const char *
output_move_stricthi(rtx * operands)3154 output_move_stricthi (rtx *operands)
3155 {
3156 if (operands[1] == const0_rtx
3157 /* clr insns on 68000 read before writing. */
3158 && ((TARGET_68010 || TARGET_COLDFIRE)
3159 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
3160 return "clr%.w %0";
3161 return "move%.w %1,%0";
3162 }
3163
3164 const char *
output_move_strictqi(rtx * operands)3165 output_move_strictqi (rtx *operands)
3166 {
3167 if (operands[1] == const0_rtx
3168 /* clr insns on 68000 read before writing. */
3169 && ((TARGET_68010 || TARGET_COLDFIRE)
3170 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
3171 return "clr%.b %0";
3172 return "move%.b %1,%0";
3173 }
3174
3175 /* Return the best assembler insn template
3176 for moving operands[1] into operands[0] as a fullword. */
3177
3178 static const char *
singlemove_string(rtx * operands)3179 singlemove_string (rtx *operands)
3180 {
3181 if (GET_CODE (operands[1]) == CONST_INT)
3182 return output_move_simode_const (operands);
3183 return "move%.l %1,%0";
3184 }
3185
3186
3187 /* Output assembler or rtl code to perform a doubleword move insn
3188 with operands OPERANDS.
3189 Pointers to 3 helper functions should be specified:
3190 HANDLE_REG_ADJUST to adjust a register by a small value,
3191 HANDLE_COMPADR to compute an address and
3192 HANDLE_MOVSI to move 4 bytes. */
3193
3194 static void
handle_move_double(rtx operands[2],void (* handle_reg_adjust)(rtx,int),void (* handle_compadr)(rtx[2]),void (* handle_movsi)(rtx[2]))3195 handle_move_double (rtx operands[2],
3196 void (*handle_reg_adjust) (rtx, int),
3197 void (*handle_compadr) (rtx [2]),
3198 void (*handle_movsi) (rtx [2]))
3199 {
3200 enum
3201 {
3202 REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP
3203 } optype0, optype1;
3204 rtx latehalf[2];
3205 rtx middlehalf[2];
3206 rtx xops[2];
3207 rtx addreg0 = 0, addreg1 = 0;
3208 int dest_overlapped_low = 0;
3209 int size = GET_MODE_SIZE (GET_MODE (operands[0]));
3210
3211 middlehalf[0] = 0;
3212 middlehalf[1] = 0;
3213
3214 /* First classify both operands. */
3215
3216 if (REG_P (operands[0]))
3217 optype0 = REGOP;
3218 else if (offsettable_memref_p (operands[0]))
3219 optype0 = OFFSOP;
3220 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
3221 optype0 = POPOP;
3222 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
3223 optype0 = PUSHOP;
3224 else if (GET_CODE (operands[0]) == MEM)
3225 optype0 = MEMOP;
3226 else
3227 optype0 = RNDOP;
3228
3229 if (REG_P (operands[1]))
3230 optype1 = REGOP;
3231 else if (CONSTANT_P (operands[1]))
3232 optype1 = CNSTOP;
3233 else if (offsettable_memref_p (operands[1]))
3234 optype1 = OFFSOP;
3235 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
3236 optype1 = POPOP;
3237 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
3238 optype1 = PUSHOP;
3239 else if (GET_CODE (operands[1]) == MEM)
3240 optype1 = MEMOP;
3241 else
3242 optype1 = RNDOP;
3243
3244 /* Check for the cases that the operand constraints are not supposed
3245 to allow to happen. Generating code for these cases is
3246 painful. */
3247 gcc_assert (optype0 != RNDOP && optype1 != RNDOP);
3248
3249 /* If one operand is decrementing and one is incrementing
3250 decrement the former register explicitly
3251 and change that operand into ordinary indexing. */
3252
3253 if (optype0 == PUSHOP && optype1 == POPOP)
3254 {
3255 operands[0] = XEXP (XEXP (operands[0], 0), 0);
3256
3257 handle_reg_adjust (operands[0], -size);
3258
3259 if (GET_MODE (operands[1]) == XFmode)
3260 operands[0] = gen_rtx_MEM (XFmode, operands[0]);
3261 else if (GET_MODE (operands[0]) == DFmode)
3262 operands[0] = gen_rtx_MEM (DFmode, operands[0]);
3263 else
3264 operands[0] = gen_rtx_MEM (DImode, operands[0]);
3265 optype0 = OFFSOP;
3266 }
3267 if (optype0 == POPOP && optype1 == PUSHOP)
3268 {
3269 operands[1] = XEXP (XEXP (operands[1], 0), 0);
3270
3271 handle_reg_adjust (operands[1], -size);
3272
3273 if (GET_MODE (operands[1]) == XFmode)
3274 operands[1] = gen_rtx_MEM (XFmode, operands[1]);
3275 else if (GET_MODE (operands[1]) == DFmode)
3276 operands[1] = gen_rtx_MEM (DFmode, operands[1]);
3277 else
3278 operands[1] = gen_rtx_MEM (DImode, operands[1]);
3279 optype1 = OFFSOP;
3280 }
3281
3282 /* If an operand is an unoffsettable memory ref, find a register
3283 we can increment temporarily to make it refer to the second word. */
3284
3285 if (optype0 == MEMOP)
3286 addreg0 = find_addr_reg (XEXP (operands[0], 0));
3287
3288 if (optype1 == MEMOP)
3289 addreg1 = find_addr_reg (XEXP (operands[1], 0));
3290
3291 /* Ok, we can do one word at a time.
3292 Normally we do the low-numbered word first,
3293 but if either operand is autodecrementing then we
3294 do the high-numbered word first.
3295
3296 In either case, set up in LATEHALF the operands to use
3297 for the high-numbered word and in some cases alter the
3298 operands in OPERANDS to be suitable for the low-numbered word. */
3299
3300 if (size == 12)
3301 {
3302 if (optype0 == REGOP)
3303 {
3304 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2);
3305 middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3306 }
3307 else if (optype0 == OFFSOP)
3308 {
3309 middlehalf[0] = adjust_address (operands[0], SImode, 4);
3310 latehalf[0] = adjust_address (operands[0], SImode, size - 4);
3311 }
3312 else
3313 {
3314 middlehalf[0] = adjust_address (operands[0], SImode, 0);
3315 latehalf[0] = adjust_address (operands[0], SImode, 0);
3316 }
3317
3318 if (optype1 == REGOP)
3319 {
3320 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
3321 middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
3322 }
3323 else if (optype1 == OFFSOP)
3324 {
3325 middlehalf[1] = adjust_address (operands[1], SImode, 4);
3326 latehalf[1] = adjust_address (operands[1], SImode, size - 4);
3327 }
3328 else if (optype1 == CNSTOP)
3329 {
3330 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3331 {
3332 long l[3];
3333
3334 REAL_VALUE_TO_TARGET_LONG_DOUBLE
3335 (*CONST_DOUBLE_REAL_VALUE (operands[1]), l);
3336 operands[1] = GEN_INT (l[0]);
3337 middlehalf[1] = GEN_INT (l[1]);
3338 latehalf[1] = GEN_INT (l[2]);
3339 }
3340 else
3341 {
3342 /* No non-CONST_DOUBLE constant should ever appear
3343 here. */
3344 gcc_assert (!CONSTANT_P (operands[1]));
3345 }
3346 }
3347 else
3348 {
3349 middlehalf[1] = adjust_address (operands[1], SImode, 0);
3350 latehalf[1] = adjust_address (operands[1], SImode, 0);
3351 }
3352 }
3353 else
3354 /* size is not 12: */
3355 {
3356 if (optype0 == REGOP)
3357 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3358 else if (optype0 == OFFSOP)
3359 latehalf[0] = adjust_address (operands[0], SImode, size - 4);
3360 else
3361 latehalf[0] = adjust_address (operands[0], SImode, 0);
3362
3363 if (optype1 == REGOP)
3364 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
3365 else if (optype1 == OFFSOP)
3366 latehalf[1] = adjust_address (operands[1], SImode, size - 4);
3367 else if (optype1 == CNSTOP)
3368 split_double (operands[1], &operands[1], &latehalf[1]);
3369 else
3370 latehalf[1] = adjust_address (operands[1], SImode, 0);
3371 }
3372
3373 /* If insn is effectively movd N(REG),-(REG) then we will do the high
3374 word first. We should use the adjusted operand 1 (which is N+4(REG))
3375 for the low word as well, to compensate for the first decrement of
3376 REG. */
3377 if (optype0 == PUSHOP
3378 && reg_overlap_mentioned_p (XEXP (XEXP (operands[0], 0), 0), operands[1]))
3379 operands[1] = middlehalf[1] = latehalf[1];
3380
3381 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
3382 if the upper part of reg N does not appear in the MEM, arrange to
3383 emit the move late-half first. Otherwise, compute the MEM address
3384 into the upper part of N and use that as a pointer to the memory
3385 operand. */
3386 if (optype0 == REGOP
3387 && (optype1 == OFFSOP || optype1 == MEMOP))
3388 {
3389 rtx testlow = gen_rtx_REG (SImode, REGNO (operands[0]));
3390
3391 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
3392 && reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
3393 {
3394 /* If both halves of dest are used in the src memory address,
3395 compute the address into latehalf of dest.
3396 Note that this can't happen if the dest is two data regs. */
3397 compadr:
3398 xops[0] = latehalf[0];
3399 xops[1] = XEXP (operands[1], 0);
3400
3401 handle_compadr (xops);
3402 if (GET_MODE (operands[1]) == XFmode)
3403 {
3404 operands[1] = gen_rtx_MEM (XFmode, latehalf[0]);
3405 middlehalf[1] = adjust_address (operands[1], DImode, size - 8);
3406 latehalf[1] = adjust_address (operands[1], DImode, size - 4);
3407 }
3408 else
3409 {
3410 operands[1] = gen_rtx_MEM (DImode, latehalf[0]);
3411 latehalf[1] = adjust_address (operands[1], DImode, size - 4);
3412 }
3413 }
3414 else if (size == 12
3415 && reg_overlap_mentioned_p (middlehalf[0],
3416 XEXP (operands[1], 0)))
3417 {
3418 /* Check for two regs used by both source and dest.
3419 Note that this can't happen if the dest is all data regs.
3420 It can happen if the dest is d6, d7, a0.
3421 But in that case, latehalf is an addr reg, so
3422 the code at compadr does ok. */
3423
3424 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
3425 || reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
3426 goto compadr;
3427
3428 /* JRV says this can't happen: */
3429 gcc_assert (!addreg0 && !addreg1);
3430
3431 /* Only the middle reg conflicts; simply put it last. */
3432 handle_movsi (operands);
3433 handle_movsi (latehalf);
3434 handle_movsi (middlehalf);
3435
3436 return;
3437 }
3438 else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)))
3439 /* If the low half of dest is mentioned in the source memory
3440 address, the arrange to emit the move late half first. */
3441 dest_overlapped_low = 1;
3442 }
3443
3444 /* If one or both operands autodecrementing,
3445 do the two words, high-numbered first. */
3446
3447 /* Likewise, the first move would clobber the source of the second one,
3448 do them in the other order. This happens only for registers;
3449 such overlap can't happen in memory unless the user explicitly
3450 sets it up, and that is an undefined circumstance. */
3451
3452 if (optype0 == PUSHOP || optype1 == PUSHOP
3453 || (optype0 == REGOP && optype1 == REGOP
3454 && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1]))
3455 || REGNO (operands[0]) == REGNO (latehalf[1])))
3456 || dest_overlapped_low)
3457 {
3458 /* Make any unoffsettable addresses point at high-numbered word. */
3459 if (addreg0)
3460 handle_reg_adjust (addreg0, size - 4);
3461 if (addreg1)
3462 handle_reg_adjust (addreg1, size - 4);
3463
3464 /* Do that word. */
3465 handle_movsi (latehalf);
3466
3467 /* Undo the adds we just did. */
3468 if (addreg0)
3469 handle_reg_adjust (addreg0, -4);
3470 if (addreg1)
3471 handle_reg_adjust (addreg1, -4);
3472
3473 if (size == 12)
3474 {
3475 handle_movsi (middlehalf);
3476
3477 if (addreg0)
3478 handle_reg_adjust (addreg0, -4);
3479 if (addreg1)
3480 handle_reg_adjust (addreg1, -4);
3481 }
3482
3483 /* Do low-numbered word. */
3484
3485 handle_movsi (operands);
3486 return;
3487 }
3488
3489 /* Normal case: do the two words, low-numbered first. */
3490
3491 m68k_final_prescan_insn (NULL, operands, 2);
3492 handle_movsi (operands);
3493
3494 /* Do the middle one of the three words for long double */
3495 if (size == 12)
3496 {
3497 if (addreg0)
3498 handle_reg_adjust (addreg0, 4);
3499 if (addreg1)
3500 handle_reg_adjust (addreg1, 4);
3501
3502 m68k_final_prescan_insn (NULL, middlehalf, 2);
3503 handle_movsi (middlehalf);
3504 }
3505
3506 /* Make any unoffsettable addresses point at high-numbered word. */
3507 if (addreg0)
3508 handle_reg_adjust (addreg0, 4);
3509 if (addreg1)
3510 handle_reg_adjust (addreg1, 4);
3511
3512 /* Do that word. */
3513 m68k_final_prescan_insn (NULL, latehalf, 2);
3514 handle_movsi (latehalf);
3515
3516 /* Undo the adds we just did. */
3517 if (addreg0)
3518 handle_reg_adjust (addreg0, -(size - 4));
3519 if (addreg1)
3520 handle_reg_adjust (addreg1, -(size - 4));
3521
3522 return;
3523 }
3524
3525 /* Output assembler code to adjust REG by N. */
3526 static void
output_reg_adjust(rtx reg,int n)3527 output_reg_adjust (rtx reg, int n)
3528 {
3529 const char *s;
3530
3531 gcc_assert (GET_MODE (reg) == SImode && n >= -12 && n != 0 && n <= 12);
3532
3533 switch (n)
3534 {
3535 case 12:
3536 s = "add%.l #12,%0";
3537 break;
3538
3539 case 8:
3540 s = "addq%.l #8,%0";
3541 break;
3542
3543 case 4:
3544 s = "addq%.l #4,%0";
3545 break;
3546
3547 case -12:
3548 s = "sub%.l #12,%0";
3549 break;
3550
3551 case -8:
3552 s = "subq%.l #8,%0";
3553 break;
3554
3555 case -4:
3556 s = "subq%.l #4,%0";
3557 break;
3558
3559 default:
3560 gcc_unreachable ();
3561 s = NULL;
3562 }
3563
3564 output_asm_insn (s, ®);
3565 }
3566
3567 /* Emit rtl code to adjust REG by N. */
3568 static void
emit_reg_adjust(rtx reg1,int n)3569 emit_reg_adjust (rtx reg1, int n)
3570 {
3571 rtx reg2;
3572
3573 gcc_assert (GET_MODE (reg1) == SImode && n >= -12 && n != 0 && n <= 12);
3574
3575 reg1 = copy_rtx (reg1);
3576 reg2 = copy_rtx (reg1);
3577
3578 if (n < 0)
3579 emit_insn (gen_subsi3 (reg1, reg2, GEN_INT (-n)));
3580 else if (n > 0)
3581 emit_insn (gen_addsi3 (reg1, reg2, GEN_INT (n)));
3582 else
3583 gcc_unreachable ();
3584 }
3585
3586 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
3587 static void
output_compadr(rtx operands[2])3588 output_compadr (rtx operands[2])
3589 {
3590 output_asm_insn ("lea %a1,%0", operands);
3591 }
3592
3593 /* Output the best assembler insn for moving operands[1] into operands[0]
3594 as a fullword. */
3595 static void
output_movsi(rtx operands[2])3596 output_movsi (rtx operands[2])
3597 {
3598 output_asm_insn (singlemove_string (operands), operands);
3599 }
3600
3601 /* Copy OP and change its mode to MODE. */
3602 static rtx
copy_operand(rtx op,machine_mode mode)3603 copy_operand (rtx op, machine_mode mode)
3604 {
3605 /* ??? This looks really ugly. There must be a better way
3606 to change a mode on the operand. */
3607 if (GET_MODE (op) != VOIDmode)
3608 {
3609 if (REG_P (op))
3610 op = gen_rtx_REG (mode, REGNO (op));
3611 else
3612 {
3613 op = copy_rtx (op);
3614 PUT_MODE (op, mode);
3615 }
3616 }
3617
3618 return op;
3619 }
3620
3621 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
3622 static void
emit_movsi(rtx operands[2])3623 emit_movsi (rtx operands[2])
3624 {
3625 operands[0] = copy_operand (operands[0], SImode);
3626 operands[1] = copy_operand (operands[1], SImode);
3627
3628 emit_insn (gen_movsi (operands[0], operands[1]));
3629 }
3630
3631 /* Output assembler code to perform a doubleword move insn
3632 with operands OPERANDS. */
3633 const char *
output_move_double(rtx * operands)3634 output_move_double (rtx *operands)
3635 {
3636 handle_move_double (operands,
3637 output_reg_adjust, output_compadr, output_movsi);
3638
3639 return "";
3640 }
3641
3642 /* Output rtl code to perform a doubleword move insn
3643 with operands OPERANDS. */
3644 void
m68k_emit_move_double(rtx operands[2])3645 m68k_emit_move_double (rtx operands[2])
3646 {
3647 handle_move_double (operands, emit_reg_adjust, emit_movsi, emit_movsi);
3648 }
3649
3650 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
3651 new rtx with the correct mode. */
3652
3653 static rtx
force_mode(machine_mode mode,rtx orig)3654 force_mode (machine_mode mode, rtx orig)
3655 {
3656 if (mode == GET_MODE (orig))
3657 return orig;
3658
3659 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
3660 abort ();
3661
3662 return gen_rtx_REG (mode, REGNO (orig));
3663 }
3664
3665 static int
fp_reg_operand(rtx op,machine_mode mode ATTRIBUTE_UNUSED)3666 fp_reg_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
3667 {
3668 return reg_renumber && FP_REG_P (op);
3669 }
3670
3671 /* Emit insns to move operands[1] into operands[0].
3672
3673 Return 1 if we have written out everything that needs to be done to
3674 do the move. Otherwise, return 0 and the caller will emit the move
3675 normally.
3676
3677 Note SCRATCH_REG may not be in the proper mode depending on how it
3678 will be used. This routine is responsible for creating a new copy
3679 of SCRATCH_REG in the proper mode. */
3680
3681 int
emit_move_sequence(rtx * operands,machine_mode mode,rtx scratch_reg)3682 emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
3683 {
3684 register rtx operand0 = operands[0];
3685 register rtx operand1 = operands[1];
3686 register rtx tem;
3687
3688 if (scratch_reg
3689 && reload_in_progress && GET_CODE (operand0) == REG
3690 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
3691 operand0 = reg_equiv_mem (REGNO (operand0));
3692 else if (scratch_reg
3693 && reload_in_progress && GET_CODE (operand0) == SUBREG
3694 && GET_CODE (SUBREG_REG (operand0)) == REG
3695 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
3696 {
3697 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3698 the code which tracks sets/uses for delete_output_reload. */
3699 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
3700 reg_equiv_mem (REGNO (SUBREG_REG (operand0))),
3701 SUBREG_BYTE (operand0));
3702 operand0 = alter_subreg (&temp, true);
3703 }
3704
3705 if (scratch_reg
3706 && reload_in_progress && GET_CODE (operand1) == REG
3707 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
3708 operand1 = reg_equiv_mem (REGNO (operand1));
3709 else if (scratch_reg
3710 && reload_in_progress && GET_CODE (operand1) == SUBREG
3711 && GET_CODE (SUBREG_REG (operand1)) == REG
3712 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
3713 {
3714 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3715 the code which tracks sets/uses for delete_output_reload. */
3716 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
3717 reg_equiv_mem (REGNO (SUBREG_REG (operand1))),
3718 SUBREG_BYTE (operand1));
3719 operand1 = alter_subreg (&temp, true);
3720 }
3721
3722 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
3723 && ((tem = find_replacement (&XEXP (operand0, 0)))
3724 != XEXP (operand0, 0)))
3725 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
3726 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
3727 && ((tem = find_replacement (&XEXP (operand1, 0)))
3728 != XEXP (operand1, 0)))
3729 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
3730
3731 /* Handle secondary reloads for loads/stores of FP registers where
3732 the address is symbolic by using the scratch register */
3733 if (fp_reg_operand (operand0, mode)
3734 && ((GET_CODE (operand1) == MEM
3735 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
3736 || ((GET_CODE (operand1) == SUBREG
3737 && GET_CODE (XEXP (operand1, 0)) == MEM
3738 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
3739 && scratch_reg)
3740 {
3741 if (GET_CODE (operand1) == SUBREG)
3742 operand1 = XEXP (operand1, 0);
3743
3744 /* SCRATCH_REG will hold an address. We want
3745 it in SImode regardless of what mode it was originally given
3746 to us. */
3747 scratch_reg = force_mode (SImode, scratch_reg);
3748
3749 /* D might not fit in 14 bits either; for such cases load D into
3750 scratch reg. */
3751 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
3752 {
3753 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
3754 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
3755 Pmode,
3756 XEXP (XEXP (operand1, 0), 0),
3757 scratch_reg));
3758 }
3759 else
3760 emit_move_insn (scratch_reg, XEXP (operand1, 0));
3761 emit_insn (gen_rtx_SET (operand0, gen_rtx_MEM (mode, scratch_reg)));
3762 return 1;
3763 }
3764 else if (fp_reg_operand (operand1, mode)
3765 && ((GET_CODE (operand0) == MEM
3766 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
3767 || ((GET_CODE (operand0) == SUBREG)
3768 && GET_CODE (XEXP (operand0, 0)) == MEM
3769 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
3770 && scratch_reg)
3771 {
3772 if (GET_CODE (operand0) == SUBREG)
3773 operand0 = XEXP (operand0, 0);
3774
3775 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3776 it in SIMODE regardless of what mode it was originally given
3777 to us. */
3778 scratch_reg = force_mode (SImode, scratch_reg);
3779
3780 /* D might not fit in 14 bits either; for such cases load D into
3781 scratch reg. */
3782 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
3783 {
3784 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
3785 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
3786 0)),
3787 Pmode,
3788 XEXP (XEXP (operand0, 0),
3789 0),
3790 scratch_reg));
3791 }
3792 else
3793 emit_move_insn (scratch_reg, XEXP (operand0, 0));
3794 emit_insn (gen_rtx_SET (gen_rtx_MEM (mode, scratch_reg), operand1));
3795 return 1;
3796 }
3797 /* Handle secondary reloads for loads of FP registers from constant
3798 expressions by forcing the constant into memory.
3799
3800 use scratch_reg to hold the address of the memory location.
3801
3802 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3803 NO_REGS when presented with a const_int and an register class
3804 containing only FP registers. Doing so unfortunately creates
3805 more problems than it solves. Fix this for 2.5. */
3806 else if (fp_reg_operand (operand0, mode)
3807 && CONSTANT_P (operand1)
3808 && scratch_reg)
3809 {
3810 rtx xoperands[2];
3811
3812 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3813 it in SIMODE regardless of what mode it was originally given
3814 to us. */
3815 scratch_reg = force_mode (SImode, scratch_reg);
3816
3817 /* Force the constant into memory and put the address of the
3818 memory location into scratch_reg. */
3819 xoperands[0] = scratch_reg;
3820 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
3821 emit_insn (gen_rtx_SET (scratch_reg, xoperands[1]));
3822
3823 /* Now load the destination register. */
3824 emit_insn (gen_rtx_SET (operand0, gen_rtx_MEM (mode, scratch_reg)));
3825 return 1;
3826 }
3827
3828 /* Now have insn-emit do whatever it normally does. */
3829 return 0;
3830 }
3831
3832 /* Split one or more DImode RTL references into pairs of SImode
3833 references. The RTL can be REG, offsettable MEM, integer constant, or
3834 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3835 split and "num" is its length. lo_half and hi_half are output arrays
3836 that parallel "operands". */
3837
3838 void
split_di(rtx operands[],int num,rtx lo_half[],rtx hi_half[])3839 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
3840 {
3841 while (num--)
3842 {
3843 rtx op = operands[num];
3844
3845 /* simplify_subreg refuses to split volatile memory addresses,
3846 but we still have to handle it. */
3847 if (GET_CODE (op) == MEM)
3848 {
3849 lo_half[num] = adjust_address (op, SImode, 4);
3850 hi_half[num] = adjust_address (op, SImode, 0);
3851 }
3852 else
3853 {
3854 lo_half[num] = simplify_gen_subreg (SImode, op,
3855 GET_MODE (op) == VOIDmode
3856 ? DImode : GET_MODE (op), 4);
3857 hi_half[num] = simplify_gen_subreg (SImode, op,
3858 GET_MODE (op) == VOIDmode
3859 ? DImode : GET_MODE (op), 0);
3860 }
3861 }
3862 }
3863
3864 /* Split X into a base and a constant offset, storing them in *BASE
3865 and *OFFSET respectively. */
3866
3867 static void
m68k_split_offset(rtx x,rtx * base,HOST_WIDE_INT * offset)3868 m68k_split_offset (rtx x, rtx *base, HOST_WIDE_INT *offset)
3869 {
3870 *offset = 0;
3871 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
3872 {
3873 *offset += INTVAL (XEXP (x, 1));
3874 x = XEXP (x, 0);
3875 }
3876 *base = x;
3877 }
3878
3879 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3880 instruction. STORE_P says whether the move is a load or store.
3881
3882 If the instruction uses post-increment or pre-decrement addressing,
3883 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3884 adjustment. This adjustment will be made by the first element of
3885 PARALLEL, with the loads or stores starting at element 1. If the
3886 instruction does not use post-increment or pre-decrement addressing,
3887 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3888 start at element 0. */
3889
3890 bool
m68k_movem_pattern_p(rtx pattern,rtx automod_base,HOST_WIDE_INT automod_offset,bool store_p)3891 m68k_movem_pattern_p (rtx pattern, rtx automod_base,
3892 HOST_WIDE_INT automod_offset, bool store_p)
3893 {
3894 rtx base, mem_base, set, mem, reg, last_reg;
3895 HOST_WIDE_INT offset, mem_offset;
3896 int i, first, len;
3897 enum reg_class rclass;
3898
3899 len = XVECLEN (pattern, 0);
3900 first = (automod_base != NULL);
3901
3902 if (automod_base)
3903 {
3904 /* Stores must be pre-decrement and loads must be post-increment. */
3905 if (store_p != (automod_offset < 0))
3906 return false;
3907
3908 /* Work out the base and offset for lowest memory location. */
3909 base = automod_base;
3910 offset = (automod_offset < 0 ? automod_offset : 0);
3911 }
3912 else
3913 {
3914 /* Allow any valid base and offset in the first access. */
3915 base = NULL;
3916 offset = 0;
3917 }
3918
3919 last_reg = NULL;
3920 rclass = NO_REGS;
3921 for (i = first; i < len; i++)
3922 {
3923 /* We need a plain SET. */
3924 set = XVECEXP (pattern, 0, i);
3925 if (GET_CODE (set) != SET)
3926 return false;
3927
3928 /* Check that we have a memory location... */
3929 mem = XEXP (set, !store_p);
3930 if (!MEM_P (mem) || !memory_operand (mem, VOIDmode))
3931 return false;
3932
3933 /* ...with the right address. */
3934 if (base == NULL)
3935 {
3936 m68k_split_offset (XEXP (mem, 0), &base, &offset);
3937 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3938 There are no mode restrictions for 680x0 besides the
3939 automodification rules enforced above. */
3940 if (TARGET_COLDFIRE
3941 && !m68k_legitimate_base_reg_p (base, reload_completed))
3942 return false;
3943 }
3944 else
3945 {
3946 m68k_split_offset (XEXP (mem, 0), &mem_base, &mem_offset);
3947 if (!rtx_equal_p (base, mem_base) || offset != mem_offset)
3948 return false;
3949 }
3950
3951 /* Check that we have a register of the required mode and class. */
3952 reg = XEXP (set, store_p);
3953 if (!REG_P (reg)
3954 || !HARD_REGISTER_P (reg)
3955 || GET_MODE (reg) != reg_raw_mode[REGNO (reg)])
3956 return false;
3957
3958 if (last_reg)
3959 {
3960 /* The register must belong to RCLASS and have a higher number
3961 than the register in the previous SET. */
3962 if (!TEST_HARD_REG_BIT (reg_class_contents[rclass], REGNO (reg))
3963 || REGNO (last_reg) >= REGNO (reg))
3964 return false;
3965 }
3966 else
3967 {
3968 /* Work out which register class we need. */
3969 if (INT_REGNO_P (REGNO (reg)))
3970 rclass = GENERAL_REGS;
3971 else if (FP_REGNO_P (REGNO (reg)))
3972 rclass = FP_REGS;
3973 else
3974 return false;
3975 }
3976
3977 last_reg = reg;
3978 offset += GET_MODE_SIZE (GET_MODE (reg));
3979 }
3980
3981 /* If we have an automodification, check whether the final offset is OK. */
3982 if (automod_base && offset != (automod_offset < 0 ? 0 : automod_offset))
3983 return false;
3984
3985 /* Reject unprofitable cases. */
3986 if (len < first + (rclass == FP_REGS ? MIN_FMOVEM_REGS : MIN_MOVEM_REGS))
3987 return false;
3988
3989 return true;
3990 }
3991
3992 /* Return the assembly code template for a movem or fmovem instruction
3993 whose pattern is given by PATTERN. Store the template's operands
3994 in OPERANDS.
3995
3996 If the instruction uses post-increment or pre-decrement addressing,
3997 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3998 is true if this is a store instruction. */
3999
4000 const char *
m68k_output_movem(rtx * operands,rtx pattern,HOST_WIDE_INT automod_offset,bool store_p)4001 m68k_output_movem (rtx *operands, rtx pattern,
4002 HOST_WIDE_INT automod_offset, bool store_p)
4003 {
4004 unsigned int mask;
4005 int i, first;
4006
4007 gcc_assert (GET_CODE (pattern) == PARALLEL);
4008 mask = 0;
4009 first = (automod_offset != 0);
4010 for (i = first; i < XVECLEN (pattern, 0); i++)
4011 {
4012 /* When using movem with pre-decrement addressing, register X + D0_REG
4013 is controlled by bit 15 - X. For all other addressing modes,
4014 register X + D0_REG is controlled by bit X. Confusingly, the
4015 register mask for fmovem is in the opposite order to that for
4016 movem. */
4017 unsigned int regno;
4018
4019 gcc_assert (MEM_P (XEXP (XVECEXP (pattern, 0, i), !store_p)));
4020 gcc_assert (REG_P (XEXP (XVECEXP (pattern, 0, i), store_p)));
4021 regno = REGNO (XEXP (XVECEXP (pattern, 0, i), store_p));
4022 if (automod_offset < 0)
4023 {
4024 if (FP_REGNO_P (regno))
4025 mask |= 1 << (regno - FP0_REG);
4026 else
4027 mask |= 1 << (15 - (regno - D0_REG));
4028 }
4029 else
4030 {
4031 if (FP_REGNO_P (regno))
4032 mask |= 1 << (7 - (regno - FP0_REG));
4033 else
4034 mask |= 1 << (regno - D0_REG);
4035 }
4036 }
4037 CC_STATUS_INIT;
4038
4039 if (automod_offset == 0)
4040 operands[0] = XEXP (XEXP (XVECEXP (pattern, 0, first), !store_p), 0);
4041 else if (automod_offset < 0)
4042 operands[0] = gen_rtx_PRE_DEC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0)));
4043 else
4044 operands[0] = gen_rtx_POST_INC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0)));
4045 operands[1] = GEN_INT (mask);
4046 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern, 0, first), store_p))))
4047 {
4048 if (store_p)
4049 return "fmovem %1,%a0";
4050 else
4051 return "fmovem %a0,%1";
4052 }
4053 else
4054 {
4055 if (store_p)
4056 return "movem%.l %1,%a0";
4057 else
4058 return "movem%.l %a0,%1";
4059 }
4060 }
4061
4062 /* Return a REG that occurs in ADDR with coefficient 1.
4063 ADDR can be effectively incremented by incrementing REG. */
4064
4065 static rtx
find_addr_reg(rtx addr)4066 find_addr_reg (rtx addr)
4067 {
4068 while (GET_CODE (addr) == PLUS)
4069 {
4070 if (GET_CODE (XEXP (addr, 0)) == REG)
4071 addr = XEXP (addr, 0);
4072 else if (GET_CODE (XEXP (addr, 1)) == REG)
4073 addr = XEXP (addr, 1);
4074 else if (CONSTANT_P (XEXP (addr, 0)))
4075 addr = XEXP (addr, 1);
4076 else if (CONSTANT_P (XEXP (addr, 1)))
4077 addr = XEXP (addr, 0);
4078 else
4079 gcc_unreachable ();
4080 }
4081 gcc_assert (GET_CODE (addr) == REG);
4082 return addr;
4083 }
4084
4085 /* Output assembler code to perform a 32-bit 3-operand add. */
4086
4087 const char *
output_addsi3(rtx * operands)4088 output_addsi3 (rtx *operands)
4089 {
4090 if (! operands_match_p (operands[0], operands[1]))
4091 {
4092 if (!ADDRESS_REG_P (operands[1]))
4093 {
4094 rtx tmp = operands[1];
4095
4096 operands[1] = operands[2];
4097 operands[2] = tmp;
4098 }
4099
4100 /* These insns can result from reloads to access
4101 stack slots over 64k from the frame pointer. */
4102 if (GET_CODE (operands[2]) == CONST_INT
4103 && (INTVAL (operands[2]) < -32768 || INTVAL (operands[2]) > 32767))
4104 return "move%.l %2,%0\n\tadd%.l %1,%0";
4105 if (GET_CODE (operands[2]) == REG)
4106 return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
4107 return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
4108 }
4109 if (GET_CODE (operands[2]) == CONST_INT)
4110 {
4111 if (INTVAL (operands[2]) > 0
4112 && INTVAL (operands[2]) <= 8)
4113 return "addq%.l %2,%0";
4114 if (INTVAL (operands[2]) < 0
4115 && INTVAL (operands[2]) >= -8)
4116 {
4117 operands[2] = GEN_INT (- INTVAL (operands[2]));
4118 return "subq%.l %2,%0";
4119 }
4120 /* On the CPU32 it is faster to use two addql instructions to
4121 add a small integer (8 < N <= 16) to a register.
4122 Likewise for subql. */
4123 if (TUNE_CPU32 && REG_P (operands[0]))
4124 {
4125 if (INTVAL (operands[2]) > 8
4126 && INTVAL (operands[2]) <= 16)
4127 {
4128 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
4129 return "addq%.l #8,%0\n\taddq%.l %2,%0";
4130 }
4131 if (INTVAL (operands[2]) < -8
4132 && INTVAL (operands[2]) >= -16)
4133 {
4134 operands[2] = GEN_INT (- INTVAL (operands[2]) - 8);
4135 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
4136 }
4137 }
4138 if (ADDRESS_REG_P (operands[0])
4139 && INTVAL (operands[2]) >= -0x8000
4140 && INTVAL (operands[2]) < 0x8000)
4141 {
4142 if (TUNE_68040)
4143 return "add%.w %2,%0";
4144 else
4145 return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
4146 }
4147 }
4148 return "add%.l %2,%0";
4149 }
4150
4151 /* Store in cc_status the expressions that the condition codes will
4152 describe after execution of an instruction whose pattern is EXP.
4153 Do not alter them if the instruction would not alter the cc's. */
4154
4155 /* On the 68000, all the insns to store in an address register fail to
4156 set the cc's. However, in some cases these instructions can make it
4157 possibly invalid to use the saved cc's. In those cases we clear out
4158 some or all of the saved cc's so they won't be used. */
4159
4160 void
notice_update_cc(rtx exp,rtx insn)4161 notice_update_cc (rtx exp, rtx insn)
4162 {
4163 if (GET_CODE (exp) == SET)
4164 {
4165 if (GET_CODE (SET_SRC (exp)) == CALL)
4166 CC_STATUS_INIT;
4167 else if (ADDRESS_REG_P (SET_DEST (exp)))
4168 {
4169 if (cc_status.value1 && modified_in_p (cc_status.value1, insn))
4170 cc_status.value1 = 0;
4171 if (cc_status.value2 && modified_in_p (cc_status.value2, insn))
4172 cc_status.value2 = 0;
4173 }
4174 /* fmoves to memory or data registers do not set the condition
4175 codes. Normal moves _do_ set the condition codes, but not in
4176 a way that is appropriate for comparison with 0, because -0.0
4177 would be treated as a negative nonzero number. Note that it
4178 isn't appropriate to conditionalize this restriction on
4179 HONOR_SIGNED_ZEROS because that macro merely indicates whether
4180 we care about the difference between -0.0 and +0.0. */
4181 else if (!FP_REG_P (SET_DEST (exp))
4182 && SET_DEST (exp) != cc0_rtx
4183 && (FP_REG_P (SET_SRC (exp))
4184 || GET_CODE (SET_SRC (exp)) == FIX
4185 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp)))))
4186 CC_STATUS_INIT;
4187 /* A pair of move insns doesn't produce a useful overall cc. */
4188 else if (!FP_REG_P (SET_DEST (exp))
4189 && !FP_REG_P (SET_SRC (exp))
4190 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4
4191 && (GET_CODE (SET_SRC (exp)) == REG
4192 || GET_CODE (SET_SRC (exp)) == MEM
4193 || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE))
4194 CC_STATUS_INIT;
4195 else if (SET_DEST (exp) != pc_rtx)
4196 {
4197 cc_status.flags = 0;
4198 cc_status.value1 = SET_DEST (exp);
4199 cc_status.value2 = SET_SRC (exp);
4200 }
4201 }
4202 else if (GET_CODE (exp) == PARALLEL
4203 && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
4204 {
4205 rtx dest = SET_DEST (XVECEXP (exp, 0, 0));
4206 rtx src = SET_SRC (XVECEXP (exp, 0, 0));
4207
4208 if (ADDRESS_REG_P (dest))
4209 CC_STATUS_INIT;
4210 else if (dest != pc_rtx)
4211 {
4212 cc_status.flags = 0;
4213 cc_status.value1 = dest;
4214 cc_status.value2 = src;
4215 }
4216 }
4217 else
4218 CC_STATUS_INIT;
4219 if (cc_status.value2 != 0
4220 && ADDRESS_REG_P (cc_status.value2)
4221 && GET_MODE (cc_status.value2) == QImode)
4222 CC_STATUS_INIT;
4223 if (cc_status.value2 != 0)
4224 switch (GET_CODE (cc_status.value2))
4225 {
4226 case ASHIFT: case ASHIFTRT: case LSHIFTRT:
4227 case ROTATE: case ROTATERT:
4228 /* These instructions always clear the overflow bit, and set
4229 the carry to the bit shifted out. */
4230 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
4231 break;
4232
4233 case PLUS: case MINUS: case MULT:
4234 case DIV: case UDIV: case MOD: case UMOD: case NEG:
4235 if (GET_MODE (cc_status.value2) != VOIDmode)
4236 cc_status.flags |= CC_NO_OVERFLOW;
4237 break;
4238 case ZERO_EXTEND:
4239 /* (SET r1 (ZERO_EXTEND r2)) on this machine
4240 ends with a move insn moving r2 in r2's mode.
4241 Thus, the cc's are set for r2.
4242 This can set N bit spuriously. */
4243 cc_status.flags |= CC_NOT_NEGATIVE;
4244
4245 default:
4246 break;
4247 }
4248 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG
4249 && cc_status.value2
4250 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
4251 cc_status.value2 = 0;
4252 /* Check for PRE_DEC in dest modifying a register used in src. */
4253 if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM
4254 && GET_CODE (XEXP (cc_status.value1, 0)) == PRE_DEC
4255 && cc_status.value2
4256 && reg_overlap_mentioned_p (XEXP (XEXP (cc_status.value1, 0), 0),
4257 cc_status.value2))
4258 cc_status.value2 = 0;
4259 if (((cc_status.value1 && FP_REG_P (cc_status.value1))
4260 || (cc_status.value2 && FP_REG_P (cc_status.value2))))
4261 cc_status.flags = CC_IN_68881;
4262 if (cc_status.value2 && GET_CODE (cc_status.value2) == COMPARE
4263 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status.value2, 0))) == MODE_FLOAT)
4264 {
4265 cc_status.flags = CC_IN_68881;
4266 if (!FP_REG_P (XEXP (cc_status.value2, 0))
4267 && FP_REG_P (XEXP (cc_status.value2, 1)))
4268 cc_status.flags |= CC_REVERSED;
4269 }
4270 }
4271
4272 const char *
output_move_const_double(rtx * operands)4273 output_move_const_double (rtx *operands)
4274 {
4275 int code = standard_68881_constant_p (operands[1]);
4276
4277 if (code != 0)
4278 {
4279 static char buf[40];
4280
4281 sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff);
4282 return buf;
4283 }
4284 return "fmove%.d %1,%0";
4285 }
4286
4287 const char *
output_move_const_single(rtx * operands)4288 output_move_const_single (rtx *operands)
4289 {
4290 int code = standard_68881_constant_p (operands[1]);
4291
4292 if (code != 0)
4293 {
4294 static char buf[40];
4295
4296 sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff);
4297 return buf;
4298 }
4299 return "fmove%.s %f1,%0";
4300 }
4301
4302 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
4303 from the "fmovecr" instruction.
4304 The value, anded with 0xff, gives the code to use in fmovecr
4305 to get the desired constant. */
4306
4307 /* This code has been fixed for cross-compilation. */
4308
4309 static int inited_68881_table = 0;
4310
4311 static const char *const strings_68881[7] = {
4312 "0.0",
4313 "1.0",
4314 "10.0",
4315 "100.0",
4316 "10000.0",
4317 "1e8",
4318 "1e16"
4319 };
4320
4321 static const int codes_68881[7] = {
4322 0x0f,
4323 0x32,
4324 0x33,
4325 0x34,
4326 0x35,
4327 0x36,
4328 0x37
4329 };
4330
4331 REAL_VALUE_TYPE values_68881[7];
4332
4333 /* Set up values_68881 array by converting the decimal values
4334 strings_68881 to binary. */
4335
4336 void
init_68881_table(void)4337 init_68881_table (void)
4338 {
4339 int i;
4340 REAL_VALUE_TYPE r;
4341 machine_mode mode;
4342
4343 mode = SFmode;
4344 for (i = 0; i < 7; i++)
4345 {
4346 if (i == 6)
4347 mode = DFmode;
4348 r = REAL_VALUE_ATOF (strings_68881[i], mode);
4349 values_68881[i] = r;
4350 }
4351 inited_68881_table = 1;
4352 }
4353
4354 int
standard_68881_constant_p(rtx x)4355 standard_68881_constant_p (rtx x)
4356 {
4357 const REAL_VALUE_TYPE *r;
4358 int i;
4359
4360 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
4361 used at all on those chips. */
4362 if (TUNE_68040_60)
4363 return 0;
4364
4365 if (! inited_68881_table)
4366 init_68881_table ();
4367
4368 r = CONST_DOUBLE_REAL_VALUE (x);
4369
4370 /* Use real_identical instead of real_equal so that -0.0 is rejected. */
4371 for (i = 0; i < 6; i++)
4372 {
4373 if (real_identical (r, &values_68881[i]))
4374 return (codes_68881[i]);
4375 }
4376
4377 if (GET_MODE (x) == SFmode)
4378 return 0;
4379
4380 if (real_equal (r, &values_68881[6]))
4381 return (codes_68881[6]);
4382
4383 /* larger powers of ten in the constants ram are not used
4384 because they are not equal to a `double' C constant. */
4385 return 0;
4386 }
4387
4388 /* If X is a floating-point constant, return the logarithm of X base 2,
4389 or 0 if X is not a power of 2. */
4390
4391 int
floating_exact_log2(rtx x)4392 floating_exact_log2 (rtx x)
4393 {
4394 const REAL_VALUE_TYPE *r;
4395 REAL_VALUE_TYPE r1;
4396 int exp;
4397
4398 r = CONST_DOUBLE_REAL_VALUE (x);
4399
4400 if (real_less (r, &dconst1))
4401 return 0;
4402
4403 exp = real_exponent (r);
4404 real_2expN (&r1, exp, DFmode);
4405 if (real_equal (&r1, r))
4406 return exp;
4407
4408 return 0;
4409 }
4410
4411 /* A C compound statement to output to stdio stream STREAM the
4412 assembler syntax for an instruction operand X. X is an RTL
4413 expression.
4414
4415 CODE is a value that can be used to specify one of several ways
4416 of printing the operand. It is used when identical operands
4417 must be printed differently depending on the context. CODE
4418 comes from the `%' specification that was used to request
4419 printing of the operand. If the specification was just `%DIGIT'
4420 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4421 is the ASCII code for LTR.
4422
4423 If X is a register, this macro should print the register's name.
4424 The names can be found in an array `reg_names' whose type is
4425 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4426
4427 When the machine description has a specification `%PUNCT' (a `%'
4428 followed by a punctuation character), this macro is called with
4429 a null pointer for X and the punctuation character for CODE.
4430
4431 The m68k specific codes are:
4432
4433 '.' for dot needed in Motorola-style opcode names.
4434 '-' for an operand pushing on the stack:
4435 sp@-, -(sp) or -(%sp) depending on the style of syntax.
4436 '+' for an operand pushing on the stack:
4437 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
4438 '@' for a reference to the top word on the stack:
4439 sp@, (sp) or (%sp) depending on the style of syntax.
4440 '#' for an immediate operand prefix (# in MIT and Motorola syntax
4441 but & in SGS syntax).
4442 '!' for the cc register (used in an `and to cc' insn).
4443 '$' for the letter `s' in an op code, but only on the 68040.
4444 '&' for the letter `d' in an op code, but only on the 68040.
4445 '/' for register prefix needed by longlong.h.
4446 '?' for m68k_library_id_string
4447
4448 'b' for byte insn (no effect, on the Sun; this is for the ISI).
4449 'd' to force memory addressing to be absolute, not relative.
4450 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
4451 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
4452 or print pair of registers as rx:ry.
4453 'p' print an address with @PLTPC attached, but only if the operand
4454 is not locally-bound. */
4455
4456 void
print_operand(FILE * file,rtx op,int letter)4457 print_operand (FILE *file, rtx op, int letter)
4458 {
4459 if (letter == '.')
4460 {
4461 if (MOTOROLA)
4462 fprintf (file, ".");
4463 }
4464 else if (letter == '#')
4465 asm_fprintf (file, "%I");
4466 else if (letter == '-')
4467 asm_fprintf (file, MOTOROLA ? "-(%Rsp)" : "%Rsp@-");
4468 else if (letter == '+')
4469 asm_fprintf (file, MOTOROLA ? "(%Rsp)+" : "%Rsp@+");
4470 else if (letter == '@')
4471 asm_fprintf (file, MOTOROLA ? "(%Rsp)" : "%Rsp@");
4472 else if (letter == '!')
4473 asm_fprintf (file, "%Rfpcr");
4474 else if (letter == '$')
4475 {
4476 if (TARGET_68040)
4477 fprintf (file, "s");
4478 }
4479 else if (letter == '&')
4480 {
4481 if (TARGET_68040)
4482 fprintf (file, "d");
4483 }
4484 else if (letter == '/')
4485 asm_fprintf (file, "%R");
4486 else if (letter == '?')
4487 asm_fprintf (file, m68k_library_id_string);
4488 else if (letter == 'p')
4489 {
4490 output_addr_const (file, op);
4491 if (!(GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op)))
4492 fprintf (file, "@PLTPC");
4493 }
4494 else if (GET_CODE (op) == REG)
4495 {
4496 if (letter == 'R')
4497 /* Print out the second register name of a register pair.
4498 I.e., R (6) => 7. */
4499 fputs (M68K_REGNAME(REGNO (op) + 1), file);
4500 else
4501 fputs (M68K_REGNAME(REGNO (op)), file);
4502 }
4503 else if (GET_CODE (op) == MEM)
4504 {
4505 output_address (GET_MODE (op), XEXP (op, 0));
4506 if (letter == 'd' && ! TARGET_68020
4507 && CONSTANT_ADDRESS_P (XEXP (op, 0))
4508 && !(GET_CODE (XEXP (op, 0)) == CONST_INT
4509 && INTVAL (XEXP (op, 0)) < 0x8000
4510 && INTVAL (XEXP (op, 0)) >= -0x8000))
4511 fprintf (file, MOTOROLA ? ".l" : ":l");
4512 }
4513 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode)
4514 {
4515 long l;
4516 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), l);
4517 asm_fprintf (file, "%I0x%lx", l & 0xFFFFFFFF);
4518 }
4519 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode)
4520 {
4521 long l[3];
4522 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
4523 asm_fprintf (file, "%I0x%lx%08lx%08lx", l[0] & 0xFFFFFFFF,
4524 l[1] & 0xFFFFFFFF, l[2] & 0xFFFFFFFF);
4525 }
4526 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode)
4527 {
4528 long l[2];
4529 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
4530 asm_fprintf (file, "%I0x%lx%08lx", l[0] & 0xFFFFFFFF, l[1] & 0xFFFFFFFF);
4531 }
4532 else
4533 {
4534 /* Use `print_operand_address' instead of `output_addr_const'
4535 to ensure that we print relevant PIC stuff. */
4536 asm_fprintf (file, "%I");
4537 if (TARGET_PCREL
4538 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST))
4539 print_operand_address (file, op);
4540 else
4541 output_addr_const (file, op);
4542 }
4543 }
4544
4545 /* Return string for TLS relocation RELOC. */
4546
4547 static const char *
m68k_get_reloc_decoration(enum m68k_reloc reloc)4548 m68k_get_reloc_decoration (enum m68k_reloc reloc)
4549 {
4550 /* To my knowledge, !MOTOROLA assemblers don't support TLS. */
4551 gcc_assert (MOTOROLA || reloc == RELOC_GOT);
4552
4553 switch (reloc)
4554 {
4555 case RELOC_GOT:
4556 if (MOTOROLA)
4557 {
4558 if (flag_pic == 1 && TARGET_68020)
4559 return "@GOT.w";
4560 else
4561 return "@GOT";
4562 }
4563 else
4564 {
4565 if (TARGET_68020)
4566 {
4567 switch (flag_pic)
4568 {
4569 case 1:
4570 return ":w";
4571 case 2:
4572 return ":l";
4573 default:
4574 return "";
4575 }
4576 }
4577 }
4578 gcc_unreachable ();
4579
4580 case RELOC_TLSGD:
4581 return "@TLSGD";
4582
4583 case RELOC_TLSLDM:
4584 return "@TLSLDM";
4585
4586 case RELOC_TLSLDO:
4587 return "@TLSLDO";
4588
4589 case RELOC_TLSIE:
4590 return "@TLSIE";
4591
4592 case RELOC_TLSLE:
4593 return "@TLSLE";
4594
4595 default:
4596 gcc_unreachable ();
4597 }
4598 }
4599
4600 /* m68k implementation of TARGET_OUTPUT_ADDR_CONST_EXTRA. */
4601
4602 static bool
m68k_output_addr_const_extra(FILE * file,rtx x)4603 m68k_output_addr_const_extra (FILE *file, rtx x)
4604 {
4605 if (GET_CODE (x) == UNSPEC)
4606 {
4607 switch (XINT (x, 1))
4608 {
4609 case UNSPEC_RELOC16:
4610 case UNSPEC_RELOC32:
4611 output_addr_const (file, XVECEXP (x, 0, 0));
4612 fputs (m68k_get_reloc_decoration
4613 ((enum m68k_reloc) INTVAL (XVECEXP (x, 0, 1))), file);
4614 return true;
4615
4616 default:
4617 break;
4618 }
4619 }
4620
4621 return false;
4622 }
4623
4624 /* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
4625
4626 static void
m68k_output_dwarf_dtprel(FILE * file,int size,rtx x)4627 m68k_output_dwarf_dtprel (FILE *file, int size, rtx x)
4628 {
4629 gcc_assert (size == 4);
4630 fputs ("\t.long\t", file);
4631 output_addr_const (file, x);
4632 fputs ("@TLSLDO+0x8000", file);
4633 }
4634
4635 /* In the name of slightly smaller debug output, and to cater to
4636 general assembler lossage, recognize various UNSPEC sequences
4637 and turn them back into a direct symbol reference. */
4638
4639 static rtx
m68k_delegitimize_address(rtx orig_x)4640 m68k_delegitimize_address (rtx orig_x)
4641 {
4642 rtx x;
4643 struct m68k_address addr;
4644 rtx unspec;
4645
4646 orig_x = delegitimize_mem_from_attrs (orig_x);
4647 x = orig_x;
4648 if (MEM_P (x))
4649 x = XEXP (x, 0);
4650
4651 if (GET_CODE (x) != PLUS || GET_MODE (x) != Pmode)
4652 return orig_x;
4653
4654 if (!m68k_decompose_address (GET_MODE (x), x, false, &addr)
4655 || addr.offset == NULL_RTX
4656 || GET_CODE (addr.offset) != CONST)
4657 return orig_x;
4658
4659 unspec = XEXP (addr.offset, 0);
4660 if (GET_CODE (unspec) == PLUS && CONST_INT_P (XEXP (unspec, 1)))
4661 unspec = XEXP (unspec, 0);
4662 if (GET_CODE (unspec) != UNSPEC
4663 || (XINT (unspec, 1) != UNSPEC_RELOC16
4664 && XINT (unspec, 1) != UNSPEC_RELOC32))
4665 return orig_x;
4666 x = XVECEXP (unspec, 0, 0);
4667 gcc_assert (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF);
4668 if (unspec != XEXP (addr.offset, 0))
4669 x = gen_rtx_PLUS (Pmode, x, XEXP (XEXP (addr.offset, 0), 1));
4670 if (addr.index)
4671 {
4672 rtx idx = addr.index;
4673 if (addr.scale != 1)
4674 idx = gen_rtx_MULT (Pmode, idx, GEN_INT (addr.scale));
4675 x = gen_rtx_PLUS (Pmode, idx, x);
4676 }
4677 if (addr.base)
4678 x = gen_rtx_PLUS (Pmode, addr.base, x);
4679 if (MEM_P (orig_x))
4680 x = replace_equiv_address_nv (orig_x, x);
4681 return x;
4682 }
4683
4684
4685 /* A C compound statement to output to stdio stream STREAM the
4686 assembler syntax for an instruction operand that is a memory
4687 reference whose address is ADDR. ADDR is an RTL expression.
4688
4689 Note that this contains a kludge that knows that the only reason
4690 we have an address (plus (label_ref...) (reg...)) when not generating
4691 PIC code is in the insn before a tablejump, and we know that m68k.md
4692 generates a label LInnn: on such an insn.
4693
4694 It is possible for PIC to generate a (plus (label_ref...) (reg...))
4695 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
4696
4697 This routine is responsible for distinguishing between -fpic and -fPIC
4698 style relocations in an address. When generating -fpic code the
4699 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
4700 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
4701
4702 void
print_operand_address(FILE * file,rtx addr)4703 print_operand_address (FILE *file, rtx addr)
4704 {
4705 struct m68k_address address;
4706
4707 if (!m68k_decompose_address (QImode, addr, true, &address))
4708 gcc_unreachable ();
4709
4710 if (address.code == PRE_DEC)
4711 fprintf (file, MOTOROLA ? "-(%s)" : "%s@-",
4712 M68K_REGNAME (REGNO (address.base)));
4713 else if (address.code == POST_INC)
4714 fprintf (file, MOTOROLA ? "(%s)+" : "%s@+",
4715 M68K_REGNAME (REGNO (address.base)));
4716 else if (!address.base && !address.index)
4717 {
4718 /* A constant address. */
4719 gcc_assert (address.offset == addr);
4720 if (GET_CODE (addr) == CONST_INT)
4721 {
4722 /* (xxx).w or (xxx).l. */
4723 if (IN_RANGE (INTVAL (addr), -0x8000, 0x7fff))
4724 fprintf (file, MOTOROLA ? "%d.w" : "%d:w", (int) INTVAL (addr));
4725 else
4726 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (addr));
4727 }
4728 else if (TARGET_PCREL)
4729 {
4730 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
4731 fputc ('(', file);
4732 output_addr_const (file, addr);
4733 asm_fprintf (file, flag_pic == 1 ? ":w,%Rpc)" : ":l,%Rpc)");
4734 }
4735 else
4736 {
4737 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
4738 name ends in `.<letter>', as the last 2 characters can be
4739 mistaken as a size suffix. Put the name in parentheses. */
4740 if (GET_CODE (addr) == SYMBOL_REF
4741 && strlen (XSTR (addr, 0)) > 2
4742 && XSTR (addr, 0)[strlen (XSTR (addr, 0)) - 2] == '.')
4743 {
4744 putc ('(', file);
4745 output_addr_const (file, addr);
4746 putc (')', file);
4747 }
4748 else
4749 output_addr_const (file, addr);
4750 }
4751 }
4752 else
4753 {
4754 int labelno;
4755
4756 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
4757 label being accessed, otherwise it is -1. */
4758 labelno = (address.offset
4759 && !address.base
4760 && GET_CODE (address.offset) == LABEL_REF
4761 ? CODE_LABEL_NUMBER (XEXP (address.offset, 0))
4762 : -1);
4763 if (MOTOROLA)
4764 {
4765 /* Print the "offset(base" component. */
4766 if (labelno >= 0)
4767 asm_fprintf (file, "%LL%d(%Rpc,", labelno);
4768 else
4769 {
4770 if (address.offset)
4771 output_addr_const (file, address.offset);
4772
4773 putc ('(', file);
4774 if (address.base)
4775 fputs (M68K_REGNAME (REGNO (address.base)), file);
4776 }
4777 /* Print the ",index" component, if any. */
4778 if (address.index)
4779 {
4780 if (address.base)
4781 putc (',', file);
4782 fprintf (file, "%s.%c",
4783 M68K_REGNAME (REGNO (address.index)),
4784 GET_MODE (address.index) == HImode ? 'w' : 'l');
4785 if (address.scale != 1)
4786 fprintf (file, "*%d", address.scale);
4787 }
4788 putc (')', file);
4789 }
4790 else /* !MOTOROLA */
4791 {
4792 if (!address.offset && !address.index)
4793 fprintf (file, "%s@", M68K_REGNAME (REGNO (address.base)));
4794 else
4795 {
4796 /* Print the "base@(offset" component. */
4797 if (labelno >= 0)
4798 asm_fprintf (file, "%Rpc@(%LL%d", labelno);
4799 else
4800 {
4801 if (address.base)
4802 fputs (M68K_REGNAME (REGNO (address.base)), file);
4803 fprintf (file, "@(");
4804 if (address.offset)
4805 output_addr_const (file, address.offset);
4806 }
4807 /* Print the ",index" component, if any. */
4808 if (address.index)
4809 {
4810 fprintf (file, ",%s:%c",
4811 M68K_REGNAME (REGNO (address.index)),
4812 GET_MODE (address.index) == HImode ? 'w' : 'l');
4813 if (address.scale != 1)
4814 fprintf (file, ":%d", address.scale);
4815 }
4816 putc (')', file);
4817 }
4818 }
4819 }
4820 }
4821
4822 /* Check for cases where a clr insns can be omitted from code using
4823 strict_low_part sets. For example, the second clrl here is not needed:
4824 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
4825
4826 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
4827 insn we are checking for redundancy. TARGET is the register set by the
4828 clear insn. */
4829
4830 bool
strict_low_part_peephole_ok(machine_mode mode,rtx_insn * first_insn,rtx target)4831 strict_low_part_peephole_ok (machine_mode mode, rtx_insn *first_insn,
4832 rtx target)
4833 {
4834 rtx_insn *p = first_insn;
4835
4836 while ((p = PREV_INSN (p)))
4837 {
4838 if (NOTE_INSN_BASIC_BLOCK_P (p))
4839 return false;
4840
4841 if (NOTE_P (p))
4842 continue;
4843
4844 /* If it isn't an insn, then give up. */
4845 if (!INSN_P (p))
4846 return false;
4847
4848 if (reg_set_p (target, p))
4849 {
4850 rtx set = single_set (p);
4851 rtx dest;
4852
4853 /* If it isn't an easy to recognize insn, then give up. */
4854 if (! set)
4855 return false;
4856
4857 dest = SET_DEST (set);
4858
4859 /* If this sets the entire target register to zero, then our
4860 first_insn is redundant. */
4861 if (rtx_equal_p (dest, target)
4862 && SET_SRC (set) == const0_rtx)
4863 return true;
4864 else if (GET_CODE (dest) == STRICT_LOW_PART
4865 && GET_CODE (XEXP (dest, 0)) == REG
4866 && REGNO (XEXP (dest, 0)) == REGNO (target)
4867 && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0)))
4868 <= GET_MODE_SIZE (mode)))
4869 /* This is a strict low part set which modifies less than
4870 we are using, so it is safe. */
4871 ;
4872 else
4873 return false;
4874 }
4875 }
4876
4877 return false;
4878 }
4879
4880 /* Operand predicates for implementing asymmetric pc-relative addressing
4881 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4882 when used as a source operand, but not as a destination operand.
4883
4884 We model this by restricting the meaning of the basic predicates
4885 (general_operand, memory_operand, etc) to forbid the use of this
4886 addressing mode, and then define the following predicates that permit
4887 this addressing mode. These predicates can then be used for the
4888 source operands of the appropriate instructions.
4889
4890 n.b. While it is theoretically possible to change all machine patterns
4891 to use this addressing more where permitted by the architecture,
4892 it has only been implemented for "common" cases: SImode, HImode, and
4893 QImode operands, and only for the principle operations that would
4894 require this addressing mode: data movement and simple integer operations.
4895
4896 In parallel with these new predicates, two new constraint letters
4897 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4898 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4899 In the pcrel case 's' is only valid in combination with 'a' registers.
4900 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4901 of how these constraints are used.
4902
4903 The use of these predicates is strictly optional, though patterns that
4904 don't will cause an extra reload register to be allocated where one
4905 was not necessary:
4906
4907 lea (abc:w,%pc),%a0 ; need to reload address
4908 moveq &1,%d1 ; since write to pc-relative space
4909 movel %d1,%a0@ ; is not allowed
4910 ...
4911 lea (abc:w,%pc),%a1 ; no need to reload address here
4912 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4913
4914 For more info, consult tiemann@cygnus.com.
4915
4916
4917 All of the ugliness with predicates and constraints is due to the
4918 simple fact that the m68k does not allow a pc-relative addressing
4919 mode as a destination. gcc does not distinguish between source and
4920 destination addresses. Hence, if we claim that pc-relative address
4921 modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we
4922 end up with invalid code. To get around this problem, we left
4923 pc-relative modes as invalid addresses, and then added special
4924 predicates and constraints to accept them.
4925
4926 A cleaner way to handle this is to modify gcc to distinguish
4927 between source and destination addresses. We can then say that
4928 pc-relative is a valid source address but not a valid destination
4929 address, and hopefully avoid a lot of the predicate and constraint
4930 hackery. Unfortunately, this would be a pretty big change. It would
4931 be a useful change for a number of ports, but there aren't any current
4932 plans to undertake this.
4933
4934 ***************************************************************************/
4935
4936
4937 const char *
output_andsi3(rtx * operands)4938 output_andsi3 (rtx *operands)
4939 {
4940 int logval;
4941 if (GET_CODE (operands[2]) == CONST_INT
4942 && (INTVAL (operands[2]) | 0xffff) == -1
4943 && (DATA_REG_P (operands[0])
4944 || offsettable_memref_p (operands[0]))
4945 && !TARGET_COLDFIRE)
4946 {
4947 if (GET_CODE (operands[0]) != REG)
4948 operands[0] = adjust_address (operands[0], HImode, 2);
4949 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
4950 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4951 CC_STATUS_INIT;
4952 if (operands[2] == const0_rtx)
4953 return "clr%.w %0";
4954 return "and%.w %2,%0";
4955 }
4956 if (GET_CODE (operands[2]) == CONST_INT
4957 && (logval = exact_log2 (~ INTVAL (operands[2]) & 0xffffffff)) >= 0
4958 && (DATA_REG_P (operands[0])
4959 || offsettable_memref_p (operands[0])))
4960 {
4961 if (DATA_REG_P (operands[0]))
4962 operands[1] = GEN_INT (logval);
4963 else
4964 {
4965 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
4966 operands[1] = GEN_INT (logval % 8);
4967 }
4968 /* This does not set condition codes in a standard way. */
4969 CC_STATUS_INIT;
4970 return "bclr %1,%0";
4971 }
4972 return "and%.l %2,%0";
4973 }
4974
4975 const char *
output_iorsi3(rtx * operands)4976 output_iorsi3 (rtx *operands)
4977 {
4978 register int logval;
4979 if (GET_CODE (operands[2]) == CONST_INT
4980 && INTVAL (operands[2]) >> 16 == 0
4981 && (DATA_REG_P (operands[0])
4982 || offsettable_memref_p (operands[0]))
4983 && !TARGET_COLDFIRE)
4984 {
4985 if (GET_CODE (operands[0]) != REG)
4986 operands[0] = adjust_address (operands[0], HImode, 2);
4987 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4988 CC_STATUS_INIT;
4989 if (INTVAL (operands[2]) == 0xffff)
4990 return "mov%.w %2,%0";
4991 return "or%.w %2,%0";
4992 }
4993 if (GET_CODE (operands[2]) == CONST_INT
4994 && (logval = exact_log2 (INTVAL (operands[2]) & 0xffffffff)) >= 0
4995 && (DATA_REG_P (operands[0])
4996 || offsettable_memref_p (operands[0])))
4997 {
4998 if (DATA_REG_P (operands[0]))
4999 operands[1] = GEN_INT (logval);
5000 else
5001 {
5002 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
5003 operands[1] = GEN_INT (logval % 8);
5004 }
5005 CC_STATUS_INIT;
5006 return "bset %1,%0";
5007 }
5008 return "or%.l %2,%0";
5009 }
5010
5011 const char *
output_xorsi3(rtx * operands)5012 output_xorsi3 (rtx *operands)
5013 {
5014 register int logval;
5015 if (GET_CODE (operands[2]) == CONST_INT
5016 && INTVAL (operands[2]) >> 16 == 0
5017 && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0]))
5018 && !TARGET_COLDFIRE)
5019 {
5020 if (! DATA_REG_P (operands[0]))
5021 operands[0] = adjust_address (operands[0], HImode, 2);
5022 /* Do not delete a following tstl %0 insn; that would be incorrect. */
5023 CC_STATUS_INIT;
5024 if (INTVAL (operands[2]) == 0xffff)
5025 return "not%.w %0";
5026 return "eor%.w %2,%0";
5027 }
5028 if (GET_CODE (operands[2]) == CONST_INT
5029 && (logval = exact_log2 (INTVAL (operands[2]) & 0xffffffff)) >= 0
5030 && (DATA_REG_P (operands[0])
5031 || offsettable_memref_p (operands[0])))
5032 {
5033 if (DATA_REG_P (operands[0]))
5034 operands[1] = GEN_INT (logval);
5035 else
5036 {
5037 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
5038 operands[1] = GEN_INT (logval % 8);
5039 }
5040 CC_STATUS_INIT;
5041 return "bchg %1,%0";
5042 }
5043 return "eor%.l %2,%0";
5044 }
5045
5046 /* Return the instruction that should be used for a call to address X,
5047 which is known to be in operand 0. */
5048
5049 const char *
output_call(rtx x)5050 output_call (rtx x)
5051 {
5052 if (symbolic_operand (x, VOIDmode))
5053 return m68k_symbolic_call;
5054 else
5055 return "jsr %a0";
5056 }
5057
5058 /* Likewise sibling calls. */
5059
5060 const char *
output_sibcall(rtx x)5061 output_sibcall (rtx x)
5062 {
5063 if (symbolic_operand (x, VOIDmode))
5064 return m68k_symbolic_jump;
5065 else
5066 return "jmp %a0";
5067 }
5068
5069 static void
m68k_output_mi_thunk(FILE * file,tree thunk ATTRIBUTE_UNUSED,HOST_WIDE_INT delta,HOST_WIDE_INT vcall_offset,tree function)5070 m68k_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
5071 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
5072 tree function)
5073 {
5074 rtx this_slot, offset, addr, mem, tmp;
5075 rtx_insn *insn;
5076
5077 /* Avoid clobbering the struct value reg by using the
5078 static chain reg as a temporary. */
5079 tmp = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
5080
5081 /* Pretend to be a post-reload pass while generating rtl. */
5082 reload_completed = 1;
5083
5084 /* The "this" pointer is stored at 4(%sp). */
5085 this_slot = gen_rtx_MEM (Pmode, plus_constant (Pmode,
5086 stack_pointer_rtx, 4));
5087
5088 /* Add DELTA to THIS. */
5089 if (delta != 0)
5090 {
5091 /* Make the offset a legitimate operand for memory addition. */
5092 offset = GEN_INT (delta);
5093 if ((delta < -8 || delta > 8)
5094 && (TARGET_COLDFIRE || USE_MOVQ (delta)))
5095 {
5096 emit_move_insn (gen_rtx_REG (Pmode, D0_REG), offset);
5097 offset = gen_rtx_REG (Pmode, D0_REG);
5098 }
5099 emit_insn (gen_add3_insn (copy_rtx (this_slot),
5100 copy_rtx (this_slot), offset));
5101 }
5102
5103 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
5104 if (vcall_offset != 0)
5105 {
5106 /* Set the static chain register to *THIS. */
5107 emit_move_insn (tmp, this_slot);
5108 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
5109
5110 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
5111 addr = plus_constant (Pmode, tmp, vcall_offset);
5112 if (!m68k_legitimate_address_p (Pmode, addr, true))
5113 {
5114 emit_insn (gen_rtx_SET (tmp, addr));
5115 addr = tmp;
5116 }
5117
5118 /* Load the offset into %d0 and add it to THIS. */
5119 emit_move_insn (gen_rtx_REG (Pmode, D0_REG),
5120 gen_rtx_MEM (Pmode, addr));
5121 emit_insn (gen_add3_insn (copy_rtx (this_slot),
5122 copy_rtx (this_slot),
5123 gen_rtx_REG (Pmode, D0_REG)));
5124 }
5125
5126 /* Jump to the target function. Use a sibcall if direct jumps are
5127 allowed, otherwise load the address into a register first. */
5128 mem = DECL_RTL (function);
5129 if (!sibcall_operand (XEXP (mem, 0), VOIDmode))
5130 {
5131 gcc_assert (flag_pic);
5132
5133 if (!TARGET_SEP_DATA)
5134 {
5135 /* Use the static chain register as a temporary (call-clobbered)
5136 GOT pointer for this function. We can use the static chain
5137 register because it isn't live on entry to the thunk. */
5138 SET_REGNO (pic_offset_table_rtx, STATIC_CHAIN_REGNUM);
5139 emit_insn (gen_load_got (pic_offset_table_rtx));
5140 }
5141 legitimize_pic_address (XEXP (mem, 0), Pmode, tmp);
5142 mem = replace_equiv_address (mem, tmp);
5143 }
5144 insn = emit_call_insn (gen_sibcall (mem, const0_rtx));
5145 SIBLING_CALL_P (insn) = 1;
5146
5147 /* Run just enough of rest_of_compilation. */
5148 insn = get_insns ();
5149 split_all_insns_noflow ();
5150 final_start_function (insn, file, 1);
5151 final (insn, file, 1);
5152 final_end_function ();
5153
5154 /* Clean up the vars set above. */
5155 reload_completed = 0;
5156
5157 /* Restore the original PIC register. */
5158 if (flag_pic)
5159 SET_REGNO (pic_offset_table_rtx, PIC_REG);
5160 }
5161
5162 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5163
5164 static rtx
m68k_struct_value_rtx(tree fntype ATTRIBUTE_UNUSED,int incoming ATTRIBUTE_UNUSED)5165 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
5166 int incoming ATTRIBUTE_UNUSED)
5167 {
5168 return gen_rtx_REG (Pmode, M68K_STRUCT_VALUE_REGNUM);
5169 }
5170
5171 /* Return nonzero if register old_reg can be renamed to register new_reg. */
5172 int
m68k_hard_regno_rename_ok(unsigned int old_reg ATTRIBUTE_UNUSED,unsigned int new_reg)5173 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
5174 unsigned int new_reg)
5175 {
5176
5177 /* Interrupt functions can only use registers that have already been
5178 saved by the prologue, even if they would normally be
5179 call-clobbered. */
5180
5181 if ((m68k_get_function_kind (current_function_decl)
5182 == m68k_fk_interrupt_handler)
5183 && !df_regs_ever_live_p (new_reg))
5184 return 0;
5185
5186 return 1;
5187 }
5188
5189 /* Implement TARGET_HARD_REGNO_NREGS.
5190
5191 On the m68k, ordinary registers hold 32 bits worth;
5192 for the 68881 registers, a single register is always enough for
5193 anything that can be stored in them at all. */
5194
5195 static unsigned int
m68k_hard_regno_nregs(unsigned int regno,machine_mode mode)5196 m68k_hard_regno_nregs (unsigned int regno, machine_mode mode)
5197 {
5198 if (regno >= 16)
5199 return GET_MODE_NUNITS (mode);
5200 return CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD);
5201 }
5202
5203 /* Implement TARGET_HARD_REGNO_MODE_OK. On the 68000, we let the cpu
5204 registers can hold any mode, but restrict the 68881 registers to
5205 floating-point modes. */
5206
5207 static bool
m68k_hard_regno_mode_ok(unsigned int regno,machine_mode mode)5208 m68k_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
5209 {
5210 if (DATA_REGNO_P (regno))
5211 {
5212 /* Data Registers, can hold aggregate if fits in. */
5213 if (regno + GET_MODE_SIZE (mode) / 4 <= 8)
5214 return true;
5215 }
5216 else if (ADDRESS_REGNO_P (regno))
5217 {
5218 if (regno + GET_MODE_SIZE (mode) / 4 <= 16)
5219 return true;
5220 }
5221 else if (FP_REGNO_P (regno))
5222 {
5223 /* FPU registers, hold float or complex float of long double or
5224 smaller. */
5225 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
5226 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5227 && GET_MODE_UNIT_SIZE (mode) <= TARGET_FP_REG_SIZE)
5228 return true;
5229 }
5230 return false;
5231 }
5232
5233 /* Implement TARGET_MODES_TIEABLE_P. */
5234
5235 static bool
m68k_modes_tieable_p(machine_mode mode1,machine_mode mode2)5236 m68k_modes_tieable_p (machine_mode mode1, machine_mode mode2)
5237 {
5238 return (!TARGET_HARD_FLOAT
5239 || ((GET_MODE_CLASS (mode1) == MODE_FLOAT
5240 || GET_MODE_CLASS (mode1) == MODE_COMPLEX_FLOAT)
5241 == (GET_MODE_CLASS (mode2) == MODE_FLOAT
5242 || GET_MODE_CLASS (mode2) == MODE_COMPLEX_FLOAT)));
5243 }
5244
5245 /* Implement SECONDARY_RELOAD_CLASS. */
5246
5247 enum reg_class
m68k_secondary_reload_class(enum reg_class rclass,machine_mode mode,rtx x)5248 m68k_secondary_reload_class (enum reg_class rclass,
5249 machine_mode mode, rtx x)
5250 {
5251 int regno;
5252
5253 regno = true_regnum (x);
5254
5255 /* If one operand of a movqi is an address register, the other
5256 operand must be a general register or constant. Other types
5257 of operand must be reloaded through a data register. */
5258 if (GET_MODE_SIZE (mode) == 1
5259 && reg_classes_intersect_p (rclass, ADDR_REGS)
5260 && !(INT_REGNO_P (regno) || CONSTANT_P (x)))
5261 return DATA_REGS;
5262
5263 /* PC-relative addresses must be loaded into an address register first. */
5264 if (TARGET_PCREL
5265 && !reg_class_subset_p (rclass, ADDR_REGS)
5266 && symbolic_operand (x, VOIDmode))
5267 return ADDR_REGS;
5268
5269 return NO_REGS;
5270 }
5271
5272 /* Implement PREFERRED_RELOAD_CLASS. */
5273
5274 enum reg_class
m68k_preferred_reload_class(rtx x,enum reg_class rclass)5275 m68k_preferred_reload_class (rtx x, enum reg_class rclass)
5276 {
5277 enum reg_class secondary_class;
5278
5279 /* If RCLASS might need a secondary reload, try restricting it to
5280 a class that doesn't. */
5281 secondary_class = m68k_secondary_reload_class (rclass, GET_MODE (x), x);
5282 if (secondary_class != NO_REGS
5283 && reg_class_subset_p (secondary_class, rclass))
5284 return secondary_class;
5285
5286 /* Prefer to use moveq for in-range constants. */
5287 if (GET_CODE (x) == CONST_INT
5288 && reg_class_subset_p (DATA_REGS, rclass)
5289 && IN_RANGE (INTVAL (x), -0x80, 0x7f))
5290 return DATA_REGS;
5291
5292 /* ??? Do we really need this now? */
5293 if (GET_CODE (x) == CONST_DOUBLE
5294 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
5295 {
5296 if (TARGET_HARD_FLOAT && reg_class_subset_p (FP_REGS, rclass))
5297 return FP_REGS;
5298
5299 return NO_REGS;
5300 }
5301
5302 return rclass;
5303 }
5304
5305 /* Return floating point values in a 68881 register. This makes 68881 code
5306 a little bit faster. It also makes -msoft-float code incompatible with
5307 hard-float code, so people have to be careful not to mix the two.
5308 For ColdFire it was decided the ABI incompatibility is undesirable.
5309 If there is need for a hard-float ABI it is probably worth doing it
5310 properly and also passing function arguments in FP registers. */
5311 rtx
m68k_libcall_value(machine_mode mode)5312 m68k_libcall_value (machine_mode mode)
5313 {
5314 switch (mode) {
5315 case E_SFmode:
5316 case E_DFmode:
5317 case E_XFmode:
5318 if (TARGET_68881)
5319 return gen_rtx_REG (mode, FP0_REG);
5320 break;
5321 default:
5322 break;
5323 }
5324
5325 return gen_rtx_REG (mode, m68k_libcall_value_in_a0_p ? A0_REG : D0_REG);
5326 }
5327
5328 /* Location in which function value is returned.
5329 NOTE: Due to differences in ABIs, don't call this function directly,
5330 use FUNCTION_VALUE instead. */
5331 rtx
m68k_function_value(const_tree valtype,const_tree func ATTRIBUTE_UNUSED)5332 m68k_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED)
5333 {
5334 machine_mode mode;
5335
5336 mode = TYPE_MODE (valtype);
5337 switch (mode) {
5338 case E_SFmode:
5339 case E_DFmode:
5340 case E_XFmode:
5341 if (TARGET_68881)
5342 return gen_rtx_REG (mode, FP0_REG);
5343 break;
5344 default:
5345 break;
5346 }
5347
5348 /* If the function returns a pointer, push that into %a0. */
5349 if (func && POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func))))
5350 /* For compatibility with the large body of existing code which
5351 does not always properly declare external functions returning
5352 pointer types, the m68k/SVR4 convention is to copy the value
5353 returned for pointer functions from a0 to d0 in the function
5354 epilogue, so that callers that have neglected to properly
5355 declare the callee can still find the correct return value in
5356 d0. */
5357 return gen_rtx_PARALLEL
5358 (mode,
5359 gen_rtvec (2,
5360 gen_rtx_EXPR_LIST (VOIDmode,
5361 gen_rtx_REG (mode, A0_REG),
5362 const0_rtx),
5363 gen_rtx_EXPR_LIST (VOIDmode,
5364 gen_rtx_REG (mode, D0_REG),
5365 const0_rtx)));
5366 else if (POINTER_TYPE_P (valtype))
5367 return gen_rtx_REG (mode, A0_REG);
5368 else
5369 return gen_rtx_REG (mode, D0_REG);
5370 }
5371
5372 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5373 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
5374 static bool
m68k_return_in_memory(const_tree type,const_tree fntype ATTRIBUTE_UNUSED)5375 m68k_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
5376 {
5377 machine_mode mode = TYPE_MODE (type);
5378
5379 if (mode == BLKmode)
5380 return true;
5381
5382 /* If TYPE's known alignment is less than the alignment of MODE that
5383 would contain the structure, then return in memory. We need to
5384 do so to maintain the compatibility between code compiled with
5385 -mstrict-align and that compiled with -mno-strict-align. */
5386 if (AGGREGATE_TYPE_P (type)
5387 && TYPE_ALIGN (type) < GET_MODE_ALIGNMENT (mode))
5388 return true;
5389
5390 return false;
5391 }
5392 #endif
5393
5394 /* CPU to schedule the program for. */
5395 enum attr_cpu m68k_sched_cpu;
5396
5397 /* MAC to schedule the program for. */
5398 enum attr_mac m68k_sched_mac;
5399
5400 /* Operand type. */
5401 enum attr_op_type
5402 {
5403 /* No operand. */
5404 OP_TYPE_NONE,
5405
5406 /* Integer register. */
5407 OP_TYPE_RN,
5408
5409 /* FP register. */
5410 OP_TYPE_FPN,
5411
5412 /* Implicit mem reference (e.g. stack). */
5413 OP_TYPE_MEM1,
5414
5415 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
5416 OP_TYPE_MEM234,
5417
5418 /* Memory with offset but without indexing. EA mode 5. */
5419 OP_TYPE_MEM5,
5420
5421 /* Memory with indexing. EA mode 6. */
5422 OP_TYPE_MEM6,
5423
5424 /* Memory referenced by absolute address. EA mode 7. */
5425 OP_TYPE_MEM7,
5426
5427 /* Immediate operand that doesn't require extension word. */
5428 OP_TYPE_IMM_Q,
5429
5430 /* Immediate 16 bit operand. */
5431 OP_TYPE_IMM_W,
5432
5433 /* Immediate 32 bit operand. */
5434 OP_TYPE_IMM_L
5435 };
5436
5437 /* Return type of memory ADDR_RTX refers to. */
5438 static enum attr_op_type
sched_address_type(machine_mode mode,rtx addr_rtx)5439 sched_address_type (machine_mode mode, rtx addr_rtx)
5440 {
5441 struct m68k_address address;
5442
5443 if (symbolic_operand (addr_rtx, VOIDmode))
5444 return OP_TYPE_MEM7;
5445
5446 if (!m68k_decompose_address (mode, addr_rtx,
5447 reload_completed, &address))
5448 {
5449 gcc_assert (!reload_completed);
5450 /* Reload will likely fix the address to be in the register. */
5451 return OP_TYPE_MEM234;
5452 }
5453
5454 if (address.scale != 0)
5455 return OP_TYPE_MEM6;
5456
5457 if (address.base != NULL_RTX)
5458 {
5459 if (address.offset == NULL_RTX)
5460 return OP_TYPE_MEM234;
5461
5462 return OP_TYPE_MEM5;
5463 }
5464
5465 gcc_assert (address.offset != NULL_RTX);
5466
5467 return OP_TYPE_MEM7;
5468 }
5469
5470 /* Return X or Y (depending on OPX_P) operand of INSN. */
5471 static rtx
sched_get_operand(rtx_insn * insn,bool opx_p)5472 sched_get_operand (rtx_insn *insn, bool opx_p)
5473 {
5474 int i;
5475
5476 if (recog_memoized (insn) < 0)
5477 gcc_unreachable ();
5478
5479 extract_constrain_insn_cached (insn);
5480
5481 if (opx_p)
5482 i = get_attr_opx (insn);
5483 else
5484 i = get_attr_opy (insn);
5485
5486 if (i >= recog_data.n_operands)
5487 return NULL;
5488
5489 return recog_data.operand[i];
5490 }
5491
5492 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
5493 If ADDRESS_P is true, return type of memory location operand refers to. */
5494 static enum attr_op_type
sched_attr_op_type(rtx_insn * insn,bool opx_p,bool address_p)5495 sched_attr_op_type (rtx_insn *insn, bool opx_p, bool address_p)
5496 {
5497 rtx op;
5498
5499 op = sched_get_operand (insn, opx_p);
5500
5501 if (op == NULL)
5502 {
5503 gcc_assert (!reload_completed);
5504 return OP_TYPE_RN;
5505 }
5506
5507 if (address_p)
5508 return sched_address_type (QImode, op);
5509
5510 if (memory_operand (op, VOIDmode))
5511 return sched_address_type (GET_MODE (op), XEXP (op, 0));
5512
5513 if (register_operand (op, VOIDmode))
5514 {
5515 if ((!reload_completed && FLOAT_MODE_P (GET_MODE (op)))
5516 || (reload_completed && FP_REG_P (op)))
5517 return OP_TYPE_FPN;
5518
5519 return OP_TYPE_RN;
5520 }
5521
5522 if (GET_CODE (op) == CONST_INT)
5523 {
5524 int ival;
5525
5526 ival = INTVAL (op);
5527
5528 /* Check for quick constants. */
5529 switch (get_attr_type (insn))
5530 {
5531 case TYPE_ALUQ_L:
5532 if (IN_RANGE (ival, 1, 8) || IN_RANGE (ival, -8, -1))
5533 return OP_TYPE_IMM_Q;
5534
5535 gcc_assert (!reload_completed);
5536 break;
5537
5538 case TYPE_MOVEQ_L:
5539 if (USE_MOVQ (ival))
5540 return OP_TYPE_IMM_Q;
5541
5542 gcc_assert (!reload_completed);
5543 break;
5544
5545 case TYPE_MOV3Q_L:
5546 if (valid_mov3q_const (ival))
5547 return OP_TYPE_IMM_Q;
5548
5549 gcc_assert (!reload_completed);
5550 break;
5551
5552 default:
5553 break;
5554 }
5555
5556 if (IN_RANGE (ival, -0x8000, 0x7fff))
5557 return OP_TYPE_IMM_W;
5558
5559 return OP_TYPE_IMM_L;
5560 }
5561
5562 if (GET_CODE (op) == CONST_DOUBLE)
5563 {
5564 switch (GET_MODE (op))
5565 {
5566 case E_SFmode:
5567 return OP_TYPE_IMM_W;
5568
5569 case E_VOIDmode:
5570 case E_DFmode:
5571 return OP_TYPE_IMM_L;
5572
5573 default:
5574 gcc_unreachable ();
5575 }
5576 }
5577
5578 if (GET_CODE (op) == CONST
5579 || symbolic_operand (op, VOIDmode)
5580 || LABEL_P (op))
5581 {
5582 switch (GET_MODE (op))
5583 {
5584 case E_QImode:
5585 return OP_TYPE_IMM_Q;
5586
5587 case E_HImode:
5588 return OP_TYPE_IMM_W;
5589
5590 case E_SImode:
5591 return OP_TYPE_IMM_L;
5592
5593 default:
5594 if (symbolic_operand (m68k_unwrap_symbol (op, false), VOIDmode))
5595 /* Just a guess. */
5596 return OP_TYPE_IMM_W;
5597
5598 return OP_TYPE_IMM_L;
5599 }
5600 }
5601
5602 gcc_assert (!reload_completed);
5603
5604 if (FLOAT_MODE_P (GET_MODE (op)))
5605 return OP_TYPE_FPN;
5606
5607 return OP_TYPE_RN;
5608 }
5609
5610 /* Implement opx_type attribute.
5611 Return type of INSN's operand X.
5612 If ADDRESS_P is true, return type of memory location operand refers to. */
5613 enum attr_opx_type
m68k_sched_attr_opx_type(rtx_insn * insn,int address_p)5614 m68k_sched_attr_opx_type (rtx_insn *insn, int address_p)
5615 {
5616 switch (sched_attr_op_type (insn, true, address_p != 0))
5617 {
5618 case OP_TYPE_RN:
5619 return OPX_TYPE_RN;
5620
5621 case OP_TYPE_FPN:
5622 return OPX_TYPE_FPN;
5623
5624 case OP_TYPE_MEM1:
5625 return OPX_TYPE_MEM1;
5626
5627 case OP_TYPE_MEM234:
5628 return OPX_TYPE_MEM234;
5629
5630 case OP_TYPE_MEM5:
5631 return OPX_TYPE_MEM5;
5632
5633 case OP_TYPE_MEM6:
5634 return OPX_TYPE_MEM6;
5635
5636 case OP_TYPE_MEM7:
5637 return OPX_TYPE_MEM7;
5638
5639 case OP_TYPE_IMM_Q:
5640 return OPX_TYPE_IMM_Q;
5641
5642 case OP_TYPE_IMM_W:
5643 return OPX_TYPE_IMM_W;
5644
5645 case OP_TYPE_IMM_L:
5646 return OPX_TYPE_IMM_L;
5647
5648 default:
5649 gcc_unreachable ();
5650 }
5651 }
5652
5653 /* Implement opy_type attribute.
5654 Return type of INSN's operand Y.
5655 If ADDRESS_P is true, return type of memory location operand refers to. */
5656 enum attr_opy_type
m68k_sched_attr_opy_type(rtx_insn * insn,int address_p)5657 m68k_sched_attr_opy_type (rtx_insn *insn, int address_p)
5658 {
5659 switch (sched_attr_op_type (insn, false, address_p != 0))
5660 {
5661 case OP_TYPE_RN:
5662 return OPY_TYPE_RN;
5663
5664 case OP_TYPE_FPN:
5665 return OPY_TYPE_FPN;
5666
5667 case OP_TYPE_MEM1:
5668 return OPY_TYPE_MEM1;
5669
5670 case OP_TYPE_MEM234:
5671 return OPY_TYPE_MEM234;
5672
5673 case OP_TYPE_MEM5:
5674 return OPY_TYPE_MEM5;
5675
5676 case OP_TYPE_MEM6:
5677 return OPY_TYPE_MEM6;
5678
5679 case OP_TYPE_MEM7:
5680 return OPY_TYPE_MEM7;
5681
5682 case OP_TYPE_IMM_Q:
5683 return OPY_TYPE_IMM_Q;
5684
5685 case OP_TYPE_IMM_W:
5686 return OPY_TYPE_IMM_W;
5687
5688 case OP_TYPE_IMM_L:
5689 return OPY_TYPE_IMM_L;
5690
5691 default:
5692 gcc_unreachable ();
5693 }
5694 }
5695
5696 /* Return size of INSN as int. */
5697 static int
sched_get_attr_size_int(rtx_insn * insn)5698 sched_get_attr_size_int (rtx_insn *insn)
5699 {
5700 int size;
5701
5702 switch (get_attr_type (insn))
5703 {
5704 case TYPE_IGNORE:
5705 /* There should be no references to m68k_sched_attr_size for 'ignore'
5706 instructions. */
5707 gcc_unreachable ();
5708 return 0;
5709
5710 case TYPE_MUL_L:
5711 size = 2;
5712 break;
5713
5714 default:
5715 size = 1;
5716 break;
5717 }
5718
5719 switch (get_attr_opx_type (insn))
5720 {
5721 case OPX_TYPE_NONE:
5722 case OPX_TYPE_RN:
5723 case OPX_TYPE_FPN:
5724 case OPX_TYPE_MEM1:
5725 case OPX_TYPE_MEM234:
5726 case OPY_TYPE_IMM_Q:
5727 break;
5728
5729 case OPX_TYPE_MEM5:
5730 case OPX_TYPE_MEM6:
5731 /* Here we assume that most absolute references are short. */
5732 case OPX_TYPE_MEM7:
5733 case OPY_TYPE_IMM_W:
5734 ++size;
5735 break;
5736
5737 case OPY_TYPE_IMM_L:
5738 size += 2;
5739 break;
5740
5741 default:
5742 gcc_unreachable ();
5743 }
5744
5745 switch (get_attr_opy_type (insn))
5746 {
5747 case OPY_TYPE_NONE:
5748 case OPY_TYPE_RN:
5749 case OPY_TYPE_FPN:
5750 case OPY_TYPE_MEM1:
5751 case OPY_TYPE_MEM234:
5752 case OPY_TYPE_IMM_Q:
5753 break;
5754
5755 case OPY_TYPE_MEM5:
5756 case OPY_TYPE_MEM6:
5757 /* Here we assume that most absolute references are short. */
5758 case OPY_TYPE_MEM7:
5759 case OPY_TYPE_IMM_W:
5760 ++size;
5761 break;
5762
5763 case OPY_TYPE_IMM_L:
5764 size += 2;
5765 break;
5766
5767 default:
5768 gcc_unreachable ();
5769 }
5770
5771 if (size > 3)
5772 {
5773 gcc_assert (!reload_completed);
5774
5775 size = 3;
5776 }
5777
5778 return size;
5779 }
5780
5781 /* Return size of INSN as attribute enum value. */
5782 enum attr_size
m68k_sched_attr_size(rtx_insn * insn)5783 m68k_sched_attr_size (rtx_insn *insn)
5784 {
5785 switch (sched_get_attr_size_int (insn))
5786 {
5787 case 1:
5788 return SIZE_1;
5789
5790 case 2:
5791 return SIZE_2;
5792
5793 case 3:
5794 return SIZE_3;
5795
5796 default:
5797 gcc_unreachable ();
5798 }
5799 }
5800
5801 /* Return operand X or Y (depending on OPX_P) of INSN,
5802 if it is a MEM, or NULL overwise. */
5803 static enum attr_op_type
sched_get_opxy_mem_type(rtx_insn * insn,bool opx_p)5804 sched_get_opxy_mem_type (rtx_insn *insn, bool opx_p)
5805 {
5806 if (opx_p)
5807 {
5808 switch (get_attr_opx_type (insn))
5809 {
5810 case OPX_TYPE_NONE:
5811 case OPX_TYPE_RN:
5812 case OPX_TYPE_FPN:
5813 case OPX_TYPE_IMM_Q:
5814 case OPX_TYPE_IMM_W:
5815 case OPX_TYPE_IMM_L:
5816 return OP_TYPE_RN;
5817
5818 case OPX_TYPE_MEM1:
5819 case OPX_TYPE_MEM234:
5820 case OPX_TYPE_MEM5:
5821 case OPX_TYPE_MEM7:
5822 return OP_TYPE_MEM1;
5823
5824 case OPX_TYPE_MEM6:
5825 return OP_TYPE_MEM6;
5826
5827 default:
5828 gcc_unreachable ();
5829 }
5830 }
5831 else
5832 {
5833 switch (get_attr_opy_type (insn))
5834 {
5835 case OPY_TYPE_NONE:
5836 case OPY_TYPE_RN:
5837 case OPY_TYPE_FPN:
5838 case OPY_TYPE_IMM_Q:
5839 case OPY_TYPE_IMM_W:
5840 case OPY_TYPE_IMM_L:
5841 return OP_TYPE_RN;
5842
5843 case OPY_TYPE_MEM1:
5844 case OPY_TYPE_MEM234:
5845 case OPY_TYPE_MEM5:
5846 case OPY_TYPE_MEM7:
5847 return OP_TYPE_MEM1;
5848
5849 case OPY_TYPE_MEM6:
5850 return OP_TYPE_MEM6;
5851
5852 default:
5853 gcc_unreachable ();
5854 }
5855 }
5856 }
5857
5858 /* Implement op_mem attribute. */
5859 enum attr_op_mem
m68k_sched_attr_op_mem(rtx_insn * insn)5860 m68k_sched_attr_op_mem (rtx_insn *insn)
5861 {
5862 enum attr_op_type opx;
5863 enum attr_op_type opy;
5864
5865 opx = sched_get_opxy_mem_type (insn, true);
5866 opy = sched_get_opxy_mem_type (insn, false);
5867
5868 if (opy == OP_TYPE_RN && opx == OP_TYPE_RN)
5869 return OP_MEM_00;
5870
5871 if (opy == OP_TYPE_RN && opx == OP_TYPE_MEM1)
5872 {
5873 switch (get_attr_opx_access (insn))
5874 {
5875 case OPX_ACCESS_R:
5876 return OP_MEM_10;
5877
5878 case OPX_ACCESS_W:
5879 return OP_MEM_01;
5880
5881 case OPX_ACCESS_RW:
5882 return OP_MEM_11;
5883
5884 default:
5885 gcc_unreachable ();
5886 }
5887 }
5888
5889 if (opy == OP_TYPE_RN && opx == OP_TYPE_MEM6)
5890 {
5891 switch (get_attr_opx_access (insn))
5892 {
5893 case OPX_ACCESS_R:
5894 return OP_MEM_I0;
5895
5896 case OPX_ACCESS_W:
5897 return OP_MEM_0I;
5898
5899 case OPX_ACCESS_RW:
5900 return OP_MEM_I1;
5901
5902 default:
5903 gcc_unreachable ();
5904 }
5905 }
5906
5907 if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_RN)
5908 return OP_MEM_10;
5909
5910 if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_MEM1)
5911 {
5912 switch (get_attr_opx_access (insn))
5913 {
5914 case OPX_ACCESS_W:
5915 return OP_MEM_11;
5916
5917 default:
5918 gcc_assert (!reload_completed);
5919 return OP_MEM_11;
5920 }
5921 }
5922
5923 if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_MEM6)
5924 {
5925 switch (get_attr_opx_access (insn))
5926 {
5927 case OPX_ACCESS_W:
5928 return OP_MEM_1I;
5929
5930 default:
5931 gcc_assert (!reload_completed);
5932 return OP_MEM_1I;
5933 }
5934 }
5935
5936 if (opy == OP_TYPE_MEM6 && opx == OP_TYPE_RN)
5937 return OP_MEM_I0;
5938
5939 if (opy == OP_TYPE_MEM6 && opx == OP_TYPE_MEM1)
5940 {
5941 switch (get_attr_opx_access (insn))
5942 {
5943 case OPX_ACCESS_W:
5944 return OP_MEM_I1;
5945
5946 default:
5947 gcc_assert (!reload_completed);
5948 return OP_MEM_I1;
5949 }
5950 }
5951
5952 gcc_assert (opy == OP_TYPE_MEM6 && opx == OP_TYPE_MEM6);
5953 gcc_assert (!reload_completed);
5954 return OP_MEM_I1;
5955 }
5956
5957 /* Data for ColdFire V4 index bypass.
5958 Producer modifies register that is used as index in consumer with
5959 specified scale. */
5960 static struct
5961 {
5962 /* Producer instruction. */
5963 rtx pro;
5964
5965 /* Consumer instruction. */
5966 rtx con;
5967
5968 /* Scale of indexed memory access within consumer.
5969 Or zero if bypass should not be effective at the moment. */
5970 int scale;
5971 } sched_cfv4_bypass_data;
5972
5973 /* An empty state that is used in m68k_sched_adjust_cost. */
5974 static state_t sched_adjust_cost_state;
5975
5976 /* Implement adjust_cost scheduler hook.
5977 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
5978 static int
m68k_sched_adjust_cost(rtx_insn * insn,int,rtx_insn * def_insn,int cost,unsigned int)5979 m68k_sched_adjust_cost (rtx_insn *insn, int, rtx_insn *def_insn, int cost,
5980 unsigned int)
5981 {
5982 int delay;
5983
5984 if (recog_memoized (def_insn) < 0
5985 || recog_memoized (insn) < 0)
5986 return cost;
5987
5988 if (sched_cfv4_bypass_data.scale == 1)
5989 /* Handle ColdFire V4 bypass for indexed address with 1x scale. */
5990 {
5991 /* haifa-sched.c: insn_cost () calls bypass_p () just before
5992 targetm.sched.adjust_cost (). Hence, we can be relatively sure
5993 that the data in sched_cfv4_bypass_data is up to date. */
5994 gcc_assert (sched_cfv4_bypass_data.pro == def_insn
5995 && sched_cfv4_bypass_data.con == insn);
5996
5997 if (cost < 3)
5998 cost = 3;
5999
6000 sched_cfv4_bypass_data.pro = NULL;
6001 sched_cfv4_bypass_data.con = NULL;
6002 sched_cfv4_bypass_data.scale = 0;
6003 }
6004 else
6005 gcc_assert (sched_cfv4_bypass_data.pro == NULL
6006 && sched_cfv4_bypass_data.con == NULL
6007 && sched_cfv4_bypass_data.scale == 0);
6008
6009 /* Don't try to issue INSN earlier than DFA permits.
6010 This is especially useful for instructions that write to memory,
6011 as their true dependence (default) latency is better to be set to 0
6012 to workaround alias analysis limitations.
6013 This is, in fact, a machine independent tweak, so, probably,
6014 it should be moved to haifa-sched.c: insn_cost (). */
6015 delay = min_insn_conflict_delay (sched_adjust_cost_state, def_insn, insn);
6016 if (delay > cost)
6017 cost = delay;
6018
6019 return cost;
6020 }
6021
6022 /* Return maximal number of insns that can be scheduled on a single cycle. */
6023 static int
m68k_sched_issue_rate(void)6024 m68k_sched_issue_rate (void)
6025 {
6026 switch (m68k_sched_cpu)
6027 {
6028 case CPU_CFV1:
6029 case CPU_CFV2:
6030 case CPU_CFV3:
6031 return 1;
6032
6033 case CPU_CFV4:
6034 return 2;
6035
6036 default:
6037 gcc_unreachable ();
6038 return 0;
6039 }
6040 }
6041
6042 /* Maximal length of instruction for current CPU.
6043 E.g. it is 3 for any ColdFire core. */
6044 static int max_insn_size;
6045
6046 /* Data to model instruction buffer of CPU. */
6047 struct _sched_ib
6048 {
6049 /* True if instruction buffer model is modeled for current CPU. */
6050 bool enabled_p;
6051
6052 /* Size of the instruction buffer in words. */
6053 int size;
6054
6055 /* Number of filled words in the instruction buffer. */
6056 int filled;
6057
6058 /* Additional information about instruction buffer for CPUs that have
6059 a buffer of instruction records, rather then a plain buffer
6060 of instruction words. */
6061 struct _sched_ib_records
6062 {
6063 /* Size of buffer in records. */
6064 int n_insns;
6065
6066 /* Array to hold data on adjustments made to the size of the buffer. */
6067 int *adjust;
6068
6069 /* Index of the above array. */
6070 int adjust_index;
6071 } records;
6072
6073 /* An insn that reserves (marks empty) one word in the instruction buffer. */
6074 rtx insn;
6075 };
6076
6077 static struct _sched_ib sched_ib;
6078
6079 /* ID of memory unit. */
6080 static int sched_mem_unit_code;
6081
6082 /* Implementation of the targetm.sched.variable_issue () hook.
6083 It is called after INSN was issued. It returns the number of insns
6084 that can possibly get scheduled on the current cycle.
6085 It is used here to determine the effect of INSN on the instruction
6086 buffer. */
6087 static int
m68k_sched_variable_issue(FILE * sched_dump ATTRIBUTE_UNUSED,int sched_verbose ATTRIBUTE_UNUSED,rtx_insn * insn,int can_issue_more)6088 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED,
6089 int sched_verbose ATTRIBUTE_UNUSED,
6090 rtx_insn *insn, int can_issue_more)
6091 {
6092 int insn_size;
6093
6094 if (recog_memoized (insn) >= 0 && get_attr_type (insn) != TYPE_IGNORE)
6095 {
6096 switch (m68k_sched_cpu)
6097 {
6098 case CPU_CFV1:
6099 case CPU_CFV2:
6100 insn_size = sched_get_attr_size_int (insn);
6101 break;
6102
6103 case CPU_CFV3:
6104 insn_size = sched_get_attr_size_int (insn);
6105
6106 /* ColdFire V3 and V4 cores have instruction buffers that can
6107 accumulate up to 8 instructions regardless of instructions'
6108 sizes. So we should take care not to "prefetch" 24 one-word
6109 or 12 two-words instructions.
6110 To model this behavior we temporarily decrease size of the
6111 buffer by (max_insn_size - insn_size) for next 7 instructions. */
6112 {
6113 int adjust;
6114
6115 adjust = max_insn_size - insn_size;
6116 sched_ib.size -= adjust;
6117
6118 if (sched_ib.filled > sched_ib.size)
6119 sched_ib.filled = sched_ib.size;
6120
6121 sched_ib.records.adjust[sched_ib.records.adjust_index] = adjust;
6122 }
6123
6124 ++sched_ib.records.adjust_index;
6125 if (sched_ib.records.adjust_index == sched_ib.records.n_insns)
6126 sched_ib.records.adjust_index = 0;
6127
6128 /* Undo adjustment we did 7 instructions ago. */
6129 sched_ib.size
6130 += sched_ib.records.adjust[sched_ib.records.adjust_index];
6131
6132 break;
6133
6134 case CPU_CFV4:
6135 gcc_assert (!sched_ib.enabled_p);
6136 insn_size = 0;
6137 break;
6138
6139 default:
6140 gcc_unreachable ();
6141 }
6142
6143 if (insn_size > sched_ib.filled)
6144 /* Scheduling for register pressure does not always take DFA into
6145 account. Workaround instruction buffer not being filled enough. */
6146 {
6147 gcc_assert (sched_pressure == SCHED_PRESSURE_WEIGHTED);
6148 insn_size = sched_ib.filled;
6149 }
6150
6151 --can_issue_more;
6152 }
6153 else if (GET_CODE (PATTERN (insn)) == ASM_INPUT
6154 || asm_noperands (PATTERN (insn)) >= 0)
6155 insn_size = sched_ib.filled;
6156 else
6157 insn_size = 0;
6158
6159 sched_ib.filled -= insn_size;
6160
6161 return can_issue_more;
6162 }
6163
6164 /* Return how many instructions should scheduler lookahead to choose the
6165 best one. */
6166 static int
m68k_sched_first_cycle_multipass_dfa_lookahead(void)6167 m68k_sched_first_cycle_multipass_dfa_lookahead (void)
6168 {
6169 return m68k_sched_issue_rate () - 1;
6170 }
6171
6172 /* Implementation of targetm.sched.init_global () hook.
6173 It is invoked once per scheduling pass and is used here
6174 to initialize scheduler constants. */
6175 static void
m68k_sched_md_init_global(FILE * sched_dump ATTRIBUTE_UNUSED,int sched_verbose ATTRIBUTE_UNUSED,int n_insns ATTRIBUTE_UNUSED)6176 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED,
6177 int sched_verbose ATTRIBUTE_UNUSED,
6178 int n_insns ATTRIBUTE_UNUSED)
6179 {
6180 /* Check that all instructions have DFA reservations and
6181 that all instructions can be issued from a clean state. */
6182 if (flag_checking)
6183 {
6184 rtx_insn *insn;
6185 state_t state;
6186
6187 state = alloca (state_size ());
6188
6189 for (insn = get_insns (); insn != NULL; insn = NEXT_INSN (insn))
6190 {
6191 if (INSN_P (insn) && recog_memoized (insn) >= 0)
6192 {
6193 gcc_assert (insn_has_dfa_reservation_p (insn));
6194
6195 state_reset (state);
6196 if (state_transition (state, insn) >= 0)
6197 gcc_unreachable ();
6198 }
6199 }
6200 }
6201
6202 /* Setup target cpu. */
6203
6204 /* ColdFire V4 has a set of features to keep its instruction buffer full
6205 (e.g., a separate memory bus for instructions) and, hence, we do not model
6206 buffer for this CPU. */
6207 sched_ib.enabled_p = (m68k_sched_cpu != CPU_CFV4);
6208
6209 switch (m68k_sched_cpu)
6210 {
6211 case CPU_CFV4:
6212 sched_ib.filled = 0;
6213
6214 /* FALLTHRU */
6215
6216 case CPU_CFV1:
6217 case CPU_CFV2:
6218 max_insn_size = 3;
6219 sched_ib.records.n_insns = 0;
6220 sched_ib.records.adjust = NULL;
6221 break;
6222
6223 case CPU_CFV3:
6224 max_insn_size = 3;
6225 sched_ib.records.n_insns = 8;
6226 sched_ib.records.adjust = XNEWVEC (int, sched_ib.records.n_insns);
6227 break;
6228
6229 default:
6230 gcc_unreachable ();
6231 }
6232
6233 sched_mem_unit_code = get_cpu_unit_code ("cf_mem1");
6234
6235 sched_adjust_cost_state = xmalloc (state_size ());
6236 state_reset (sched_adjust_cost_state);
6237
6238 start_sequence ();
6239 emit_insn (gen_ib ());
6240 sched_ib.insn = get_insns ();
6241 end_sequence ();
6242 }
6243
6244 /* Scheduling pass is now finished. Free/reset static variables. */
6245 static void
m68k_sched_md_finish_global(FILE * dump ATTRIBUTE_UNUSED,int verbose ATTRIBUTE_UNUSED)6246 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
6247 int verbose ATTRIBUTE_UNUSED)
6248 {
6249 sched_ib.insn = NULL;
6250
6251 free (sched_adjust_cost_state);
6252 sched_adjust_cost_state = NULL;
6253
6254 sched_mem_unit_code = 0;
6255
6256 free (sched_ib.records.adjust);
6257 sched_ib.records.adjust = NULL;
6258 sched_ib.records.n_insns = 0;
6259 max_insn_size = 0;
6260 }
6261
6262 /* Implementation of targetm.sched.init () hook.
6263 It is invoked each time scheduler starts on the new block (basic block or
6264 extended basic block). */
6265 static void
m68k_sched_md_init(FILE * sched_dump ATTRIBUTE_UNUSED,int sched_verbose ATTRIBUTE_UNUSED,int n_insns ATTRIBUTE_UNUSED)6266 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED,
6267 int sched_verbose ATTRIBUTE_UNUSED,
6268 int n_insns ATTRIBUTE_UNUSED)
6269 {
6270 switch (m68k_sched_cpu)
6271 {
6272 case CPU_CFV1:
6273 case CPU_CFV2:
6274 sched_ib.size = 6;
6275 break;
6276
6277 case CPU_CFV3:
6278 sched_ib.size = sched_ib.records.n_insns * max_insn_size;
6279
6280 memset (sched_ib.records.adjust, 0,
6281 sched_ib.records.n_insns * sizeof (*sched_ib.records.adjust));
6282 sched_ib.records.adjust_index = 0;
6283 break;
6284
6285 case CPU_CFV4:
6286 gcc_assert (!sched_ib.enabled_p);
6287 sched_ib.size = 0;
6288 break;
6289
6290 default:
6291 gcc_unreachable ();
6292 }
6293
6294 if (sched_ib.enabled_p)
6295 /* haifa-sched.c: schedule_block () calls advance_cycle () just before
6296 the first cycle. Workaround that. */
6297 sched_ib.filled = -2;
6298 }
6299
6300 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
6301 It is invoked just before current cycle finishes and is used here
6302 to track if instruction buffer got its two words this cycle. */
6303 static void
m68k_sched_dfa_pre_advance_cycle(void)6304 m68k_sched_dfa_pre_advance_cycle (void)
6305 {
6306 if (!sched_ib.enabled_p)
6307 return;
6308
6309 if (!cpu_unit_reservation_p (curr_state, sched_mem_unit_code))
6310 {
6311 sched_ib.filled += 2;
6312
6313 if (sched_ib.filled > sched_ib.size)
6314 sched_ib.filled = sched_ib.size;
6315 }
6316 }
6317
6318 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
6319 It is invoked just after new cycle begins and is used here
6320 to setup number of filled words in the instruction buffer so that
6321 instructions which won't have all their words prefetched would be
6322 stalled for a cycle. */
6323 static void
m68k_sched_dfa_post_advance_cycle(void)6324 m68k_sched_dfa_post_advance_cycle (void)
6325 {
6326 int i;
6327
6328 if (!sched_ib.enabled_p)
6329 return;
6330
6331 /* Setup number of prefetched instruction words in the instruction
6332 buffer. */
6333 i = max_insn_size - sched_ib.filled;
6334
6335 while (--i >= 0)
6336 {
6337 if (state_transition (curr_state, sched_ib.insn) >= 0)
6338 /* Pick up scheduler state. */
6339 ++sched_ib.filled;
6340 }
6341 }
6342
6343 /* Return X or Y (depending on OPX_P) operand of INSN,
6344 if it is an integer register, or NULL overwise. */
6345 static rtx
sched_get_reg_operand(rtx_insn * insn,bool opx_p)6346 sched_get_reg_operand (rtx_insn *insn, bool opx_p)
6347 {
6348 rtx op = NULL;
6349
6350 if (opx_p)
6351 {
6352 if (get_attr_opx_type (insn) == OPX_TYPE_RN)
6353 {
6354 op = sched_get_operand (insn, true);
6355 gcc_assert (op != NULL);
6356
6357 if (!reload_completed && !REG_P (op))
6358 return NULL;
6359 }
6360 }
6361 else
6362 {
6363 if (get_attr_opy_type (insn) == OPY_TYPE_RN)
6364 {
6365 op = sched_get_operand (insn, false);
6366 gcc_assert (op != NULL);
6367
6368 if (!reload_completed && !REG_P (op))
6369 return NULL;
6370 }
6371 }
6372
6373 return op;
6374 }
6375
6376 /* Return true, if X or Y (depending on OPX_P) operand of INSN
6377 is a MEM. */
6378 static bool
sched_mem_operand_p(rtx_insn * insn,bool opx_p)6379 sched_mem_operand_p (rtx_insn *insn, bool opx_p)
6380 {
6381 switch (sched_get_opxy_mem_type (insn, opx_p))
6382 {
6383 case OP_TYPE_MEM1:
6384 case OP_TYPE_MEM6:
6385 return true;
6386
6387 default:
6388 return false;
6389 }
6390 }
6391
6392 /* Return X or Y (depending on OPX_P) operand of INSN,
6393 if it is a MEM, or NULL overwise. */
6394 static rtx
sched_get_mem_operand(rtx_insn * insn,bool must_read_p,bool must_write_p)6395 sched_get_mem_operand (rtx_insn *insn, bool must_read_p, bool must_write_p)
6396 {
6397 bool opx_p;
6398 bool opy_p;
6399
6400 opx_p = false;
6401 opy_p = false;
6402
6403 if (must_read_p)
6404 {
6405 opx_p = true;
6406 opy_p = true;
6407 }
6408
6409 if (must_write_p)
6410 {
6411 opx_p = true;
6412 opy_p = false;
6413 }
6414
6415 if (opy_p && sched_mem_operand_p (insn, false))
6416 return sched_get_operand (insn, false);
6417
6418 if (opx_p && sched_mem_operand_p (insn, true))
6419 return sched_get_operand (insn, true);
6420
6421 gcc_unreachable ();
6422 return NULL;
6423 }
6424
6425 /* Return non-zero if PRO modifies register used as part of
6426 address in CON. */
6427 int
m68k_sched_address_bypass_p(rtx_insn * pro,rtx_insn * con)6428 m68k_sched_address_bypass_p (rtx_insn *pro, rtx_insn *con)
6429 {
6430 rtx pro_x;
6431 rtx con_mem_read;
6432
6433 pro_x = sched_get_reg_operand (pro, true);
6434 if (pro_x == NULL)
6435 return 0;
6436
6437 con_mem_read = sched_get_mem_operand (con, true, false);
6438 gcc_assert (con_mem_read != NULL);
6439
6440 if (reg_mentioned_p (pro_x, con_mem_read))
6441 return 1;
6442
6443 return 0;
6444 }
6445
6446 /* Helper function for m68k_sched_indexed_address_bypass_p.
6447 if PRO modifies register used as index in CON,
6448 return scale of indexed memory access in CON. Return zero overwise. */
6449 static int
sched_get_indexed_address_scale(rtx_insn * pro,rtx_insn * con)6450 sched_get_indexed_address_scale (rtx_insn *pro, rtx_insn *con)
6451 {
6452 rtx reg;
6453 rtx mem;
6454 struct m68k_address address;
6455
6456 reg = sched_get_reg_operand (pro, true);
6457 if (reg == NULL)
6458 return 0;
6459
6460 mem = sched_get_mem_operand (con, true, false);
6461 gcc_assert (mem != NULL && MEM_P (mem));
6462
6463 if (!m68k_decompose_address (GET_MODE (mem), XEXP (mem, 0), reload_completed,
6464 &address))
6465 gcc_unreachable ();
6466
6467 if (REGNO (reg) == REGNO (address.index))
6468 {
6469 gcc_assert (address.scale != 0);
6470 return address.scale;
6471 }
6472
6473 return 0;
6474 }
6475
6476 /* Return non-zero if PRO modifies register used
6477 as index with scale 2 or 4 in CON. */
6478 int
m68k_sched_indexed_address_bypass_p(rtx_insn * pro,rtx_insn * con)6479 m68k_sched_indexed_address_bypass_p (rtx_insn *pro, rtx_insn *con)
6480 {
6481 gcc_assert (sched_cfv4_bypass_data.pro == NULL
6482 && sched_cfv4_bypass_data.con == NULL
6483 && sched_cfv4_bypass_data.scale == 0);
6484
6485 switch (sched_get_indexed_address_scale (pro, con))
6486 {
6487 case 1:
6488 /* We can't have a variable latency bypass, so
6489 remember to adjust the insn cost in adjust_cost hook. */
6490 sched_cfv4_bypass_data.pro = pro;
6491 sched_cfv4_bypass_data.con = con;
6492 sched_cfv4_bypass_data.scale = 1;
6493 return 0;
6494
6495 case 2:
6496 case 4:
6497 return 1;
6498
6499 default:
6500 return 0;
6501 }
6502 }
6503
6504 /* We generate a two-instructions program at M_TRAMP :
6505 movea.l &CHAIN_VALUE,%a0
6506 jmp FNADDR
6507 where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */
6508
6509 static void
m68k_trampoline_init(rtx m_tramp,tree fndecl,rtx chain_value)6510 m68k_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
6511 {
6512 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
6513 rtx mem;
6514
6515 gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM));
6516
6517 mem = adjust_address (m_tramp, HImode, 0);
6518 emit_move_insn (mem, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM-8) << 9)));
6519 mem = adjust_address (m_tramp, SImode, 2);
6520 emit_move_insn (mem, chain_value);
6521
6522 mem = adjust_address (m_tramp, HImode, 6);
6523 emit_move_insn (mem, GEN_INT(0x4EF9));
6524 mem = adjust_address (m_tramp, SImode, 8);
6525 emit_move_insn (mem, fnaddr);
6526
6527 FINALIZE_TRAMPOLINE (XEXP (m_tramp, 0));
6528 }
6529
6530 /* On the 68000, the RTS insn cannot pop anything.
6531 On the 68010, the RTD insn may be used to pop them if the number
6532 of args is fixed, but if the number is variable then the caller
6533 must pop them all. RTD can't be used for library calls now
6534 because the library is compiled with the Unix compiler.
6535 Use of RTD is a selectable option, since it is incompatible with
6536 standard Unix calling sequences. If the option is not selected,
6537 the caller must always pop the args. */
6538
6539 static poly_int64
m68k_return_pops_args(tree fundecl,tree funtype,poly_int64 size)6540 m68k_return_pops_args (tree fundecl, tree funtype, poly_int64 size)
6541 {
6542 return ((TARGET_RTD
6543 && (!fundecl
6544 || TREE_CODE (fundecl) != IDENTIFIER_NODE)
6545 && (!stdarg_p (funtype)))
6546 ? (HOST_WIDE_INT) size : 0);
6547 }
6548
6549 /* Make sure everything's fine if we *don't* have a given processor.
6550 This assumes that putting a register in fixed_regs will keep the
6551 compiler's mitts completely off it. We don't bother to zero it out
6552 of register classes. */
6553
6554 static void
m68k_conditional_register_usage(void)6555 m68k_conditional_register_usage (void)
6556 {
6557 int i;
6558 HARD_REG_SET x;
6559 if (!TARGET_HARD_FLOAT)
6560 {
6561 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]);
6562 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
6563 if (TEST_HARD_REG_BIT (x, i))
6564 fixed_regs[i] = call_used_regs[i] = 1;
6565 }
6566 if (flag_pic)
6567 fixed_regs[PIC_REG] = call_used_regs[PIC_REG] = 1;
6568 }
6569
6570 static void
m68k_init_sync_libfuncs(void)6571 m68k_init_sync_libfuncs (void)
6572 {
6573 init_sync_libfuncs (UNITS_PER_WORD);
6574 }
6575
6576 /* Implements EPILOGUE_USES. All registers are live on exit from an
6577 interrupt routine. */
6578 bool
m68k_epilogue_uses(int regno ATTRIBUTE_UNUSED)6579 m68k_epilogue_uses (int regno ATTRIBUTE_UNUSED)
6580 {
6581 return (reload_completed
6582 && (m68k_get_function_kind (current_function_decl)
6583 == m68k_fk_interrupt_handler));
6584 }
6585
6586
6587 /* Implement TARGET_C_EXCESS_PRECISION.
6588
6589 Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
6590 instructions, we get proper intermediate rounding, otherwise we
6591 get extended precision results. */
6592
6593 static enum flt_eval_method
m68k_excess_precision(enum excess_precision_type type)6594 m68k_excess_precision (enum excess_precision_type type)
6595 {
6596 switch (type)
6597 {
6598 case EXCESS_PRECISION_TYPE_FAST:
6599 /* The fastest type to promote to will always be the native type,
6600 whether that occurs with implicit excess precision or
6601 otherwise. */
6602 return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT;
6603 case EXCESS_PRECISION_TYPE_STANDARD:
6604 case EXCESS_PRECISION_TYPE_IMPLICIT:
6605 /* Otherwise, the excess precision we want when we are
6606 in a standards compliant mode, and the implicit precision we
6607 provide can be identical. */
6608 if (TARGET_68040 || ! TARGET_68881)
6609 return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT;
6610
6611 return FLT_EVAL_METHOD_PROMOTE_TO_LONG_DOUBLE;
6612 default:
6613 gcc_unreachable ();
6614 }
6615 return FLT_EVAL_METHOD_UNPREDICTABLE;
6616 }
6617
6618 /* Implement PUSH_ROUNDING. On the 680x0, sp@- in a byte insn really pushes
6619 a word. On the ColdFire, sp@- in a byte insn pushes just a byte. */
6620
6621 poly_int64
m68k_push_rounding(poly_int64 bytes)6622 m68k_push_rounding (poly_int64 bytes)
6623 {
6624 if (TARGET_COLDFIRE)
6625 return bytes;
6626 return (bytes + 1) & ~1;
6627 }
6628
6629 /* Implement TARGET_PROMOTE_FUNCTION_MODE. */
6630
6631 static machine_mode
m68k_promote_function_mode(const_tree type,machine_mode mode,int * punsignedp ATTRIBUTE_UNUSED,const_tree fntype ATTRIBUTE_UNUSED,int for_return)6632 m68k_promote_function_mode (const_tree type, machine_mode mode,
6633 int *punsignedp ATTRIBUTE_UNUSED,
6634 const_tree fntype ATTRIBUTE_UNUSED,
6635 int for_return)
6636 {
6637 /* Promote libcall arguments narrower than int to match the normal C
6638 ABI (for which promotions are handled via
6639 TARGET_PROMOTE_PROTOTYPES). */
6640 if (type == NULL_TREE && !for_return && (mode == QImode || mode == HImode))
6641 return SImode;
6642 return mode;
6643 }
6644
6645 #include "gt-m68k.h"
6646