1;; Constraint definitions for IA-32 and x86-64. 2;; Copyright (C) 2006-2014 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 3, or (at your option) 9;; any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20;;; Unused letters: 21;;; B H 22;;; h j 23 24;; Integer register constraints. 25;; It is not necessary to define 'r' here. 26(define_register_constraint "R" "LEGACY_REGS" 27 "Legacy register---the eight integer registers available on all 28 i386 processors (@code{a}, @code{b}, @code{c}, @code{d}, 29 @code{si}, @code{di}, @code{bp}, @code{sp}).") 30 31(define_register_constraint "q" "TARGET_64BIT ? GENERAL_REGS : Q_REGS" 32 "Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a}, 33 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.") 34 35(define_register_constraint "Q" "Q_REGS" 36 "Any register accessible as @code{@var{r}h}: @code{a}, @code{b}, 37 @code{c}, and @code{d}.") 38 39(define_register_constraint "l" "INDEX_REGS" 40 "@internal Any register that can be used as the index in a base+index 41 memory access: that is, any general register except the stack pointer.") 42 43(define_register_constraint "a" "AREG" 44 "The @code{a} register.") 45 46(define_register_constraint "b" "BREG" 47 "The @code{b} register.") 48 49(define_register_constraint "c" "CREG" 50 "The @code{c} register.") 51 52(define_register_constraint "d" "DREG" 53 "The @code{d} register.") 54 55(define_register_constraint "S" "SIREG" 56 "The @code{si} register.") 57 58(define_register_constraint "D" "DIREG" 59 "The @code{di} register.") 60 61(define_register_constraint "A" "AD_REGS" 62 "The @code{a} and @code{d} registers, as a pair (for instructions 63 that return half the result in one and half in the other).") 64 65(define_register_constraint "U" "CLOBBERED_REGS" 66 "The call-clobbered integer registers.") 67 68;; Floating-point register constraints. 69(define_register_constraint "f" 70 "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FLOAT_REGS : NO_REGS" 71 "Any 80387 floating-point (stack) register.") 72 73(define_register_constraint "t" 74 "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_TOP_REG : NO_REGS" 75 "Top of 80387 floating-point stack (@code{%st(0)}).") 76 77(define_register_constraint "u" 78 "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_SECOND_REG : NO_REGS" 79 "Second from top of 80387 floating-point stack (@code{%st(1)}).") 80 81(define_register_constraint "Yk" "TARGET_AVX512F ? MASK_EVEX_REGS : NO_REGS" 82"@internal Any mask register that can be used as predicate, i.e. k1-k7.") 83 84(define_register_constraint "k" "TARGET_AVX512F ? MASK_REGS : NO_REGS" 85"@internal Any mask register.") 86 87;; Vector registers (also used for plain floating point nowadays). 88(define_register_constraint "y" "TARGET_MMX ? MMX_REGS : NO_REGS" 89 "Any MMX register.") 90 91(define_register_constraint "x" "TARGET_SSE ? SSE_REGS : NO_REGS" 92 "Any SSE register.") 93 94;; We use the Y prefix to denote any number of conditional register sets: 95;; z First SSE register. 96;; i SSE2 inter-unit moves to SSE register enabled 97;; j SSE2 inter-unit moves from SSE register enabled 98;; m MMX inter-unit moves to MMX register enabled 99;; n MMX inter-unit moves from MMX register enabled 100;; a Integer register when zero extensions with AND are disabled 101;; p Integer register when TARGET_PARTIAL_REG_STALL is disabled 102;; d Integer register when integer DFmode moves are enabled 103;; x Integer register when integer XFmode moves are enabled 104;; f x87 register when 80387 floating point arithmetic is enabled 105 106(define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS" 107 "First SSE register (@code{%xmm0}).") 108 109(define_register_constraint "Yi" 110 "TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC ? ALL_SSE_REGS : NO_REGS" 111 "@internal Any SSE register, when SSE2 and inter-unit moves to vector registers are enabled.") 112 113(define_register_constraint "Yj" 114 "TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_FROM_VEC ? ALL_SSE_REGS : NO_REGS" 115 "@internal Any SSE register, when SSE2 and inter-unit moves from vector registers are enabled.") 116 117(define_register_constraint "Ym" 118 "TARGET_MMX && TARGET_INTER_UNIT_MOVES_TO_VEC ? MMX_REGS : NO_REGS" 119 "@internal Any MMX register, when inter-unit moves to vector registers are enabled.") 120 121(define_register_constraint "Yn" 122 "TARGET_MMX && TARGET_INTER_UNIT_MOVES_FROM_VEC ? MMX_REGS : NO_REGS" 123 "@internal Any MMX register, when inter-unit moves from vector registers are enabled.") 124 125(define_register_constraint "Yp" 126 "TARGET_PARTIAL_REG_STALL ? NO_REGS : GENERAL_REGS" 127 "@internal Any integer register when TARGET_PARTIAL_REG_STALL is disabled.") 128 129(define_register_constraint "Ya" 130 "TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun) 131 ? NO_REGS : GENERAL_REGS" 132 "@internal Any integer register when zero extensions with AND are disabled.") 133 134(define_register_constraint "Yd" 135 "TARGET_INTEGER_DFMODE_MOVES && optimize_function_for_speed_p (cfun) 136 ? GENERAL_REGS : NO_REGS" 137 "@internal Any integer register when integer DFmode moves are enabled.") 138 139(define_register_constraint "Yx" 140 "optimize_function_for_speed_p (cfun) ? GENERAL_REGS : NO_REGS" 141 "@internal Any integer register when integer XFmode moves are enabled.") 142 143(define_register_constraint "Yf" 144 "(ix86_fpmath & FPMATH_387) ? FLOAT_REGS : NO_REGS" 145 "@internal Any x87 register when 80387 FP arithmetic is enabled.") 146 147(define_register_constraint "v" "TARGET_SSE ? ALL_SSE_REGS : NO_REGS" 148 "Any EVEX encodable SSE register (@code{%xmm0-%xmm31}).") 149 150(define_constraint "z" 151 "@internal Constant call address operand." 152 (match_operand 0 "constant_call_address_operand")) 153 154(define_constraint "w" 155 "@internal Call memory operand." 156 (and (not (match_test "TARGET_X32")) 157 (match_operand 0 "memory_operand"))) 158 159;; Integer constant constraints. 160(define_constraint "I" 161 "Integer constant in the range 0 @dots{} 31, for 32-bit shifts." 162 (and (match_code "const_int") 163 (match_test "IN_RANGE (ival, 0, 31)"))) 164 165(define_constraint "J" 166 "Integer constant in the range 0 @dots{} 63, for 64-bit shifts." 167 (and (match_code "const_int") 168 (match_test "IN_RANGE (ival, 0, 63)"))) 169 170(define_constraint "K" 171 "Signed 8-bit integer constant." 172 (and (match_code "const_int") 173 (match_test "IN_RANGE (ival, -128, 127)"))) 174 175(define_constraint "L" 176 "@code{0xFF}, @code{0xFFFF} or @code{0xFFFFFFFF} 177 for AND as a zero-extending move." 178 (and (match_code "const_int") 179 (match_test "ival == 0xff || ival == 0xffff 180 || ival == (HOST_WIDE_INT) 0xffffffff"))) 181 182(define_constraint "M" 183 "0, 1, 2, or 3 (shifts for the @code{lea} instruction)." 184 (and (match_code "const_int") 185 (match_test "IN_RANGE (ival, 0, 3)"))) 186 187(define_constraint "N" 188 "Unsigned 8-bit integer constant (for @code{in} and @code{out} 189 instructions)." 190 (and (match_code "const_int") 191 (match_test "IN_RANGE (ival, 0, 255)"))) 192 193(define_constraint "O" 194 "@internal Integer constant in the range 0 @dots{} 127, for 128-bit shifts." 195 (and (match_code "const_int") 196 (match_test "IN_RANGE (ival, 0, 127)"))) 197 198;; Floating-point constant constraints. 199;; We allow constants even if TARGET_80387 isn't set, because the 200;; stack register converter may need to load 0.0 into the function 201;; value register (top of stack). 202(define_constraint "G" 203 "Standard 80387 floating point constant." 204 (and (match_code "const_double") 205 (match_test "standard_80387_constant_p (op) > 0"))) 206 207;; This can theoretically be any mode's CONST0_RTX. 208(define_constraint "C" 209 "Standard SSE floating point constant." 210 (match_test "standard_sse_constant_p (op)")) 211 212;; Constant-or-symbol-reference constraints. 213 214(define_constraint "e" 215 "32-bit signed integer constant, or a symbolic reference known 216 to fit that range (for immediate operands in sign-extending x86-64 217 instructions)." 218 (match_operand 0 "x86_64_immediate_operand")) 219 220;; We use W prefix to denote any number of 221;; constant-or-symbol-reference constraints 222 223(define_constraint "We" 224 "32-bit signed integer constant, or a symbolic reference known 225 to fit that range (for sign-extending conversion operations that 226 require non-VOIDmode immediate operands)." 227 (and (match_operand 0 "x86_64_immediate_operand") 228 (match_test "GET_MODE (op) != VOIDmode"))) 229 230(define_constraint "Wz" 231 "32-bit unsigned integer constant, or a symbolic reference known 232 to fit that range (for zero-extending conversion operations that 233 require non-VOIDmode immediate operands)." 234 (and (match_operand 0 "x86_64_zext_immediate_operand") 235 (match_test "GET_MODE (op) != VOIDmode"))) 236 237(define_constraint "Z" 238 "32-bit unsigned integer constant, or a symbolic reference known 239 to fit that range (for immediate operands in zero-extending x86-64 240 instructions)." 241 (match_operand 0 "x86_64_zext_immediate_operand")) 242 243;; T prefix is used for different address constraints 244;; v - VSIB address 245;; s - address with no segment register 246 247(define_address_constraint "Tv" 248 "VSIB address operand" 249 (match_operand 0 "vsib_address_operand")) 250 251(define_address_constraint "Ts" 252 "Address operand without segment register" 253 (match_operand 0 "address_no_seg_operand")) 254