1 /* Definitions of target machine for GNU compiler. MIPS version. 2 Copyright (C) 1989-2014 Free Software Foundation, Inc. 3 Contributed by A. Lichnewsky (lich@inria.inria.fr). 4 Changed by Michael Meissner (meissner@osf.org). 5 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and 6 Brendan Eich (brendan@microunity.com). 7 8 This file is part of GCC. 9 10 GCC is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 3, or (at your option) 13 any later version. 14 15 GCC is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with GCC; see the file COPYING3. If not see 22 <http://www.gnu.org/licenses/>. */ 23 24 25 #include "config/vxworks-dummy.h" 26 27 #ifdef GENERATOR_FILE 28 /* This is used in some insn conditions, so needs to be declared, but 29 does not need to be defined. */ 30 extern int target_flags_explicit; 31 #endif 32 33 /* MIPS external variables defined in mips.c. */ 34 35 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32), 36 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended 37 to work on a 64-bit machine. */ 38 39 #define ABI_32 0 40 #define ABI_N32 1 41 #define ABI_64 2 42 #define ABI_EABI 3 43 #define ABI_O64 4 44 45 /* Masks that affect tuning. 46 47 PTF_AVOID_BRANCHLIKELY 48 Set if it is usually not profitable to use branch-likely instructions 49 for this target, typically because the branches are always predicted 50 taken and so incur a large overhead when not taken. 51 52 PTF_AVOID_IMADD 53 Set if it is usually not profitable to use the integer MADD or MSUB 54 instructions because of the overhead of getting the result out of 55 the HI/LO registers. */ 56 57 #define PTF_AVOID_BRANCHLIKELY 0x1 58 #define PTF_AVOID_IMADD 0x2 59 60 /* Information about one recognized processor. Defined here for the 61 benefit of TARGET_CPU_CPP_BUILTINS. */ 62 struct mips_cpu_info { 63 /* The 'canonical' name of the processor as far as GCC is concerned. 64 It's typically a manufacturer's prefix followed by a numerical 65 designation. It should be lowercase. */ 66 const char *name; 67 68 /* The internal processor number that most closely matches this 69 entry. Several processors can have the same value, if there's no 70 difference between them from GCC's point of view. */ 71 enum processor cpu; 72 73 /* The ISA level that the processor implements. */ 74 int isa; 75 76 /* A mask of PTF_* values. */ 77 unsigned int tune_flags; 78 }; 79 80 #include "config/mips/mips-opts.h" 81 82 /* Macros to silence warnings about numbers being signed in traditional 83 C and unsigned in ISO C when compiled on 32-bit hosts. */ 84 85 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */ 86 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */ 87 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */ 88 89 90 /* Run-time compilation parameters selecting different hardware subsets. */ 91 92 /* True if we are generating position-independent VxWorks RTP code. */ 93 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic) 94 95 /* True if the output file is marked as ".abicalls; .option pic0" 96 (-call_nonpic). */ 97 #define TARGET_ABICALLS_PIC0 \ 98 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT) 99 100 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */ 101 #define TARGET_ABICALLS_PIC2 \ 102 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0) 103 104 /* True if the call patterns should be split into a jalr followed by 105 an instruction to restore $gp. It is only safe to split the load 106 from the call when every use of $gp is explicit. 107 108 See mips_must_initialize_gp_p for details about how we manage the 109 global pointer. */ 110 111 #define TARGET_SPLIT_CALLS \ 112 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed) 113 114 /* True if we're generating a form of -mabicalls in which we can use 115 operators like %hi and %lo to refer to locally-binding symbols. 116 We can only do this for -mno-shared, and only then if we can use 117 relocation operations instead of assembly macros. It isn't really 118 worth using absolute sequences for 64-bit symbols because GOT 119 accesses are so much shorter. */ 120 121 #define TARGET_ABSOLUTE_ABICALLS \ 122 (TARGET_ABICALLS \ 123 && !TARGET_SHARED \ 124 && TARGET_EXPLICIT_RELOCS \ 125 && !ABI_HAS_64BIT_SYMBOLS) 126 127 /* True if we can optimize sibling calls. For simplicity, we only 128 handle cases in which call_insn_operand will reject invalid 129 sibcall addresses. There are two cases in which this isn't true: 130 131 - TARGET_MIPS16. call_insn_operand accepts constant addresses 132 but there is no direct jump instruction. It isn't worth 133 using sibling calls in this case anyway; they would usually 134 be longer than normal calls. 135 136 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand 137 accepts global constants, but all sibcalls must be indirect. */ 138 #define TARGET_SIBCALLS \ 139 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS)) 140 141 /* True if we need to use a global offset table to access some symbols. */ 142 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC) 143 144 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */ 145 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI) 146 147 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */ 148 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP) 149 150 /* True if we should use .cprestore to store to the cprestore slot. 151 152 We continue to use .cprestore for explicit-reloc code so that JALs 153 inside inline asms will work correctly. */ 154 #define TARGET_CPRESTORE_DIRECTIVE \ 155 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16) 156 157 /* True if we can use the J and JAL instructions. */ 158 #define TARGET_ABSOLUTE_JUMPS \ 159 (!flag_pic || TARGET_ABSOLUTE_ABICALLS) 160 161 /* True if indirect calls must use register class PIC_FN_ADDR_REG. 162 This is true for both the PIC and non-PIC VxWorks RTP modes. */ 163 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP) 164 165 /* True if .gpword or .gpdword should be used for switch tables. */ 166 #define TARGET_GPWORD \ 167 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS) 168 169 /* True if the output must have a writable .eh_frame. 170 See ASM_PREFERRED_EH_DATA_FORMAT for details. */ 171 #ifdef HAVE_LD_PERSONALITY_RELAXATION 172 #define TARGET_WRITABLE_EH_FRAME 0 173 #else 174 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED) 175 #endif 176 177 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */ 178 #ifdef HAVE_AS_DSPR1_MULT 179 #define ISA_HAS_DSP_MULT ISA_HAS_DSP 180 #else 181 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2 182 #endif 183 184 /* The ISA compression flags that are currently in effect. */ 185 #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS)) 186 187 /* Generate mips16 code */ 188 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0) 189 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */ 190 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32) 191 /* Generate mips16e register save/restore sequences. */ 192 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32) 193 194 /* True if we're generating a form of MIPS16 code in which general 195 text loads are allowed. */ 196 #define TARGET_MIPS16_TEXT_LOADS \ 197 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES) 198 199 /* True if we're generating a form of MIPS16 code in which PC-relative 200 loads are allowed. */ 201 #define TARGET_MIPS16_PCREL_LOADS \ 202 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL) 203 204 /* Generic ISA defines. */ 205 #define ISA_MIPS1 (mips_isa == 1) 206 #define ISA_MIPS2 (mips_isa == 2) 207 #define ISA_MIPS3 (mips_isa == 3) 208 #define ISA_MIPS4 (mips_isa == 4) 209 #define ISA_MIPS32 (mips_isa == 32) 210 #define ISA_MIPS32R2 (mips_isa == 33) 211 #define ISA_MIPS64 (mips_isa == 64) 212 #define ISA_MIPS64R2 (mips_isa == 65) 213 214 /* Architecture target defines. */ 215 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E) 216 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F) 217 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F) 218 #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A) 219 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900) 220 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000) 221 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120) 222 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130) 223 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400) 224 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500) 225 #define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900) 226 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000) 227 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000) 228 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \ 229 || mips_arch == PROCESSOR_OCTEON2) 230 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2) 231 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \ 232 || mips_arch == PROCESSOR_SB1A) 233 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000) 234 #define TARGET_XLP (mips_arch == PROCESSOR_XLP) 235 236 /* Scheduling target defines. */ 237 #define TUNE_20KC (mips_tune == PROCESSOR_20KC) 238 #define TUNE_24K (mips_tune == PROCESSOR_24KC \ 239 || mips_tune == PROCESSOR_24KF2_1 \ 240 || mips_tune == PROCESSOR_24KF1_1) 241 #define TUNE_74K (mips_tune == PROCESSOR_74KC \ 242 || mips_tune == PROCESSOR_74KF2_1 \ 243 || mips_tune == PROCESSOR_74KF1_1 \ 244 || mips_tune == PROCESSOR_74KF3_2) 245 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \ 246 || mips_tune == PROCESSOR_LOONGSON_2F) 247 #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A) 248 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) 249 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900) 250 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000) 251 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120) 252 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130) 253 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000) 254 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400) 255 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500) 256 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000) 257 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000) 258 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000) 259 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \ 260 || mips_tune == PROCESSOR_OCTEON2) 261 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \ 262 || mips_tune == PROCESSOR_SB1A) 263 264 /* Whether vector modes and intrinsics for ST Microelectronics 265 Loongson-2E/2F processors should be enabled. In o32 pairs of 266 floating-point registers provide 64-bit values. */ 267 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \ 268 && (TARGET_LOONGSON_2EF \ 269 || TARGET_LOONGSON_3A)) 270 271 /* True if the pre-reload scheduler should try to create chains of 272 multiply-add or multiply-subtract instructions. For example, 273 suppose we have: 274 275 t1 = a * b 276 t2 = t1 + c * d 277 t3 = e * f 278 t4 = t3 - g * h 279 280 t1 will have a higher priority than t2 and t3 will have a higher 281 priority than t4. However, before reload, there is no dependence 282 between t1 and t3, and they can often have similar priorities. 283 The scheduler will then tend to prefer: 284 285 t1 = a * b 286 t3 = e * f 287 t2 = t1 + c * d 288 t4 = t3 - g * h 289 290 which stops us from making full use of macc/madd-style instructions. 291 This sort of situation occurs frequently in Fourier transforms and 292 in unrolled loops. 293 294 To counter this, the TUNE_MACC_CHAINS code will reorder the ready 295 queue so that chained multiply-add and multiply-subtract instructions 296 appear ahead of any other instruction that is likely to clobber lo. 297 In the example above, if t2 and t3 become ready at the same time, 298 the code ensures that t2 is scheduled first. 299 300 Multiply-accumulate instructions are a bigger win for some targets 301 than others, so this macro is defined on an opt-in basis. */ 302 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \ 303 || TUNE_MIPS4120 \ 304 || TUNE_MIPS4130 \ 305 || TUNE_24K) 306 307 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64) 308 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64) 309 310 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is 311 directly accessible, while the command-line options select 312 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI 313 in use. */ 314 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16) 315 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16) 316 317 /* False if SC acts as a memory barrier with respect to itself, 318 otherwise a SYNC will be emitted after SC for atomic operations 319 that require ordering between the SC and following loads and 320 stores. It does not tell anything about ordering of loads and 321 stores prior to and following the SC, only about the SC itself and 322 those loads and stores follow it. */ 323 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP) 324 325 /* Define preprocessor macros for the -march and -mtune options. 326 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected 327 processor. If INFO's canonical name is "foo", define PREFIX to 328 be "foo", and define an additional macro PREFIX_FOO. */ 329 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \ 330 do \ 331 { \ 332 char *macro, *p; \ 333 \ 334 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \ 335 for (p = macro; *p != 0; p++) \ 336 if (*p == '+') \ 337 *p = 'P'; \ 338 else \ 339 *p = TOUPPER (*p); \ 340 \ 341 builtin_define (macro); \ 342 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \ 343 free (macro); \ 344 } \ 345 while (0) 346 347 /* Target CPU builtins. */ 348 #define TARGET_CPU_CPP_BUILTINS() \ 349 do \ 350 { \ 351 builtin_assert ("machine=mips"); \ 352 builtin_assert ("cpu=mips"); \ 353 builtin_define ("__mips__"); \ 354 builtin_define ("_mips"); \ 355 \ 356 /* We do this here because __mips is defined below and so we \ 357 can't use builtin_define_std. We don't ever want to define \ 358 "mips" for VxWorks because some of the VxWorks headers \ 359 construct include filenames from a root directory macro, \ 360 an architecture macro and a filename, where the architecture \ 361 macro expands to 'mips'. If we define 'mips' to 1, the \ 362 architecture macro expands to 1 as well. */ \ 363 if (!flag_iso && !TARGET_VXWORKS) \ 364 builtin_define ("mips"); \ 365 \ 366 if (TARGET_64BIT) \ 367 builtin_define ("__mips64"); \ 368 \ 369 /* Treat _R3000 and _R4000 like register-size \ 370 defines, which is how they've historically \ 371 been used. */ \ 372 if (TARGET_64BIT) \ 373 { \ 374 builtin_define_std ("R4000"); \ 375 builtin_define ("_R4000"); \ 376 } \ 377 else \ 378 { \ 379 builtin_define_std ("R3000"); \ 380 builtin_define ("_R3000"); \ 381 } \ 382 \ 383 if (TARGET_FLOAT64) \ 384 builtin_define ("__mips_fpr=64"); \ 385 else \ 386 builtin_define ("__mips_fpr=32"); \ 387 \ 388 if (mips_base_compression_flags & MASK_MIPS16) \ 389 builtin_define ("__mips16"); \ 390 \ 391 if (TARGET_MIPS3D) \ 392 builtin_define ("__mips3d"); \ 393 \ 394 if (TARGET_SMARTMIPS) \ 395 builtin_define ("__mips_smartmips"); \ 396 \ 397 if (mips_base_compression_flags & MASK_MICROMIPS) \ 398 builtin_define ("__mips_micromips"); \ 399 \ 400 if (TARGET_MCU) \ 401 builtin_define ("__mips_mcu"); \ 402 \ 403 if (TARGET_EVA) \ 404 builtin_define ("__mips_eva"); \ 405 \ 406 if (TARGET_DSP) \ 407 { \ 408 builtin_define ("__mips_dsp"); \ 409 if (TARGET_DSPR2) \ 410 { \ 411 builtin_define ("__mips_dspr2"); \ 412 builtin_define ("__mips_dsp_rev=2"); \ 413 } \ 414 else \ 415 builtin_define ("__mips_dsp_rev=1"); \ 416 } \ 417 \ 418 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \ 419 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \ 420 \ 421 if (ISA_MIPS1) \ 422 { \ 423 builtin_define ("__mips=1"); \ 424 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \ 425 } \ 426 else if (ISA_MIPS2) \ 427 { \ 428 builtin_define ("__mips=2"); \ 429 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \ 430 } \ 431 else if (ISA_MIPS3) \ 432 { \ 433 builtin_define ("__mips=3"); \ 434 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \ 435 } \ 436 else if (ISA_MIPS4) \ 437 { \ 438 builtin_define ("__mips=4"); \ 439 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \ 440 } \ 441 else if (ISA_MIPS32) \ 442 { \ 443 builtin_define ("__mips=32"); \ 444 builtin_define ("__mips_isa_rev=1"); \ 445 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \ 446 } \ 447 else if (ISA_MIPS32R2) \ 448 { \ 449 builtin_define ("__mips=32"); \ 450 builtin_define ("__mips_isa_rev=2"); \ 451 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \ 452 } \ 453 else if (ISA_MIPS64) \ 454 { \ 455 builtin_define ("__mips=64"); \ 456 builtin_define ("__mips_isa_rev=1"); \ 457 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \ 458 } \ 459 else if (ISA_MIPS64R2) \ 460 { \ 461 builtin_define ("__mips=64"); \ 462 builtin_define ("__mips_isa_rev=2"); \ 463 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \ 464 } \ 465 \ 466 switch (mips_abi) \ 467 { \ 468 case ABI_32: \ 469 builtin_define ("_ABIO32=1"); \ 470 builtin_define ("_MIPS_SIM=_ABIO32"); \ 471 break; \ 472 \ 473 case ABI_N32: \ 474 builtin_define ("_ABIN32=2"); \ 475 builtin_define ("_MIPS_SIM=_ABIN32"); \ 476 break; \ 477 \ 478 case ABI_64: \ 479 builtin_define ("_ABI64=3"); \ 480 builtin_define ("_MIPS_SIM=_ABI64"); \ 481 break; \ 482 \ 483 case ABI_O64: \ 484 builtin_define ("_ABIO64=4"); \ 485 builtin_define ("_MIPS_SIM=_ABIO64"); \ 486 break; \ 487 } \ 488 \ 489 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \ 490 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \ 491 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \ 492 builtin_define_with_int_value ("_MIPS_FPSET", \ 493 32 / MAX_FPRS_PER_FMT); \ 494 \ 495 /* These defines reflect the ABI in use, not whether the \ 496 FPU is directly accessible. */ \ 497 if (TARGET_NO_FLOAT) \ 498 builtin_define ("__mips_no_float"); \ 499 else if (TARGET_HARD_FLOAT_ABI) \ 500 builtin_define ("__mips_hard_float"); \ 501 else \ 502 builtin_define ("__mips_soft_float"); \ 503 \ 504 if (TARGET_SINGLE_FLOAT) \ 505 builtin_define ("__mips_single_float"); \ 506 \ 507 if (TARGET_PAIRED_SINGLE_FLOAT) \ 508 builtin_define ("__mips_paired_single_float"); \ 509 \ 510 if (mips_abs == MIPS_IEEE_754_2008) \ 511 builtin_define ("__mips_abs2008"); \ 512 \ 513 if (mips_nan == MIPS_IEEE_754_2008) \ 514 builtin_define ("__mips_nan2008"); \ 515 \ 516 if (TARGET_BIG_ENDIAN) \ 517 { \ 518 builtin_define_std ("MIPSEB"); \ 519 builtin_define ("_MIPSEB"); \ 520 } \ 521 else \ 522 { \ 523 builtin_define_std ("MIPSEL"); \ 524 builtin_define ("_MIPSEL"); \ 525 } \ 526 \ 527 /* Whether calls should go through $25. The separate __PIC__ \ 528 macro indicates whether abicalls code might use a GOT. */ \ 529 if (TARGET_ABICALLS) \ 530 builtin_define ("__mips_abicalls"); \ 531 \ 532 /* Whether Loongson vector modes are enabled. */ \ 533 if (TARGET_LOONGSON_VECTORS) \ 534 builtin_define ("__mips_loongson_vector_rev"); \ 535 \ 536 /* Historical Octeon macro. */ \ 537 if (TARGET_OCTEON) \ 538 builtin_define ("__OCTEON__"); \ 539 \ 540 if (TARGET_SYNCI) \ 541 builtin_define ("__mips_synci"); \ 542 \ 543 /* Macros dependent on the C dialect. */ \ 544 if (preprocessing_asm_p ()) \ 545 { \ 546 builtin_define_std ("LANGUAGE_ASSEMBLY"); \ 547 builtin_define ("_LANGUAGE_ASSEMBLY"); \ 548 } \ 549 else if (c_dialect_cxx ()) \ 550 { \ 551 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \ 552 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \ 553 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \ 554 } \ 555 else \ 556 { \ 557 builtin_define_std ("LANGUAGE_C"); \ 558 builtin_define ("_LANGUAGE_C"); \ 559 } \ 560 if (c_dialect_objc ()) \ 561 { \ 562 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \ 563 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \ 564 /* Bizarre, but retained for backwards compatibility. */ \ 565 builtin_define_std ("LANGUAGE_C"); \ 566 builtin_define ("_LANGUAGE_C"); \ 567 } \ 568 \ 569 if (mips_abi == ABI_EABI) \ 570 builtin_define ("__mips_eabi"); \ 571 \ 572 if (TARGET_CACHE_BUILTIN) \ 573 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \ 574 } \ 575 while (0) 576 577 /* Default target_flags if no switches are specified */ 578 579 #ifndef TARGET_DEFAULT 580 #define TARGET_DEFAULT 0 581 #endif 582 583 #ifndef TARGET_CPU_DEFAULT 584 #define TARGET_CPU_DEFAULT 0 585 #endif 586 587 #ifndef TARGET_ENDIAN_DEFAULT 588 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN 589 #endif 590 591 #ifdef IN_LIBGCC2 592 #undef TARGET_64BIT 593 /* Make this compile time constant for libgcc2 */ 594 #ifdef __mips64 595 #define TARGET_64BIT 1 596 #else 597 #define TARGET_64BIT 0 598 #endif 599 #endif /* IN_LIBGCC2 */ 600 601 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code 602 when compiled with hardware floating point. This is because MIPS16 603 code cannot save and restore the floating-point registers, which is 604 important if in a mixed MIPS16/non-MIPS16 environment. */ 605 606 #ifdef IN_LIBGCC2 607 #if __mips_hard_float 608 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__)) 609 #endif 610 #endif /* IN_LIBGCC2 */ 611 612 #define TARGET_LIBGCC_SDATA_SECTION ".sdata" 613 614 #ifndef MULTILIB_ENDIAN_DEFAULT 615 #if TARGET_ENDIAN_DEFAULT == 0 616 #define MULTILIB_ENDIAN_DEFAULT "EL" 617 #else 618 #define MULTILIB_ENDIAN_DEFAULT "EB" 619 #endif 620 #endif 621 622 #ifndef MULTILIB_ISA_DEFAULT 623 #if MIPS_ISA_DEFAULT == 1 624 #define MULTILIB_ISA_DEFAULT "mips1" 625 #elif MIPS_ISA_DEFAULT == 2 626 #define MULTILIB_ISA_DEFAULT "mips2" 627 #elif MIPS_ISA_DEFAULT == 3 628 #define MULTILIB_ISA_DEFAULT "mips3" 629 #elif MIPS_ISA_DEFAULT == 4 630 #define MULTILIB_ISA_DEFAULT "mips4" 631 #elif MIPS_ISA_DEFAULT == 32 632 #define MULTILIB_ISA_DEFAULT "mips32" 633 #elif MIPS_ISA_DEFAULT == 33 634 #define MULTILIB_ISA_DEFAULT "mips32r2" 635 #elif MIPS_ISA_DEFAULT == 64 636 #define MULTILIB_ISA_DEFAULT "mips64" 637 #elif MIPS_ISA_DEFAULT == 65 638 #define MULTILIB_ISA_DEFAULT "mips64r2" 639 #else 640 #define MULTILIB_ISA_DEFAULT "mips1" 641 #endif 642 #endif 643 644 #ifndef MIPS_ABI_DEFAULT 645 #define MIPS_ABI_DEFAULT ABI_32 646 #endif 647 648 /* Use the most portable ABI flag for the ASM specs. */ 649 650 #if MIPS_ABI_DEFAULT == ABI_32 651 #define MULTILIB_ABI_DEFAULT "mabi=32" 652 #elif MIPS_ABI_DEFAULT == ABI_O64 653 #define MULTILIB_ABI_DEFAULT "mabi=o64" 654 #elif MIPS_ABI_DEFAULT == ABI_N32 655 #define MULTILIB_ABI_DEFAULT "mabi=n32" 656 #elif MIPS_ABI_DEFAULT == ABI_64 657 #define MULTILIB_ABI_DEFAULT "mabi=64" 658 #elif MIPS_ABI_DEFAULT == ABI_EABI 659 #define MULTILIB_ABI_DEFAULT "mabi=eabi" 660 #endif 661 662 #ifndef MULTILIB_DEFAULTS 663 #define MULTILIB_DEFAULTS \ 664 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT } 665 #endif 666 667 /* We must pass -EL to the linker by default for little endian embedded 668 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the 669 linker will default to using big-endian output files. The OUTPUT_FORMAT 670 line must be in the linker script, otherwise -EB/-EL will not work. */ 671 672 #ifndef ENDIAN_SPEC 673 #if TARGET_ENDIAN_DEFAULT == 0 674 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}" 675 #else 676 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}" 677 #endif 678 #endif 679 680 /* A spec condition that matches all non-mips16 -mips arguments. */ 681 682 #define MIPS_ISA_LEVEL_OPTION_SPEC \ 683 "mips1|mips2|mips3|mips4|mips32*|mips64*" 684 685 /* A spec condition that matches all non-mips16 architecture arguments. */ 686 687 #define MIPS_ARCH_OPTION_SPEC \ 688 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*" 689 690 /* A spec that infers a -mips argument from an -march argument, 691 or injects the default if no architecture is specified. */ 692 693 #define MIPS_ISA_LEVEL_SPEC \ 694 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \ 695 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \ 696 %{march=mips2|march=r6000:-mips2} \ 697 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \ 698 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \ 699 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \ 700 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \ 701 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \ 702 |march=34k*|march=74k*|march=m14k*|march=1004k*: -mips32r2} \ 703 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \ 704 |march=xlr: -mips64} \ 705 %{march=mips64r2|march=loongson3a|march=octeon|march=xlp: -mips64r2} \ 706 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}" 707 708 /* A spec that infers a -mhard-float or -msoft-float setting from an 709 -march argument. Note that soft-float and hard-float code are not 710 link-compatible. */ 711 712 #define MIPS_ARCH_FLOAT_SPEC \ 713 "%{mhard-float|msoft-float|mno-float|march=mips*:; \ 714 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \ 715 |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \ 716 |march=m14k*|march=octeon|march=xlr: -msoft-float; \ 717 march=*: -mhard-float}" 718 719 /* A spec condition that matches 32-bit options. It only works if 720 MIPS_ISA_LEVEL_SPEC has been applied. */ 721 722 #define MIPS_32BIT_OPTION_SPEC \ 723 "mips1|mips2|mips32*|mgp32" 724 725 /* Infer a -msynci setting from a -mips argument, on the assumption that 726 -msynci is desired where possible. */ 727 #define MIPS_ISA_SYNCI_SPEC \ 728 "%{msynci|mno-synci:;:%{mips32r2|mips64r2:-msynci;:-mno-synci}}" 729 730 #if (MIPS_ABI_DEFAULT == ABI_O64 \ 731 || MIPS_ABI_DEFAULT == ABI_N32 \ 732 || MIPS_ABI_DEFAULT == ABI_64) 733 #define OPT_ARCH64 "mabi=32|mgp32:;" 734 #define OPT_ARCH32 "mabi=32|mgp32" 735 #else 736 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64" 737 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;" 738 #endif 739 740 /* Support for a compile-time default CPU, et cetera. The rules are: 741 --with-arch is ignored if -march is specified or a -mips is specified 742 (other than -mips16); likewise --with-arch-32 and --with-arch-64. 743 --with-tune is ignored if -mtune is specified; likewise 744 --with-tune-32 and --with-tune-64. 745 --with-abi is ignored if -mabi is specified. 746 --with-float is ignored if -mhard-float or -msoft-float are 747 specified. 748 --with-nan is ignored if -mnan is specified. 749 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are 750 specified. */ 751 #define OPTION_DEFAULT_SPECS \ 752 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \ 753 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \ 754 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \ 755 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ 756 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \ 757 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \ 758 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \ 759 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \ 760 {"fpu", "%{!msingle-float:%{!mdouble-float:-m%(VALUE)-float}}" }, \ 761 {"nan", "%{!mnan=*:-mnan=%(VALUE)}" }, \ 762 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \ 763 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \ 764 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \ 765 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" } 766 767 /* A spec that infers the -mdsp setting from an -march argument. */ 768 #define BASE_DRIVER_SELF_SPECS \ 769 "%{!mno-dsp: \ 770 %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k*: -mdsp} \ 771 %{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}" 772 773 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS 774 775 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \ 776 && ISA_HAS_COND_TRAP) 777 778 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16) 779 780 /* True if the ABI can only work with 64-bit integer registers. We 781 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but 782 otherwise floating-point registers must also be 64-bit. */ 783 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64) 784 785 /* Likewise for 32-bit regs. */ 786 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32) 787 788 /* True if the file format uses 64-bit symbols. At present, this is 789 only true for n64, which uses 64-bit ELF. */ 790 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64) 791 792 /* True if symbols are 64 bits wide. This is usually determined by 793 the ABI's file format, but it can be overridden by -msym32. Note that 794 overriding the size with -msym32 changes the ABI of relocatable objects, 795 although it doesn't change the ABI of a fully-linked object. */ 796 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \ 797 && Pmode == DImode \ 798 && !TARGET_SYM32) 799 800 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */ 801 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \ 802 || ISA_MIPS4 \ 803 || ISA_MIPS64 \ 804 || ISA_MIPS64R2) 805 806 /* ISA has branch likely instructions (e.g. mips2). */ 807 /* Disable branchlikely for tx39 until compare rewrite. They haven't 808 been generated up to this point. */ 809 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1) 810 811 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */ 812 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \ 813 || TARGET_MIPS5400 \ 814 || TARGET_MIPS5500 \ 815 || TARGET_MIPS5900 \ 816 || TARGET_MIPS7000 \ 817 || TARGET_MIPS9000 \ 818 || TARGET_MAD \ 819 || ISA_MIPS32 \ 820 || ISA_MIPS32R2 \ 821 || ISA_MIPS64 \ 822 || ISA_MIPS64R2) \ 823 && !TARGET_MIPS16) 824 825 /* ISA has a three-operand multiplication instruction. */ 826 #define ISA_HAS_DMUL3 (TARGET_64BIT \ 827 && TARGET_OCTEON \ 828 && !TARGET_MIPS16) 829 830 /* ISA supports instructions DMULT and DMULTU. */ 831 #define ISA_HAS_DMULT (TARGET_64BIT && !TARGET_MIPS5900) 832 833 /* ISA supports instructions MULT and MULTU. 834 This is always true, but the macro is needed for ISA_HAS_<D>MULT 835 in mips.md. */ 836 #define ISA_HAS_MULT (1) 837 838 /* ISA supports instructions DDIV and DDIVU. */ 839 #define ISA_HAS_DDIV (TARGET_64BIT && !TARGET_MIPS5900) 840 841 /* ISA supports instructions DIV and DIVU. 842 This is always true, but the macro is needed for ISA_HAS_<D>DIV 843 in mips.md. */ 844 #define ISA_HAS_DIV (1) 845 846 #define ISA_HAS_DIV3 ((TARGET_LOONGSON_2EF \ 847 || TARGET_LOONGSON_3A) \ 848 && !TARGET_MIPS16) 849 850 /* ISA has the floating-point conditional move instructions introduced 851 in mips4. */ 852 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \ 853 || ISA_MIPS32 \ 854 || ISA_MIPS32R2 \ 855 || ISA_MIPS64 \ 856 || ISA_MIPS64R2) \ 857 && !TARGET_MIPS5500 \ 858 && !TARGET_MIPS16) 859 860 /* ISA has the integer conditional move instructions introduced in mips4 and 861 ST Loongson 2E/2F. */ 862 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \ 863 || TARGET_MIPS5900 \ 864 || TARGET_LOONGSON_2EF) 865 866 /* ISA has LDC1 and SDC1. */ 867 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 \ 868 && !TARGET_MIPS5900 \ 869 && !TARGET_MIPS16) 870 871 /* ISA has the mips4 FP condition code instructions: FP-compare to CC, 872 branch on CC, and move (both FP and non-FP) on CC. */ 873 #define ISA_HAS_8CC (ISA_MIPS4 \ 874 || ISA_MIPS32 \ 875 || ISA_MIPS32R2 \ 876 || ISA_MIPS64 \ 877 || ISA_MIPS64R2) 878 879 /* This is a catch all for other mips4 instructions: indexed load, the 880 FP madd and msub instructions, and the FP recip and recip sqrt 881 instructions. Note that this macro should only be used by other 882 ISA_HAS_* macros. */ 883 #define ISA_HAS_FP4 ((ISA_MIPS4 \ 884 || ISA_MIPS32R2 \ 885 || ISA_MIPS64 \ 886 || ISA_MIPS64R2) \ 887 && !TARGET_MIPS16) 888 889 /* ISA has floating-point indexed load and store instructions 890 (LWXC1, LDXC1, SWXC1 and SDXC1). */ 891 #define ISA_HAS_LXC1_SXC1 ISA_HAS_FP4 892 893 /* ISA has paired-single instructions. */ 894 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2) 895 896 /* ISA has conditional trap instructions. */ 897 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \ 898 && !TARGET_MIPS16) 899 900 /* ISA has integer multiply-accumulate instructions, madd and msub. */ 901 #define ISA_HAS_MADD_MSUB (ISA_MIPS32 \ 902 || ISA_MIPS32R2 \ 903 || ISA_MIPS64 \ 904 || ISA_MIPS64R2) 905 906 /* Integer multiply-accumulate instructions should be generated. */ 907 #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16) 908 909 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */ 910 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4 911 912 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */ 913 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF 914 915 /* ISA has floating-point nmadd and nmsub instructions 916 'd = -((a * b) [+-] c)'. */ 917 #define ISA_HAS_NMADD4_NMSUB4 ISA_HAS_FP4 918 919 /* ISA has floating-point nmadd and nmsub instructions 920 'c = -((a * b) [+-] c)'. */ 921 #define ISA_HAS_NMADD3_NMSUB3 TARGET_LOONGSON_2EF 922 923 /* ISA has floating-point RECIP.fmt and RSQRT.fmt instructions. The 924 MIPS64 rev. 1 ISA says that RECIP.D and RSQRT.D are unpredictable when 925 doubles are stored in pairs of FPRs, so for safety's sake, we apply 926 this restriction to the MIPS IV ISA too. */ 927 #define ISA_HAS_FP_RECIP_RSQRT(MODE) \ 928 (((ISA_HAS_FP4 \ 929 && ((MODE) == SFmode \ 930 || ((TARGET_FLOAT64 \ 931 || ISA_MIPS32R2 \ 932 || ISA_MIPS64R2) \ 933 && (MODE) == DFmode))) \ 934 || (TARGET_SB1 \ 935 && (MODE) == V2SFmode)) \ 936 && !TARGET_MIPS16) 937 938 /* ISA has count leading zeroes/ones instruction (not implemented). */ 939 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \ 940 || ISA_MIPS32R2 \ 941 || ISA_MIPS64 \ 942 || ISA_MIPS64R2) \ 943 && !TARGET_MIPS16) 944 945 /* ISA has three operand multiply instructions that put 946 the high part in an accumulator: mulhi or mulhiu. */ 947 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \ 948 || TARGET_MIPS5500 \ 949 || TARGET_SR71K) \ 950 && !TARGET_MIPS16) 951 952 /* ISA has three operand multiply instructions that negate the 953 result and put the result in an accumulator. */ 954 #define ISA_HAS_MULS ((TARGET_MIPS5400 \ 955 || TARGET_MIPS5500 \ 956 || TARGET_SR71K) \ 957 && !TARGET_MIPS16) 958 959 /* ISA has three operand multiply instructions that subtract the 960 result from a 4th operand and put the result in an accumulator. */ 961 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \ 962 || TARGET_MIPS5500 \ 963 || TARGET_SR71K) \ 964 && !TARGET_MIPS16) 965 966 /* ISA has three operand multiply instructions that add the result 967 to a 4th operand and put the result in an accumulator. */ 968 #define ISA_HAS_MACC ((TARGET_MIPS4120 \ 969 || TARGET_MIPS4130 \ 970 || TARGET_MIPS5400 \ 971 || TARGET_MIPS5500 \ 972 || TARGET_SR71K) \ 973 && !TARGET_MIPS16) 974 975 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */ 976 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \ 977 || TARGET_MIPS4130) \ 978 && !TARGET_MIPS16) 979 980 /* ISA has the "ror" (rotate right) instructions. */ 981 #define ISA_HAS_ROR ((ISA_MIPS32R2 \ 982 || ISA_MIPS64R2 \ 983 || TARGET_MIPS5400 \ 984 || TARGET_MIPS5500 \ 985 || TARGET_SR71K \ 986 || TARGET_SMARTMIPS) \ 987 && !TARGET_MIPS16) 988 989 /* ISA has the WSBH (word swap bytes within halfwords) instruction. 990 64-bit targets also provide DSBH and DSHD. */ 991 #define ISA_HAS_WSBH ((ISA_MIPS32R2 || ISA_MIPS64R2) \ 992 && !TARGET_MIPS16) 993 994 /* ISA has data prefetch instructions. This controls use of 'pref'. */ 995 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \ 996 || TARGET_LOONGSON_2EF \ 997 || TARGET_MIPS5900 \ 998 || ISA_MIPS32 \ 999 || ISA_MIPS32R2 \ 1000 || ISA_MIPS64 \ 1001 || ISA_MIPS64R2) \ 1002 && !TARGET_MIPS16) 1003 1004 /* ISA has data indexed prefetch instructions. This controls use of 1005 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT. 1006 (prefx is a cop1x instruction, so can only be used if FP is 1007 enabled.) */ 1008 #define ISA_HAS_PREFETCHX ISA_HAS_FP4 1009 1010 /* True if trunc.w.s and trunc.w.d are real (not synthetic) 1011 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d 1012 also requires TARGET_DOUBLE_FLOAT. */ 1013 #define ISA_HAS_TRUNC_W (!ISA_MIPS1) 1014 1015 /* ISA includes the MIPS32r2 seb and seh instructions. */ 1016 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \ 1017 || ISA_MIPS64R2) \ 1018 && !TARGET_MIPS16) 1019 1020 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */ 1021 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \ 1022 || ISA_MIPS64R2) \ 1023 && !TARGET_MIPS16) 1024 1025 /* ISA has instructions for accessing top part of 64-bit fp regs. */ 1026 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \ 1027 && (ISA_MIPS32R2 \ 1028 || ISA_MIPS64R2)) 1029 1030 /* ISA has lwxs instruction (load w/scaled index address. */ 1031 #define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \ 1032 && !TARGET_MIPS16) 1033 1034 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */ 1035 #define ISA_HAS_LBX (TARGET_OCTEON2) 1036 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2) 1037 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2) 1038 #define ISA_HAS_LHUX (TARGET_OCTEON2) 1039 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2) 1040 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT) 1041 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \ 1042 && TARGET_64BIT) 1043 1044 /* The DSP ASE is available. */ 1045 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16) 1046 1047 /* Revision 2 of the DSP ASE is available. */ 1048 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16) 1049 1050 /* True if the result of a load is not available to the next instruction. 1051 A nop will then be needed between instructions like "lw $4,..." 1052 and "addiu $4,$4,1". */ 1053 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \ 1054 && !TARGET_MIPS3900 \ 1055 && !TARGET_MIPS5900 \ 1056 && !TARGET_MIPS16 \ 1057 && !TARGET_MICROMIPS) 1058 1059 /* Likewise mtc1 and mfc1. */ 1060 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \ 1061 && !TARGET_MIPS5900 \ 1062 && !TARGET_LOONGSON_2EF) 1063 1064 /* Likewise floating-point comparisons. */ 1065 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \ 1066 && !TARGET_MIPS5900 \ 1067 && !TARGET_LOONGSON_2EF) 1068 1069 /* True if mflo and mfhi can be immediately followed by instructions 1070 which write to the HI and LO registers. 1071 1072 According to MIPS specifications, MIPS ISAs I, II, and III need 1073 (at least) two instructions between the reads of HI/LO and 1074 instructions which write them, and later ISAs do not. Contradicting 1075 the MIPS specifications, some MIPS IV processor user manuals (e.g. 1076 the UM for the NEC Vr5000) document needing the instructions between 1077 HI/LO reads and writes, as well. Therefore, we declare only MIPS32, 1078 MIPS64 and later ISAs to have the interlocks, plus any specific 1079 earlier-ISA CPUs for which CPU documentation declares that the 1080 instructions are really interlocked. */ 1081 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \ 1082 || ISA_MIPS32R2 \ 1083 || ISA_MIPS64 \ 1084 || ISA_MIPS64R2 \ 1085 || TARGET_MIPS5500 \ 1086 || TARGET_MIPS5900 \ 1087 || TARGET_LOONGSON_2EF) 1088 1089 /* ISA includes synci, jr.hb and jalr.hb. */ 1090 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \ 1091 || ISA_MIPS64R2) \ 1092 && !TARGET_MIPS16) 1093 1094 /* ISA includes sync. */ 1095 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16) 1096 #define GENERATE_SYNC \ 1097 (target_flags_explicit & MASK_LLSC \ 1098 ? TARGET_LLSC && !TARGET_MIPS16 \ 1099 : ISA_HAS_SYNC) 1100 1101 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC 1102 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC 1103 instructions. */ 1104 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS5900 && !TARGET_MIPS16) 1105 #define GENERATE_LL_SC \ 1106 (target_flags_explicit & MASK_LLSC \ 1107 ? TARGET_LLSC && !TARGET_MIPS16 \ 1108 : ISA_HAS_LL_SC) 1109 1110 #define ISA_HAS_SWAP (TARGET_XLP) 1111 #define ISA_HAS_LDADD (TARGET_XLP) 1112 1113 /* ISA includes the baddu instruction. */ 1114 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16) 1115 1116 /* ISA includes the bbit* instructions. */ 1117 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16) 1118 1119 /* ISA includes the cins instruction. */ 1120 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16) 1121 1122 /* ISA includes the exts instruction. */ 1123 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16) 1124 1125 /* ISA includes the seq and sne instructions. */ 1126 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16) 1127 1128 /* ISA includes the pop instruction. */ 1129 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16) 1130 1131 /* The CACHE instruction is available in non-MIPS16 code. */ 1132 #define TARGET_CACHE_BUILTIN (mips_isa >= 3) 1133 1134 /* The CACHE instruction is available. */ 1135 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16) 1136 1137 /* Tell collect what flags to pass to nm. */ 1138 #ifndef NM_FLAGS 1139 #define NM_FLAGS "-Bn" 1140 #endif 1141 1142 1143 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to 1144 the assembler. It may be overridden by subtargets. 1145 1146 Beginning with gas 2.13, -mdebug must be passed to correctly handle 1147 COFF debugging info. */ 1148 1149 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC 1150 #define SUBTARGET_ASM_DEBUGGING_SPEC "\ 1151 %{g} %{g0} %{g1} %{g2} %{g3} \ 1152 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \ 1153 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \ 1154 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \ 1155 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \ 1156 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}" 1157 #endif 1158 1159 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be 1160 overridden by subtargets. */ 1161 1162 #ifndef SUBTARGET_ASM_SPEC 1163 #define SUBTARGET_ASM_SPEC "" 1164 #endif 1165 1166 #undef ASM_SPEC 1167 #define ASM_SPEC "\ 1168 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \ 1169 %{mips32*} %{mips64*} \ 1170 %{mips16} %{mno-mips16:-no-mips16} \ 1171 %{mmicromips} %{mno-micromips} \ 1172 %{mips3d} %{mno-mips3d:-no-mips3d} \ 1173 %{mdmx} %{mno-mdmx:-no-mdmx} \ 1174 %{mdsp} %{mno-dsp} \ 1175 %{mdspr2} %{mno-dspr2} \ 1176 %{mmcu} %{mno-mcu} \ 1177 %{meva} %{mno-eva} \ 1178 %{mvirt} %{mno-virt} \ 1179 %{msmartmips} %{mno-smartmips} \ 1180 %{mmt} %{mno-mt} \ 1181 %{mfix-rm7000} %{mno-fix-rm7000} \ 1182 %{mfix-vr4120} %{mfix-vr4130} \ 1183 %{mfix-24k} \ 1184 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \ 1185 %(subtarget_asm_debugging_spec) \ 1186 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \ 1187 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \ 1188 %{mfp32} %{mfp64} %{mnan=*} \ 1189 %{mshared} %{mno-shared} \ 1190 %{msym32} %{mno-sym32} \ 1191 %{mtune=*} \ 1192 %(subtarget_asm_spec)" 1193 1194 /* Extra switches sometimes passed to the linker. */ 1195 1196 #ifndef LINK_SPEC 1197 #define LINK_SPEC "\ 1198 %(endian_spec) \ 1199 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \ 1200 %{shared}" 1201 #endif /* LINK_SPEC defined */ 1202 1203 1204 /* Specs for the compiler proper */ 1205 1206 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be 1207 overridden by subtargets. */ 1208 #ifndef SUBTARGET_CC1_SPEC 1209 #define SUBTARGET_CC1_SPEC "" 1210 #endif 1211 1212 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */ 1213 1214 #undef CC1_SPEC 1215 #define CC1_SPEC "\ 1216 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \ 1217 %(subtarget_cc1_spec)" 1218 1219 /* Preprocessor specs. */ 1220 1221 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be 1222 overridden by subtargets. */ 1223 #ifndef SUBTARGET_CPP_SPEC 1224 #define SUBTARGET_CPP_SPEC "" 1225 #endif 1226 1227 #define CPP_SPEC "%(subtarget_cpp_spec)" 1228 1229 /* This macro defines names of additional specifications to put in the specs 1230 that can be used in various specifications like CC1_SPEC. Its definition 1231 is an initializer with a subgrouping for each command option. 1232 1233 Each subgrouping contains a string constant, that defines the 1234 specification name, and a string constant that used by the GCC driver 1235 program. 1236 1237 Do not define this macro if it does not need to do anything. */ 1238 1239 #define EXTRA_SPECS \ 1240 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \ 1241 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 1242 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \ 1243 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \ 1244 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \ 1245 { "endian_spec", ENDIAN_SPEC }, \ 1246 SUBTARGET_EXTRA_SPECS 1247 1248 #ifndef SUBTARGET_EXTRA_SPECS 1249 #define SUBTARGET_EXTRA_SPECS 1250 #endif 1251 1252 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */ 1253 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */ 1254 1255 #ifndef PREFERRED_DEBUGGING_TYPE 1256 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG 1257 #endif 1258 1259 /* The size of DWARF addresses should be the same as the size of symbols 1260 in the target file format. They shouldn't depend on things like -msym32, 1261 because many DWARF consumers do not allow the mixture of address sizes 1262 that one would then get from linking -msym32 code with -msym64 code. 1263 1264 Note that the default POINTER_SIZE test is not appropriate for MIPS. 1265 EABI64 has 64-bit pointers but uses 32-bit ELF. */ 1266 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4) 1267 1268 /* By default, turn on GDB extensions. */ 1269 #define DEFAULT_GDB_EXTENSIONS 1 1270 1271 /* Local compiler-generated symbols must have a prefix that the assembler 1272 understands. By default, this is $, although some targets (e.g., 1273 NetBSD-ELF) need to override this. */ 1274 1275 #ifndef LOCAL_LABEL_PREFIX 1276 #define LOCAL_LABEL_PREFIX "$" 1277 #endif 1278 1279 /* By default on the mips, external symbols do not have an underscore 1280 prepended, but some targets (e.g., NetBSD) require this. */ 1281 1282 #ifndef USER_LABEL_PREFIX 1283 #define USER_LABEL_PREFIX "" 1284 #endif 1285 1286 /* On Sun 4, this limit is 2048. We use 1500 to be safe, 1287 since the length can run past this up to a continuation point. */ 1288 #undef DBX_CONTIN_LENGTH 1289 #define DBX_CONTIN_LENGTH 1500 1290 1291 /* How to renumber registers for dbx and gdb. */ 1292 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO] 1293 1294 /* The mapping from gcc register number to DWARF 2 CFA column number. */ 1295 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO] 1296 1297 /* The DWARF 2 CFA column which tracks the return address. */ 1298 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM 1299 1300 /* Before the prologue, RA lives in r31. */ 1301 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM) 1302 1303 /* Describe how we implement __builtin_eh_return. */ 1304 #define EH_RETURN_DATA_REGNO(N) \ 1305 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM) 1306 1307 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3) 1308 1309 #define EH_USES(N) mips_eh_uses (N) 1310 1311 /* Offsets recorded in opcodes are a multiple of this alignment factor. 1312 The default for this in 64-bit mode is 8, which causes problems with 1313 SFmode register saves. */ 1314 #define DWARF_CIE_DATA_ALIGNMENT -4 1315 1316 /* Correct the offset of automatic variables and arguments. Note that 1317 the MIPS debug format wants all automatic variables and arguments 1318 to be in terms of the virtual frame pointer (stack pointer before 1319 any adjustment in the function), while the MIPS 3.0 linker wants 1320 the frame pointer to be the stack pointer after the initial 1321 adjustment. */ 1322 1323 #define DEBUGGER_AUTO_OFFSET(X) \ 1324 mips_debugger_offset (X, (HOST_WIDE_INT) 0) 1325 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \ 1326 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET) 1327 1328 /* Target machine storage layout */ 1329 1330 #define BITS_BIG_ENDIAN 0 1331 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 1332 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 1333 1334 #define MAX_BITS_PER_WORD 64 1335 1336 /* Width of a word, in units (bytes). */ 1337 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 1338 #ifndef IN_LIBGCC2 1339 #define MIN_UNITS_PER_WORD 4 1340 #endif 1341 1342 /* For MIPS, width of a floating point register. */ 1343 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4) 1344 1345 /* The number of consecutive floating-point registers needed to store the 1346 largest format supported by the FPU. */ 1347 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2) 1348 1349 /* The number of consecutive floating-point registers needed to store the 1350 smallest format supported by the FPU. */ 1351 #define MIN_FPRS_PER_FMT \ 1352 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \ 1353 ? 1 : MAX_FPRS_PER_FMT) 1354 1355 /* The largest size of value that can be held in floating-point 1356 registers and moved with a single instruction. */ 1357 #define UNITS_PER_HWFPVALUE \ 1358 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG) 1359 1360 /* The largest size of value that can be held in floating-point 1361 registers. */ 1362 #define UNITS_PER_FPVALUE \ 1363 (TARGET_SOFT_FLOAT_ABI ? 0 \ 1364 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \ 1365 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT) 1366 1367 /* The number of bytes in a double. */ 1368 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT) 1369 1370 /* Set the sizes of the core types. */ 1371 #define SHORT_TYPE_SIZE 16 1372 #define INT_TYPE_SIZE 32 1373 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32) 1374 #define LONG_LONG_TYPE_SIZE 64 1375 1376 #define FLOAT_TYPE_SIZE 32 1377 #define DOUBLE_TYPE_SIZE 64 1378 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64) 1379 1380 /* Define the sizes of fixed-point types. */ 1381 #define SHORT_FRACT_TYPE_SIZE 8 1382 #define FRACT_TYPE_SIZE 16 1383 #define LONG_FRACT_TYPE_SIZE 32 1384 #define LONG_LONG_FRACT_TYPE_SIZE 64 1385 1386 #define SHORT_ACCUM_TYPE_SIZE 16 1387 #define ACCUM_TYPE_SIZE 32 1388 #define LONG_ACCUM_TYPE_SIZE 64 1389 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC 1390 doesn't support 128-bit integers for MIPS32 currently. */ 1391 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64) 1392 1393 /* long double is not a fixed mode, but the idea is that, if we 1394 support long double, we also want a 128-bit integer type. */ 1395 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE 1396 1397 #ifdef IN_LIBGCC2 1398 #if ((defined _ABIN32 && _MIPS_SIM == _ABIN32) \ 1399 || (defined _ABI64 && _MIPS_SIM == _ABI64)) 1400 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 1401 # else 1402 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 1403 # endif 1404 #endif 1405 1406 /* Width in bits of a pointer. */ 1407 #ifndef POINTER_SIZE 1408 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32) 1409 #endif 1410 1411 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 1412 #define PARM_BOUNDARY BITS_PER_WORD 1413 1414 /* Allocation boundary (in *bits*) for the code of a function. */ 1415 #define FUNCTION_BOUNDARY 32 1416 1417 /* Alignment of field after `int : 0' in a structure. */ 1418 #define EMPTY_FIELD_BOUNDARY 32 1419 1420 /* Every structure's size must be a multiple of this. */ 1421 /* 8 is observed right on a DECstation and on riscos 4.02. */ 1422 #define STRUCTURE_SIZE_BOUNDARY 8 1423 1424 /* There is no point aligning anything to a rounder boundary than this. */ 1425 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE 1426 1427 /* All accesses must be aligned. */ 1428 #define STRICT_ALIGNMENT 1 1429 1430 /* Define this if you wish to imitate the way many other C compilers 1431 handle alignment of bitfields and the structures that contain 1432 them. 1433 1434 The behavior is that the type written for a bit-field (`int', 1435 `short', or other integer type) imposes an alignment for the 1436 entire structure, as if the structure really did contain an 1437 ordinary field of that type. In addition, the bit-field is placed 1438 within the structure so that it would fit within such a field, 1439 not crossing a boundary for it. 1440 1441 Thus, on most machines, a bit-field whose type is written as `int' 1442 would not cross a four-byte boundary, and would force four-byte 1443 alignment for the whole structure. (The alignment used may not 1444 be four bytes; it is controlled by the other alignment 1445 parameters.) 1446 1447 If the macro is defined, its definition should be a C expression; 1448 a nonzero value for the expression enables this behavior. */ 1449 1450 #define PCC_BITFIELD_TYPE_MATTERS 1 1451 1452 /* If defined, a C expression to compute the alignment given to a 1453 constant that is being placed in memory. CONSTANT is the constant 1454 and ALIGN is the alignment that the object would ordinarily have. 1455 The value of this macro is used instead of that alignment to align 1456 the object. 1457 1458 If this macro is not defined, then ALIGN is used. 1459 1460 The typical use of this macro is to increase alignment for string 1461 constants to be word aligned so that `strcpy' calls that copy 1462 constants can be done inline. */ 1463 1464 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 1465 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \ 1466 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 1467 1468 /* If defined, a C expression to compute the alignment for a static 1469 variable. TYPE is the data type, and ALIGN is the alignment that 1470 the object would ordinarily have. The value of this macro is used 1471 instead of that alignment to align the object. 1472 1473 If this macro is not defined, then ALIGN is used. 1474 1475 One use of this macro is to increase alignment of medium-size 1476 data to make it all fit in fewer cache lines. Another is to 1477 cause character arrays to be word-aligned so that `strcpy' calls 1478 that copy constants to character arrays can be done inline. */ 1479 1480 #undef DATA_ALIGNMENT 1481 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 1482 ((((ALIGN) < BITS_PER_WORD) \ 1483 && (TREE_CODE (TYPE) == ARRAY_TYPE \ 1484 || TREE_CODE (TYPE) == UNION_TYPE \ 1485 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 1486 1487 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause 1488 character arrays to be word-aligned so that `strcpy' calls that copy 1489 constants to character arrays can be done inline, and 'strcmp' can be 1490 optimised to use word loads. */ 1491 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 1492 DATA_ALIGNMENT (TYPE, ALIGN) 1493 1494 #define PAD_VARARGS_DOWN \ 1495 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward) 1496 1497 /* Define if operations between registers always perform the operation 1498 on the full register even if a narrower mode is specified. */ 1499 #define WORD_REGISTER_OPERATIONS 1500 1501 /* When in 64-bit mode, move insns will sign extend SImode and CCmode 1502 moves. All other references are zero extended. */ 1503 #define LOAD_EXTEND_OP(MODE) \ 1504 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \ 1505 ? SIGN_EXTEND : ZERO_EXTEND) 1506 1507 /* Define this macro if it is advisable to hold scalars in registers 1508 in a wider mode than that declared by the program. In such cases, 1509 the value is constrained to be within the bounds of the declared 1510 type, but kept valid in the wider mode. The signedness of the 1511 extension may differ from that of the type. */ 1512 1513 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 1514 if (GET_MODE_CLASS (MODE) == MODE_INT \ 1515 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 1516 { \ 1517 if ((MODE) == SImode) \ 1518 (UNSIGNEDP) = 0; \ 1519 (MODE) = Pmode; \ 1520 } 1521 1522 /* Pmode is always the same as ptr_mode, but not always the same as word_mode. 1523 Extensions of pointers to word_mode must be signed. */ 1524 #define POINTERS_EXTEND_UNSIGNED false 1525 1526 /* Define if loading short immediate values into registers sign extends. */ 1527 #define SHORT_IMMEDIATES_SIGN_EXTEND 1528 1529 /* The [d]clz instructions have the natural values at 0. */ 1530 1531 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1532 ((VALUE) = GET_MODE_BITSIZE (MODE), 2) 1533 1534 /* Standard register usage. */ 1535 1536 /* Number of hardware registers. We have: 1537 1538 - 32 integer registers 1539 - 32 floating point registers 1540 - 8 condition code registers 1541 - 2 accumulator registers (hi and lo) 1542 - 32 registers each for coprocessors 0, 2 and 3 1543 - 4 fake registers: 1544 - ARG_POINTER_REGNUM 1545 - FRAME_POINTER_REGNUM 1546 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details) 1547 - CPRESTORE_SLOT_REGNUM 1548 - 2 dummy entries that were used at various times in the past. 1549 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE 1550 - 6 DSP control registers */ 1551 1552 #define FIRST_PSEUDO_REGISTER 188 1553 1554 /* By default, fix the kernel registers ($26 and $27), the global 1555 pointer ($28) and the stack pointer ($29). This can change 1556 depending on the command-line options. 1557 1558 Regarding coprocessor registers: without evidence to the contrary, 1559 it's best to assume that each coprocessor register has a unique 1560 use. This can be overridden, in, e.g., mips_option_override or 1561 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be 1562 inappropriate for a particular target. */ 1563 1564 #define FIXED_REGISTERS \ 1565 { \ 1566 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1567 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \ 1568 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1569 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1570 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \ 1571 /* COP0 registers */ \ 1572 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1573 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1574 /* COP2 registers */ \ 1575 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1576 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1577 /* COP3 registers */ \ 1578 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1579 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1580 /* 6 DSP accumulator registers & 6 control registers */ \ 1581 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \ 1582 } 1583 1584 1585 /* Set up this array for o32 by default. 1586 1587 Note that we don't mark $31 as a call-clobbered register. The idea is 1588 that it's really the call instructions themselves which clobber $31. 1589 We don't care what the called function does with it afterwards. 1590 1591 This approach makes it easier to implement sibcalls. Unlike normal 1592 calls, sibcalls don't clobber $31, so the register reaches the 1593 called function in tact. EPILOGUE_USES says that $31 is useful 1594 to the called function. */ 1595 1596 #define CALL_USED_REGISTERS \ 1597 { \ 1598 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1599 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \ 1600 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1601 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1602 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1603 /* COP0 registers */ \ 1604 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1605 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1606 /* COP2 registers */ \ 1607 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1608 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1609 /* COP3 registers */ \ 1610 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1611 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1612 /* 6 DSP accumulator registers & 6 control registers */ \ 1613 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ 1614 } 1615 1616 1617 /* Define this since $28, though fixed, is call-saved in many ABIs. */ 1618 1619 #define CALL_REALLY_USED_REGISTERS \ 1620 { /* General registers. */ \ 1621 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1622 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \ 1623 /* Floating-point registers. */ \ 1624 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1625 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1626 /* Others. */ \ 1627 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \ 1628 /* COP0 registers */ \ 1629 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1630 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1631 /* COP2 registers */ \ 1632 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1633 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1634 /* COP3 registers */ \ 1635 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1636 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1637 /* 6 DSP accumulator registers & 6 control registers */ \ 1638 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \ 1639 } 1640 1641 /* Internal macros to classify a register number as to whether it's a 1642 general purpose register, a floating point register, a 1643 multiply/divide register, or a status register. */ 1644 1645 #define GP_REG_FIRST 0 1646 #define GP_REG_LAST 31 1647 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) 1648 #define GP_DBX_FIRST 0 1649 #define K0_REG_NUM (GP_REG_FIRST + 26) 1650 #define K1_REG_NUM (GP_REG_FIRST + 27) 1651 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM)) 1652 1653 #define FP_REG_FIRST 32 1654 #define FP_REG_LAST 63 1655 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1) 1656 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32) 1657 1658 #define MD_REG_FIRST 64 1659 #define MD_REG_LAST 65 1660 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1) 1661 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM) 1662 1663 /* The DWARF 2 CFA column which tracks the return address from a 1664 signal handler context. This means that to maintain backwards 1665 compatibility, no hard register can be assigned this column if it 1666 would need to be handled by the DWARF unwinder. */ 1667 #define DWARF_ALT_FRAME_RETURN_COLUMN 66 1668 1669 #define ST_REG_FIRST 67 1670 #define ST_REG_LAST 74 1671 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1) 1672 1673 1674 /* FIXME: renumber. */ 1675 #define COP0_REG_FIRST 80 1676 #define COP0_REG_LAST 111 1677 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1) 1678 1679 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12) 1680 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13) 1681 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14) 1682 1683 #define COP2_REG_FIRST 112 1684 #define COP2_REG_LAST 143 1685 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1) 1686 1687 #define COP3_REG_FIRST 144 1688 #define COP3_REG_LAST 175 1689 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1) 1690 1691 /* These definitions assume that COP0, 2 and 3 are numbered consecutively. */ 1692 #define ALL_COP_REG_FIRST COP0_REG_FIRST 1693 #define ALL_COP_REG_LAST COP3_REG_LAST 1694 #define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1) 1695 1696 #define DSP_ACC_REG_FIRST 176 1697 #define DSP_ACC_REG_LAST 181 1698 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1) 1699 1700 #define AT_REGNUM (GP_REG_FIRST + 1) 1701 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1) 1702 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST) 1703 1704 /* A few bitfield locations for the coprocessor registers. */ 1705 /* Request Interrupt Priority Level is from bit 10 to bit 15 of 1706 the cause register for the EIC interrupt mode. */ 1707 #define CAUSE_IPL 10 1708 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */ 1709 #define SR_IPL 10 1710 /* Exception Level is at bit 1 of the status register. */ 1711 #define SR_EXL 1 1712 /* Interrupt Enable is at bit 0 of the status register. */ 1713 #define SR_IE 0 1714 1715 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC. 1716 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG 1717 should be used instead. */ 1718 #define FPSW_REGNUM ST_REG_FIRST 1719 1720 #define GP_REG_P(REGNO) \ 1721 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM) 1722 #define M16_REG_P(REGNO) \ 1723 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17) 1724 #define M16STORE_REG_P(REGNO) \ 1725 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17) 1726 #define FP_REG_P(REGNO) \ 1727 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM) 1728 #define MD_REG_P(REGNO) \ 1729 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM) 1730 #define ST_REG_P(REGNO) \ 1731 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM) 1732 #define COP0_REG_P(REGNO) \ 1733 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM) 1734 #define COP2_REG_P(REGNO) \ 1735 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM) 1736 #define COP3_REG_P(REGNO) \ 1737 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM) 1738 #define ALL_COP_REG_P(REGNO) \ 1739 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM) 1740 /* Test if REGNO is one of the 6 new DSP accumulators. */ 1741 #define DSP_ACC_REG_P(REGNO) \ 1742 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM) 1743 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */ 1744 #define ACC_REG_P(REGNO) \ 1745 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO)) 1746 1747 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) 1748 1749 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used 1750 to initialize the mips16 gp pseudo register. */ 1751 #define CONST_GP_P(X) \ 1752 (GET_CODE (X) == CONST \ 1753 && GET_CODE (XEXP (X, 0)) == UNSPEC \ 1754 && XINT (XEXP (X, 0), 1) == UNSPEC_GP) 1755 1756 /* Return coprocessor number from register number. */ 1757 1758 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \ 1759 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \ 1760 : COP3_REG_P (REGNO) ? '3' : '?') 1761 1762 1763 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE) 1764 1765 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1766 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ] 1767 1768 #define MODES_TIEABLE_P mips_modes_tieable_p 1769 1770 /* Register to use for pushing function arguments. */ 1771 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29) 1772 1773 /* These two registers don't really exist: they get eliminated to either 1774 the stack or hard frame pointer. */ 1775 #define ARG_POINTER_REGNUM 77 1776 #define FRAME_POINTER_REGNUM 78 1777 1778 /* $30 is not available on the mips16, so we use $17 as the frame 1779 pointer. */ 1780 #define HARD_FRAME_POINTER_REGNUM \ 1781 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30) 1782 1783 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 1784 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 1785 1786 /* Register in which static-chain is passed to a function. */ 1787 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15) 1788 1789 /* Registers used as temporaries in prologue/epilogue code: 1790 1791 - If a MIPS16 PIC function needs access to _gp, it first loads 1792 the value into MIPS16_PIC_TEMP and then copies it to $gp. 1793 1794 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary 1795 register. The register must not conflict with MIPS16_PIC_TEMP. 1796 1797 - If we aren't generating MIPS16 code, the prologue can also use 1798 MIPS_PROLOGUE_TEMP2 as a general temporary register. 1799 1800 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary 1801 register. 1802 1803 If we're generating MIPS16 code, these registers must come from the 1804 core set of 8. The prologue registers mustn't conflict with any 1805 incoming arguments, the static chain pointer, or the frame pointer. 1806 The epilogue temporary mustn't conflict with the return registers, 1807 the PIC call register ($25), the frame pointer, the EH stack adjustment, 1808 or the EH data registers. 1809 1810 If we're generating interrupt handlers, we use K0 as a temporary register 1811 in prologue/epilogue code. */ 1812 1813 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2) 1814 #define MIPS_PROLOGUE_TEMP_REGNUM \ 1815 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3) 1816 #define MIPS_PROLOGUE_TEMP2_REGNUM \ 1817 (TARGET_MIPS16 \ 1818 ? (gcc_unreachable (), INVALID_REGNUM) \ 1819 : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12) 1820 #define MIPS_EPILOGUE_TEMP_REGNUM \ 1821 (cfun->machine->interrupt_handler_p \ 1822 ? K0_REG_NUM \ 1823 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8)) 1824 1825 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM) 1826 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM) 1827 #define MIPS_PROLOGUE_TEMP2(MODE) \ 1828 gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM) 1829 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM) 1830 1831 /* Define this macro if it is as good or better to call a constant 1832 function address than to call an address kept in a register. */ 1833 #define NO_FUNCTION_CSE 1 1834 1835 /* The ABI-defined global pointer. Sometimes we use a different 1836 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */ 1837 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28) 1838 1839 /* We normally use $28 as the global pointer. However, when generating 1840 n32/64 PIC, it is better for leaf functions to use a call-clobbered 1841 register instead. They can then avoid saving and restoring $28 1842 and perhaps avoid using a frame at all. 1843 1844 When a leaf function uses something other than $28, mips_expand_prologue 1845 will modify pic_offset_table_rtx in place. Take the register number 1846 from there after reload. */ 1847 #define PIC_OFFSET_TABLE_REGNUM \ 1848 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM) 1849 1850 /* Define the classes of registers for register constraints in the 1851 machine description. Also define ranges of constants. 1852 1853 One of the classes must always be named ALL_REGS and include all hard regs. 1854 If there is more than one class, another class must be named NO_REGS 1855 and contain no registers. 1856 1857 The name GENERAL_REGS must be the name of a class (or an alias for 1858 another name such as ALL_REGS). This is the class of registers 1859 that is allowed by "g" or "r" in a register constraint. 1860 Also, registers outside this class are allocated only when 1861 instructions express preferences for them. 1862 1863 The classes must be numbered in nondecreasing order; that is, 1864 a larger-numbered class must never be contained completely 1865 in a smaller-numbered class. 1866 1867 For any two classes, it is very desirable that there be another 1868 class that represents their union. */ 1869 1870 enum reg_class 1871 { 1872 NO_REGS, /* no registers in set */ 1873 M16_REGS, /* mips16 directly accessible registers */ 1874 T_REG, /* mips16 T register ($24) */ 1875 M16_T_REGS, /* mips16 registers plus T register */ 1876 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */ 1877 V1_REG, /* Register $v1 ($3) used for TLS access. */ 1878 LEA_REGS, /* Every GPR except $25 */ 1879 GR_REGS, /* integer registers */ 1880 FP_REGS, /* floating point registers */ 1881 MD0_REG, /* first multiply/divide register */ 1882 MD1_REG, /* second multiply/divide register */ 1883 MD_REGS, /* multiply/divide registers (hi/lo) */ 1884 COP0_REGS, /* generic coprocessor classes */ 1885 COP2_REGS, 1886 COP3_REGS, 1887 ST_REGS, /* status registers (fp status) */ 1888 DSP_ACC_REGS, /* DSP accumulator registers */ 1889 ACC_REGS, /* Hi/Lo and DSP accumulator registers */ 1890 FRAME_REGS, /* $arg and $frame */ 1891 GR_AND_MD0_REGS, /* union classes */ 1892 GR_AND_MD1_REGS, 1893 GR_AND_MD_REGS, 1894 GR_AND_ACC_REGS, 1895 ALL_REGS, /* all registers */ 1896 LIM_REG_CLASSES /* max value + 1 */ 1897 }; 1898 1899 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1900 1901 #define GENERAL_REGS GR_REGS 1902 1903 /* An initializer containing the names of the register classes as C 1904 string constants. These names are used in writing some of the 1905 debugging dumps. */ 1906 1907 #define REG_CLASS_NAMES \ 1908 { \ 1909 "NO_REGS", \ 1910 "M16_REGS", \ 1911 "T_REG", \ 1912 "M16_T_REGS", \ 1913 "PIC_FN_ADDR_REG", \ 1914 "V1_REG", \ 1915 "LEA_REGS", \ 1916 "GR_REGS", \ 1917 "FP_REGS", \ 1918 "MD0_REG", \ 1919 "MD1_REG", \ 1920 "MD_REGS", \ 1921 /* coprocessor registers */ \ 1922 "COP0_REGS", \ 1923 "COP2_REGS", \ 1924 "COP3_REGS", \ 1925 "ST_REGS", \ 1926 "DSP_ACC_REGS", \ 1927 "ACC_REGS", \ 1928 "FRAME_REGS", \ 1929 "GR_AND_MD0_REGS", \ 1930 "GR_AND_MD1_REGS", \ 1931 "GR_AND_MD_REGS", \ 1932 "GR_AND_ACC_REGS", \ 1933 "ALL_REGS" \ 1934 } 1935 1936 /* An initializer containing the contents of the register classes, 1937 as integers which are bit masks. The Nth integer specifies the 1938 contents of class N. The way the integer MASK is interpreted is 1939 that register R is in the class if `MASK & (1 << R)' is 1. 1940 1941 When the machine has more than 32 registers, an integer does not 1942 suffice. Then the integers are replaced by sub-initializers, 1943 braced groupings containing several integers. Each 1944 sub-initializer must be suitable as an initializer for the type 1945 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */ 1946 1947 #define REG_CLASS_CONTENTS \ 1948 { \ 1949 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 1950 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \ 1951 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \ 1952 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \ 1953 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \ 1954 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \ 1955 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \ 1956 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \ 1957 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \ 1958 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \ 1959 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \ 1960 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \ 1961 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \ 1962 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \ 1963 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \ 1964 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \ 1965 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \ 1966 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \ 1967 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \ 1968 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \ 1969 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \ 1970 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \ 1971 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \ 1972 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \ 1973 } 1974 1975 1976 /* A C expression whose value is a register class containing hard 1977 register REGNO. In general there is more that one such class; 1978 choose a class which is "minimal", meaning that no smaller class 1979 also contains the register. */ 1980 1981 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ] 1982 1983 /* A macro whose definition is the name of the class to which a 1984 valid base register must belong. A base register is one used in 1985 an address which is the register value plus a displacement. */ 1986 1987 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS) 1988 1989 /* A macro whose definition is the name of the class to which a 1990 valid index register must belong. An index register is one used 1991 in an address where its value is either multiplied by a scale 1992 factor or added to another register (as well as added to a 1993 displacement). */ 1994 1995 #define INDEX_REG_CLASS NO_REGS 1996 1997 /* We generally want to put call-clobbered registers ahead of 1998 call-saved ones. (IRA expects this.) */ 1999 2000 #define REG_ALLOC_ORDER \ 2001 { /* Accumulator registers. When GPRs and accumulators have equal \ 2002 cost, we generally prefer to use accumulators. For example, \ 2003 a division of multiplication result is better allocated to LO, \ 2004 so that we put the MFLO at the point of use instead of at the \ 2005 point of definition. It's also needed if we're to take advantage \ 2006 of the extra accumulators available with -mdspr2. In some cases, \ 2007 it can also help to reduce register pressure. */ \ 2008 64, 65,176,177,178,179,180,181, \ 2009 /* Call-clobbered GPRs. */ \ 2010 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ 2011 24, 25, 31, \ 2012 /* The global pointer. This is call-clobbered for o32 and o64 \ 2013 abicalls, call-saved for n32 and n64 abicalls, and a program \ 2014 invariant otherwise. Putting it between the call-clobbered \ 2015 and call-saved registers should cope with all eventualities. */ \ 2016 28, \ 2017 /* Call-saved GPRs. */ \ 2018 16, 17, 18, 19, 20, 21, 22, 23, 30, \ 2019 /* GPRs that can never be exposed to the register allocator. */ \ 2020 0, 26, 27, 29, \ 2021 /* Call-clobbered FPRs. */ \ 2022 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 2023 48, 49, 50, 51, \ 2024 /* FPRs that are usually call-saved. The odd ones are actually \ 2025 call-clobbered for n32, but listing them ahead of the even \ 2026 registers might encourage the register allocator to fragment \ 2027 the available FPR pairs. We need paired FPRs to store long \ 2028 doubles, so it isn't clear that using a different order \ 2029 for n32 would be a win. */ \ 2030 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \ 2031 /* None of the remaining classes have defined call-saved \ 2032 registers. */ \ 2033 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ 2034 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \ 2035 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \ 2036 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \ 2037 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \ 2038 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \ 2039 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \ 2040 182,183,184,185,186,187 \ 2041 } 2042 2043 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order 2044 to be rearranged based on a particular function. On the mips16, we 2045 want to allocate $24 (T_REG) before other registers for 2046 instructions for which it is possible. */ 2047 2048 #define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc () 2049 2050 /* True if VALUE is an unsigned 6-bit number. */ 2051 2052 #define UIMM6_OPERAND(VALUE) \ 2053 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0) 2054 2055 /* True if VALUE is a signed 10-bit number. */ 2056 2057 #define IMM10_OPERAND(VALUE) \ 2058 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400) 2059 2060 /* True if VALUE is a signed 16-bit number. */ 2061 2062 #define SMALL_OPERAND(VALUE) \ 2063 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000) 2064 2065 /* True if VALUE is an unsigned 16-bit number. */ 2066 2067 #define SMALL_OPERAND_UNSIGNED(VALUE) \ 2068 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0) 2069 2070 /* True if VALUE can be loaded into a register using LUI. */ 2071 2072 #define LUI_OPERAND(VALUE) \ 2073 (((VALUE) | 0x7fff0000) == 0x7fff0000 \ 2074 || ((VALUE) | 0x7fff0000) + 0x10000 == 0) 2075 2076 /* Return a value X with the low 16 bits clear, and such that 2077 VALUE - X is a signed 16-bit value. */ 2078 2079 #define CONST_HIGH_PART(VALUE) \ 2080 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff) 2081 2082 #define CONST_LOW_PART(VALUE) \ 2083 ((VALUE) - CONST_HIGH_PART (VALUE)) 2084 2085 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X)) 2086 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X)) 2087 #define LUI_INT(X) LUI_OPERAND (INTVAL (X)) 2088 #define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047)) 2089 2090 /* The HI and LO registers can only be reloaded via the general 2091 registers. Condition code registers can only be loaded to the 2092 general registers, and from the floating point registers. */ 2093 2094 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 2095 mips_secondary_reload_class (CLASS, MODE, X, true) 2096 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 2097 mips_secondary_reload_class (CLASS, MODE, X, false) 2098 2099 /* Return the maximum number of consecutive registers 2100 needed to represent mode MODE in a register of class CLASS. */ 2101 2102 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE) 2103 2104 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 2105 mips_cannot_change_mode_class (FROM, TO, CLASS) 2106 2107 /* Stack layout; function entry, exit and calling. */ 2108 2109 #define STACK_GROWS_DOWNWARD 2110 2111 #define FRAME_GROWS_DOWNWARD flag_stack_protect 2112 2113 /* Size of the area allocated in the frame to save the GP. */ 2114 2115 #define MIPS_GP_SAVE_AREA_SIZE \ 2116 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0) 2117 2118 /* The offset of the first local variable from the frame pointer. See 2119 mips_compute_frame_info for details about the frame layout. */ 2120 2121 #define STARTING_FRAME_OFFSET \ 2122 (FRAME_GROWS_DOWNWARD \ 2123 ? 0 \ 2124 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE) 2125 2126 #define RETURN_ADDR_RTX mips_return_addr 2127 2128 /* Mask off the MIPS16 ISA bit in unwind addresses. 2129 2130 The reason for this is a little subtle. When unwinding a call, 2131 we are given the call's return address, which on most targets 2132 is the address of the following instruction. However, what we 2133 actually want to find is the EH region for the call itself. 2134 The target-independent unwind code therefore searches for "RA - 1". 2135 2136 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address. 2137 RA - 1 is therefore the real (even-valued) start of the return 2138 instruction. EH region labels are usually odd-valued MIPS16 symbols 2139 too, so a search for an even address within a MIPS16 region would 2140 usually work. 2141 2142 However, there is an exception. If the end of an EH region is also 2143 the end of a function, the end label is allowed to be even. This is 2144 necessary because a following non-MIPS16 function may also need EH 2145 information for its first instruction. 2146 2147 Thus a MIPS16 region may be terminated by an ISA-encoded or a 2148 non-ISA-encoded address. This probably isn't ideal, but it is 2149 the traditional (legacy) behavior. It is therefore only safe 2150 to search MIPS EH regions for an _odd-valued_ address. 2151 2152 Masking off the ISA bit means that the target-independent code 2153 will search for "(RA & -2) - 1", which is guaranteed to be odd. */ 2154 #define MASK_RETURN_ADDR GEN_INT (-2) 2155 2156 2157 /* Similarly, don't use the least-significant bit to tell pointers to 2158 code from vtable index. */ 2159 2160 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 2161 2162 /* The eliminations to $17 are only used for mips16 code. See the 2163 definition of HARD_FRAME_POINTER_REGNUM. */ 2164 2165 #define ELIMINABLE_REGS \ 2166 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 2167 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \ 2168 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \ 2169 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 2170 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \ 2171 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}} 2172 2173 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 2174 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO)) 2175 2176 /* Allocate stack space for arguments at the beginning of each function. */ 2177 #define ACCUMULATE_OUTGOING_ARGS 1 2178 2179 /* The argument pointer always points to the first argument. */ 2180 #define FIRST_PARM_OFFSET(FNDECL) 0 2181 2182 /* o32 and o64 reserve stack space for all argument registers. */ 2183 #define REG_PARM_STACK_SPACE(FNDECL) \ 2184 (TARGET_OLDABI \ 2185 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \ 2186 : 0) 2187 2188 /* Define this if it is the responsibility of the caller to 2189 allocate the area reserved for arguments passed in registers. 2190 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect 2191 of this macro is to determine whether the space is included in 2192 `crtl->outgoing_args_size'. */ 2193 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 2194 2195 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64) 2196 2197 /* Symbolic macros for the registers used to return integer and floating 2198 point values. */ 2199 2200 #define GP_RETURN (GP_REG_FIRST + 2) 2201 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0)) 2202 2203 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8) 2204 2205 /* Symbolic macros for the first/last argument registers. */ 2206 2207 #define GP_ARG_FIRST (GP_REG_FIRST + 4) 2208 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) 2209 #define FP_ARG_FIRST (FP_REG_FIRST + 12) 2210 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) 2211 2212 /* 1 if N is a possible register number for function argument passing. 2213 We have no FP argument registers when soft-float. When FP registers 2214 are 32 bits, we can't directly reference the odd numbered ones. */ 2215 2216 #define FUNCTION_ARG_REGNO_P(N) \ 2217 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \ 2218 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \ 2219 && !fixed_regs[N]) 2220 2221 /* This structure has to cope with two different argument allocation 2222 schemes. Most MIPS ABIs view the arguments as a structure, of which 2223 the first N words go in registers and the rest go on the stack. If I 2224 < N, the Ith word might go in Ith integer argument register or in a 2225 floating-point register. For these ABIs, we only need to remember 2226 the offset of the current argument into the structure. 2227 2228 The EABI instead allocates the integer and floating-point arguments 2229 separately. The first N words of FP arguments go in FP registers, 2230 the rest go on the stack. Likewise, the first N words of the other 2231 arguments go in integer registers, and the rest go on the stack. We 2232 need to maintain three counts: the number of integer registers used, 2233 the number of floating-point registers used, and the number of words 2234 passed on the stack. 2235 2236 We could keep separate information for the two ABIs (a word count for 2237 the standard ABIs, and three separate counts for the EABI). But it 2238 seems simpler to view the standard ABIs as forms of EABI that do not 2239 allocate floating-point registers. 2240 2241 So for the standard ABIs, the first N words are allocated to integer 2242 registers, and mips_function_arg decides on an argument-by-argument 2243 basis whether that argument should really go in an integer register, 2244 or in a floating-point one. */ 2245 2246 typedef struct mips_args { 2247 /* Always true for varargs functions. Otherwise true if at least 2248 one argument has been passed in an integer register. */ 2249 int gp_reg_found; 2250 2251 /* The number of arguments seen so far. */ 2252 unsigned int arg_number; 2253 2254 /* The number of integer registers used so far. For all ABIs except 2255 EABI, this is the number of words that have been added to the 2256 argument structure, limited to MAX_ARGS_IN_REGISTERS. */ 2257 unsigned int num_gprs; 2258 2259 /* For EABI, the number of floating-point registers used so far. */ 2260 unsigned int num_fprs; 2261 2262 /* The number of words passed on the stack. */ 2263 unsigned int stack_words; 2264 2265 /* On the mips16, we need to keep track of which floating point 2266 arguments were passed in general registers, but would have been 2267 passed in the FP regs if this were a 32-bit function, so that we 2268 can move them to the FP regs if we wind up calling a 32-bit 2269 function. We record this information in fp_code, encoded in base 2270 four. A zero digit means no floating point argument, a one digit 2271 means an SFmode argument, and a two digit means a DFmode argument, 2272 and a three digit is not used. The low order digit is the first 2273 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by 2274 an SFmode argument. ??? A more sophisticated approach will be 2275 needed if MIPS_ABI != ABI_32. */ 2276 int fp_code; 2277 2278 /* True if the function has a prototype. */ 2279 int prototype; 2280 } CUMULATIVE_ARGS; 2281 2282 /* Initialize a variable CUM of type CUMULATIVE_ARGS 2283 for a call to a function whose data type is FNTYPE. 2284 For a library call, FNTYPE is 0. */ 2285 2286 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 2287 mips_init_cumulative_args (&CUM, FNTYPE) 2288 2289 #define FUNCTION_ARG_PADDING(MODE, TYPE) \ 2290 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward) 2291 2292 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 2293 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward) 2294 2295 /* True if using EABI and varargs can be passed in floating-point 2296 registers. Under these conditions, we need a more complex form 2297 of va_list, which tracks GPR, FPR and stack arguments separately. */ 2298 #define EABI_FLOAT_VARARGS_P \ 2299 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE) 2300 2301 2302 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO) 2303 2304 /* Treat LOC as a byte offset from the stack pointer and round it up 2305 to the next fully-aligned offset. */ 2306 #define MIPS_STACK_ALIGN(LOC) \ 2307 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8) 2308 2309 2310 /* Output assembler code to FILE to increment profiler label # LABELNO 2311 for profiling a function entry. */ 2312 2313 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE)) 2314 2315 /* The profiler preserves all interesting registers, including $31. */ 2316 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false 2317 2318 /* No mips port has ever used the profiler counter word, so don't emit it 2319 or the label for it. */ 2320 2321 #define NO_PROFILE_COUNTERS 1 2322 2323 /* Define this macro if the code for function profiling should come 2324 before the function prologue. Normally, the profiling code comes 2325 after. */ 2326 2327 /* #define PROFILE_BEFORE_PROLOGUE */ 2328 2329 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 2330 the stack pointer does not matter. The value is tested only in 2331 functions that have frame pointers. 2332 No definition is equivalent to always zero. */ 2333 2334 #define EXIT_IGNORE_STACK 1 2335 2336 2337 /* Trampolines are a block of code followed by two pointers. */ 2338 2339 #define TRAMPOLINE_SIZE \ 2340 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2) 2341 2342 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two 2343 pointers from a single LUI base. */ 2344 2345 #define TRAMPOLINE_ALIGNMENT 64 2346 2347 /* mips_trampoline_init calls this library function to flush 2348 program and data caches. */ 2349 2350 #ifndef CACHE_FLUSH_FUNC 2351 #define CACHE_FLUSH_FUNC "_flush_cache" 2352 #endif 2353 2354 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \ 2355 /* Flush both caches. We need to flush the data cache in case \ 2356 the system has a write-back cache. */ \ 2357 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \ 2358 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \ 2359 GEN_INT (3), TYPE_MODE (integer_type_node)) 2360 2361 2362 /* Addressing modes, and classification of registers for them. */ 2363 2364 #define REGNO_OK_FOR_INDEX_P(REGNO) 0 2365 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 2366 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1) 2367 2368 /* Maximum number of registers that can appear in a valid memory address. */ 2369 2370 #define MAX_REGS_PER_ADDRESS 1 2371 2372 /* Check for constness inline but use mips_legitimate_address_p 2373 to check whether a constant really is an address. */ 2374 2375 #define CONSTANT_ADDRESS_P(X) \ 2376 (CONSTANT_P (X) && memory_address_p (SImode, X)) 2377 2378 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means 2379 'the start of the function that this code is output in'. */ 2380 2381 #define ASM_OUTPUT_LABELREF(FILE,NAME) \ 2382 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \ 2383 asm_fprintf ((FILE), "%U%s", \ 2384 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \ 2385 else \ 2386 asm_fprintf ((FILE), "%U%s", (NAME)) 2387 2388 /* Flag to mark a function decl symbol that requires a long call. */ 2389 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0) 2390 #define SYMBOL_REF_LONG_CALL_P(X) \ 2391 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0) 2392 2393 /* This flag marks functions that cannot be lazily bound. */ 2394 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1) 2395 #define SYMBOL_REF_BIND_NOW_P(RTX) \ 2396 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0) 2397 2398 /* True if we're generating a form of MIPS16 code in which jump tables 2399 are stored in the text section and encoded as 16-bit PC-relative 2400 offsets. This is only possible when general text loads are allowed, 2401 since the table access itself will be an "lh" instruction. If the 2402 PC-relative offsets grow too large, 32-bit offsets are used instead. */ 2403 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS 2404 2405 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES 2406 2407 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode) 2408 2409 /* Only use short offsets if their range will not overflow. */ 2410 #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \ 2411 (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \ 2412 : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \ 2413 : SImode) 2414 2415 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES 2416 2417 /* Define this as 1 if `char' should by default be signed; else as 0. */ 2418 #ifndef DEFAULT_SIGNED_CHAR 2419 #define DEFAULT_SIGNED_CHAR 1 2420 #endif 2421 2422 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets, 2423 we generally don't want to use them for copying arbitrary data. 2424 A single N-word move is usually the same cost as N single-word moves. */ 2425 #define MOVE_MAX UNITS_PER_WORD 2426 #define MAX_MOVE_MAX 8 2427 2428 /* Define this macro as a C expression which is nonzero if 2429 accessing less than a word of memory (i.e. a `char' or a 2430 `short') is no faster than accessing a word of memory, i.e., if 2431 such access require more than one instruction or if there is no 2432 difference in cost between byte and (aligned) word loads. 2433 2434 On RISC machines, it tends to generate better code to define 2435 this as 1, since it avoids making a QI or HI mode register. 2436 2437 But, generating word accesses for -mips16 is generally bad as shifts 2438 (often extended) would be needed for byte accesses. */ 2439 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16) 2440 2441 /* Standard MIPS integer shifts truncate the shift amount to the 2442 width of the shifted operand. However, Loongson vector shifts 2443 do not truncate the shift amount at all. */ 2444 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS) 2445 2446 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 2447 is done just by pretending it is already truncated. */ 2448 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \ 2449 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1) 2450 2451 2452 /* Specify the machine mode that pointers have. 2453 After generation of rtl, the compiler makes no further distinction 2454 between pointers and any other objects of this machine mode. */ 2455 2456 #ifndef Pmode 2457 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode) 2458 #endif 2459 2460 /* Give call MEMs SImode since it is the "most permissive" mode 2461 for both 32-bit and 64-bit targets. */ 2462 2463 #define FUNCTION_MODE SImode 2464 2465 2466 /* We allocate $fcc registers by hand and can't cope with moves of 2467 CCmode registers to and from pseudos (or memory). */ 2468 #define AVOID_CCMODE_COPIES 2469 2470 /* A C expression for the cost of a branch instruction. A value of 2471 1 is the default; other values are interpreted relative to that. */ 2472 2473 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost 2474 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 2475 2476 /* The MIPS port has several functions that return an instruction count. 2477 Multiplying the count by this value gives the number of bytes that 2478 the instructions occupy. */ 2479 #define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4) 2480 2481 /* The length of a NOP in bytes. */ 2482 #define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4) 2483 2484 /* If defined, modifies the length assigned to instruction INSN as a 2485 function of the context in which it is used. LENGTH is an lvalue 2486 that contains the initially computed length of the insn and should 2487 be updated with the correct length of the insn. */ 2488 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \ 2489 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH))) 2490 2491 /* Return the asm template for a non-MIPS16 conditional branch instruction. 2492 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for 2493 its operands. */ 2494 #define MIPS_BRANCH(OPCODE, OPERANDS) \ 2495 "%*" OPCODE "%?\t" OPERANDS "%/" 2496 2497 /* Return an asm string that forces INSN to be treated as an absolute 2498 J or JAL instruction instead of an assembler macro. */ 2499 #define MIPS_ABSOLUTE_JUMP(INSN) \ 2500 (TARGET_ABICALLS_PIC2 \ 2501 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \ 2502 : INSN) 2503 2504 /* Return the asm template for a call. INSN is the instruction's mnemonic 2505 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand 2506 number of the target. SIZE_OPNO is the operand number of the argument size 2507 operand that can optionally hold the call attributes. If SIZE_OPNO is not 2508 -1 and the call is indirect, use the function symbol from the call 2509 attributes to attach a R_MIPS_JALR relocation to the call. 2510 2511 When generating GOT code without explicit relocation operators, 2512 all calls should use assembly macros. Otherwise, all indirect 2513 calls should use "jr" or "jalr"; we will arrange to restore $gp 2514 afterwards if necessary. Finally, we can only generate direct 2515 calls for -mabicalls by temporarily switching to non-PIC mode. 2516 2517 For microMIPS jal(r), we try to generate jal(r)s when a 16-bit 2518 instruction is in the delay slot of jal(r). */ 2519 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \ 2520 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \ 2521 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \ 2522 : REG_P (OPERANDS[TARGET_OPNO]) \ 2523 ? (mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO) \ 2524 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \ 2525 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \ 2526 : TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \ 2527 ? "%*" INSN "r%!\t%" #TARGET_OPNO "%/" \ 2528 : "%*" INSN "r\t%" #TARGET_OPNO "%/") \ 2529 : TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \ 2530 ? MIPS_ABSOLUTE_JUMP ("%*" INSN "%!\t%" #TARGET_OPNO "%/") \ 2531 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/")) \ 2532 2533 /* Similar to MIPS_CALL, but this is for MICROMIPS "j" to generate 2534 "jrc" when nop is in the delay slot of "jr". */ 2535 2536 #define MICROMIPS_J(INSN, OPERANDS, OPNO) \ 2537 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \ 2538 ? "%*j\t%" #OPNO "%/" \ 2539 : REG_P (OPERANDS[OPNO]) \ 2540 ? "%*jr%:\t%" #OPNO \ 2541 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #OPNO "%/")) 2542 2543 2544 /* Control the assembler format that we output. */ 2545 2546 /* Output to assembler file text saying following lines 2547 may contain character constants, extra white space, comments, etc. */ 2548 2549 #ifndef ASM_APP_ON 2550 #define ASM_APP_ON " #APP\n" 2551 #endif 2552 2553 /* Output to assembler file text saying following lines 2554 no longer contain unusual constructs. */ 2555 2556 #ifndef ASM_APP_OFF 2557 #define ASM_APP_OFF " #NO_APP\n" 2558 #endif 2559 2560 #define REGISTER_NAMES \ 2561 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \ 2562 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \ 2563 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \ 2564 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \ 2565 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \ 2566 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \ 2567 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \ 2568 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \ 2569 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \ 2570 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \ 2571 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \ 2572 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \ 2573 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \ 2574 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \ 2575 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \ 2576 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \ 2577 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \ 2578 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \ 2579 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \ 2580 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \ 2581 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \ 2582 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \ 2583 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \ 2584 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" } 2585 2586 /* List the "software" names for each register. Also list the numerical 2587 names for $fp and $sp. */ 2588 2589 #define ADDITIONAL_REGISTER_NAMES \ 2590 { \ 2591 { "$29", 29 + GP_REG_FIRST }, \ 2592 { "$30", 30 + GP_REG_FIRST }, \ 2593 { "at", 1 + GP_REG_FIRST }, \ 2594 { "v0", 2 + GP_REG_FIRST }, \ 2595 { "v1", 3 + GP_REG_FIRST }, \ 2596 { "a0", 4 + GP_REG_FIRST }, \ 2597 { "a1", 5 + GP_REG_FIRST }, \ 2598 { "a2", 6 + GP_REG_FIRST }, \ 2599 { "a3", 7 + GP_REG_FIRST }, \ 2600 { "t0", 8 + GP_REG_FIRST }, \ 2601 { "t1", 9 + GP_REG_FIRST }, \ 2602 { "t2", 10 + GP_REG_FIRST }, \ 2603 { "t3", 11 + GP_REG_FIRST }, \ 2604 { "t4", 12 + GP_REG_FIRST }, \ 2605 { "t5", 13 + GP_REG_FIRST }, \ 2606 { "t6", 14 + GP_REG_FIRST }, \ 2607 { "t7", 15 + GP_REG_FIRST }, \ 2608 { "s0", 16 + GP_REG_FIRST }, \ 2609 { "s1", 17 + GP_REG_FIRST }, \ 2610 { "s2", 18 + GP_REG_FIRST }, \ 2611 { "s3", 19 + GP_REG_FIRST }, \ 2612 { "s4", 20 + GP_REG_FIRST }, \ 2613 { "s5", 21 + GP_REG_FIRST }, \ 2614 { "s6", 22 + GP_REG_FIRST }, \ 2615 { "s7", 23 + GP_REG_FIRST }, \ 2616 { "t8", 24 + GP_REG_FIRST }, \ 2617 { "t9", 25 + GP_REG_FIRST }, \ 2618 { "k0", 26 + GP_REG_FIRST }, \ 2619 { "k1", 27 + GP_REG_FIRST }, \ 2620 { "gp", 28 + GP_REG_FIRST }, \ 2621 { "sp", 29 + GP_REG_FIRST }, \ 2622 { "fp", 30 + GP_REG_FIRST }, \ 2623 { "ra", 31 + GP_REG_FIRST } \ 2624 } 2625 2626 #define DBR_OUTPUT_SEQEND(STREAM) \ 2627 do \ 2628 { \ 2629 /* Undo the effect of '%*'. */ \ 2630 mips_pop_asm_switch (&mips_nomacro); \ 2631 mips_pop_asm_switch (&mips_noreorder); \ 2632 /* Emit a blank line after the delay slot for emphasis. */ \ 2633 fputs ("\n", STREAM); \ 2634 } \ 2635 while (0) 2636 2637 /* The MIPS implementation uses some labels for its own purpose. The 2638 following lists what labels are created, and are all formed by the 2639 pattern $L[a-z].*. The machine independent portion of GCC creates 2640 labels matching: $L[A-Z][0-9]+ and $L[0-9]+. 2641 2642 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt. 2643 $Lb[0-9]+ Begin blocks for MIPS debug support 2644 $Lc[0-9]+ Label for use in s<xx> operation. 2645 $Le[0-9]+ End blocks for MIPS debug support */ 2646 2647 #undef ASM_DECLARE_OBJECT_NAME 2648 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \ 2649 mips_declare_object (STREAM, NAME, "", ":\n") 2650 2651 /* Globalizing directive for a label. */ 2652 #define GLOBAL_ASM_OP "\t.globl\t" 2653 2654 /* This says how to define a global common symbol. */ 2655 2656 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common 2657 2658 /* This says how to define a local common symbol (i.e., not visible to 2659 linker). */ 2660 2661 #ifndef ASM_OUTPUT_ALIGNED_LOCAL 2662 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \ 2663 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false) 2664 #endif 2665 2666 /* This says how to output an external. It would be possible not to 2667 output anything and let undefined symbol become external. However 2668 the assembler uses length information on externals to allocate in 2669 data/sdata bss/sbss, thereby saving exec time. */ 2670 2671 #undef ASM_OUTPUT_EXTERNAL 2672 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \ 2673 mips_output_external(STREAM,DECL,NAME) 2674 2675 /* This is how to declare a function name. The actual work of 2676 emitting the label is moved to function_prologue, so that we can 2677 get the line number correctly emitted before the .ent directive, 2678 and after any .file directives. Define as empty so that the function 2679 is not declared before the .ent directive elsewhere. */ 2680 2681 #undef ASM_DECLARE_FUNCTION_NAME 2682 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) 2683 2684 /* This is how to store into the string LABEL 2685 the symbol_ref name of an internal numbered label where 2686 PREFIX is the class of label and NUM is the number within the class. 2687 This is suitable for output with `assemble_name'. */ 2688 2689 #undef ASM_GENERATE_INTERNAL_LABEL 2690 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 2691 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM)) 2692 2693 /* Print debug labels as "foo = ." rather than "foo:" because they should 2694 represent a byte pointer rather than an ISA-encoded address. This is 2695 particularly important for code like: 2696 2697 $LFBxxx = . 2698 .cfi_startproc 2699 ... 2700 .section .gcc_except_table,... 2701 ... 2702 .uleb128 foo-$LFBxxx 2703 2704 The .uleb128 requies $LFBxxx to match the FDE start address, which is 2705 likewise a byte pointer rather than an ISA-encoded address. 2706 2707 At the time of writing, this hook is not used for the function end 2708 label: 2709 2710 $LFExxx: 2711 .end foo 2712 2713 But this doesn't matter, because GAS doesn't treat a pre-.end label 2714 as a MIPS16 one anyway. */ 2715 2716 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \ 2717 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM) 2718 2719 /* This is how to output an element of a case-vector that is absolute. */ 2720 2721 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ 2722 fprintf (STREAM, "\t%s\t%sL%d\n", \ 2723 ptr_mode == DImode ? ".dword" : ".word", \ 2724 LOCAL_LABEL_PREFIX, \ 2725 VALUE) 2726 2727 /* This is how to output an element of a case-vector. We can make the 2728 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word 2729 is supported. */ 2730 2731 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ 2732 do { \ 2733 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \ 2734 { \ 2735 if (GET_MODE (BODY) == HImode) \ 2736 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \ 2737 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \ 2738 else \ 2739 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \ 2740 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \ 2741 } \ 2742 else if (TARGET_GPWORD) \ 2743 fprintf (STREAM, "\t%s\t%sL%d\n", \ 2744 ptr_mode == DImode ? ".gpdword" : ".gpword", \ 2745 LOCAL_LABEL_PREFIX, VALUE); \ 2746 else if (TARGET_RTP_PIC) \ 2747 { \ 2748 /* Make the entry relative to the start of the function. */ \ 2749 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \ 2750 fprintf (STREAM, "\t%s\t%sL%d-", \ 2751 Pmode == DImode ? ".dword" : ".word", \ 2752 LOCAL_LABEL_PREFIX, VALUE); \ 2753 assemble_name (STREAM, XSTR (fnsym, 0)); \ 2754 fprintf (STREAM, "\n"); \ 2755 } \ 2756 else \ 2757 fprintf (STREAM, "\t%s\t%sL%d\n", \ 2758 ptr_mode == DImode ? ".dword" : ".word", \ 2759 LOCAL_LABEL_PREFIX, VALUE); \ 2760 } while (0) 2761 2762 /* This is how to output an assembler line 2763 that says to advance the location counter 2764 to a multiple of 2**LOG bytes. */ 2765 2766 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \ 2767 fprintf (STREAM, "\t.align\t%d\n", (LOG)) 2768 2769 /* This is how to output an assembler line to advance the location 2770 counter by SIZE bytes. */ 2771 2772 #undef ASM_OUTPUT_SKIP 2773 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \ 2774 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) 2775 2776 /* This is how to output a string. */ 2777 #undef ASM_OUTPUT_ASCII 2778 #define ASM_OUTPUT_ASCII mips_output_ascii 2779 2780 2781 /* Default to -G 8 */ 2782 #ifndef MIPS_DEFAULT_GVALUE 2783 #define MIPS_DEFAULT_GVALUE 8 2784 #endif 2785 2786 /* Define the strings to put out for each section in the object file. */ 2787 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */ 2788 #define DATA_SECTION_ASM_OP "\t.data" /* large data */ 2789 2790 #undef READONLY_DATA_SECTION_ASM_OP 2791 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */ 2792 2793 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \ 2794 do \ 2795 { \ 2796 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \ 2797 TARGET_64BIT ? "daddiu" : "addiu", \ 2798 reg_names[STACK_POINTER_REGNUM], \ 2799 reg_names[STACK_POINTER_REGNUM], \ 2800 TARGET_64BIT ? "sd" : "sw", \ 2801 reg_names[REGNO], \ 2802 reg_names[STACK_POINTER_REGNUM]); \ 2803 } \ 2804 while (0) 2805 2806 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \ 2807 do \ 2808 { \ 2809 mips_push_asm_switch (&mips_noreorder); \ 2810 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \ 2811 TARGET_64BIT ? "ld" : "lw", \ 2812 reg_names[REGNO], \ 2813 reg_names[STACK_POINTER_REGNUM], \ 2814 TARGET_64BIT ? "daddu" : "addu", \ 2815 reg_names[STACK_POINTER_REGNUM], \ 2816 reg_names[STACK_POINTER_REGNUM]); \ 2817 mips_pop_asm_switch (&mips_noreorder); \ 2818 } \ 2819 while (0) 2820 2821 /* How to start an assembler comment. 2822 The leading space is important (the mips native assembler requires it). */ 2823 #ifndef ASM_COMMENT_START 2824 #define ASM_COMMENT_START " #" 2825 #endif 2826 2827 #undef SIZE_TYPE 2828 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int") 2829 2830 #undef PTRDIFF_TYPE 2831 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int") 2832 2833 /* The maximum number of bytes that can be copied by one iteration of 2834 a movmemsi loop; see mips_block_move_loop. */ 2835 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \ 2836 (UNITS_PER_WORD * 4) 2837 2838 /* The maximum number of bytes that can be copied by a straight-line 2839 implementation of movmemsi; see mips_block_move_straight. We want 2840 to make sure that any loop-based implementation will iterate at 2841 least twice. */ 2842 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \ 2843 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2) 2844 2845 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These 2846 values were determined experimentally by benchmarking with CSiBE. 2847 In theory, the call overhead is higher for TARGET_ABICALLS (especially 2848 for o32 where we have to restore $gp afterwards as well as make an 2849 indirect call), but in practice, bumping this up higher for 2850 TARGET_ABICALLS doesn't make much difference to code size. */ 2851 2852 #define MIPS_CALL_RATIO 8 2853 2854 /* Any loop-based implementation of movmemsi will have at least 2855 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory 2856 moves, so allow individual copies of fewer elements. 2857 2858 When movmemsi is not available, use a value approximating 2859 the length of a memcpy call sequence, so that move_by_pieces 2860 will generate inline code if it is shorter than a function call. 2861 Since move_by_pieces_ninsns counts memory-to-memory moves, but 2862 we'll have to generate a load/store pair for each, halve the 2863 value of MIPS_CALL_RATIO to take that into account. */ 2864 2865 #define MOVE_RATIO(speed) \ 2866 (HAVE_movmemsi \ 2867 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \ 2868 : MIPS_CALL_RATIO / 2) 2869 2870 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \ 2871 mips_move_by_pieces_p (SIZE, ALIGN) 2872 2873 /* For CLEAR_RATIO, when optimizing for size, give a better estimate 2874 of the length of a memset call, but use the default otherwise. */ 2875 2876 #define CLEAR_RATIO(speed)\ 2877 ((speed) ? 15 : MIPS_CALL_RATIO) 2878 2879 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when 2880 optimizing for size adjust the ratio to account for the overhead of 2881 loading the constant and replicating it across the word. */ 2882 2883 #define SET_RATIO(speed) \ 2884 ((speed) ? 15 : MIPS_CALL_RATIO - 2) 2885 2886 #define STORE_BY_PIECES_P(SIZE, ALIGN) \ 2887 mips_store_by_pieces_p (SIZE, ALIGN) 2888 2889 /* Since the bits of the _init and _fini function is spread across 2890 many object files, each potentially with its own GP, we must assume 2891 we need to load our GP. We don't preserve $gp or $ra, since each 2892 init/fini chunk is supposed to initialize $gp, and crti/crtn 2893 already take care of preserving $ra and, when appropriate, $gp. */ 2894 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32) 2895 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2896 asm (SECTION_OP "\n\ 2897 .set push\n\ 2898 .set nomips16\n\ 2899 .set noreorder\n\ 2900 bal 1f\n\ 2901 nop\n\ 2902 1: .cpload $31\n\ 2903 .set reorder\n\ 2904 jal " USER_LABEL_PREFIX #FUNC "\n\ 2905 .set pop\n\ 2906 " TEXT_SECTION_ASM_OP); 2907 #elif ((defined _ABIN32 && _MIPS_SIM == _ABIN32) \ 2908 || (defined _ABI64 && _MIPS_SIM == _ABI64)) 2909 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2910 asm (SECTION_OP "\n\ 2911 .set push\n\ 2912 .set nomips16\n\ 2913 .set noreorder\n\ 2914 bal 1f\n\ 2915 nop\n\ 2916 1: .set reorder\n\ 2917 .cpsetup $31, $2, 1b\n\ 2918 jal " USER_LABEL_PREFIX #FUNC "\n\ 2919 .set pop\n\ 2920 " TEXT_SECTION_ASM_OP); 2921 #endif 2922 2923 #ifndef HAVE_AS_TLS 2924 #define HAVE_AS_TLS 0 2925 #endif 2926 2927 #ifndef HAVE_AS_NAN 2928 #define HAVE_AS_NAN 0 2929 #endif 2930 2931 #ifndef USED_FOR_TARGET 2932 /* Information about ".set noFOO; ...; .set FOO" blocks. */ 2933 struct mips_asm_switch { 2934 /* The FOO in the description above. */ 2935 const char *name; 2936 2937 /* The current block nesting level, or 0 if we aren't in a block. */ 2938 int nesting_level; 2939 }; 2940 2941 extern const enum reg_class mips_regno_to_class[]; 2942 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER]; 2943 extern const char *current_function_file; /* filename current function is in */ 2944 extern int num_source_filenames; /* current .file # */ 2945 extern struct mips_asm_switch mips_noreorder; 2946 extern struct mips_asm_switch mips_nomacro; 2947 extern struct mips_asm_switch mips_noat; 2948 extern int mips_dbx_regno[]; 2949 extern int mips_dwarf_regno[]; 2950 extern bool mips_split_p[]; 2951 extern bool mips_split_hi_p[]; 2952 extern bool mips_use_pcrel_pool_p[]; 2953 extern const char *mips_lo_relocs[]; 2954 extern const char *mips_hi_relocs[]; 2955 extern enum processor mips_arch; /* which cpu to codegen for */ 2956 extern enum processor mips_tune; /* which cpu to schedule for */ 2957 extern int mips_isa; /* architectural level */ 2958 extern const struct mips_cpu_info *mips_arch_info; 2959 extern const struct mips_cpu_info *mips_tune_info; 2960 extern unsigned int mips_base_compression_flags; 2961 extern GTY(()) struct target_globals *mips16_globals; 2962 #endif 2963 2964 /* Enable querying of DFA units. */ 2965 #define CPU_UNITS_QUERY 1 2966 2967 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 2968 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS) 2969 2970 /* As on most targets, we want the .eh_frame section to be read-only where 2971 possible. And as on most targets, this means two things: 2972 2973 (a) Non-locally-binding pointers must have an indirect encoding, 2974 so that the addresses in the .eh_frame section itself become 2975 locally-binding. 2976 2977 (b) A shared library's .eh_frame section must encode locally-binding 2978 pointers in a relative (relocation-free) form. 2979 2980 However, MIPS has traditionally not allowed directives like: 2981 2982 .long x-. 2983 2984 in cases where "x" is in a different section, or is not defined in the 2985 same assembly file. We are therefore unable to emit the PC-relative 2986 form required by (b) at assembly time. 2987 2988 Fortunately, the linker is able to convert absolute addresses into 2989 PC-relative addresses on our behalf. Unfortunately, only certain 2990 versions of the linker know how to do this for indirect pointers, 2991 and for personality data. We must fall back on using writable 2992 .eh_frame sections for shared libraries if the linker does not 2993 support this feature. */ 2994 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 2995 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr) 2996 2997 /* For switching between MIPS16 and non-MIPS16 modes. */ 2998 #define SWITCHABLE_TARGET 1 2999 3000 /* Several named MIPS patterns depend on Pmode. These patterns have the 3001 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode. 3002 Add the appropriate suffix to generator function NAME and invoke it 3003 with arguments ARGS. */ 3004 #define PMODE_INSN(NAME, ARGS) \ 3005 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS) 3006