1;; Pipeline description for Freescale PowerPC e6500 core.
2;;   Copyright (C) 2012-2014 Free Software Foundation, Inc.
3;;   Contributed by Edmar Wienskoski (edmar@freescale.com)
4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published
9;; by the Free Software Foundation; either version 3, or (at your
10;; option) any later version.
11;;
12;; GCC is distributed in the hope that it will be useful, but WITHOUT
13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15;; License for more details.
16;;
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3.  If not see
19;; <http://www.gnu.org/licenses/>.
20;;
21;; e6500 64-bit SFX(2), CFX, LSU, FPU, BU, VSFX, VCFX, VFPU, VPERM
22;; Max issue 3 insns/clock cycle (includes 1 branch)
23
24(define_automaton "e6500_most,e6500_long,e6500_vec")
25(define_cpu_unit "e6500_decode_0,e6500_decode_1" "e6500_most")
26
27;; SFX.
28(define_cpu_unit "e6500_sfx_0,e6500_sfx_1" "e6500_most")
29
30;; CFX.
31(define_cpu_unit "e6500_cfx_stage0,e6500_cfx_stage1" "e6500_most")
32
33;; Non-pipelined division.
34(define_cpu_unit "e6500_cfx_div" "e6500_long")
35
36;; LSU.
37(define_cpu_unit "e6500_lsu" "e6500_most")
38
39;; FPU.
40(define_cpu_unit "e6500_fpu" "e6500_long")
41
42;; BU.
43(define_cpu_unit "e6500_bu" "e6500_most")
44
45;; Altivec unit
46(define_cpu_unit "e6500_vec,e6500_vecperm" "e6500_vec")
47
48;; The following units are used to make the automata deterministic.
49(define_cpu_unit "present_e6500_decode_0" "e6500_most")
50(define_cpu_unit "present_e6500_sfx_0" "e6500_most")
51(presence_set "present_e6500_decode_0" "e6500_decode_0")
52(presence_set "present_e6500_sfx_0" "e6500_sfx_0")
53
54;; Some useful abbreviations.
55(define_reservation "e6500_decode"
56    "e6500_decode_0|e6500_decode_1+present_e6500_decode_0")
57(define_reservation "e6500_sfx"
58   "e6500_sfx_0|e6500_sfx_1+present_e6500_sfx_0")
59
60;; SFX.
61(define_insn_reservation "e6500_sfx" 1
62  (and (eq_attr "type" "integer,insert_word,insert_dword,delayed_compare,\
63	shift,cntlz,exts")
64       (eq_attr "cpu" "ppce6500"))
65  "e6500_decode,e6500_sfx")
66
67(define_insn_reservation "e6500_sfx2" 2
68  (and (eq_attr "type" "cmp,compare,fast_compare,trap")
69       (eq_attr "cpu" "ppce6500"))
70  "e6500_decode,e6500_sfx")
71
72(define_insn_reservation "e6500_delayed" 2
73  (and (eq_attr "type" "var_shift_rotate,var_delayed_compare")
74       (eq_attr "cpu" "ppce6500"))
75  "e6500_decode,e6500_sfx*2")
76
77(define_insn_reservation "e6500_two" 2
78  (and (eq_attr "type" "two")
79       (eq_attr "cpu" "ppce6500"))
80  "e6500_decode,e6500_decode+e6500_sfx,e6500_sfx")
81
82(define_insn_reservation "e6500_three" 3
83  (and (eq_attr "type" "three")
84       (eq_attr "cpu" "ppce6500"))
85  "e6500_decode,(e6500_decode+e6500_sfx)*2,e6500_sfx")
86
87;; SFX - Mfcr.
88(define_insn_reservation "e6500_mfcr" 4
89  (and (eq_attr "type" "mfcr")
90       (eq_attr "cpu" "ppce6500"))
91  "e6500_decode,e6500_sfx_0*4")
92
93;; SFX - Mtcrf.
94(define_insn_reservation "e6500_mtcrf" 1
95  (and (eq_attr "type" "mtcr")
96       (eq_attr "cpu" "ppce6500"))
97  "e6500_decode,e6500_sfx_0")
98
99;; SFX - Mtjmpr.
100(define_insn_reservation "e6500_mtjmpr" 1
101  (and (eq_attr "type" "mtjmpr,mfjmpr")
102       (eq_attr "cpu" "ppce6500"))
103  "e6500_decode,e6500_sfx")
104
105;; CFX - Multiply.
106(define_insn_reservation "e6500_multiply" 4
107  (and (eq_attr "type" "imul")
108       (eq_attr "cpu" "ppce6500"))
109  "e6500_decode,e6500_cfx_stage0,e6500_cfx_stage1")
110
111(define_insn_reservation "e6500_multiply_i" 5
112  (and (eq_attr "type" "imul2,imul3,imul_compare")
113       (eq_attr "cpu" "ppce6500"))
114  "e6500_decode,e6500_cfx_stage0,\
115   e6500_cfx_stage0+e6500_cfx_stage1,e6500_cfx_stage1")
116
117;; CFX - Divide.
118(define_insn_reservation "e6500_divide" 16
119  (and (eq_attr "type" "idiv")
120       (eq_attr "cpu" "ppce6500"))
121  "e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\
122   e6500_cfx_div*15")
123
124(define_insn_reservation "e6500_divide_d" 26
125  (and (eq_attr "type" "ldiv")
126       (eq_attr "cpu" "ppce6500"))
127  "e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\
128   e6500_cfx_div*25")
129
130;; LSU - Loads.
131(define_insn_reservation "e6500_load" 3
132  (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
133			load_l,sync")
134       (eq_attr "cpu" "ppce6500"))
135  "e6500_decode,e6500_lsu")
136
137(define_insn_reservation "e6500_fpload" 4
138  (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
139       (eq_attr "cpu" "ppce6500"))
140  "e6500_decode,e6500_lsu")
141
142(define_insn_reservation "e6500_vecload" 4
143  (and (eq_attr "type" "vecload")
144       (eq_attr "cpu" "ppce6500"))
145  "e6500_decode,e6500_lsu")
146
147;; LSU - Stores.
148(define_insn_reservation "e6500_store" 3
149  (and (eq_attr "type" "store,store_ux,store_u,store_c")
150       (eq_attr "cpu" "ppce6500"))
151  "e6500_decode,e6500_lsu")
152
153(define_insn_reservation "e6500_fpstore" 3
154  (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
155       (eq_attr "cpu" "ppce6500"))
156  "e6500_decode,e6500_lsu")
157
158(define_insn_reservation "e6500_vecstore" 4
159  (and (eq_attr "type" "vecstore")
160       (eq_attr "cpu" "ppce6500"))
161  "e6500_decode,e6500_lsu")
162
163;; FP.
164(define_insn_reservation "e6500_float" 7
165  (and (eq_attr "type" "fpsimple,fp,fpcompare,dmul")
166       (eq_attr "cpu" "ppce6500"))
167  "e6500_decode,e6500_fpu")
168
169(define_insn_reservation "e6500_sdiv" 20
170  (and (eq_attr "type" "sdiv")
171       (eq_attr "cpu" "ppce6500"))
172  "e6500_decode,e6500_fpu*20")
173
174(define_insn_reservation "e6500_ddiv" 35
175  (and (eq_attr "type" "ddiv")
176       (eq_attr "cpu" "ppce6500"))
177  "e6500_decode,e6500_fpu*35")
178
179;; BU.
180(define_insn_reservation "e6500_branch" 1
181  (and (eq_attr "type" "jmpreg,branch,isync")
182       (eq_attr "cpu" "ppce6500"))
183  "e6500_decode,e6500_bu")
184
185;; BU - CR logical.
186(define_insn_reservation "e6500_cr_logical" 1
187  (and (eq_attr "type" "cr_logical,delayed_cr")
188       (eq_attr "cpu" "ppce6500"))
189  "e6500_decode,e6500_bu")
190
191;; VSFX.
192(define_insn_reservation "e6500_vecsimple" 1
193  (and (eq_attr "type" "vecsimple,veccmp")
194       (eq_attr "cpu" "ppce6500"))
195  "e6500_decode,e6500_vec")
196
197;; VCFX.
198(define_insn_reservation "e6500_veccomplex" 4
199  (and (eq_attr "type" "veccomplex")
200       (eq_attr "cpu" "ppce6500"))
201  "e6500_decode,e6500_vec")
202
203;; VFPU.
204(define_insn_reservation "e6500_vecfloat" 6
205  (and (eq_attr "type" "vecfloat")
206       (eq_attr "cpu" "ppce6500"))
207  "e6500_decode,e6500_vec")
208
209;; VPERM.
210(define_insn_reservation "e6500_vecperm" 2
211  (and (eq_attr "type" "vecperm")
212       (eq_attr "cpu" "ppce6500"))
213  "e6500_decode,e6500_vecperm")
214