1 /* ppc.h -- Header file for PowerPC opcode table 2 Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 3 2007, 2008, 2009, 2010, 2012 Free Software Foundation, Inc. 4 Written by Ian Lance Taylor, Cygnus Support 5 6 This file is part of GDB, GAS, and the GNU binutils. 7 8 GDB, GAS, and the GNU binutils are free software; you can redistribute 9 them and/or modify them under the terms of the GNU General Public 10 License as published by the Free Software Foundation; either version 3, 11 or (at your option) any later version. 12 13 GDB, GAS, and the GNU binutils are distributed in the hope that they 14 will be useful, but WITHOUT ANY WARRANTY; without even the implied 15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 16 the GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this file; see the file COPYING3. If not, write to the Free 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 21 MA 02110-1301, USA. */ 22 23 #ifndef PPC_H 24 #define PPC_H 25 26 #include "bfd_stdint.h" 27 28 typedef uint64_t ppc_cpu_t; 29 30 /* The opcode table is an array of struct powerpc_opcode. */ 31 32 struct powerpc_opcode 33 { 34 /* The opcode name. */ 35 const char *name; 36 37 /* The opcode itself. Those bits which will be filled in with 38 operands are zeroes. */ 39 unsigned long opcode; 40 41 /* The opcode mask. This is used by the disassembler. This is a 42 mask containing ones indicating those bits which must match the 43 opcode field, and zeroes indicating those bits which need not 44 match (and are presumably filled in by operands). */ 45 unsigned long mask; 46 47 /* One bit flags for the opcode. These are used to indicate which 48 specific processors support the instructions. The defined values 49 are listed below. */ 50 ppc_cpu_t flags; 51 52 /* One bit flags for the opcode. These are used to indicate which 53 specific processors no longer support the instructions. The defined 54 values are listed below. */ 55 ppc_cpu_t deprecated; 56 57 /* An array of operand codes. Each code is an index into the 58 operand table. They appear in the order which the operands must 59 appear in assembly code, and are terminated by a zero. */ 60 unsigned char operands[8]; 61 }; 62 63 /* The table itself is sorted by major opcode number, and is otherwise 64 in the order in which the disassembler should consider 65 instructions. */ 66 extern const struct powerpc_opcode powerpc_opcodes[]; 67 extern const int powerpc_num_opcodes; 68 extern const struct powerpc_opcode vle_opcodes[]; 69 extern const int vle_num_opcodes; 70 71 /* Values defined for the flags field of a struct powerpc_opcode. */ 72 73 /* Opcode is defined for the PowerPC architecture. */ 74 #define PPC_OPCODE_PPC 1 75 76 /* Opcode is defined for the POWER (RS/6000) architecture. */ 77 #define PPC_OPCODE_POWER 2 78 79 /* Opcode is defined for the POWER2 (Rios 2) architecture. */ 80 #define PPC_OPCODE_POWER2 4 81 82 /* Opcode is supported by the Motorola PowerPC 601 processor. The 601 83 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, 84 but it also supports many additional POWER instructions. */ 85 #define PPC_OPCODE_601 8 86 87 /* Opcode is supported in both the Power and PowerPC architectures 88 (ie, compiler's -mcpu=common or assembler's -mcom). More than just 89 the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER 90 and PPC_OPCODE_POWER2 because many instructions changed mnemonics 91 between POWER and POWERPC. */ 92 #define PPC_OPCODE_COMMON 0x10 93 94 /* Opcode is supported for any Power or PowerPC platform (this is 95 for the assembler's -many option, and it eliminates duplicates). */ 96 #define PPC_OPCODE_ANY 0x20 97 98 /* Opcode is only defined on 64 bit architectures. */ 99 #define PPC_OPCODE_64 0x40 100 101 /* Opcode is supported as part of the 64-bit bridge. */ 102 #define PPC_OPCODE_64_BRIDGE 0x80 103 104 /* Opcode is supported by Altivec Vector Unit */ 105 #define PPC_OPCODE_ALTIVEC 0x100 106 107 /* Opcode is supported by PowerPC 403 processor. */ 108 #define PPC_OPCODE_403 0x200 109 110 /* Opcode is supported by PowerPC BookE processor. */ 111 #define PPC_OPCODE_BOOKE 0x400 112 113 /* Opcode is supported by PowerPC 440 processor. */ 114 #define PPC_OPCODE_440 0x800 115 116 /* Opcode is only supported by Power4 architecture. */ 117 #define PPC_OPCODE_POWER4 0x1000 118 119 /* Opcode is only supported by Power7 architecture. */ 120 #define PPC_OPCODE_POWER7 0x2000 121 122 /* Opcode is only supported by e500x2 Core. */ 123 #define PPC_OPCODE_SPE 0x4000 124 125 /* Opcode is supported by e500x2 Integer select APU. */ 126 #define PPC_OPCODE_ISEL 0x8000 127 128 /* Opcode is an e500 SPE floating point instruction. */ 129 #define PPC_OPCODE_EFS 0x10000 130 131 /* Opcode is supported by branch locking APU. */ 132 #define PPC_OPCODE_BRLOCK 0x20000 133 134 /* Opcode is supported by performance monitor APU. */ 135 #define PPC_OPCODE_PMR 0x40000 136 137 /* Opcode is supported by cache locking APU. */ 138 #define PPC_OPCODE_CACHELCK 0x80000 139 140 /* Opcode is supported by machine check APU. */ 141 #define PPC_OPCODE_RFMCI 0x100000 142 143 /* Opcode is only supported by Power5 architecture. */ 144 #define PPC_OPCODE_POWER5 0x200000 145 146 /* Opcode is supported by PowerPC e300 family. */ 147 #define PPC_OPCODE_E300 0x400000 148 149 /* Opcode is only supported by Power6 architecture. */ 150 #define PPC_OPCODE_POWER6 0x800000 151 152 /* Opcode is only supported by PowerPC Cell family. */ 153 #define PPC_OPCODE_CELL 0x1000000 154 155 /* Opcode is supported by CPUs with paired singles support. */ 156 #define PPC_OPCODE_PPCPS 0x2000000 157 158 /* Opcode is supported by Power E500MC */ 159 #define PPC_OPCODE_E500MC 0x4000000 160 161 /* Opcode is supported by PowerPC 405 processor. */ 162 #define PPC_OPCODE_405 0x8000000 163 164 /* Opcode is supported by Vector-Scalar (VSX) Unit */ 165 #define PPC_OPCODE_VSX 0x10000000 166 167 /* Opcode is supported by A2. */ 168 #define PPC_OPCODE_A2 0x20000000 169 170 /* Opcode is supported by PowerPC 476 processor. */ 171 #define PPC_OPCODE_476 0x40000000 172 173 /* Opcode is supported by AppliedMicro Titan core */ 174 #define PPC_OPCODE_TITAN 0x80000000 175 176 /* Opcode which is supported by the e500 family */ 177 #define PPC_OPCODE_E500 0x100000000ull 178 179 /* Opcode is supported by Extended Altivec Vector Unit */ 180 #define PPC_OPCODE_ALTIVEC2 0x200000000ull 181 182 /* Opcode is supported by Power E6500 */ 183 #define PPC_OPCODE_E6500 0x400000000ull 184 185 /* Opcode is supported by Thread management APU */ 186 #define PPC_OPCODE_TMR 0x800000000ull 187 188 /* Opcode which is supported by the VLE extension. */ 189 #define PPC_OPCODE_VLE 0x1000000000ull 190 191 /* Opcode is only supported by Power8 architecture. */ 192 #define PPC_OPCODE_POWER8 0x2000000000ull 193 194 /* Opcode which is supported by the Hardware Transactional Memory extension. */ 195 /* Currently, this is the same as the POWER8 mask. If another cpu comes out 196 that isn't a superset of POWER8, we can define this to its own mask. */ 197 #define PPC_OPCODE_HTM PPC_OPCODE_POWER8 198 199 /* A macro to extract the major opcode from an instruction. */ 200 #define PPC_OP(i) (((i) >> 26) & 0x3f) 201 202 /* A macro to determine if the instruction is a 2-byte VLE insn. */ 203 #define PPC_OP_SE_VLE(m) ((m) <= 0xffff) 204 205 /* A macro to extract the major opcode from a VLE instruction. */ 206 #define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f) 207 208 /* A macro to convert a VLE opcode to a VLE opcode segment. */ 209 #define VLE_OP_TO_SEG(i) ((i) >> 1) 210 211 /* The operands table is an array of struct powerpc_operand. */ 212 213 struct powerpc_operand 214 { 215 /* A bitmask of bits in the operand. */ 216 unsigned int bitm; 217 218 /* The shift operation to be applied to the operand. No shift 219 is made if this is zero. For positive values, the operand 220 is shifted left by SHIFT. For negative values, the operand 221 is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate 222 that BITM and SHIFT cannot be used to determine where the 223 operand goes in the insn. */ 224 int shift; 225 226 /* Insertion function. This is used by the assembler. To insert an 227 operand value into an instruction, check this field. 228 229 If it is NULL, execute 230 if (o->shift >= 0) 231 i |= (op & o->bitm) << o->shift; 232 else 233 i |= (op & o->bitm) >> -o->shift; 234 (i is the instruction which we are filling in, o is a pointer to 235 this structure, and op is the operand value). 236 237 If this field is not NULL, then simply call it with the 238 instruction and the operand value. It will return the new value 239 of the instruction. If the ERRMSG argument is not NULL, then if 240 the operand value is illegal, *ERRMSG will be set to a warning 241 string (the operand will be inserted in any case). If the 242 operand value is legal, *ERRMSG will be unchanged (most operands 243 can accept any value). */ 244 unsigned long (*insert) 245 (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg); 246 247 /* Extraction function. This is used by the disassembler. To 248 extract this operand type from an instruction, check this field. 249 250 If it is NULL, compute 251 if (o->shift >= 0) 252 op = (i >> o->shift) & o->bitm; 253 else 254 op = (i << -o->shift) & o->bitm; 255 if ((o->flags & PPC_OPERAND_SIGNED) != 0) 256 sign_extend (op); 257 (i is the instruction, o is a pointer to this structure, and op 258 is the result). 259 260 If this field is not NULL, then simply call it with the 261 instruction value. It will return the value of the operand. If 262 the INVALID argument is not NULL, *INVALID will be set to 263 non-zero if this operand type can not actually be extracted from 264 this operand (i.e., the instruction does not match). If the 265 operand is valid, *INVALID will not be changed. */ 266 long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid); 267 268 /* One bit syntax flags. */ 269 unsigned long flags; 270 }; 271 272 /* Elements in the table are retrieved by indexing with values from 273 the operands field of the powerpc_opcodes table. */ 274 275 extern const struct powerpc_operand powerpc_operands[]; 276 extern const unsigned int num_powerpc_operands; 277 278 /* Use with the shift field of a struct powerpc_operand to indicate 279 that BITM and SHIFT cannot be used to determine where the operand 280 goes in the insn. */ 281 #define PPC_OPSHIFT_INV (-1 << 31) 282 283 /* Values defined for the flags field of a struct powerpc_operand. */ 284 285 /* This operand takes signed values. */ 286 #define PPC_OPERAND_SIGNED (0x1) 287 288 /* This operand takes signed values, but also accepts a full positive 289 range of values when running in 32 bit mode. That is, if bits is 290 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, 291 this flag is ignored. */ 292 #define PPC_OPERAND_SIGNOPT (0x2) 293 294 /* This operand does not actually exist in the assembler input. This 295 is used to support extended mnemonics such as mr, for which two 296 operands fields are identical. The assembler should call the 297 insert function with any op value. The disassembler should call 298 the extract function, ignore the return value, and check the value 299 placed in the valid argument. */ 300 #define PPC_OPERAND_FAKE (0x4) 301 302 /* The next operand should be wrapped in parentheses rather than 303 separated from this one by a comma. This is used for the load and 304 store instructions which want their operands to look like 305 reg,displacement(reg) 306 */ 307 #define PPC_OPERAND_PARENS (0x8) 308 309 /* This operand may use the symbolic names for the CR fields, which 310 are 311 lt 0 gt 1 eq 2 so 3 un 3 312 cr0 0 cr1 1 cr2 2 cr3 3 313 cr4 4 cr5 5 cr6 6 cr7 7 314 These may be combined arithmetically, as in cr2*4+gt. These are 315 only supported on the PowerPC, not the POWER. */ 316 #define PPC_OPERAND_CR_BIT (0x10) 317 318 /* This operand names a register. The disassembler uses this to print 319 register names with a leading 'r'. */ 320 #define PPC_OPERAND_GPR (0x20) 321 322 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ 323 #define PPC_OPERAND_GPR_0 (0x40) 324 325 /* This operand names a floating point register. The disassembler 326 prints these with a leading 'f'. */ 327 #define PPC_OPERAND_FPR (0x80) 328 329 /* This operand is a relative branch displacement. The disassembler 330 prints these symbolically if possible. */ 331 #define PPC_OPERAND_RELATIVE (0x100) 332 333 /* This operand is an absolute branch address. The disassembler 334 prints these symbolically if possible. */ 335 #define PPC_OPERAND_ABSOLUTE (0x200) 336 337 /* This operand is optional, and is zero if omitted. This is used for 338 example, in the optional BF field in the comparison instructions. The 339 assembler must count the number of operands remaining on the line, 340 and the number of operands remaining for the opcode, and decide 341 whether this operand is present or not. The disassembler should 342 print this operand out only if it is not zero. */ 343 #define PPC_OPERAND_OPTIONAL (0x400) 344 345 /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand 346 is omitted, then for the next operand use this operand value plus 347 1, ignoring the next operand field for the opcode. This wretched 348 hack is needed because the Power rotate instructions can take 349 either 4 or 5 operands. The disassembler should print this operand 350 out regardless of the PPC_OPERAND_OPTIONAL field. */ 351 #define PPC_OPERAND_NEXT (0x800) 352 353 /* This operand should be regarded as a negative number for the 354 purposes of overflow checking (i.e., the normal most negative 355 number is disallowed and one more than the normal most positive 356 number is allowed). This flag will only be set for a signed 357 operand. */ 358 #define PPC_OPERAND_NEGATIVE (0x1000) 359 360 /* This operand names a vector unit register. The disassembler 361 prints these with a leading 'v'. */ 362 #define PPC_OPERAND_VR (0x2000) 363 364 /* This operand is for the DS field in a DS form instruction. */ 365 #define PPC_OPERAND_DS (0x4000) 366 367 /* This operand is for the DQ field in a DQ form instruction. */ 368 #define PPC_OPERAND_DQ (0x8000) 369 370 /* Valid range of operand is 0..n rather than 0..n-1. */ 371 #define PPC_OPERAND_PLUS1 (0x10000) 372 373 /* Xilinx APU and FSL related operands */ 374 #define PPC_OPERAND_FSL (0x20000) 375 #define PPC_OPERAND_FCR (0x40000) 376 #define PPC_OPERAND_UDI (0x80000) 377 378 /* This operand names a vector-scalar unit register. The disassembler 379 prints these with a leading 'vs'. */ 380 #define PPC_OPERAND_VSR (0x100000) 381 382 /* This is a CR FIELD that does not use symbolic names. */ 383 #define PPC_OPERAND_CR_REG (0x200000) 384 385 /* The POWER and PowerPC assemblers use a few macros. We keep them 386 with the operands table for simplicity. The macro table is an 387 array of struct powerpc_macro. */ 388 389 struct powerpc_macro 390 { 391 /* The macro name. */ 392 const char *name; 393 394 /* The number of operands the macro takes. */ 395 unsigned int operands; 396 397 /* One bit flags for the opcode. These are used to indicate which 398 specific processors support the instructions. The values are the 399 same as those for the struct powerpc_opcode flags field. */ 400 ppc_cpu_t flags; 401 402 /* A format string to turn the macro into a normal instruction. 403 Each %N in the string is replaced with operand number N (zero 404 based). */ 405 const char *format; 406 }; 407 408 extern const struct powerpc_macro powerpc_macros[]; 409 extern const int powerpc_num_macros; 410 411 extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *); 412 413 #endif /* PPC_H */ 414