1		ifndef	__regm163inc
2__regm163inc	equ	1
3                save
4                listing off   ; no listing over this file
5
6;****************************************************************************
7;*                                                                          *
8;*   AS 1.42 - File REGM163.INC                                             *
9;*                                                                          *
10;*   Contains Bit & Register Definitions for ATmega163                      *
11;*                                                                          *
12;****************************************************************************
13
14;----------------------------------------------------------------------------
15; Memory Limits
16
17E2END           equ     511
18RAMSTART	equ	0x60,data
19RAMEND		equ     0x45f,data
20FLASHEND	label   0x3fff
21
22;----------------------------------------------------------------------------
23; Chip Configuration
24
25MCUCR		port	0x35		; MCU General Control Register
26SM0		avrbit	MCUCR,4		; Sleep Mode Select
27SM1		avrbit	MCUCR,5
28SE		avrbit	MCUCR,6		; Sleep Enable
29
30MCUSR		port	0x34		; MCU Status Register
31WDRF		avrbit	MCUSR,3		; Watchdog Reset Occured
32BORF		avrbit	MCUSR,2		; Brown-Out Occured
33EXTRF		avrbit	MCUSR,1		; External Reset Occured
34PORF		avrbit	MCUSR,0		; Power-On Reset Occured
35
36OSCCAL		port	0x31		; Oscillator Calibration
37
38;----------------------------------------------------------------------------
39; EEPROM/Program Memory Access
40
41		include	"eem.inc"
42
43SPMCR		port	0x37		; Store Program Memory Control Register
44ASB		avrbit	SPMCR,6		; Application Section Busy
45ASRE		avrbit	SPMCR,4		; Application Section Rd Enable
46BLBSET		avrbit	SPMCR,3		; Boot Lock Bit Set
47PGWRT		avrbit	SPMCR,2		; Page Write
48PGERS		avrbit	SPMCR,1		; Page Erase
49SPMEN		avrbit	SPMCR,0		; Store Program Memory Enable
50
51;----------------------------------------------------------------------------
52; GPIO
53
54PINA		port	0x19		; Port A @ 0x19 (IO) ff.
55PINB		port	0x16		; Port B @ 0x16 (IO) ff.
56PINC		port	0x13		; Port C @ 0x13 (IO) ff.
57PIND		port	0x10		; Port D @ 0x10 (IO) ff.
58
59SFIOR		port	0x30		; Special Function I/O Register
60PUD		avrbit	SFIOR,2		; Pull-Up Disable
61
62;----------------------------------------------------------------------------
63; Interrupt Vectors
64
65		enumconf 2,code
66		enum	 INT0_vect=2		; External Interrupt Request 0
67		nextenum INT1_vect		; External Interrupt Request 1
68		nextenum TIMER2_COMP_vect	; Timer/Counter 2 Compare Match
69		nextenum TIMER2_OVF_vect	; Timer/Counter 2 Overflow
70		nextenum TIMER1_CAPT_vect	; Timer/Counter 1 Capture Event
71		nextenum TIMER1_COMPA_vect	; Timer/Counter 1 Compare Match A
72		nextenum TIMER1_COMPB_vect	; Timer/Counter 1 Compare Match B
73		nextenum TIMER1_OVF_vect	; Timer/Counter 1 Overflow
74		nextenum TIMER0_OVF_vect	; Timer/Counter 0 Overflow
75		nextenum SPI_STC_vect		; SPI Transfer Complete
76		nextenum UART_RX_vect		; UART Rx Complete
77		nextenum UART_UDRE_vect		; UART Data Register Empty
78		nextenum UART_TX_vect		; UART Tx Complete
79		nextenum ADC_vect		; ADC Conversion Complete
80		nextenum EE_RDY_vect		; EEPROM Ready
81		nextenum ANA_COMP_vect		; Analog Comparator
82		nextenum TWI_vect		; 2-Wire Serial interface
83
84;----------------------------------------------------------------------------
85; External Interrupts
86
87ISC00		avrbit	MCUCR,0		; External Interrupt 0 Sense Control
88ISC01		avrbit	MCUCR,1
89ISC10		avrbit	MCUCR,2		; External Interrupt 1 Sense Control
90ISC11		avrbit	MCUCR,3
91
92GIMSK		port	0x3b		; General Interrupt Mask Register
93INT0		avrbit	GIMSK,6		; Enable External Interrupt 0
94INT1		avrbit	GIMSK,7		; Enable External Interrupt 1
95
96GIFR		port	0x3a		; External Interrupt-Flags
97INTF0		avrbit	GIFR,6		; External Interrupt 0 Occured
98INTF1	        avrbit	GIFR,7		; External Interrupt 1 Occured
99
100;----------------------------------------------------------------------------
101; Timers
102
103PSR10		avrbit	SFIOR,0		; Prescaler Reset T0/1
104PSR2		avrbit	SFIOR,1		; Prescaler Reset T2
105
106TCCR0		port	0x33		; Timer/Counter 0 Control Register
107CS00		avrbit	TCCR0,0		; Timer/Counter 0 Clock Select
108CS01		avrbit	TCCR0,1
109CS02		avrbit	TCCR0,2
110TCNT0		port	0x32		; Timer/Counter 0 Value
111
112TCCR1A		port	0x2f		; Timer/Counter 1 Control Register A
113PWM10		avrbit	TCCR1A,0	; Timer/Counter 1 PWM config
114PWM11		avrbit	TCCR1A,1
115FOC1B		avrbit	TCCR1A,2	; Timer/Counter 1 Force Output Compare B
116FOC1A		avrbit	TCCR1A,3	; Timer/Counter 1 Force Output Compare A
117COM1B0		avrbit	TCCR1A,4	; Timer/Counter 1 Compare Mode B
118COM1B1		avrbit	TCCR1A,5
119COM1A0		avrbit	TCCR1A,6	; Timer/Counter 1 Compare Mode A
120COM1A1		avrbit	TCCR1A,7
121TCCR1B		port	0x2e		; Timer/Counter 1 Control Register B
122CS10		avrbit	TCCR1B,0	; Timer/Counter 1 Prescaler Setting
123CS11		avrbit	TCCR1B,1
124CS12		avrbit	TCCR1B,2
125CTC1		avrbit	TCCR1B,3	; Timer/Counter 1 Clear on Match
126ICES1		avrbit	TCCR1B,6	; Timer/Counter 1 Capture Slope Selection
127ICNC1		avrbit	TCCR1B,7	; Timer/Counter 1 Capture Noise Filter
128TCNT1L		port	0x2c		; Timer/Counter 1 Value LSB
129TCNT1H		port	0x2d		; Timer/Counter 1 Value MSB
130OCR1AL		port	0x2a		; Timer/Counter 1 Output Compare Value A LSB
131OCR1AH		port	0x2b		; Timer/Counter 1 Output Compare Value A MSB
132OCR1BL		port	0x28		; Timer/Counter 1 Output Compare Value B LSB
133OCR1BH		port	0x29		; Timer/Counter 1 Output Compare Value B MSB
134ICR1L		port	0x26		; Timer/Counter 1 Input Capture Value LSB
135ICR1H		port	0x27		; Timer/Counter 1 Input Capture Value MSB
136
137TCCR2		port	0x25		; Timer/Counter 2 Control Register
138CS20		avrbit	TCCR2,0		; Timer/Counter 2 Prescaler Setting
139CS21		avrbit	TCCR2,1
140CS22		avrbit	TCCR2,2
141CTC2		avrbit	TCCR2,3		; Timer/Counter 2 Clear on Match
142COM20		avrbit	TCCR2,4		; Timer/Counter 2 Compare Mode
143COM21		avrbit	TCCR2,5
144PWM2		avrbit	TCCR2,6		; Timer/Counter 2 PWM Config
145FOC2		avrbit	TCCR2,7		; Timer/Counter 2 Force Output Compare
146TCNT2		port	0x24		; Timer/Counter 2 Value
147OCR2		port	0x23		; Timer/Counter 2 Output Compare Value
148
149TIMSK		port	0x39		; Timer Interrupt Mask Register
150TOIE0		avrbit	TIMSK,0		; Timer/Counter 0 Overflow Interrupt Enable
151TOIE1		avrbit	TIMSK,2		; Timer/Counter 1 Overflow Interrupt Enable
152OCIE1B		avrbit	TIMSK,3		; Timer/Counter 1 Output Compare Interrupt Enable B
153OCIE1A		avrbit	TIMSK,4		; Timer/Counter 1 Output Compare Interrupt Enable A
154TICIE1		avrbit	TIMSK,5		; Timer/Counter 1 Input Capture Interrupt Enable
155TOIE2		avrbit	TIMSK,6		; Timer/Counter 2 Overflow Interrupt Enable
156OCIE2		avrbit	TIMSK,7		; Timer/Counter 2 Output Compare Interrupt Enable
157
158TIFR		port	0x38		; Timer Interrupt Flag Register
159
160ASSR		port	0x22		; Asynchronous Status Register
161TCR2UB		avrbit	ASSR,0		; Timer/Counter Control Register 2 Update Busy
162OCR2UB		avrbit	ASSR,1		; Output Compare Register 2 Update Busy
163TCN2UB		avrbit	ASSR,2		; Timer/Counter 2 Update Busy
164AS2		avrbit	ASSR,3		; Asynchronous Timer/Counter 2
165
166;----------------------------------------------------------------------------
167; Watchdog Timer
168
169		include	"wdm21.inc"
170WDTOE		avrbit	WDTCR,4		; Turn-Off Enable
171
172;----------------------------------------------------------------------------
173; UART
174
175UDR		port	0x0c		; I/O Data Register
176
177UCSRA		port	0x0b		; Control & Status Register A
178MPCM		avrbit	UCSRA,0		; Multi Processor Communication Mode
179U2X		avrbit	UCSRA,1		; Double Transmission Speed
180OR		avrbit	UCSRA,3		; Overrun
181FE		avrbit	UCSRA,4		; Framing Error
182UDRE		avrbit	UCSRA,5		; Data Register Empty
183TXC		avrbit	UCSRA,6		; Transmit Complete
184RXC		avrbit	UCSRA,7		; Receive Complete
185
186UCSRB		port	0x0a		; Control & Status Register B
187TXB8		avrbit	UCSRB,0		; Transmit Bit 8
188RXB8		avrbit	UCSRB,1		; Receive Bit 8
189CHR9		avrbit	UCSRB,2		; Character Size
190TXEN		avrbit	UCSRB,3		; Enable Transmitter
191RXEN		avrbit	UCSRB,4		; Enable Receiver
192UDRIE		avrbit	UCSRB,5		; Enable Data Register Empty Interrupt
193TXCIE		avrbit	UCSRB,6		; Enable Transmit Complete Interrupt
194RXCIE		avrbit	UCSRB,7		; Enable Receive Complete Interrupt
195
196UCSRC		port	0x20		; Control & Status Register C
197UCPOL		avrbit	UCSRC,0		; Clock Polarity
198UCSZ0		avrbit	UCSRC,1		; Character Size
199UCSZ1		avrbit	UCSRC,2
200USBS		avrbit	UCSRC,3		; Stop Bit Select
201UPM0		avrbit	UCSRC,4		; Parity Mode : Odd/Even
202UPM1		avrbit	UCSRC,5		; Parity Mode : Enable/Disable
203UMSEL		avrbit	UCSRC,6		; USART Mode Select
204URSEL		avrbit	UCSRC,7		; Register Select (1 for UCSRC)
205
206UBRR		port	0x09		; Baud Rate Register LSB
207UBRRHI		port	0x20		; Baud Rate Register MSB
208
209;----------------------------------------------------------------------------
210; SPI
211
212		include	"spim.inc"
213
214;----------------------------------------------------------------------------
215; TWI
216
217		include	"twim.inc"
218
219;----------------------------------------------------------------------------
220; A/D Converter
221
222		include	"adcm8.inc"
223
224;----------------------------------------------------------------------------
225; Analog Comparator
226
227		include "acm.inc"
228
229		restore			; re-enable listing
230
231		endif			; __regm163inc
232