1 ifndef __regtn43uinc 2__regtn43uinc equ 1 3 save 4 listing off ; kein Listing ueber diesen File 5 6;**************************************************************************** 7;* * 8;* AS 1.42 - File REGTN43U.INC * 9;* * 10;* Contains Bit & Register Definitions for ATtiny43U * 11;* * 12;**************************************************************************** 13 14;---------------------------------------------------------------------------- 15; Memory Limits 16 17E2END equ 63 ; end address EEPROM 18RAMSTART equ 0x60,data ; start address SRAM 19RAMEND equ 0x15f,data ; end address SRAM 20FLASHEND label 4095 ; end address Flash 21 22;---------------------------------------------------------------------------- 23; Chip Configuration 24 25MCUCR port 0x35 ; MCU General Control Register 26BODSE avrbit MCUCR,2 ; BOD Sleep 27SM0 avrbit MCUCR,3 ; Sleep Mode Select 28SM1 avrbit MCUCR,4 29SE avrbit MCUCR,5 ; Sleep Enable 30BODS avrbit MCUCR,7 ; BOD Sleep Enable 31 32MCUSR port 0x34 ; MCU Status Register 33WDRF avrbit MCUSR,3 ; Watchdog Reset Flag 34BORF avrbit MCUSR,2 ; Brown-out Reset Flag 35EXTRF avrbit MCUSR,1 ; External Reset Flag 36PORF avrbit MCUSR,0 ; Power-On Reset Flag 37 38OSCCAL port 0x31 ; Oscillator Calibration 39 40CLKPR port 0x26 ; Clock Prescaler 41CLKPS0 avrbit CLKPS0,0 ; Prescaler Select 42CLKPS1 avrbit CLKPS0,1 43CLKPS2 avrbit CLKPS0,2 44CLKPS3 avrbit CLKPS0,3 45CLKPCE avrbit CLKPS0,7 ; Clock Prescaler Change Enable 46 47PRR port 0x00 ; Power Reduction Register 48PRADC avrbit PRR,0 ; Power Reduction AD Converter 49PRUSI avrbit PRR,1 ; Power Reduction USI 50PRTIM0 avrbit PRR,2 ; Power Reduction Timer/Counter 0 51PRTIM1 avrbit PRR,3 ; Power Reduction Timer/Counter 1 52PRE0 avrbit PRR,5 ; Prepared Read Enable 53PRE1 avrbit PRR,6 54PRE2 avrbit PRR,7 55 56;---------------------------------------------------------------------------- 57; EEPROM/Flash Access 58 59EEAR port 0x1e ; EEPROM Address Register 60EEDR port 0x1d ; EEPROM Data Register 61EECR port 0x1c ; EEPROM Control Register 62EEPM1 avrbit EECR,5 ; EEPROM Program Mode 63EEPM0 avrbit EECR,4 64EERIE avrbit EECR,3 ; EEPROM Ready Interrupt Enable 65EEMPE avrbit EECR,2 ; EEPROM Master Write Enable 66EEPE avrbit EECR,1 ; EEPROM Write Enable 67EERE avrbit EECR,0 ; EEPROM Read Enable 68 69SPMCSR port 0x37 ; Store Program Memory Control/Status Register 70CTPB avrbit SPMCSR,4 ; Clear Temporary Page Buffer 71RFLB avrbit SPMCSR,3 ; Read Fuse and Lock Bits 72PGWRT avrbit SPMCSR,2 ; Page Write 73PGERS avrbit SPMCSR,1 ; Page Erase 74SPMEN avrbit SPMCSR,0 ; Self Programming Enable 75 76;---------------------------------------------------------------------------- 77; JTAG etc. 78 79DWDR port 0x27 ; debugWire Data Register 80 81;---------------------------------------------------------------------------- 82; GPIO 83 84PUD avrbit MCUCR,6 ; Pull-Up Disable 85 86PINA port 0x19 ; Port A @ 0x19 (IO) ff. 87PINB port 0x16 ; Port B @ 0x16 (IO) ff. 88 89GPIOR0 port 0x13 ; General Purpose I/O Register 0 90GPIOR1 port 0x14 ; General Purpose I/O Register 1 91GPIOR2 port 0x15 ; General Purpose I/O Register 2 92 93DIDR0 port 0x01 ; Digital Input Disable Register 0 94ADC0D avrbit DIDR0,0 ; ADC0 Digital Input Disable 95ADC1D avrbit DIDR0,1 ; ADC1 Digital Input Disable 96ADC2D avrbit DIDR0,2 ; ADC2 Digital Input Disable 97ADC3D avrbit DIDR0,3 ; ADC3 Digital Input Disable 98AIN0D avrbit DIDR0,4 ; Analog Comparator Digital Input 0 Disable 99AIN1D avrbit DIDR0,5 ; Analog Comparator Digital Input 1 Disable 100 101PCMSK0 port 0x12 ; Pin Change Interrupt Mask 0 102PCMSK1 port 0x20 ; Pin Change Interrupt Mask 1 103 104;---------------------------------------------------------------------------- 105; Interrupt Vectors 106 107 enumconf 1,code 108 enum INT0_vect=1 ; External Interrupt Request 0 109 nextenum PCINT0_vect ; Pin Change Interrupt 0 110 nextenum PCINT1_vect ; Pin Change Interrupt 1 111 nextenum WDT_vect ; Watchdog Time-Out 112 nextenum TIMER1_COMPA_vect ; Timer/Counter 1 Compare Match A 113 nextenum TIMER1_COMPB_vect ; Timer/Counter 1 Compare Match B 114 nextenum TIMER1_OVF_vect ; Timer/Counter 1 Overflow 115 nextenum TIMER0_COMPA_vect ; Timer/Counter 0 Compare Match A 116 nextenum TIMER0_COMPB_vect ; Timer/Counter 0 Compare Match B 117 nextenum TIMER0_OVF_vect ; Timer/Counter 0 Overflow 118 nextenum ANA_COMP_vect ; Analog Comparator 119 nextenum ADC_vect ; ADC Conversion Complete 120 nextenum EE_RDY_vect ; EEPROM Ready 121 nextenum USI_START_vect ; USI Start 122 nextenum USI_OVF_vect ; USI Overflow 123 124;---------------------------------------------------------------------------- 125; External Interrupts 126 127ISC00 avrbit MCUCR,0 ; External Interrupt 0 Sense Control 128ISC01 avrbit MCUCR,1 129 130GIMSK port 0x3b ; General Interrupt Mask Register 131INT0 avrbit GIMSK,6 ; Enable External Interrupt 0 132PCIE1 avrbit GIMSK,5 ; Pin Change Interrupt Enable 1 133PCIE0 avrbit GIMSK,4 ; Pin Change Interrupt Enable 0 134 135GIFR port 0x3a ; General Interrupt Flag Register 136INTF0 avrbit GIFR,6 ; External Interrupt 0 Occured 137PCIF1 avrbit GIFR,5 ; Pin Change Interrupt 1 Occured 138PCIF0 avrbit GIFR,4 ; Pin Change Interrupt 0 Occured 139 140;---------------------------------------------------------------------------- 141; Timers 142 143TCCR0A port 0x30 ; Timer/Counter 0 Control Register A 144WGM00 avrbit TCCR0A,0 ; Timer/Counter 0 Waveform Generation Mode 145WGM01 avrbit TCCR0A,1 146COM0B0 avrbit TCCR0A,4 ; Timer/Counter 0 Output Compare Mode B 147COM0B1 avrbit TCCR0A,5 148COM0A0 avrbit TCCR0A,6 ; Timer/Counter 0 Output Compare Mode A 149COM0A1 avrbit TCCR0A,7 150TCCR0B port 0x33 ; Timer/Counter 0 Control Register B 151CS00 avrbit TCCR0B,0 ; Timer/Counter 0 Clock Select 152CS01 avrbit TCCR0B,1 153CS02 avrbit TCCR0B,2 154WGM02 avrbit TCCR0B,3 155FOC0B avrbit TCCR0B,6 ; Timer/Counter 0 Force Output Compare B 156FOC0A avrbit TCCR0B,7 ; Timer/Counter 0 Force Output Compare A 157TCNT0 port 0x32 ; Timer/Counter 0 Value 158OCR0A port 0x36 ; Timer/Counter 0 Output Compare Value A 159OCR0B port 0x3c ; Timer/Counter 0 Output Compare Value B 160 161TCCR1A port 0x2f ; Timer/Counter 1 Control Register A 162WGM10 avrbit TCCR1A,0 ; Timer/Counter 1 Waveform Generation Mode 163WGM11 avrbit TCCR1A,1 164COM1B0 avrbit TCCR1A,4 ; Timer/Counter 1 Output Compare Mode B 165COM1B1 avrbit TCCR1A,5 166COM1A0 avrbit TCCR1A,6 ; Timer/Counter 1 Output Compare Mode A 167COM1A1 avrbit TCCR1A,7 168TCCR1B port 0x2e ; Timer/Counter 1 Control Register B 169CS10 avrbit TCCR1B,0 ; Timer/Counter 1 Clock Select 170CS11 avrbit TCCR1B,1 171CS12 avrbit TCCR1B,2 172WGM12 avrbit TCCR1B,3 173FOC1B avrbit TCCR1B,6 ; Timer/Counter 1 Force Output Compare B 174FOC1A avrbit TCCR1B,7 ; Timer/Counter 1 Force Output Compare A 175TCNT1 port 0x2d ; Timer/Counter 1 Value 176OCR1A port 0x2c ; Timer/Counter 1 Output Compare Value A 177OCR1B port 0x2b ; Timer/Counter 1 Output Compare Value B 178 179TIMSK0 port 0x39 ; Timer/Counter Interrupt Mask Register 0 180TOIE0 avrbit TIMSK0,0 ; Timer/Counter 0 Overflow Interrupt Enable 181OCIE0A avrbit TIMSK0,1 ; Timer/Counter 0 Output Compare Interrupt Enable A 182OCIE0B avrbit TIMSK0,2 ; Timer/Counter 0 Output Compare Interrupt Enable B 183 184TIMSK1 port 0x0c ; Timer/Counter Interrupt Mask Register 1 185TOIE1 avrbit TIMSK1,0 ; Timer/Counter 1 Overflow Interrupt Enable 186OCIE1A avrbit TIMSK1,1 ; Timer/Counter 1 Output Compare Interrupt Enable A 187OCIE1B avrbit TIMSK1,2 ; Timer/Counter 1 Output Compare Interrupt Enable B 188 189TIFR0 port 0x38 ; Timer Interrupt Status Register 0 190TIFR1 port 0x0b ; Timer Interrupt Status Register 1 191 192GTCCR port 0x23 ; General Timer/Counter Control 1 Register 193PSR10 avrbit GTCCR,0 ; Prescaler Reset Timer/Counter 0/1 194TSM avrbit GTCCR,7 ; Timer/Counter Synchronization Mode 195 196;---------------------------------------------------------------------------- 197; Watchdog Timer 198 199WDTCSR port 0x21 ; Watchdog Control/Status Register 200WDP0 avrbit WDTCSR,0 ; Prescaler 201WDP1 avrbit WDTCSR,1 202WDP2 avrbit WDTCSR,2 203WDE avrbit WDTCSR,3 ; Enable watchdog 204WDCE avrbit WDTCSR,4 ; Change Enable 205WDP3 avrbit WDTCSR,5 206WDIE avrbit WDTCSR,6 ; Enable Watchdog Interrupt 207WDIF avrbit WDTCSR,7 ; Watchdog Interrupt Occured? 208 209;---------------------------------------------------------------------------- 210; Analog Comparator 211 212 include "acm.inc" 213 214;---------------------------------------------------------------------------- 215; A/D Converter 216 217ADMUX port 0x07 ; Multiplexer Selection 218REFS avrbit ADMUX,6 ; Reference Selection 219MUX2 avrbit ADMUX,2 220MUX1 avrbit ADMUX,1 221MUX0 avrbit ADMUX,0 222 223ADCSRA port 0x06 ; Control/Status Register A 224ADEN avrbit ADCSRA,7 ; Enable ADC 225ADSC avrbit ADCSRA,6 ; Start Conversion 226ADATE avrbit ADCSRA,5 ; ADC Auto Trigger Enable 227ADIF avrbit ADCSRA,4 ; Interrupt Flag 228ADIE avrbit ADCSRA,3 ; Interrupt Enable 229ADPS2 avrbit ADCSRA,2 ; Prescaler Select 230ADPS1 avrbit ADCSRA,1 231ADPS0 avrbit ADCSRA,0 232 233ADCSRB port 0x03 ; Control/Status Register B 234BS avrbit ADCSRB,7 ; Boost Status 235ACME avrbit ADCSRB,6 ; Analog Comparator Multiplexer Enable 236ADLAR avrbit ADCSRB,4 ; Left Adjust Right 237ADTS2 avrbit ADCSRB,2 ; Auto Trigger Source 238ADTS1 avrbit ADCSRB,1 239ADTS0 avrbit ADCSRB,0 240 241ADCH port 0x05 ; Data Register 242ADCL port 0x04 243 244;---------------------------------------------------------------------------- 245; USI 246 247USIDR port 0x0f ; USI Data Register 248 249USISR port 0x0e ; USI Status Register 250USICNT0 avrbit USISR,0 ; Counter Value 251USICNT1 avrbit USISR,1 252USICNT2 avrbit USISR,2 253USICNT3 avrbit USISR,3 254USIDC avrbit USISR,4 ; Data Output Collision 255USIPF avrbit USISR,5 ; Stop Condition Flag 256USIOIF avrbit USISR,6 ; Counter Overflow Interrupt Flag 257USISIF avrbit USISR,7 ; Start Condition Interrupt Flag 258 259USICR port 0x0d ; USI Control Register 260USITC avrbit USICR,0 ; Toggle Clock Port Pin 261USICLK avrbit USICR,1 ; Clock Strobe 262USICS0 avrbit USICR,2 ; Clock Source Select 263USICS1 avrbit USICR,3 264USIWM0 avrbit USICR,4 ; Wire Mode 265USIWM1 avrbit USICR,5 266USIOIE avrbit USICR,6 ; Counter Overflow Interrupt Enable 267USISIE avrbit USICR,7 ; Start Condition Interrupt Enable 268 269USIBR port 0x10 ; USI Buffer Register 270 271 restore 272 273 endif ; __regtn43uinc 274