1 ifndef reg68332inc ; avoid multiple inclusion 2reg6833xinc equ 1 3 4 save 5 listing off ; no listing over this file 6 macexp off ; saves a bit of time 7 8;**************************************************************************** 9;* * 10;* AS 1.42 - Datei REG683XX.INC * 11;* * 12;* Contains Register Address Definitions for 68332, 68340, and 68360 * 13;* * 14;**************************************************************************** 15 16 if (MOMCPUNAME<>"68332")&&(MOMCPUNAME<>"68340")&&(MOMCPUNAME<>"68360") 17 fatal "wrong target sleected: only 68332, 68340, or 68360 supported" 18 endif 19 20 21 if MOMPASS=1 22 message "CPU32 Register Definitions (C) 1994 Alfred Arnold" 23 message "including \{MOMCPU} registers" 24 endif 25 26;----------------------------------------------------------------------------- 27; The base is either $fffa00 or $7fa000, this has to be set in advance 28; (or you live with the default :-) ). 29; On the 68340, the base may be anywhere. 30; Since the 68332 does not expose A31..A24, one could place the registers at 31; $fffffa00 and use short addresses. Anyone ever tried that? 32; An alternative is to set the base to 0 befor eincluding this file, so the 33; symbols may be used as offsets relative to the base. 34 35 ifndef SIMBase 36 if MOMCPU=$68332 37SIMBase equ $fffa00 38 elseif 39SIMBase equ $000000 40 endif 41 endif 42 43;============================================================================= 44; Since 68360, 68340, and 68332 differ significantly in their register set, 45; I did not bother to sort out common registers. 46 47 switch MOMCPUNAME 48 49;----------------------------------------------------------------------------- 50 51 case "68360" 52 53;----------------------------------------------------------------------------- 54 55MBAR equ $0003ff00 ; [L] Peripherals Start Address (CPU Space!) 56MBARE equ $0003ff04 ; [L] Disable/Enable MBAR 57 58RegBase equ SIMBase+$1000 ; Register Start Address 59 60MCR equ RegBase+$0000 ; [L] SIM Module Configuration 61 62AVR equ RegBase+$0008 ; [B] Enable Auto Vector Interrupts 63RSR equ RegBase+$0009 ; [B] Reset Status 64CLK0CR equ RegBase+$000c ; [B] Clock Output 2 & 1 Control 65PLLCR equ RegBase+$0010 ; [W] PLL Control 66CDVCR equ RegBase+$0014 ; [W] "Slow" Clock Control 67PEPAR equ RegBase+$0016 ; [W] Port E I/O Pins Assignment 68SYPCR equ RegBase+$0022 ; [B] System Monitors, Bus Timimg 69SWIV equ RegBase+$0023 ; [B] Watchdog Interrupt Vector 70PICR equ RegBase+$0026 ; [W] Periodic Interrupt Interrupt Level and Vector 71PITR equ RegBase+$002a ; [W] Periodic Interrupt Counter Value and Prescaler 72SWSR equ RegBase+$002f ; [B] Reset Watchdog 73BKAR equ RegBase+$0030 ; [L] Breakpoint Address 74BKCR equ RegBase+$0034 ; [L] Breakpoint Control 75 76GMR equ RegBase+$0040 ; [L] Memory Controller Global Control 77MSTAT equ RegBase+$0044 ; [W] Memory-Controller Status 78BR0 equ RegBase+$0050 ; [L] CS0 SRAM/DRAM Base 79OR0 equ RegBase+$0054 ; [L] CS0 DRAM/SRAM Options 80BR1 equ RegBase+$0060 ; [L] CS1 SRAM/DRAM Base 81OR1 equ RegBase+$0064 ; [L] CS1 DRAM/SRAM Options 82BR2 equ RegBase+$0070 ; [L] CS2 SRAM/DRAM Base 83OR2 equ RegBase+$0074 ; [L] CS2 DRAM/SRAM Options 84BR3 equ RegBase+$0080 ; [L] CS3 SRAM/DRAM Base 85OR3 equ RegBase+$0084 ; [L] CS3 DRAM/SRAM Options 86BR4 equ RegBase+$0090 ; [L] CS4 SRAM/DRAM Base 87OR4 equ RegBase+$0094 ; [L] CS4 DRAM/SRAM Options 88BR5 equ RegBase+$00a0 ; [L] CS5 SRAM/DRAM Base 89OR5 equ RegBase+$00a4 ; [L] CS5 DRAM/SRAM Options 90BR6 equ RegBase+$00b0 ; [L] CS6 SRAM/DRAM Base 91OR6 equ RegBase+$00b4 ; [L] CS6 DRAM/SRAM Options 92BR7 equ RegBase+$00c0 ; [L] CS7 SRAM/DRAM Base 93OR7 equ RegBase+$00c4 ; [L] CS7 DRAM/SRAM Options 94 95;----------------------------------------------------------------------------- 96; Communications Controller: 97 98RAMBase equ SIMBase ; [ ] RAM Base Address 99 100;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 101; IDMA: 102 103IDMA1Base equ RAMBase+$0e70 104IDMA2Base equ RAMBase+$0f70 105 106ICCR equ RegBase+$0500 ; [W] IDMA Channels Configuration 107CMR1 equ RegBase+$0504 ; [W] IDMA1 Mode 108CMR2 equ RegBase+$0526 ; [W] IDMA2 Mode 109__defidma macro NAME,Adr,IDMABase 110SAPR{NAME} equ Adr ; [L] Source Address for Memory Copy Transactions 111DAPR{NAME} equ Adr+4 ; [L] Target Address " " " " 112BCR{NAME} equ Adr+8 ; [L] IDMA Count Register 113FCR{NAME} equ Adr+12 ; [B] Functions Codes 114CMAR{NAME} equ Adr+14 ; [B] Channel Mask 115CSR{NAME} equ Adr+16 ; [B] IDMA Channel Status 116IDMA{NAME}_IBASE equ IDMABase+0 ; [W] Descriptor Base Address 117IDMA{NAME}_IBPTR equ IDMABase+0 ; [W] Descriptor Pointer 118IDMA{NAME}_ISTATE equ IDMABase+0 ; [L] Internal Status 119IDMA{NAME}_ITEMP equ IDMABase+0 ; [L] Temporary Storage 120 endm 121 __defidma "1",RegBase+$508 122 __defidma "2",RegBase+$528 123 124;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 125; SDMA: 126 127SDSR equ RegBase+$051c ; [B] SDMA Status 128SDCR equ RegBase+$051e ; [W] SDMA Channel Configuration 129SDAR equ RegBase+$0520 ; [L] SDMA Address Register 130 131;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 132; CPIC: 133 134CICR equ RegBase+$0540 ; [L] Interrupt Configuration 135CIPR equ RegBase+$0544 ; [L] Interrupt Flags 136CIMR equ RegBase+$0548 ; [L] Interrupt Masks 137CISR equ RegBase+$054c ; [L] Interrupts Pending 138 139;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 140; PIO: 141 142PADIR equ RegBase+$0550 ; [W] Port A Data Direction Register 143PAPAR equ RegBase+$0552 ; [W] Port A Assignment 144PAODR equ RegBase+$0554 ; [W] Port A Open Drain Control 145PADAT equ RegBase+$0556 ; [W] Port A Data Register 146 147PCDIR equ RegBase+$0560 ; [W] Port C Data Direction Register 148PCPAR equ RegBase+$0562 ; [W] Port C Assignment 149PCSO equ RegBase+$0564 ; [W] Port C Special Options 150PCDAT equ RegBase+$0566 ; [W] Port C Data Register 151PCINT equ RegBase+$0568 ; [W] Port C Interrupt Control 152 153;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 154; TIMER: 155 156TimerBase equ RAMBase+$0db0 157 158TGCR equ RegBase+$0560 ; [W] Timer Global Configuration 159TMR1 equ RegBase+$0590 ; [W] Timer 1 Mode 160TRR1 equ RegBase+$0594 ; [W] Timer 1 Reference Value 161TCR1 equ RegBase+$0598 ; [W] Timer 1 Capture Value 162TCN1 equ RegBase+$059c ; [W] Timer 1 Counter Value 163TER1 equ RegBase+$05b0 ; [W] Timer 1 Event Report 164TMR2 equ RegBase+$0592 165TRR2 equ RegBase+$0596 166TCR2 equ RegBase+$059a 167TCN2 equ RegBase+$059e 168TER2 equ RegBase+$05b2 169TMR3 equ RegBase+$05a0 170TRR3 equ RegBase+$05a4 171TCR3 equ RegBase+$05a8 172TCN3 equ RegBase+$05ac 173TER3 equ RegBase+$05b4 174TMR4 equ RegBase+$05a2 175TRR4 equ RegBase+$05a6 176TCR4 equ RegBase+$05aa 177TCN4 equ RegBase+$05ae 178TER4 equ RegBase+$05b6 179TIMER_TM_BASE equ TimerBase+$00 ; [W] Table Base Address 180TIMER_TM_ptr equ TimerBase+$02 ; [W] Table Pointer 181TIMER_R_TMR equ TimerBase+$04 ; [W] Mode 182TIMER_R_TMV equ TimerBase+$06 ; [W] Valid Register 183TIMER_TM_cmd equ TimerBase+$08 ; [L] Command Register 184TIMER_TM_cnt equ TimerBase+$0c ; [L] Internal Counter 185 186;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 187; CP: 188 189MiscBase equ RAMBase+$0cb0 190 191CR equ RegBase+$05c0 ; [W] Command Register 192RCCR equ RegBase+$05c4 ; [W] RISC-Controller Configuration 193RTER equ RegBase+$05d6 ; [W] Timer Events 194RTMR equ RegBase+$05da ; [W] Timer Mask 195CP_REV_num equ MiscBase ; [W] Microcode Revision Number 196 197;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 198; BRG: 199 200BRGC1 equ RegBase+$05f0 ; [L] Baud Rate Generator 1 Configration 201BRGC2 equ RegBase+$05f4 202BRGC3 equ RegBase+$05f8 203BRGC4 equ RegBase+$05fc 204 205;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 206; SCC: 207 208SCC1Base equ RAMBase+$0c00 209SCC2Base equ RAMBase+$0d00 210SCC3Base equ RAMBase+$0e00 211SCC4Base equ RAMBase+$0f00 212 213__defscc macro NAME,Adr,SCCBase 214GSMR_L{NAME} equ Adr+0 ; [Q] Mode 215GSMR_H{NAME} equ Adr+4 216PSMR{NAME} equ Adr+8 ; [W] Protocol Specific Mode 217TODR{NAME} equ Adr+12 ; [W] Force Transmission Start 218DSR{NAME} equ Adr+14 ; [W] SCCx Synchronisation Pattern 219SCCE{NAME} equ Adr+16 ; [W] UART Event Register 220SCCM{NAME} equ Adr+20 ; [W] UART Event Mask 221SCCS{NAME} equ Adr+23 ; [B] UART Status 222SCC{NAME}_RBASE equ SCCBase+$00 ; [W] Receive Buffer Start Address 223SCC{NAME}_TBASE equ SCCBase+$02 ; [W] Transmit Buffer Start Address 224SCC{NAME}_RFCR equ SCCBase+$04 ; [B] Receive Address Space 225SCC{NAME}_TFCR equ SCCBase+$05 ; [B] Transmit Address Space 226SCC{NAME}_MRBLR equ SCCBase+$06 ; [W] Receive Buffer Length 227SCC{NAME}_RSTATE equ SCCBase+$08 ; [L] Receiver Status 228SCC{NAME}_RBPTR equ SCCBase+$10 ; [W] Receive Address Pointer 229SCC{NAME}_TSTATE equ SCCBase+$18 ; [L] Transmitter Status 230SCC{NAME}_TBPTR equ SCCBase+$20 ; [W] Transmit Address Pointer 231SCC{NAME}_RCRC equ SCCBase+$28 ; [L] Receive CRC 232SCC{NAME}_TCRC equ SCCBase+$2c ; [L] Transmit CRC 233SCC{NAME}_MAX_IDL equ SCCBase+$38 ; [W] --UART-- Maximum Number of Idle Characters 234SCC{NAME}_IDLC equ SCCBase+$3a ; [W] Temporary Idle Counter 235SCC{NAME}_BRKCR equ SCCBase+$3c ; [W] Number of Transmit Breaks 236SCC{NAME}_PAREC equ SCCBase+$3e ; [W] Parity Error Counter 237SCC{NAME}_FRMEC equ SCCBase+$40 ; [W] Framing Error Counter 238SCC{NAME}_NOSEC equ SCCBase+$42 ; [W] Noise Counter 239SCC{NAME}_BRKEC equ SCCBase+$44 ; [W] Break Condition 240SCC{NAME}_BRKLN equ SCCBase+$46 ; [W] Length of most recent Break 241SCC{NAME}_UADDR1 equ SCCBase+$48 ; [W] Slave Addresse 242SCC{NAME}_UADDR2 equ SCCBase+$4a ; [W] 243SCC{NAME}_RTEMP equ SCCBase+$4c ; [W] Temporary Storage 244SCC{NAME}_TOSEQ equ SCCBase+$4e ; [W] Out-of-Sequence Characters 245SCC{NAME}_CHARACTER1 equ SCCBase+$50 ; [W] Characters that generate Interrupts 246SCC{NAME}_CHARACTER2 equ SCCBase+$52 ; [W] 247SCC{NAME}_CHARACTER3 equ SCCBase+$54 ; [W] 248SCC{NAME}_CHARACTER4 equ SCCBase+$56 ; [W] 249SCC{NAME}_CHARACTER5 equ SCCBase+$58 ; [W] 250SCC{NAME}_CHARACTER6 equ SCCBase+$5a ; [W] 251SCC{NAME}_CHARACTER7 equ SCCBase+$5c ; [W] 252SCC{NAME}_CHARACTER8 equ SCCBase+$5e ; [W] 253SCC{NAME}_RCCM equ SCCBase+$60 ; [W] Received Characters Mask 254SCC{NAME}_RCCR equ SCCBase+$62 ; [W] Received Character 255SCC{NAME}_RLBC equ SCCBase+$64 ; [W] Most Recent Break Character 256SCC{NAME}_C_MASK equ SCCBase+$34 ; [L] --HDLC-- CRC Polynom 257SCC{NAME}_C_PRES equ SCCBase+$38 ; [L] CRC Start Value 258SCC{NAME}_DISFC equ SCCBase+$3c ; [W] Discarded Frames Counter 259SCC{NAME}_CRCEC equ SCCBase+$3e ; [W] CRC Errors Counter 260SCC{NAME}_ABTSC equ SCCBase+$40 ; [W] Aborts Counter 261SCC{NAME}_NMARC equ SCCBase+$42 ; [W] Non-Matching Addresses Counter 262SCC{NAME}_RETRC equ SCCBase+$44 ; [W] Retransmissions Counter 263SCC{NAME}_MFLR equ SCCBase+$46 ; [W] Maximal Frame Length 264SCC{NAME}_MAX_cnt equ SCCBase+$48 ; [W] Length Counter 265SCC{NAME}_RFTHR equ SCCBase+$4a ; [W] Received Frames Threshold 266SCC{NAME}_RFCNT equ SCCBase+$4c ; [W] Received Frames Count 267SCC{NAME}_HMASK equ SCCBase+$4e ; [W] Address Mask 268SCC{NAME}_HADDR1 equ SCCBase+$50 ; [W] Addresses 269SCC{NAME}_HADDR2 equ SCCBase+$52 ; [W] 270SCC{NAME}_HADRR3 equ SCCBase+$54 ; [W] 271SCC{NAME}_HADDR4 equ SCCBase+$56 ; [W] 272SCC{NAME}_TMP equ SCCBase+$58 ; [W] Temporary Storage 273SCC{NAME}_TMP_MB equ SCCBase+$5a ; [W] " " 274SCC{NAME}_CRCC equ SCCBase+$34 ; [L] --BISYNC-- Temporary CRC Value 275SCC{NAME}_PRCRC equ SCCBase+$38 ; [W] Receiver Preset for CRC 276SCC{NAME}_PTCRC equ SCCBase+$3a ; [W] Transmitter Preset for CRC 277SCC{NAME}_B_PAREC equ SCCBase+$3c ; [W] Receiver Parity Errors Counter 278SCC{NAME}_BSYNC equ SCCBase+$3e ; [W] SYNC Characters 279SCC{NAME}_BDLE equ SCCBase+$40 ; [W] DLE Characters 280SCC{NAME}_B_CHARACTER1 equ SCCBase+$42 ; [W] Control Characters 281SCC{NAME}_B_CHARACTER2 equ SCCBase+$44 ; [W] 282SCC{NAME}_B_CHARACTER3 equ SCCBase+$46 ; [W] 283SCC{NAME}_B_CHARACTER4 equ SCCBase+$48 ; [W] 284SCC{NAME}_B_CHARACTER5 equ SCCBase+$4a ; [W] 285SCC{NAME}_B_CHARACTER6 equ SCCBase+$4c ; [W] 286SCC{NAME}_B_CHARACTER7 equ SCCBase+$4e ; [W] 287SCC{NAME}_B_CHARACTER8 equ SCCBase+$50 ; [W] 288SCC{NAME}_B_RCCM equ SCCBase+$52 ; [W] Receive Control Character Mask 289SCC{NAME}_CRC_P equ SCCBase+$30 ; [L] --Transparent-- CRC Preset 290SCC{NAME}_CRC_C equ SCCBase+$34 ; [L] CRC Constant 291SCC{NAME}_E_C_PRES equ SCCBase+$30 ; [L] --Ethernet-- CRC Preset 292SCC{NAME}_E_C_MASK equ SCCBase+$34 ; [L] CRC Mask 293SCC{NAME}_E_CRCEC equ SCCBase+$38 ; [L] CRC Error Counter 294SCC{NAME}_ALEC equ SCCBase+$3c ; [L] Alignment Error Counter 295SCC{NAME}_E_DISFC equ SCCBase+$40 ; [L] Discarded Frames Counter 296SCC{NAME}_PADS equ SCCBase+$44 ; [W] Padding Characters for Short Frames 297SCC{NAME}_RET_Lim equ SCCBase+$46 ; [W] Maximum Number of Retries 298SCC{NAME}_RET_cnt equ SCCBase+$48 ; [W] Current Number of Retries 299SCC{NAME}_E_MFLR equ SCCBase+$4a ; [W] Maximum Frame Length 300SCC{NAME}_MINFLR equ SCCBase+$4c ; [W] Minimum Frame Length 301SCC{NAME}_MAXD1 equ SCCBase+$4e ; [W] Maximal Length DMA1 302SCC{NAME}_MAXD2 equ SCCBase+$50 ; [W] Maximal Length DMA2 303SCC{NAME}_MAXD equ SCCBase+$52 ; [W] Rx Max DMA 304SCC{NAME}_DMA_cnt equ SCCBase+$54 ; [W] DMA Counter Reception 305SCC{NAME}_MAX_b equ SCCBase+$56 ; [W] Maximum BD Byte Count 306SCC{NAME}_GADDR1 equ SCCBase+$58 ; [W] Group Address Filter 307SCC{NAME}_GADDR2 equ SCCBase+$5a ; [W] 308SCC{NAME}_GADDR3 equ SCCBase+$5c ; [W] 309SCC{NAME}_GADDR4 equ SCCBase+$5e ; [W] 310SCC{NAME}_TBUF0.data0 equ SCCBase+$60 ; [L] Save Areas - Current Frame 311SCC{NAME}_TBUF0.data1 equ SCCBase+$64 ; [L] 312SCC{NAME}_TBUF0.rba0 equ SCCBase+$68 ; [L] 313SCC{NAME}_TBUF0.crc equ SCCBase+$6c ; [L] 314SCC{NAME}_TBUF0.bcnt equ SCCBase+$70 ; [W] 315SCC{NAME}_PADDR1_H equ SCCBase+$72 ; [W] Physical Address 316SCC{NAME}_PADDR1_M equ SCCBase+$74 ; [W] 317SCC{NAME}_PADDR1_L equ SCCBase+$76 ; [W] 318SCC{NAME}_P_Per equ SCCBase+$78 ; [W] Persistence 319SCC{NAME}_RFBD_ptr equ SCCBase+$7a ; [W] Rx First BD Counter 320SCC{NAME}_TFBD_ptr equ SCCBase+$7c ; [W] Tx First BD Pointer 321SCC{NAME}_TLBD_ptr equ SCCBase+$7e ; [W] Tx Last BD Pointer 322SCC{NAME}_TBUF1.data0 equ SCCBase+$80 ; [L] Save Areas - Next Frame 323SCC{NAME}_TBUF1.data1 equ SCCBase+$84 ; [L] 324SCC{NAME}_TBUF1.rba0 equ SCCBase+$88 ; [L] 325SCC{NAME}_TBUF1.crc equ SCCBase+$8c ; [L] 326SCC{NAME}_TBUF1.bcnt equ SCCBase+$90 ; [W] 327SCC{NAME}_TX_len equ SCCBase+$92 ; [W] Tx Frame Length Counter 328SCC{NAME}_IADDR1 equ SCCBase+$94 ; [W] Individual Address Filters 329SCC{NAME}_IADDR2 equ SCCBase+$96 ; [W] 330SCC{NAME}_IADDR3 equ SCCBase+$98 ; [W] 331SCC{NAME}_IADDR4 equ SCCBase+$9a ; [W] 332SCC{NAME}_BOFF_CNT equ SCCBase+$9c ; [W] Backoff Counter 333SCC{NAME}_TADDR_H equ SCCBase+$9e ; [W] Temporary Address 334SCC{NAME}_TADDR_M equ SCCBase+$9a ; [W] 335SCC{NAME}_TADDR_L equ SCCBase+$a0 ; [W] 336 endm 337 __defscc "1",RegBase+$0600,SCC1Base 338 __defscc "2",RegBase+$0620,SCC2Base 339 __defscc "3",RegBase+$0640,SCC3Base 340 __defscc "4",RegBase+$0660,SCC4Base 341 342;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 343; SMC: 344 345SMC1Base equ RAMBase+$0e80 346SMC2Base equ RAMBase+$0f80 347 348__defsmc macro NAME,Adr,SMCBase 349SMCMR{NAME} equ Adr+0 ; [W] Transparent Mode 350SMCE{NAME} equ Adr+4 ; [B] Event Register 351SMCM{NAME} equ Adr+8 ; [W] Mode 352SMC{NAME}_RBASE equ SMCBase+$00 ; [W] Receive Buffer Descriptor Address 353SMC{NAME}_TBASE equ SMCBase+$02 ; [W] Transmit Buffer Descriptor Address 354SMC{NAME}_RFCR equ SMCBase+$04 ; [B] Receive Function Code 355SMC{NAME}_TFCR equ SMCBase+$05 ; [B] Transmit Function Code 356SMC{NAME}_MRBLR equ SMCBase+$06 ; [W] Maximum Length Receive Buffer 357SMC{NAME}_RSTATE equ SMCBase+$08 ; [L] Internal Receiver Status 358SMC{NAME}_RBPTR equ SMCBase+$10 ; [W] Rx Buffer Descriptor pointer 359SMC{NAME}_TSTATE equ SMCBase+$18 ; [L] Internal Transmitter Status 360SMC{NAME}_TBPTR equ SMCBase+$20 ; [W] Tx Buffer Descriptor Pointer 361SMC{NAME}_MAX_IDL equ SMCBase+$28 ; [W] --UART-- Maximum Number Idle Characters 362SMC{NAME}_IDLC equ SMCBase+$28 ; [W] Idle Counter 363SMC{NAME}_BRKLN equ SMCBase+$28 ; [W] Length of last Break Character 364SMC{NAME}_BRKEC equ SMCBase+$28 ; [W] Receive Break Condition Counter 365SMC{NAME}_BRKCR equ SMCBase+$28 ; [W] Transmit Break Counter 366SMC{NAME}_R_mask equ SMCBase+$28 ; [W] Temporary Bit Mask 367SMC{NAME}_M_RxBD equ SMCBase+$00 ; [W] --GCI-- Monitor Channel Rx 368SMC{NAME}_M_TxBD equ SMCBase+$02 ; [W] Monitor Channel Tx 369SMC{NAME}_CI_RxBD equ SMCBase+$04 ; [W] C/I Channel Rx 370SMC{NAME}_CI_TxBD equ SMCBase+$06 ; [W] C/I Channel Tx 371SMC{NAME}_M_RxD equ SMCBase+$0c ; [W] Monitor Rx Data 372SMC{NAME}_M_TxD equ SMCBase+$0e ; [W] Monitor Tx Data 373SMC{NAME}_CI_RxD equ SMCBase+$10 ; [W] C/I Rx Data 374SMC{NAME}_CI_TxD equ SMCBase+$12 ; [W] C/I Tx Data 375 endm 376 __defsmc "1",RegBase+$0682,SMC1Base 377 __defsmc "2",RegBase+$0692,SMC2Base 378 379;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 380; SPI: 381 382SPIBase equ RAMBase+$0d80 383 384SPMODE equ RegBase+$06a0 ; [W] Mode Rregister 385SPIE equ RegBase+$06a6 ; [B] Event Register 386SPIM equ RegBase+$06aa ; [B] Mask Register 387SPICOM equ RegBase+$06ad ; [B] Command Register 388SPI_RBASE equ SPIBase+$00 ; [W] Receive Descriptor Address 389SPI_TBASE equ SPIBase+$02 ; [W] Transmit Descriptor Address 390SPI_RFCR equ SPIBase+$04 ; [B] Receive Function Code 391SPI_TFCR equ SPIBase+$05 ; [B] Transmit Function Code 392SPI_MRBLR equ SPIBase+$06 ; [W] Maximum Length Receive Buffer 393SPI_RSTATE equ SPIBase+$08 ; [L] Receiver Status 394SPI_RBPTR equ SPIBase+$10 ; [W] Currently Active Receive Descriptor 395SPI_TSTATE equ SPIBase+$18 ; [L] Trannsmitter Status 396SPI_TBPTR equ SPIBase+$20 ; [W] Currently Active Transmit Descriptor 397 398;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 399; PIP: 400 401PIPBase equ SMC2Base 402 403PIPC equ RegBase+$06b2 ; [W] Configuration Register 404PTPR equ RegBase+$06b6 ; [W] Timing Parameters 405PIPE equ SMCE2 ; [B] Event Register, overlayed!! 406PBDIR equ RegBase+$06b8 ; [L] Port B Data Direction Register 407PBPAR equ RegBase+$06bc ; [L] Port B Assignment 408PBODR equ RegBase+$06c2 ; [W] Port B Open Drain Control Bits 409PBDAT equ RegBase+$06c4 ; [L] Port B Data Register 410PIP_RBASE equ PIPBase+$00 ; [W] Receive Descriptor Address 411PIP_TBASE equ PIPBase+$02 ; [W] Transmit Descriptor Address 412PIP_CFCR equ PIPBase+$04 ; [B] Funktion Code 413PIP_SMASK equ PIPBase+$05 ; [B] Status Mask 414PIP_MRBLR equ PIPBase+$06 ; [W] Maximum Length of Receive Buffer 415PIP_RSTATE equ PIPBase+$08 ; [L] Receiver Status 416PIP_R_PTR equ PIPBase+$0c ; [L] Internal Receive Data Pointer 417PIP_RBPTR equ PIPBase+$10 ; [W] Current Receive Descriptor 418PIP_R_CNT equ PIPBase+$12 ; [W] Receive Byte Counter 419PIP_RTEMP equ PIPBase+$14 ; [L] Temporary Storage 420PIP_TSTATE equ PIPBase+$18 ; [L] Transmitter Status 421PIP_T_PTR equ PIPBase+$1c ; [L] Current Transmit Data Pointer 422PIP_TBPTR equ PIPBase+$20 ; [W] Current Transmit Data Descriptor 423PIP_T_CNT equ PIPBase+$22 ; [W] Transmit Byte Counter 424PIP_TTEMP equ PIPBase+$24 ; [L] Temporary Storage 425PIP_MAX_SL equ PIPBase+$28 ; [W] Maximuma Sleep Time 426PIP_SL_CNT equ PIPBase+$2a ; [W] Sleep Counter 427PIP_CHARACTER1 equ PIPBase+$2c ; [W] Control Characters 428PIP_CHARACTER2 equ PIPBase+$2e 429PIP_CHARACTER3 equ PIPBase+$30 430PIP_CHARACTER4 equ PIPBase+$32 431PIP_CHARACTER5 equ PIPBase+$34 432PIP_CHARACTER6 equ PIPBase+$36 433PIP_CHARACTER7 equ PIPBase+$38 434PIP_CHARACTER8 equ PIPBase+$3a 435PIP_RCCM equ PIPBase+$3c ; [W] Control Character Mask 436PIP_RCCR equ PIPBase+$3e ; [W] Control Character Register 437 438;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 439; SI: 440 441SIMODE equ RegBase+$06e0 ; [L] Serial Interface Mode 442SIGMR equ RegBase+$06e4 ; [B] Global Mode Setting 443SISTR equ RegBase+$06e6 ; [B] Address of Router RAM 444SICMR equ RegBase+$06e7 ; [B] Serial Interface Command Register 445SICR equ RegBase+$06ec ; [L] Serial Interface Clock Distribution 446SIRP equ RegBase+$06f2 ; [L] RAM Pointer 447SIRAM equ RegBase+$0700 ; [ ] Routing RAM 448 449;============================================================================= 450 451 case "68340" 452 453;----------------------------------------------------------------------------- 454; Comments may eventually be a bit less elaborate, since Motorola's Technical 455; Summary for the 68340 is not so detailed: 456 457SIMBAR equ $0003ff00 ; [L] Peripheral Address Setting 458 459MCR equ SIMBase+$000 ; [W] SIM Module Configuration 460 461SYNCR equ SIMBase+$004 ; [W] Clock Synthesizer Control 462AVR equ SIMBase+$006 ; [B] Auto Vectors 463RSR equ SIMBase+$007 ; [B] Reset Status 464 465PORTA equ SIMBase+$011 ; [B] Port A Data Register 466DDRA equ SIMBase+$013 ; [B] Port A Data Direction Register 467PPRA1 equ SIMBase+$015 ; [B] Port A Pin Assignment 468PPRA2 equ SIMBase+$017 ; [B] 469PORTB equ SIMBase+$019 ; [B] Port B Data Register 470PORTB1 equ SIMBase+$01b ; [B] ditto 471DDRB equ SIMBase+$01d ; [B] Port B Data Direction Register 472PPRARB equ SIMBase+$01f ; [B] Port B Pin Assignment 473SWIV equ SIMBase+$020 ; [B] Software Vectors 474SYPCR equ SIMBase+$021 ; [B] System Protection 475PICR equ SIMBase+$022 ; [W] PIT Control 476PITR equ SIMBase+$024 ; [W] PIT Data Register 477SWSR equ SIMBase+$027 ; [B] Software Service 478 479;----------------------------------------------------------------------------- 480; Chip Selects: 481 482__cnt set 0 483 rept 4 484__name set "\{__CNT}" 485CS{__name}AM1 set SIMBase+$040+__cnt*8 ; [W] CSn Address Mask 1 486CS{__name}AM2 set SIMBase+$042+__cnt*8 ; [W] CSn Address Mask 2 487CS{__name}BA1 set SIMBase+$044+__cnt*8 ; [W] CSn Base Address 1 488CS{__name}BA2 set SIMBase+$046+__cnt*8 ; [W] CSn Base Address 2 489__cnt set __cnt+1 490 endm 491 492;----------------------------------------------------------------------------- 493; DMA: 494 495DMABase equ SIMBase+$780 496DMAMCR1 equ DMABase+$000 ; [W] DMA Channel 1 Module Configuration 497DMAINTR1 equ DMABase+$004 ; [W] DMA Channel 1 Interrupts 498DMACCR1 equ DMABase+$008 ; [W] DMA Channel 1 Control Register 499DMACSR1 equ DMABase+$00a ; [B] DMA Channel 1 Status Register 500DMAFCR1 equ DMABase+$00b ; [B] DMA Channel 1 Function Code Register 501DMASAR1 equ DMABase+$00c ; [L] DMA Channel 1 Source Address 502DMADAR1 equ DMABase+$010 ; [L] DMA Channel 1 Destination Address 503DMABTC1 equ DMABase+$014 ; [L] DMA Channel 1 Byte Counter 504DMAMCR2 equ DMABase+$020 ; ditto for Channel 2 505DMAINTR2 equ DMABase+$024 506DMACCR2 equ DMABase+$028 507DMACSR2 equ DMABase+$02a 508DMAFCR2 equ DMABase+$02b 509DMASAR2 equ DMABase+$02c 510DMADAR2 equ DMABase+$030 511DMABTC2 equ DMABase+$034 512 513;----------------------------------------------------------------------------- 514; Serial Stuff 515 516SMBase equ SIMBase+$700 517SMMCR equ SMBase+$000 ; [W] SIM Module Configuration 518SMILR equ SMBase+$004 ; [B] Interrupt Level 519SMIVR equ SMBase+$005 ; [B] Interrupt Vector 520SMIPCR equ SMBase+$014 ; [BR] Pin Change Register 521SMACR equ SMBase+$014 ; [BW] Auxiliary Control register 522SMISR equ SMBase+$015 ; [BR] Interrupt Flags 523SMIER equ SMBase+$015 ; [BW] Interupt Enables 524SMOPCR equ SMBase+$01d ; [BW] Output Ports Control 525SMIP equ SMBase+$01d ; [BR] Input Ports Status 526SMOPS equ SMBase+$01e ; [BW] Individually Set Port Bits 527SMOPR equ SMBase+$01f ; [BW] Individually Clear Port Bits 528SMMR1A equ SMBase+$010 ; [B] Channel A Mode Register 529SMMR2A equ SMBase+$020 ; [B] Channel A Mode Register 530SMCSRA equ SMBase+$011 ; [BR] Channel A Clock Selection 531SMSRA equ SMBase+$011 ; [BW] Channel A Status Register 532SMCRA equ SMBase+$012 ; [BW] Channel A Command Register 533SMRBA equ SMBase+$013 ; [BR] Channel A Receive Data Register 534SMTBA equ SMBase+$013 ; [BW] Channel A Transmit Data Register 535SMMR1B equ SMBase+$018 ; [B] Channel B Mode Register 1 536SMMR2B equ SMBase+$021 ; [B] Channel B Mode Register 2 537SMCSRB equ SMBase+$019 ; [BR] Channel B Clock Selection 538SMSRB equ SMBase+$019 ; [BW] Channel B Status Register 539SMCRB equ SMBase+$01a ; [BW] Channel B Command Register 540SMRBB equ SMBase+$01b ; [BR] Channel B Receive Data Register 541SMTBB equ SMBase+$01b ; [BW] Channel B Transmit Data Register 542 543;----------------------------------------------------------------------------- 544; Timer: 545 546TMBase equ SIMBase+$600 547TM1MCR equ TMBase+$000 ; [W] Timer 1 Module Configuration 548TM1IR equ TMBase+$004 ; [W] Timer 1 Interrupt Configuration 549TM1CR equ TMBase+$006 ; [W] Timer 1 Control 550TM1SR equ TMBase+$008 ; [W] Timer 1 Status/Prescaler 551TM1CNTR equ TMBase+$00a ; [W] Timer 1 Count Register 552TM1PREL1 equ TMBase+$00c ; [W] Timer 1 Preset 1 553TM1PREL2 equ TMBase+$00e ; [W] Timer 1 Preset 2 554TM1COM equ TMBase+$010 ; [W] Timer 1 Compare Register 555TM2MCR equ TMBase+$040 ; ditto for Timer 2 556TM2IR equ TMBase+$044 557TM2CR equ TMBase+$046 558TM2SR equ TMBase+$048 559TM2CNTR equ TMBase+$04a 560TM2PREL1 equ TMBase+$04c 561TM2PREL2 equ TMBase+$04e 562TM2COM equ TMBase+$050 563 564;============================================================================= 565; 68332 Registers start here 566 567 case "68332" 568 569;----------------------------------------------------------------------------- 570; Fundamental SIM Control Registers 571 572SIMCR equ SIMBase+$00 ; [W] MCU Configuration 573SIYPCR equ SIMBase+$21 ; [W] Watchdog, Bus Monitor Control 574SWSR equ SIMBase+$27 ; [B] Watchdog Reset (write $55/$aa) 575PICR equ SIMBase+$22 ; [W] Timer Interrupt Control 576PITR equ SIMBase+$24 ; [W] Timer Counter Value 577 578;----------------------------------------------------------------------------- 579; Processor Clock Synthesizer 580 581SYNCR equ SIMBase+$04 ; [W] Clock Synthesizer Control 582 583;----------------------------------------------------------------------------- 584; Chip Select Outputs 585 586CSPAR0 equ SIMBase+$44 ; [W] CSBOOT,CS0..CS5 Control 587CSPAR1 equ SIMBase+$46 ; [W] CS6..CS10 Control 588CSBARBT equ SIMBase+$48 ; [W] Boot ROM Start Address 589CSORBT equ SIMBase+$4a ; [W] Boot-ROM Options 590__cnt set 0 591 rept 10 ; only generate 0..9 to avoid hex names 592__name set "\{__CNT}" 593CSBAR{__name} equ SIMBase+$4c+__cnt*4 ; [W] CSn Start Address 594CSOR{__name} equ SIMBase+$4e+__cnt*4 ; [W] CSn Options 595__cnt set __cnt+1 596 endm 597CSBAR10 equ SIMBase+$74 ; [W] CS10 Start Address 598CSOR10 equ SIMBase+$76 ; [W] CS10 Options 599 600;----------------------------------------------------------------------------- 601; Nutzung der SIM-Bits als einfache I/O-Ports 602 603PORTC equ SIMBase+$41 ; [B] Port C Data Bits 604PORTE0 equ SIMBase+$11 ; [B] Port E Data Bits 605PORTE1 equ SIMBase+$13 ; [B] ditto 606DDRE equ SIMBase+$15 ; [B] Port E Data Direction Bits 607PEPAR equ SIMBase+$17 ; [B] Port E Pins as Ports or Bus Signals Control 608PORTF0 equ SIMBase+$19 ; [B] Port F Data Bits 609PORTF1 equ SIMBase+$1b ; [B] ditto 610DDRF equ SIMBase+$1d ; [B] Port F Data Direction Bits 611PFPAR equ SIMBase+$1f ; [B] Port F Pins as Ports or Bus Signals Control 612 613;----------------------------------------------------------------------------- 614; Boundary Scan Test of SIM Registers (for Motorola use only...) 615 616SIMTR equ SIMBase+$02 ; [W] SIM Test Register 617SIMTRE equ SIMBase+$08 ; [W] E Clock Test Register 618TSTMSRA equ SIMBase+$30 ; [W] Shift Register A (Boundary Scan) 619TSTMSRB equ SIMBase+$32 ; [W] Shift Register B (Boundary Scan) 620TSTSC equ SIMBase+$34 ; [W] Shift Count Register 621TSTRC equ SIMBase+$36 ; [W] Repeat Count Register 622CREG equ SIMBase+$38 ; [W] Boundary Scan Control Register 623DREG equ SIMBase+$3a ; [W] Distributed Register (?!) 624 625;----------------------------------------------------------------------------- 626; Programmable Timers: 627 628TPUBase equ SIMBase+$400 ; TPU Register Set Base Address 629TPUMCR equ TPUBase+$00 ; [W] TPU Base Configuration 630TICR equ TPUBase+$08 ; [W] TPU Interrupt Control 631CIER equ TPUBase+$0a ; [W] TPU Interrupt Enable 632CISR equ TPUBase+$20 ; [W] TPU Interrupt Status 633CFSR0 equ TPUBase+$0c ; [W] TPU Operating Modes Channels 12..15 634CFSR1 equ TPUBase+$0e ; [W] TPU Operating Modes Channels 8..11 635CFSR2 equ TPUBase+$10 ; [W] TPU Operating Modes Channels 4.. 7 636CFSR3 equ TPUBase+$12 ; [W] TPU Operating Modes Channels 0.. 3 637HSQR0 equ TPUBase+$14 ; [W] TPU Sub Operating Modes Channels 8..15 638HSQR1 equ TPUBase+$16 ; [W] TPU Sub -Operating Modes Channels 0.. 7 639HSRR0 equ TPUBase+$18 ; [W] TPU Service Request Bits Channels 8..15 640HSRR1 equ TPUBase+$1a ; [W] TPU Service Request Bits Channels 0.. 7 641CPR0 equ TPUBase+$1c ; [W] TPU Priority Channels 8..15 642CPR1 equ TPUBase+$1e ; [W] TPU Priority Channels 0.. 7 643DSCR equ TPUBase+$04 ; [W] Debug and Test Registers 644DSSR equ TPUBase+$06 645LR equ TPUBase+$22 646SGLR equ TPUBase+$24 647DCNR equ TPUBase+$26 648TCR equ TPUBase+$02 649 650;----------------------------------------------------------------------------- 651; TPU Command RAM: 652 653TPURAMBase equ SIMBase+$100 ; TPURAM Base Address Control Register 654TRAMMCR equ TPURAMBase+$00 ; [B] TPURAM Base Configuration 655TRAMTST equ TPURAMBase+$02 ; [W] TPURAM Test Register 656TRAMBAR equ TPURAMBase+$04 ; [W] TPURAM Base Address 657 658;----------------------------------------------------------------------------- 659; serielles: 660 661QSMBase equ SIMBase+$200 ; Serial Interface Base Address 662QSMCR equ QSMBase+$00 ; [W] QSM Base Configuration 663QTEST equ QSMBase+$02 ; [W] QSM Test Register 664QILR equ QSMBase+$04 ; [B] QSM Interrupt Priorities 665QIVR equ QSMBase+$05 ; [B] QSM Interrupt Vector 666PORTQS equ QSMBase+$15 ; [B] QSM Parallel Port Data Bits 667PQSPAR equ QSMBase+$16 ; [B] Selection Port Bits QSM/Parallel Port 668DDRQS equ QSMBase+$17 ; [B] QSM Parallel Port Data Direction Register 669SPCR0 equ QSMBase+$18 ; [W] QSPI Control Register 0 670SPCR1 equ QSMBase+$1a ; [W] QSPI Control Register 1 671SPCR2 equ QSMBase+$1c ; [W] QSPI Control Register 2 672SPCR3 equ QSMBase+$1e ; [B] QSPI Control Register 3 673SPSR equ QSMBase+$1f ; [B] QSPI Status Register 674__cnt set 0 ; QSPI RAM Definition 675 rept 16 676__name set "\{__CNT}" 677RR{__name} equ QSMBase+$100+__cnt*2 ; [W] Data RAM Reception Side 678TR{__name} equ QSMBase+$120+__cnt*2 ; [W] Data RAM Transmission Side 679CR{__name} equ QSMBase+$140+__cnt ; [B] Command RAM 680__cnt set __cnt+1 681 endm 682SCCR0 equ QSMBase+$08 ; [W] SCI Control Register 0 683SCCR1 equ QSMBase+$0a ; [W] SCI Control Register 1 684SCSR equ QSMBase+$0c ; [W] SCI Status Register 685SCDR equ QSMBase+$0e ; [W] SCI Data Register 686 687;----------------------------------------------------------------------------- 688 689 endcase ; of processor distinction 690 691 restore ; re-allow listing 692 693 endif ; reg6833xinc 694