12020-07-23 Release Manager 2 3 * GCC 10.2.0 released. 4 52020-07-21 Uroš Bizjak <ubizjak@gmail.com> 6 7 * config/i386/i386.h (TARGET_AVOID_MFENCE): 8 Rename from TARGET_USE_XCHG_FOR_ATOMIC_STORE. 9 * config/i386/sync.md (atomic_store<mode>): Update for rename. 10 * config/i386/x86-tune.def (X86_TUNE_AVOID_MFENCE): 11 Rename from X86_TUNE_USE_XCHG_FOR_ATOMIC_STORE. 12 132020-07-17 Romain Naour <romain.naour@gmail.com> 14 15 Backported from master: 16 2020-06-03 Romain Naour <romain.naour@gmail.com> 17 18 * Makefile.in (SELFTEST_DEPS): Move before including language makefile 19 fragments. 20 212020-07-16 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> 22 23 Backported from master: 24 2020-06-16 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> 25 26 * config.in: Regenerate. 27 * config/s390/s390.c (print_operand): Emit vector alignment hints 28 for target z13, if AS accepts them. For other targets the logic 29 stays the same. 30 * config/s390/s390.h (TARGET_VECTOR_LOADSTORE_ALIGNMENT_HINTS): Define 31 macro. 32 * configure: Regenerate. 33 * configure.ac: Check HAVE_AS_VECTOR_LOADSTORE_ALIGNMENT_HINTS_ON_Z13. 34 352020-07-15 Richard Sandiford <richard.sandiford@arm.com> 36 37 PR target/95726 38 * config/aarch64/aarch64.c (aarch64_attribute_table): Add 39 "Advanced SIMD type". 40 * config/aarch64/aarch64-builtins.c: Include stringpool.h and 41 attribs.h. 42 (aarch64_init_simd_builtin_types): Add an "Advanced SIMD type" 43 attribute to each Advanced SIMD type. 44 * config/arm/arm.c (arm_attribute_table): Add "Advanced SIMD type". 45 * config/arm/arm-builtins.c: Include stringpool.h and attribs.h. 46 (arm_init_simd_builtin_types): Add an "Advanced SIMD type" 47 attribute to each Advanced SIMD type. 48 492020-07-15 Jakub Jelinek <jakub@redhat.com> 50 51 Backported from master: 52 2020-07-15 Jakub Jelinek <jakub@redhat.com> 53 54 PR target/96174 55 * config/i386/avx512fintrin.h (_mm512_cmpeq_pd_mask, 56 _mm512_mask_cmpeq_pd_mask, _mm512_cmplt_pd_mask, 57 _mm512_mask_cmplt_pd_mask, _mm512_cmple_pd_mask, 58 _mm512_mask_cmple_pd_mask, _mm512_cmpunord_pd_mask, 59 _mm512_mask_cmpunord_pd_mask, _mm512_cmpneq_pd_mask, 60 _mm512_mask_cmpneq_pd_mask, _mm512_cmpnlt_pd_mask, 61 _mm512_mask_cmpnlt_pd_mask, _mm512_cmpnle_pd_mask, 62 _mm512_mask_cmpnle_pd_mask, _mm512_cmpord_pd_mask, 63 _mm512_mask_cmpord_pd_mask, _mm512_cmpeq_ps_mask, 64 _mm512_mask_cmpeq_ps_mask, _mm512_cmplt_ps_mask, 65 _mm512_mask_cmplt_ps_mask, _mm512_cmple_ps_mask, 66 _mm512_mask_cmple_ps_mask, _mm512_cmpunord_ps_mask, 67 _mm512_mask_cmpunord_ps_mask, _mm512_cmpneq_ps_mask, 68 _mm512_mask_cmpneq_ps_mask, _mm512_cmpnlt_ps_mask, 69 _mm512_mask_cmpnlt_ps_mask, _mm512_cmpnle_ps_mask, 70 _mm512_mask_cmpnle_ps_mask, _mm512_cmpord_ps_mask, 71 _mm512_mask_cmpord_ps_mask): Move outside of __OPTIMIZE__ guarded 72 section. 73 742020-07-14 Matthias Klose <doko@ubuntu.com> 75 76 Backported from master: 77 2020-07-14 Matthias Klose <doko@ubuntu.com> 78 79 PR lto/95604 80 * lto-wrapper.c (merge_and_complain): Add decoded options as parameter, 81 error on different values for -fcf-protection. 82 (append_compiler_options): Pass -fcf-protection option. 83 (find_and_merge_options): Add decoded options as parameter, 84 pass decoded_options to merge_and_complain. 85 (run_gcc): Pass decoded options to find_and_merge_options. 86 * lto-opts.c (lto_write_options): Pass -fcf-protection option. 87 882020-07-14 Richard Sandiford <richard.sandiford@arm.com> 89 90 PR middle-end/95114 91 * tree.h (virtual_method_call_p): Add a default-false parameter 92 that indicates whether the function is being called from dump 93 routines. 94 (obj_type_ref_class): Likewise. 95 * tree.c (virtual_method_call_p): Likewise. 96 * ipa-devirt.c (obj_type_ref_class): Likewise. Lazily add ODR 97 type information for the type when the parameter is false. 98 * tree-pretty-print.c (dump_generic_node): Update calls to 99 virtual_method_call_p and obj_type_ref_class accordingly. 100 1012020-07-14 Richard Sandiford <richard.sandiford@arm.com> 102 103 PR tree-optimization/96146 104 * value-range.cc (value_range::set): Only decompose POLY_INT_CST 105 bounds to integers for VR_RANGE. Decay to VR_VARYING for anti-ranges 106 involving POLY_INT_CSTs. 107 1082020-07-14 Jakub Jelinek <jakub@redhat.com> 109 110 Backported from master: 111 2020-07-14 Jakub Jelinek <jakub@redhat.com> 112 113 PR middle-end/96194 114 * expr.c (expand_constructor): Don't create temporary for store to 115 volatile MEM if exp has an addressable type. 116 1172020-07-14 Matthias Klose <doko@ubuntu.com> 118 119 Backported from master: 120 2020-07-14 Matthias Klose <doko@ubuntu.com> 121 122 PR lto/95604 123 * lto-wrapper.c (merge_and_complain): Add decoded options as parameter, 124 error on different values for -fcf-protection. 125 (append_compiler_options): Pass -fcf-protection option. 126 (find_and_merge_options): Add decoded options as parameter, 127 pass decoded_options to merge_and_complain. 128 (run_gcc): Pass decoded options to find_and_merge_options. 129 * lto-opts.c (lto_write_options): Pass -fcf-protection option. 130 1312020-07-13 Szabolcs Nagy <szabolcs.nagy@arm.com> 132 133 Backported from master: 134 2020-07-13 Szabolcs Nagy <szabolcs.nagy@arm.com> 135 136 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add 137 __ARM_FEATURE_PAC_DEFAULT support. 138 1392020-07-13 Szabolcs Nagy <szabolcs.nagy@arm.com> 140 141 Backported from master: 142 2020-07-13 Szabolcs Nagy <szabolcs.nagy@arm.com> 143 144 PR target/94891 145 * doc/extend.texi: Update the text for __builtin_return_address. 146 1472020-07-13 Szabolcs Nagy <szabolcs.nagy@arm.com> 148 149 Backported from master: 150 2020-07-13 Szabolcs Nagy <szabolcs.nagy@arm.com> 151 152 PR target/94891 153 * config/aarch64/aarch64.c (aarch64_return_address_signing_enabled): 154 Disable return address signing if __builtin_eh_return is used. 155 1562020-07-13 Szabolcs Nagy <szabolcs.nagy@arm.com> 157 158 Backported from master: 159 2020-07-13 Szabolcs Nagy <szabolcs.nagy@arm.com> 160 161 PR target/94891 162 PR target/94791 163 * config/aarch64/aarch64-protos.h (aarch64_return_addr_rtx): Declare. 164 * config/aarch64/aarch64.c (aarch64_return_addr_rtx): New. 165 (aarch64_return_addr): Use aarch64_return_addr_rtx. 166 * config/aarch64/aarch64.h (PROFILE_HOOK): Likewise. 167 1682020-07-13 Szabolcs Nagy <szabolcs.nagy@arm.com> 169 170 Backported from master: 171 2020-07-09 Szabolcs Nagy <szabolcs.nagy@arm.com> 172 173 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add 174 __ARM_FEATURE_BTI_DEFAULT support. 175 1762020-07-13 Julian Brown <julian@codesourcery.com> 177 178 Backported from master: 179 2020-07-13 Julian Brown <julian@codesourcery.com> 180 Thomas Schwinge <thomas@codesourcery.com> 181 182 * gimplify.c (gimplify_scan_omp_clauses): Do not strip 183 GOMP_MAP_TO_PSET/GOMP_MAP_POINTER for OpenACC enter/exit data 184 directives (see also PR92929). 185 1862020-07-13 Jakub Jelinek <jakub@redhat.com> 187 188 Backported from master: 189 2020-07-13 Jakub Jelinek <jakub@redhat.com> 190 191 PR ipa/96130 192 * ipa-fnsummary.c (analyze_function_body): Treat NULL bb->aux 193 as false predicate. 194 1952020-07-13 Hans-Peter Nilsson <hp@axis.com> 196 197 Backported from master: 198 2020-07-13 Richard Biener <rguenther@suse.de> 199 200 PR middle-end/94600 201 * expr.c (expand_constructor): Make a temporary also if we're 202 storing to volatile memory. 203 2042020-07-12 Jakub Jelinek <jakub@redhat.com> 205 206 Backported from master: 207 2020-07-02 Jakub Jelinek <jakub@redhat.com> 208 209 PR tree-optimization/95857 210 * tree-cfg.c (group_case_labels_stmt): When removing an unreachable 211 base_bb, remember all forced and non-local labels on it and later 212 treat those as if they have NULL label_to_block. Formatting fix. 213 Fix a comment typo. 214 2152020-07-10 Bill Seurer <seurer@linux.vnet.ibm.com> 216 217 Backported from master: 218 2020-07-10 Bill Seurer <seurer@linux.vnet.ibm.com> 219 220 PR target/95581 221 * config/rs6000/rs6000-call.c: Add new type v16qi_ftype_pcvoid. 222 (altivec_init_builtins) Change __builtin_altivec_mask_for_load to use 223 v16qi_ftype_pcvoid with correct number of parameters. 224 2252020-07-10 Anton Youdkevitch <anton.youdkevitch@bell-sw.com> 226 227 * config/aarch64/aarch64.c (thunderx2t99_regmove_cost, 228 thunderx2t99_vector_cost): Likewise. 229 2302020-07-10 Peter Bergner <bergner@linux.ibm.com> 231 232 Backported from master: 233 2020-07-09 Peter Bergner <bergner@linux.ibm.com> 234 235 PR target/96125 236 * config/rs6000/rs6000-call.c (rs6000_init_builtins): Define the MMA 237 specific types __vector_quad and __vector_pair, and initialize the 238 MMA built-ins if TARGET_EXTRA_BUILTINS is set. 239 (mma_init_builtins): Don't test for mask set in rs6000_builtin_mask. 240 Remove now unneeded mask variable. 241 * config/rs6000/rs6000.c (rs6000_option_override_internal): Add the 242 OPTION_MASK_MMA flag for power10 if not already set. 243 2442020-07-10 Will Schmidt <will_schmidt@vnet.ibm.com> 245 246 Backported from master: 247 2020-07-08 Will Schmidt <will_schmidt@vnet.ibm.com> 248 249 * config/rs6000/altivec.h (vec_vmsumudm): New define. 250 * config/rs6000/altivec.md (UNSPEC_VMSUMUDM): New unspec. 251 (altivec_vmsumudm): New define_insn. 252 * config/rs6000/rs6000-builtin.def (altivec_vmsumudm): New BU_ALTIVEC_3 253 entry. (vmsumudm): New BU_ALTIVEC_OVERLOAD_3 entry. 254 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins): Add entries for 255 ALTIVEC_BUILTIN_VMSUMUDM variants of vec_msum. 256 * doc/extend.texi: Add document for vmsumudm behind vmsum. 257 2582020-07-10 Richard Biener <rguenther@suse.de> 259 260 Backported from master: 261 2020-07-10 Richard Biener <rguenther@suse.de> 262 263 PR tree-optimization/96133 264 * gimple-fold.c (fold_array_ctor_reference): Do not 265 recurse to folding a CTOR that does not fully cover the 266 asked for object. 267 2682020-07-10 Bin Cheng <bin.cheng@linux.alibaba.com> 269 270 Backported from master: 271 2020-07-09 Bin Cheng <bin.cheng@linux.alibaba.com> 272 273 PR tree-optimization/95804 274 * tree-loop-distribution.c (break_alias_scc_partitions): Force 275 negative post order to reduction partition. 276 2772020-07-10 Bin Cheng <bin.cheng@linux.alibaba.com> 278 279 Backported from master: 280 2020-06-20 Bin Cheng <bin.cheng@linux.alibaba.com> 281 282 PR tree-optimization/95638 283 * tree-loop-distribution.c (pg_edge_callback_data): New field. 284 (loop_distribution::break_alias_scc_partitions): Record and restore 285 postorder information. Fix memory leak. 286 2872020-07-09 Kito Cheng <kito.cheng@sifive.com> 288 289 Backported from master: 290 2020-07-09 Kito Cheng <kito.cheng@sifive.com> 291 292 * config/riscv/riscv-sr.c (riscv_remove_unneeded_save_restore_calls): 293 Abort if any arguments on stack. 294 2952020-07-09 Kito Cheng <kito.cheng@sifive.com> 296 297 Backported from master: 298 2020-06-22 Kito Cheng <kito.cheng@sifive.com> 299 300 * config/riscv/riscv-builtins.c (RISCV_FTYPE_NAME0): New. 301 (RISCV_FTYPE_ATYPES0): New. 302 (riscv_builtins): Using RISCV_USI_FTYPE for frflags. 303 * config/riscv/riscv-ftypes.def: Remove VOID argument. 304 3052020-07-09 Kito Cheng <kito.cheng@sifive.com> 306 307 Backported from master: 308 2020-06-16 Kito Cheng <kito.cheng@sifive.com> 309 310 PR target/95683 311 * config/riscv/riscv.c (riscv_gpr_save_operation_p): Remove 312 assertion and turn it into a early exit check. 313 3142020-07-09 Kito Cheng <kito.cheng@sifive.com> 315 316 Backported from master: 317 2020-06-15 Kito Cheng <kito.cheng@sifive.com> 318 319 * config/riscv/riscv.c (riscv_gen_gpr_save_insn): Change type to 320 unsigned for i. 321 (riscv_gpr_save_operation_p): Change type to unsigned for i and 322 len. 323 3242020-07-09 Kito Cheng <kito.cheng@sifive.com> 325 326 Backported from master: 327 2020-06-11 Kito Cheng <kito.cheng@sifive.com> 328 329 * config/riscv/riscv-protos.h (riscv_output_gpr_save): Remove. 330 * config/riscv/riscv-sr.c (riscv_sr_match_prologue): Update 331 value. 332 * config/riscv/riscv.c (riscv_output_gpr_save): Remove. 333 * config/riscv/riscv.md (gpr_save): Update output asm pattern. 334 3352020-07-09 Kito Cheng <kito.cheng@sifive.com> 336 337 Backported from master: 338 2020-06-11 Kito Cheng <kito.cheng@sifive.com> 339 340 * config/riscv/predicates.md (gpr_save_operation): New. 341 * config/riscv/riscv-protos.h (riscv_gen_gpr_save_insn): New. 342 (riscv_gpr_save_operation_p): Ditto. 343 * config/riscv/riscv-sr.c (riscv_remove_unneeded_save_restore_calls): 344 Ignore USEs for gpr_save patter. 345 * config/riscv/riscv.c (gpr_save_reg_order): New. 346 (riscv_expand_prologue): Use riscv_gen_gpr_save_insn to gen gpr_save. 347 (riscv_gen_gpr_save_insn): New. 348 (riscv_gpr_save_operation_p): Ditto. 349 * config/riscv/riscv.md (S3_REGNUM): New. 350 (S4_REGNUM): Ditto. 351 (S5_REGNUM): Ditto. 352 (S6_REGNUM): Ditto. 353 (S7_REGNUM): Ditto. 354 (S8_REGNUM): Ditto. 355 (S9_REGNUM): Ditto. 356 (S10_REGNUM): Ditto. 357 (S11_REGNUM): Ditto. 358 (gpr_save): Model USEs correctly. 359 3602020-07-09 Keith Packard <keithp@keithp.com> 361 362 Backported from master: 363 2020-05-12 Keith Packard <keithp@keithp.com> 364 365 * config/riscv/riscv.c (riscv_unique_section): New. 366 (TARGET_ASM_UNIQUE_SECTION): New. 367 3682020-07-08 Richard Sandiford <richard.sandiford@arm.com> 369 370 PR target/95105 371 * config/aarch64/aarch64-sve-builtins.cc 372 (handle_arm_sve_vector_bits_attribute): Create a copy of the 373 original type's TYPE_MAIN_VARIANT, then reapply all the differences 374 between the original type and its main variant. 375 3762020-07-07 Richard Biener <rguenther@suse.de> 377 378 Backported from master: 379 2020-07-06 Richard Biener <rguenther@suse.de> 380 381 PR tree-optimization/96075 382 * tree-vect-data-refs.c (vect_compute_data_ref_alignment): Use 383 TYPE_SIZE_UNIT of the vector component type instead of DR_STEP 384 for the misalignment calculation for negative step. 385 3862020-07-07 Richard Biener <rguenther@suse.de> 387 388 Backported from master: 389 2020-07-07 Richard Biener <rguenther@suse.de> 390 391 * lto-streamer-out.c (cmp_symbol_files): Use the computed 392 order map to sort symbols from the same sub-file together. 393 (lto_output): Compute a map of sub-file to an order number 394 it appears in the symbol output array. 395 3962020-07-06 Will Schmidt <will_schmidt@vnet.ibm.com> 397 398 * config/rs6000/altivec.h (vec_pack_to_short_fp32): Update. 399 * config/rs6000/altivec.md (UNSPEC_CONVERT_4F32_8F16): New unspec. 400 (convert_4f32_8f16): New define_expand 401 * config/rs6000/rs6000-builtin.def (convert_4f32_8f16): New builtin define 402 and overload. 403 * config/rs6000/rs6000-call.c (P9V_BUILTIN_VEC_CONVERT_4F32_8F16): New 404 overloaded builtin entry. 405 * config/rs6000/vsx.md (UNSPEC_VSX_XVCVSPHP): New unspec. 406 (vsx_xvcvsphp): New define_insn. 407 4082020-07-04 Martin Jambor <mjambor@suse.cz> 409 410 Backported from master: 411 2020-07-03 Martin Jambor <mjambor@suse.cz> 412 413 PR ipa/96040 414 * ipa-sra.c (all_callee_accesses_present_p): Do not accept type 415 mismatched accesses. 416 4172020-07-03 Martin Jambor <mjambor@suse.cz> 418 419 Backported from master: 420 2020-07-02 Martin Jambor <mjambor@suse.cz> 421 422 PR debug/95343 423 * ipa-param-manipulation.c (ipa_param_adjustments::modify_call): Adjust 424 argument index if necessary. 425 4262020-07-02 Segher Boessenkool <segher@kernel.crashing.org> 427 428 * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define 429 _ARCH_PWR10 when appropriate. 430 4312020-07-02 Peter Bergner <bergner@linux.ibm.com> 432 433 Backported from master: 434 2020-06-26 Peter Bergner <bergner@linux.ibm.com> 435 436 * config/rs6000/rs6000-call.c (cpu_is_info) <power10>: New. 437 * doc/extend.texi (PowerPC Built-in Functions): Document power10, 438 arch_3_1 and mma. 439 4402020-07-02 Michael Meissner <meissner@linux.ibm.com> 441 442 Backported from master: 443 2020-06-09 Michael Meissner <meissner@linux.ibm.com> 444 445 * config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER10): Allocate 446 'power10' PowerPC platform. 447 (PPC_FEATURE2_ARCH_3_1): New HWCAP2 bit for ARCH 3.1. 448 (PPC_FEATURE2_MMA): New HWCAP2 bit for MMA. 449 * config/rs6000/rs6000-call.c (cpu_supports_info): Add ARCH 3.1 and 450 MMA HWCAP2 bits. 451 4522020-07-01 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 453 454 Backported from master: 455 2020-06-22 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 456 457 * doc/sourcebuild.texi (arm_v8_1m_mve_fp_ok): Add item. 458 (arm_mve_hw): Likewise. 459 4602020-06-30 Segher Boessenkool <segher@kernel.crashing.org> 461 462 * config/rs6000/rs6000.md (isa): Rename "fut" to "p10". 463 4642020-06-30 Segher Boessenkool <segher@kernel.crashing.org> 465 466 * config/rs6000/driver-rs6000.c (asm_names): Use -mpwr10 for power10 467 on AIX, and -mpower10 elsewhere. 468 * config/rs6000/future.md: Delete. 469 * config/rs6000/linux64.h: Update comments. Use TARGET_POWER10, not 470 TARGET_FUTURE. 471 * config/rs6000/power10.md: New file. 472 * config/rs6000/rs6000-builtin.def: Update comments. 473 * config/rs6000/rs6000-call.c: Use P10_BUILTIN_*, not FUTURE_BUILTIN_*. 474 Update compiler messages. 475 * config/rs6000/rs6000-cpus.def: Update comments. Use ISA_3_1_*, not 476 ISA_FUTURE_*. Use OPTION_MASK_POWER10, not OPTION_MASK_FUTURE. 477 * config/rs6000/rs6000-opts.h: Use PROCESSOR_POWER10, not 478 PROCESSOR_FUTURE. 479 * config/rs6000/rs6000-string.c: Ditto. 480 * config/rs6000/rs6000-tables.opt (rs6000_cpu_opt_value): Use "power10" 481 instead of "future", reorder it to right after "power9". 482 * config/rs6000/rs6000.c: Update comments. Use OPTION_MASK_POWER10, 483 not OPTION_MASK_FUTURE. Use TARGET_POWER10, not TARGET_FUTURE. Use 484 RS6000_BTM_P10, not RS6000_BTM_FUTURE. Update compiler messages. 485 Use PROCESSOR_POWER10, not PROCESSOR_FUTURE. Use ISA_3_1_MASKS_SERVER, 486 not ISA_FUTURE_MASKS_SERVER. 487 (rs6000_opt_masks): Use "power10" instead of "future". 488 (rs6000_builtin_mask_names): Ditto. 489 (rs6000_disable_incompatible_switches): Ditto. 490 * config/rs6000/rs6000.h: Use -mpower10, not -mfuture. Use 491 -mcpu=power10, not -mcpu=future. Use MASK_POWER10, not MASK_FUTURE. 492 Use OPTION_MASK_POWER10, not OPTION_MASK_FUTURE. Use RS6000_BTM_P10, 493 not RS6000_BTM_FUTURE. 494 * config/rs6000/rs6000.md: Use "power10", not "future". Use 495 TARGET_POWER10, not TARGET_FUTURE. Include "power10.md", not 496 "future.md". 497 * config/rs6000/rs6000.opt (mfuture): Delete. 498 (mpower10): New. 499 * config/rs6000/t-rs6000: Use "power10.md", not "future.md". 500 * config/rs6000/vsx.md: Use TARGET_POWER10, not TARGET_FUTURE. 501 5022020-06-30 Alex Coplan <alex.coplan@arm.com> 503 504 Backported from master: 505 2020-05-18 Alex Coplan <alex.coplan@arm.com> 506 507 * config/arm/arm.c (output_move_double): Fix codegen when loading into 508 a register pair with an odd base register. 509 5102020-06-29 Jakub Jelinek <jakub@redhat.com> 511 512 Backported from master: 513 2020-06-24 Jakub Jelinek <jakub@redhat.com> 514 515 PR middle-end/95810 516 * fold-const.c (fold_cond_expr_with_comparison): Optimize 517 A <= 0 ? A : -A into (type)-absu(A) rather than -abs(A). 518 5192020-06-25 H.J. Lu <hjl.tools@gmail.com> 520 521 Backported from master: 522 2020-06-25 H.J. Lu <hjl.tools@gmail.com> 523 524 PR target/95874 525 * config/i386/i386.h (PTA_ICELAKE_CLIENT): Remove PTA_CLWB. 526 (PTA_ICELAKE_SERVER): Add PTA_CLWB. 527 (PTA_TIGERLAKE): Add PTA_CLWB. 528 5292020-06-24 Peter Bergner <bergner@linux.ibm.com> 530 531 Backported from master: 532 2020-06-21 Peter Bergner <bergner@linux.ibm.com> 533 534 * config/rs6000/predicates.md (mma_assemble_input_operand): New. 535 * config/rs6000/rs6000-builtin.def (BU_MMA_1, BU_MMA_V2, BU_MMA_3, 536 BU_MMA_5, BU_MMA_6, BU_VSX_1): Add support macros for defining MMA 537 built-in functions. 538 (ASSEMBLE_ACC, ASSEMBLE_PAIR, DISASSEMBLE_ACC, DISASSEMBLE_PAIR, 539 PMXVBF16GER2, PMXVBF16GER2NN, PMXVBF16GER2NP, PMXVBF16GER2PN, 540 PMXVBF16GER2PP, PMXVF16GER2, PMXVF16GER2NN, PMXVF16GER2NP, 541 PMXVF16GER2PN, PMXVF16GER2PP, PMXVF32GER, PMXVF32GERNN, 542 PMXVF32GERNP, PMXVF32GERPN, PMXVF32GERPP, PMXVF64GER, PMXVF64GERNN, 543 PMXVF64GERNP, PMXVF64GERPN, PMXVF64GERPP, PMXVI16GER2, PMXVI16GER2PP, 544 PMXVI16GER2S, PMXVI16GER2SPP, PMXVI4GER8, PMXVI4GER8PP, PMXVI8GER4, 545 PMXVI8GER4PP, PMXVI8GER4SPP, XVBF16GER2, XVBF16GER2NN, XVBF16GER2NP, 546 XVBF16GER2PN, XVBF16GER2PP, XVCVBF16SP, XVCVSPBF16, XVF16GER2, 547 XVF16GER2NN, XVF16GER2NP, XVF16GER2PN, XVF16GER2PP, XVF32GER, 548 XVF32GERNN, XVF32GERNP, XVF32GERPN, XVF32GERPP, XVF64GER, XVF64GERNN, 549 XVF64GERNP, XVF64GERPN, XVF64GERPP, XVI16GER2, XVI16GER2PP, XVI16GER2S, 550 XVI16GER2SPP, XVI4GER8, XVI4GER8PP, XVI8GER4, XVI8GER4PP, XVI8GER4SPP, 551 XXMFACC, XXMTACC, XXSETACCZ): Add MMA built-ins. 552 * config/rs6000/rs6000.c (rs6000_emit_move): Use CONST_INT_P. 553 Allow zero constants. 554 (print_operand) <case 'A'>: New output modifier. 555 (rs6000_split_multireg_move): Add support for inserting accumulator 556 priming and depriming instructions. Add support for splitting an 557 assemble accumulator pattern. 558 * config/rs6000/rs6000-call.c (mma_init_builtins, mma_expand_builtin, 559 rs6000_gimple_fold_mma_builtin): New functions. 560 (RS6000_BUILTIN_M): New macro. 561 (def_builtin): Handle RS6000_BTC_QUAD and RS6000_BTC_PAIR attributes. 562 (bdesc_mma): Add new MMA built-in support. 563 (htm_expand_builtin): Use RS6000_BTC_OPND_MASK. 564 (rs6000_invalid_builtin): Add handling of RS6000_BTM_FUTURE and 565 RS6000_BTM_MMA. 566 (rs6000_builtin_valid_without_lhs): Handle RS6000_BTC_VOID attribute. 567 (rs6000_gimple_fold_builtin): Call rs6000_builtin_is_supported_p 568 and rs6000_gimple_fold_mma_builtin. 569 (rs6000_expand_builtin): Call mma_expand_builtin. 570 Use RS6000_BTC_OPND_MASK. 571 (rs6000_init_builtins): Adjust comment. Call mma_init_builtins. 572 (htm_init_builtins): Use RS6000_BTC_OPND_MASK. 573 (builtin_function_type): Handle VSX_BUILTIN_XVCVSPBF16 and 574 VSX_BUILTIN_XVCVBF16SP. 575 * config/rs6000/rs6000.h (RS6000_BTC_QUINARY, RS6000_BTC_SENARY, 576 RS6000_BTC_OPND_MASK, RS6000_BTC_QUAD, RS6000_BTC_PAIR, 577 RS6000_BTC_QUADPAIR, RS6000_BTC_GIMPLE): New defines. 578 (RS6000_BTC_PREDICATE, RS6000_BTC_ABS, RS6000_BTC_DST, 579 RS6000_BTC_TYPE_MASK, RS6000_BTC_ATTR_MASK): Adjust values. 580 * config/rs6000/mma.md (MAX_MMA_OPERANDS): New define_constant. 581 (UNSPEC_MMA_ASSEMBLE_ACC, UNSPEC_MMA_PMXVBF16GER2, 582 UNSPEC_MMA_PMXVBF16GER2NN, UNSPEC_MMA_PMXVBF16GER2NP, 583 UNSPEC_MMA_PMXVBF16GER2PN, UNSPEC_MMA_PMXVBF16GER2PP, 584 UNSPEC_MMA_PMXVF16GER2, UNSPEC_MMA_PMXVF16GER2NN, 585 UNSPEC_MMA_PMXVF16GER2NP, UNSPEC_MMA_PMXVF16GER2PN, 586 UNSPEC_MMA_PMXVF16GER2PP, UNSPEC_MMA_PMXVF32GER, 587 UNSPEC_MMA_PMXVF32GERNN, UNSPEC_MMA_PMXVF32GERNP, 588 UNSPEC_MMA_PMXVF32GERPN, UNSPEC_MMA_PMXVF32GERPP, 589 UNSPEC_MMA_PMXVF64GER, UNSPEC_MMA_PMXVF64GERNN, 590 UNSPEC_MMA_PMXVF64GERNP, UNSPEC_MMA_PMXVF64GERPN, 591 UNSPEC_MMA_PMXVF64GERPP, UNSPEC_MMA_PMXVI16GER2, 592 UNSPEC_MMA_PMXVI16GER2PP, UNSPEC_MMA_PMXVI16GER2S, 593 UNSPEC_MMA_PMXVI16GER2SPP, UNSPEC_MMA_PMXVI4GER8, 594 UNSPEC_MMA_PMXVI4GER8PP, UNSPEC_MMA_PMXVI8GER4, 595 UNSPEC_MMA_PMXVI8GER4PP, UNSPEC_MMA_PMXVI8GER4SPP, 596 UNSPEC_MMA_XVBF16GER2, UNSPEC_MMA_XVBF16GER2NN, 597 UNSPEC_MMA_XVBF16GER2NP, UNSPEC_MMA_XVBF16GER2PN, 598 UNSPEC_MMA_XVBF16GER2PP, UNSPEC_MMA_XVF16GER2, UNSPEC_MMA_XVF16GER2NN, 599 UNSPEC_MMA_XVF16GER2NP, UNSPEC_MMA_XVF16GER2PN, UNSPEC_MMA_XVF16GER2PP, 600 UNSPEC_MMA_XVF32GER, UNSPEC_MMA_XVF32GERNN, UNSPEC_MMA_XVF32GERNP, 601 UNSPEC_MMA_XVF32GERPN, UNSPEC_MMA_XVF32GERPP, UNSPEC_MMA_XVF64GER, 602 UNSPEC_MMA_XVF64GERNN, UNSPEC_MMA_XVF64GERNP, UNSPEC_MMA_XVF64GERPN, 603 UNSPEC_MMA_XVF64GERPP, UNSPEC_MMA_XVI16GER2, UNSPEC_MMA_XVI16GER2PP, 604 UNSPEC_MMA_XVI16GER2S, UNSPEC_MMA_XVI16GER2SPP, UNSPEC_MMA_XVI4GER8, 605 UNSPEC_MMA_XVI4GER8PP, UNSPEC_MMA_XVI8GER4, UNSPEC_MMA_XVI8GER4PP, 606 UNSPEC_MMA_XVI8GER4SPP, UNSPEC_MMA_XXMFACC, UNSPEC_MMA_XXMTACC): New. 607 (MMA_ACC, MMA_VV, MMA_AVV, MMA_PV, MMA_APV, MMA_VVI4I4I8, 608 MMA_AVVI4I4I8, MMA_VVI4I4I2, MMA_AVVI4I4I2, MMA_VVI4I4, 609 MMA_AVVI4I4, MMA_PVI4I2, MMA_APVI4I2, MMA_VVI4I4I4, 610 MMA_AVVI4I4I4): New define_int_iterator. 611 (acc, vv, avv, pv, apv, vvi4i4i8, avvi4i4i8, vvi4i4i2, 612 avvi4i4i2, vvi4i4, avvi4i4, pvi4i2, apvi4i2, vvi4i4i4, 613 avvi4i4i4): New define_int_attr. 614 (*movpxi): Add zero constant alternative. 615 (mma_assemble_pair, mma_assemble_acc): New define_expand. 616 (*mma_assemble_acc): New define_insn_and_split. 617 (mma_<acc>, mma_xxsetaccz, mma_<vv>, mma_<avv>, mma_<pv>, mma_<apv>, 618 mma_<vvi4i4i8>, mma_<avvi4i4i8>, mma_<vvi4i4i2>, mma_<avvi4i4i2>, 619 mma_<vvi4i4>, mma_<avvi4i4>, mma_<pvi4i2>, mma_<apvi4i2>, 620 mma_<vvi4i4i4>, mma_<avvi4i4i4>): New define_insn. 621 * config/rs6000/rs6000.md (define_attr "type"): New type mma. 622 * config/rs6000/vsx.md (UNSPEC_VSX_XVCVBF16SP): New. 623 (UNSPEC_VSX_XVCVSPBF16): Likewise. 624 (XVCVBF16): New define_int_iterator. 625 (xvcvbf16): New define_int_attr. 626 (vsx_<xvcvbf16>): New define_insn. 627 * doc/extend.texi: Document the mma built-ins. 628 6292020-06-24 Kelvin Nilsen <wschmidt@linux.ibm.com> 630 631 * config/rs6000/predicates.md (u8bit_cint_operand): New predicate. 632 6332020-06-24 Peter Bergner <bergner@linux.ibm.com> 634 635 Backported from master: 636 2020-06-21 Peter Bergner <bergner@linux.ibm.com> 637 Michael Meissner <meissner@linux.ibm.com> 638 639 * config/rs6000/mma.md: New file. 640 * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define 641 __MMA__ for mma. 642 * config/rs6000/rs6000-call.c (rs6000_init_builtins): Add support 643 for __vector_pair and __vector_quad types. 644 * config/rs6000/rs6000-cpus.def (OTHER_FUTURE_MASKS): Add 645 OPTION_MASK_MMA. 646 (POWERPC_MASKS): Likewise. 647 * config/rs6000/rs6000-modes.def (OI, XI): New integer modes. 648 (POI, PXI): New partial integer modes. 649 * config/rs6000/rs6000.c (TARGET_INVALID_CONVERSION): Define. 650 (rs6000_hard_regno_nregs_internal): Use VECTOR_ALIGNMENT_P. 651 (rs6000_hard_regno_mode_ok_uncached): Likewise. 652 Add support for POImode being allowed in VSX registers and PXImode 653 being allowed in FP registers. 654 (rs6000_modes_tieable_p): Adjust comment. 655 Add support for POImode and PXImode. 656 (rs6000_debug_reg_global) <print_tieable_modes>: Add OImode, POImode 657 XImode, PXImode, V2SImode, V2SFmode and CCFPmode.. 658 (rs6000_setup_reg_addr_masks): Use VECTOR_ALIGNMENT_P. 659 Set up appropriate addr_masks for vector pair and vector quad addresses. 660 (rs6000_init_hard_regno_mode_ok): Add support for vector pair and 661 vector quad registers. Setup reload handlers for POImode and PXImode. 662 (rs6000_builtin_mask_calculate): Add support for RS6000_BTM_MMA. 663 (rs6000_option_override_internal): Error if -mmma is specified 664 without -mcpu=future. 665 (rs6000_slow_unaligned_access): Use VECTOR_ALIGNMENT_P. 666 (quad_address_p): Change size test to less than 16 bytes. 667 (reg_offset_addressing_ok_p): Add support for ISA 3.1 vector pair 668 and vector quad instructions. 669 (avoiding_indexed_address_p): Likewise. 670 (rs6000_emit_move): Disallow POImode and PXImode moves involving 671 constants. 672 (rs6000_preferred_reload_class): Prefer VSX registers for POImode 673 and FP registers for PXImode. 674 (rs6000_split_multireg_move): Support splitting POImode and PXImode 675 move instructions. 676 (rs6000_mangle_type): Adjust comment. Add support for mangling 677 __vector_pair and __vector_quad types. 678 (rs6000_opt_masks): Add entry for mma. 679 (rs6000_builtin_mask_names): Add RS6000_BTM_MMA and RS6000_BTM_FUTURE. 680 (rs6000_function_value): Use VECTOR_ALIGNMENT_P. 681 (address_to_insn_form): Likewise. 682 (reg_to_non_prefixed): Likewise. 683 (rs6000_invalid_conversion): New function. 684 * config/rs6000/rs6000.h (MASK_MMA): Define. 685 (BIGGEST_ALIGNMENT): Set to 512 if MMA support is enabled. 686 (VECTOR_ALIGNMENT_P): New helper macro. 687 (ALTIVEC_VECTOR_MODE): Use VECTOR_ALIGNMENT_P. 688 (RS6000_BTM_MMA): Define. 689 (RS6000_BTM_COMMON): Add RS6000_BTM_MMA and RS6000_BTM_FUTURE. 690 (rs6000_builtin_type_index): Add RS6000_BTI_vector_pair and 691 RS6000_BTI_vector_quad. 692 (vector_pair_type_node): New. 693 (vector_quad_type_node): New. 694 * config/rs6000/rs6000.md: Include mma.md. 695 (define_mode_iterator RELOAD): Add POI and PXI. 696 * config/rs6000/t-rs6000 (MD_INCLUDES): Add mma.md. 697 * config/rs6000/rs6000.opt (-mmma): New. 698 * doc/invoke.texi: Document -mmma. 699 7002020-06-24 Richard Biener <rguenther@suse.de> 701 702 Backported from master: 703 2020-06-17 Richard Biener <rguenther@suse.de> 704 705 PR tree-optimization/95717 706 * tree-vect-loop-manip.c (slpeel_tree_duplicate_loop_to_edge_cfg): 707 Move BB SSA updating before exit/latch PHI current def copying. 708 7092020-06-23 Richard Biener <rguenther@suse.de> 710 711 PR middle-end/95493 712 PR middle-end/95690 713 * cfgexpand.c (expand_debug_expr): Avoid calling 714 set_mem_attributes_minus_bitpos when we were expanding 715 an SSA name. 716 * emit-rtl.c (set_mem_attributes_minus_bitpos): Remove 717 ARRAY_REF special-casing, add CONSTRUCTOR to the set of 718 special-cases we do not want MEM_EXPRs for. Assert 719 we end up with reasonable MEM_EXPRs. 720 * varasm.c (build_constant_desc): Remove set_mem_attributes call. 721 7222020-06-23 Richard Biener <rguenther@suse.de> 723 724 PR tree-optimization/95487 725 * tree-vect-stmts.c (vectorizable_store): Use a truth type 726 for the scatter mask. 727 7282020-06-23 Richard Biener <rguenther@suse.de> 729 730 PR tree-optimization/95308 731 * tree-ssa-forwprop.c (pass_forwprop::execute): Generalize 732 test for TARGET_MEM_REFs. 733 7342020-06-23 Richard Biener <rguenther@suse.de> 735 736 PR tree-optimization/95133 737 * gimple-ssa-split-paths.c 738 (find_block_to_duplicate_for_splitting_paths): Check for 739 normal edges. 740 7412020-06-23 Richard Biener <rguenther@suse.de> 742 743 PR middle-end/95118 744 * real.c (real_to_decimal_for_mode): Make sure we handle 745 a zero with nonzero exponent. 746 7472020-06-23 Richard Biener <rguenther@suse.de> 748 749 PR tree-optimization/95049 750 * tree-ssa-sccvn.c (set_ssa_val_to): Reject lattice transition 751 between different constants. 752 7532020-06-23 Richard Biener <rguenther@suse.de> 754 755 PR middle-end/94964 756 * cfgloopmanip.c (create_preheader): Require non-complex 757 preheader edge for CP_SIMPLE_PREHEADERS. 758 7592020-06-20 Bin Cheng <bin.cheng@linux.alibaba.com> 760 761 PR tree-optimization/94969 762 * tree-data-ref.c (constant_access_functions): Rename to... 763 (invariant_access_functions): ...this. Add parameter. Check for 764 invariant access function, rather than constant. 765 (build_classic_dist_vector): Call above function. 766 * tree-loop-distribution.c (pg_add_dependence_edges): Add comment. 767 7682020-06-19 Jiufu Guo <guojiufu@linux.ibm.com> 769 770 PR target/95018 771 * common.opt (flag_cunroll_grow_size): New flag. 772 * toplev.c (process_options): Set flag_cunroll_grow_size. 773 * tree-ssa-loop-ivcanon.c (pass_complete_unroll::execute): 774 Use flag_cunroll_grow_size. 775 * config/rs6000/rs6000.c (rs6000_option_override_internal): 776 Override flag_cunroll_grow_size. 777 7782020-06-18 Aaron Sawdey <acsawdey@linux.ibm.com> 779 780 PR target/95347 781 * config/rs6000/rs6000.c (is_stfs_insn): Rename to 782 is_lfs_stfs_insn and make it recognize lfs as well. 783 (prefixed_store_p): Use is_lfs_stfs_insn(). 784 (prefixed_load_p): Use is_lfs_stfs_insn() to recognize lfs. 785 7862020-06-18 Aaron Sawdey <acsawdey@linux.ibm.com> 787 788 PR target/95347 789 * config/rs6000/rs6000.c (prefixed_store_p): Add special case 790 for stfs. 791 (is_stfs_insn): New helper function. 792 7932020-06-18 Jakub Jelinek <jakub@redhat.com> 794 795 Backported from master: 796 2020-06-18 Jakub Jelinek <jakub@redhat.com> 797 798 PR target/95713 799 * tree-ssa-forwprop.c (simplify_vector_constructor): Don't allow 800 scalar mode halfvectype other than vector boolean for 801 VEC_PACK_TRUNC_EXPR. 802 8032020-06-18 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 804 805 Backported from master: 806 2020-06-16 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 807 808 * config/arm/arm_mve.h (__arm_vaddq_m_n_s8): Correct the intrinsic 809 arguments. 810 (__arm_vaddq_m_n_s32): Likewise. 811 (__arm_vaddq_m_n_s16): Likewise. 812 (__arm_vaddq_m_n_u8): Likewise. 813 (__arm_vaddq_m_n_u32): Likewise. 814 (__arm_vaddq_m_n_u16): Likewise. 815 (__arm_vaddq_m): Modify polymorphic variant. 816 8172020-06-18 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 818 819 Backported from master: 820 2020-06-16 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 821 822 * config/arm/mve.md (mve_uqrshll_sat<supf>_di): Correct the predicate 823 and constraint of all the operands. 824 (mve_sqrshrl_sat<supf>_di): Likewise. 825 (mve_uqrshl_si): Likewise. 826 (mve_sqrshr_si): Likewise. 827 (mve_uqshll_di): Likewise. 828 (mve_urshrl_di): Likewise. 829 (mve_uqshl_si): Likewise. 830 (mve_urshr_si): Likewise. 831 (mve_sqshl_si): Likewise. 832 (mve_srshr_si): Likewise. 833 (mve_srshrl_di): Likewise. 834 (mve_sqshll_di): Likewise. 835 * config/arm/predicates.md (arm_low_register_operand): Define. 836 8372020-06-17 Thomas Schwinge <thomas@codesourcery.com> 838 839 Backported from master: 840 2020-06-17 Thomas Schwinge <thomas@codesourcery.com> 841 842 * hsa-gen.c (gen_hsa_insns_for_call): Move 'function_decl == 843 NULL_TREE' check earlier. 844 8452020-06-16 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 846 847 * config/arm/arm_mve.h (__arm_vbicq_n_u16): Correct the intrinsic 848 arguments. 849 (__arm_vbicq_n_s16): Likewise. 850 (__arm_vbicq_n_u32): Likewise. 851 (__arm_vbicq_n_s32): Likewise. 852 (__arm_vbicq): Modify polymorphic variant. 853 8542020-06-16 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 855 856 PR target/94735 857 * config/arm/predicates.md (mve_scatter_memory): Define to 858 match (mem (reg)) for scatter store memory. 859 * config/arm/mve.md (mve_vstrbq_scatter_offset_<supf><mode>): Modify 860 define_insn to define_expand. 861 (mve_vstrbq_scatter_offset_p_<supf><mode>): Likewise. 862 (mve_vstrhq_scatter_offset_<supf><mode>): Likewise. 863 (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>): Likewise. 864 (mve_vstrhq_scatter_shifted_offset_<supf><mode>): Likewise. 865 (mve_vstrdq_scatter_offset_p_<supf>v2di): Likewise. 866 (mve_vstrdq_scatter_offset_<supf>v2di): Likewise. 867 (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di): Likewise. 868 (mve_vstrdq_scatter_shifted_offset_<supf>v2di): Likewise. 869 (mve_vstrhq_scatter_offset_fv8hf): Likewise. 870 (mve_vstrhq_scatter_offset_p_fv8hf): Likewise. 871 (mve_vstrhq_scatter_shifted_offset_fv8hf): Likewise. 872 (mve_vstrhq_scatter_shifted_offset_p_fv8hf): Likewise. 873 (mve_vstrwq_scatter_offset_fv4sf): Likewise. 874 (mve_vstrwq_scatter_offset_p_fv4sf): Likewise. 875 (mve_vstrwq_scatter_offset_p_<supf>v4si): Likewise. 876 (mve_vstrwq_scatter_offset_<supf>v4si): Likewise. 877 (mve_vstrwq_scatter_shifted_offset_fv4sf): Likewise. 878 (mve_vstrwq_scatter_shifted_offset_p_fv4sf): Likewise. 879 (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si): Likewise. 880 (mve_vstrwq_scatter_shifted_offset_<supf>v4si): Likewise. 881 (mve_vstrbq_scatter_offset_<supf><mode>_insn): Define insn for scatter 882 stores. 883 (mve_vstrbq_scatter_offset_p_<supf><mode>_insn): Likewise. 884 (mve_vstrhq_scatter_offset_<supf><mode>_insn): Likewise. 885 (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn): Likewise. 886 (mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn): Likewise. 887 (mve_vstrdq_scatter_offset_p_<supf>v2di_insn): Likewise. 888 (mve_vstrdq_scatter_offset_<supf>v2di_insn): Likewise. 889 (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn): Likewise. 890 (mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn): Likewise. 891 (mve_vstrhq_scatter_offset_fv8hf_insn): Likewise. 892 (mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise. 893 (mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise. 894 (mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise. 895 (mve_vstrwq_scatter_offset_fv4sf_insn): Likewise. 896 (mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise. 897 (mve_vstrwq_scatter_offset_p_<supf>v4si_insn): Likewise. 898 (mve_vstrwq_scatter_offset_<supf>v4si_insn): Likewise. 899 (mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise. 900 (mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise. 901 (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn): Likewise. 902 (mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn): Likewise. 903 9042020-06-16 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 905 906 * config/arm/arm.c (mve_vector_mem_operand): Fix unwanted 907 fall-throughs. 908 9092020-06-16 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 910 Andre Vieira <andre.simoesdiasvieira@arm.com> 911 912 PR target/94959 913 * config/arm/arm-protos.h (arm_mode_base_reg_class): Function 914 declaration. 915 (mve_vector_mem_operand): Likewise. 916 * config/arm/arm.c (thumb2_legitimate_address_p): For MVE target check 917 the load from memory to a core register is legitimate for give mode. 918 (mve_vector_mem_operand): Define function. 919 (arm_print_operand): Modify comment. 920 (arm_mode_base_reg_class): Define. 921 * config/arm/arm.h (MODE_BASE_REG_CLASS): Modify to add check for 922 TARGET_HAVE_MVE and expand to arm_mode_base_reg_class on TRUE. 923 * config/arm/constraints.md (Ux): Likewise. 924 (Ul): Likewise. 925 * config/arm/mve.md (mve_mov): Replace constraint Us with Ux and also 926 add support for missing Vector Store Register and Vector Load Register. 927 Add a new alternative to support load from memory to PC (or label) in 928 vector store/load. 929 (mve_vstrbq_<supf><mode>): Modify constraint Us to Ux. 930 (mve_vldrbq_<supf><mode>): Modify constriant Us to Ux, predicate to 931 mve_memory_operand and also modify the MVE instructions to emit. 932 (mve_vldrbq_z_<supf><mode>): Modify constraint Us to Ux. 933 (mve_vldrhq_fv8hf): Modify constriant Us to Ux, predicate to 934 mve_memory_operand and also modify the MVE instructions to emit. 935 (mve_vldrhq_<supf><mode>): Modify constriant Us to Ux, predicate to 936 mve_memory_operand and also modify the MVE instructions to emit. 937 (mve_vldrhq_z_fv8hf): Likewise. 938 (mve_vldrhq_z_<supf><mode>): Likewise. 939 (mve_vldrwq_fv4sf): Likewise. 940 (mve_vldrwq_<supf>v4si): Likewise. 941 (mve_vldrwq_z_fv4sf): Likewise. 942 (mve_vldrwq_z_<supf>v4si): Likewise. 943 (mve_vld1q_f<mode>): Modify constriant Us to Ux. 944 (mve_vld1q_<supf><mode>): Likewise. 945 (mve_vstrhq_fv8hf): Modify constriant Us to Ux, predicate to 946 mve_memory_operand. 947 (mve_vstrhq_p_fv8hf): Modify constriant Us to Ux, predicate to 948 mve_memory_operand and also modify the MVE instructions to emit. 949 (mve_vstrhq_p_<supf><mode>): Likewise. 950 (mve_vstrhq_<supf><mode>): Modify constriant Us to Ux, predicate to 951 mve_memory_operand. 952 (mve_vstrwq_fv4sf): Modify constriant Us to Ux. 953 (mve_vstrwq_p_fv4sf): Modify constriant Us to Ux and also modify the MVE 954 instructions to emit. 955 (mve_vstrwq_p_<supf>v4si): Likewise. 956 (mve_vstrwq_<supf>v4si): Likewise.Modify constriant Us to Ux. 957 * config/arm/predicates.md (mve_memory_operand): Define. 958 9592020-06-15 Andrew Stubbs <ams@codesourcery.com> 960 961 * config/gcn/gcn-valu.md (v<expander><mode>3): Fix unsignedp. 962 9632020-06-15 Tobias Burnus <tobias@codesourcery.com> 964 965 * omp-offload.c (add_decls_addresses_to_decl_constructor, 966 omp_finish_file): With in_lto_p, stream out all offload-table 967 items even if the symtab_node does not exist. 968 9692020-06-15 Tobias Burnus <tobias@codesourcery.com> 970 971 PR lto/94848 972 PR middle-end/95551 973 * omp-offload.c (add_decls_addresses_to_decl_constructor, 974 omp_finish_file): Skip removed items. 975 * lto-cgraph.c (output_offload_tables): Likewise; set force_output 976 to this node for variables and functions. 977 9782020-06-14 Jakub Jelinek <jakub@redhat.com> 979 980 PR target/95528 981 * tree-ssa-forwprop.c (simplify_vector_constructor): Don't use 982 VEC_UNPACK*_EXPR or VEC_PACK_TRUNC_EXPR with scalar modes unless the 983 type is vector boolean. 984 9852020-06-14 Jakub Jelinek <jakub@redhat.com> 986 987 PR c++/95197 988 * gimplify.c (find_combined_omp_for): Move to omp-general.c. 989 * omp-general.h (find_combined_omp_for): Declare. 990 * omp-general.c: Include tree-iterator.h. 991 (find_combined_omp_for): New function, moved from gimplify.c. 992 9932020-06-14 Jakub Jelinek <jakub@redhat.com> 994 995 PR middle-end/95108 996 * omp-simd-clone.c (struct modify_stmt_info): Add after_stmt member. 997 (ipa_simd_modify_stmt_ops): For PHIs, only add before first stmt in 998 entry block if info->after_stmt is NULL, otherwise add after that stmt 999 and update it after adding each stmt. 1000 (ipa_simd_modify_function_body): Initialize info.after_stmt. 1001 10022020-06-14 Jakub Jelinek <jakub@redhat.com> 1003 1004 PR debug/95080 1005 * cfgrtl.c (purge_dead_edges): Skip over debug and note insns even 1006 if the last insn is a note. 1007 10082020-06-12 Martin Liska <mliska@suse.cz> 1009 Jakub Jelinek <jakub@redhat.com> 1010 1011 PR sanitizer/95634 1012 * asan.c (asan_emit_stack_protection): Fix emission for ilp32 1013 by using Pmode instead of ptr_mode. 1014 10152020-06-12 Martin Liska <mliska@suse.cz> 1016 1017 PR sanitizer/94910 1018 * asan.c (asan_emit_stack_protection): Emit 1019 also **SavedFlagPtr(FakeStack, class_id) = 0 in order to release 1020 a stack frame. 1021 10222020-06-08 Martin Jambor <mjambor@suse.cz> 1023 1024 PR ipa/95113 1025 * tree-ssa-dce.c (mark_stmt_if_obviously_necessary): Move non-call 1026 exceptions check to... 1027 * tree-eh.c (stmt_unremovable_because_of_non_call_eh_p): ...this 1028 new function. 1029 * tree-eh.h (stmt_unremovable_because_of_non_call_eh_p): Declare it. 1030 * ipa-sra.c (isra_track_scalar_value_uses): Use it. New parameter 1031 fun. 1032 10332020-06-05 Thomas Schwinge <thomas@codesourcery.com> 1034 Julian Brown <julian@codesourcery.com> 1035 1036 * gimplify.c (gimplify_adjust_omp_clauses): Remove 1037 'GOMP_MAP_STRUCT' mapping from OpenACC 'exit data' directives. 1038 10392020-06-05 H.J. Lu <hjl.tools@gmail.com> 1040 1041 * config/i386/driver-i386.c (host_detect_local_cpu): Support 1042 Intel Airmont, Tremont, Comet Lake, Ice Lake and Tiger Lake 1043 processor families. 1044 10452020-06-05 Lili Cui <lili.cui@intel.com> 1046 1047 PR target/95525 1048 * config/i386/i386.h (PTA_WAITPKG): Change bitmask value. 1049 10502020-06-02 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 1051 1052 * config/aarch64/aarch64-cores.def (zeus): Define. 1053 * config/aarch64/aarch64-tune.md: Regenerate. 1054 * doc/invoke.texi (AArch64 Options): Document zeus -mcpu option. 1055 10562020-06-02 Iain Buclaw <ibuclaw@gdcproject.org> 1057 1058 PR target/95420 1059 * config.gcc (arm-wrs-vxworks7*): Set default cpu to generic-armv7-a. 1060 10612020-05-29 Alex Coplan <alex.coplan@arm.com> 1062 1063 PR target/94591 1064 * config/aarch64/aarch64.c (aarch64_evpc_rev_local): Don't match 1065 identity permutation. 1066 10672020-05-29 Andrew Stubbs <ams@codesourcery.com> 1068 1069 * config/gcn/gcn-valu.md (add<mode>3_zext_dup): Change to a 1070 define_expand, and rename the original to ... 1071 (add<mode>3_vcc_zext_dup): ... this, and add a custom VCC operand. 1072 (add<mode>3_zext_dup_exec): Likewise, with ... 1073 (add<mode>3_vcc_zext_dup_exec): ... this. 1074 (add<mode>3_zext_dup2): Likewise, with ... 1075 (add<mode>3_zext_dup_exec): ... this. 1076 (add<mode>3_zext_dup2_exec): Likewise, with ... 1077 (add<mode>3_zext_dup2): ... this. 1078 * config/gcn/gcn.c (gcn_expand_scalar_to_vector_address): Switch 1079 addv64di3_zext* calls to use addv64di3_vcc_zext*. 1080 10812020-05-29 Dong JianQiang <dongjianqiang2@huawei.com> 1082 1083 PR gcov-profile/95332 1084 * gcov-io.c (gcov_var::endian): Move field. 1085 (from_file): Add IN_GCOV_TOOL check. 1086 * gcov-io.h (gcov_magic): Ditto. 1087 10882020-05-28 Richard Sandiford <richard.sandiford@arm.com> 1089 1090 PR testsuite/95361 1091 * config/aarch64/aarch64.c (aarch64_expand_epilogue): Only 1092 redefine the CFA if we have CFI operations. 1093 10942020-05-28 Uroš Bizjak <ubizjak@gmail.com> 1095 1096 * config/i386/mmx.md (mmx_haddsubv2sf3): Correct 1097 RTL template to model horizontal subtraction and addition. 1098 10992020-05-28 Uroš Bizjak <ubizjak@gmail.com> 1100 1101 PR target/95355 1102 * config/i386/sse.md 1103 (<mask_codefor>avx512f_<code>v16qiv16si2<mask_name>): 1104 Remove %q operand modifier from insn template. 1105 (avx512f_<code>v8hiv8di2<mask_name>): Ditto. 1106 11072020-05-28 Martin Liska <mliska@suse.cz> 1108 1109 PR web/95380 1110 * doc/invoke.texi: Add missing params, remove max-once-peeled-insns and 1111 rename ipcp-unit-growth to ipa-cp-unit-growth. 1112 11132020-05-24 Uroš Bizjak <ubizjak@gmail.com> 1114 1115 PR target/95255 1116 * config/i386/i386.md (<rounding_insn><mode>2): Do not try to 1117 expand non-sse4 ROUND_ROUNDEVEN rounding via SSE support routines. 1118 11192020-05-24 Iain Sandoe <iain@sandoe.co.uk> 1120 1121 Backported from master. 1122 2020-05-22 Iain Sandoe <iain@sandoe.co.uk> 1123 1124 * config/darwin.h (ASM_GENERATE_INTERNAL_LABEL): 1125 Make ubsan_{data,type},ASAN linker-visible. 1126 11272020-05-24 H.J. Lu <hongjiu.lu@intel.com> 1128 1129 PR target/95258 1130 * config/i386/driver-i386.c (host_detect_local_cpu): Detect 1131 AVX512VPOPCNTDQ. 1132 11332020-05-22 Richard Biener <rguenther@suse.de> 1134 1135 PR lto/95190 1136 * doc/invoke.texi (flto): Document behavior of diagnostic 1137 options. 1138 11392020-05-21 Uroš Bizjak <ubizjak@gmail.com> 1140 1141 PR target/95169 1142 * config/i386/i386-expand.c (ix86_expand_int_movcc): 1143 Avoid reversing a non-trapping comparison to a trapping one. 1144 11452020-05-21 Martin Liska <mliska@suse.cz> 1146 1147 * common/config/aarch64/aarch64-common.c (aarch64_handle_option): 1148 Handle OPT_moutline_atomics. 1149 * config/aarch64/aarch64.c: Add outline-atomics to 1150 aarch64_attributes. 1151 * doc/extend.texi: Document the newly added target attribute. 1152 11532020-05-21 H.J. Lu <hongjiu.lu@intel.com> 1154 1155 Backport from master 1156 2020-05-21 H.J. Lu <hongjiu.lu@intel.com> 1157 1158 PR target/95212 1159 * config/i386/i386-builtins.c (processor_features): Move 1160 F_AVX512VP2INTERSECT after F_AVX512BF16. 1161 (isa_names_table): Likewise. 1162 11632020-05-19 Gerald Pfeifer <gerald@pfeifer.com> 1164 1165 Backport from mainline 1166 2020-05-10 Gerald Pfeifer <gerald@pfeifer.com> 1167 1168 * config/i386/i386-c.c (ix86_target_macros): Define _ILP32 and 1169 __ILP32__ for 32-bit targets. 1170 11712020-05-19 Tobias Burnus <tobias@codesourcery.com> 1172 1173 Backport from mainline 1174 2020-05-15 Tobias Burnus <tobias@codesourcery.com> 1175 1176 PR middle-end/94635 1177 * gimplify.c (gimplify_scan_omp_clauses): For MAP_TO_PSET with 1178 OMP_TARGET_EXIT_DATA, use 'release:' unless the associated 1179 item is 'delete:'. 1180 11812020-05-18 Martin Sebor <msebor@redhat.com> 1182 1183 PR middle-end/94940 1184 * tree-vrp.c (vrp_prop::check_mem_ref): Remove unreachable code. 1185 * tree.c (component_ref_size): Correct the handling or array members 1186 of unions. 1187 Drop a pointless test. 1188 Rename a local variable. 1189 11902020-05-12 Richard Biener <rguenther@suse.de> 1191 1192 Backport from mainline 1193 2020-05-07 Richard Biener <rguenther@suse.de> 1194 1195 PR ipa/94947 1196 * tree-ssa-structalias.c (refered_from_nonlocal_fn): Use 1197 DECL_EXTERNAL || TREE_PUBLIC instead of externally_visible. 1198 (refered_from_nonlocal_var): Likewise. 1199 (ipa_pta_execute): Likewise. 1200 1201 2020-05-05 Richard Biener <rguenther@suse.de> 1202 1203 PR ipa/94947 1204 * tree-ssa-structalias.c (ipa_pta_execute): Use 1205 varpool_node::externally_visible_p (). 1206 (refered_from_nonlocal_var): Likewise. 1207 12082020-05-12 David Edelsohn <dje.gcc@gmail.com> 1209 1210 Backport from mainline 1211 2020-05-04 Clement Chigot <clement.chigot@atos.net> 1212 David Edelsohn <dje.gcc@gmail.com> 1213 1214 * config/rs6000/rs6000-call.c (rs6000_init_builtins): Override explicit 1215 for fmodl, frexpl, ldexpl and modfl builtins. 1216 12172020-05-11 Sebastian Huber <sebastian.huber@embedded-brains.de> 1218 1219 Backport from mainline 1220 2020-05-05 Sebastian Huber <sebastian.huber@embedded-brains.de> 1221 1222 * config/rtems.h (RTEMS_STARTFILE_SPEC): Define if undefined. 1223 (RTEMS_ENDFILE_SPEC): Likewise. 1224 (STARTFILE_SPEC): Update comment. Add RTEMS_STARTFILE_SPEC. 1225 (ENDFILE_SPEC): Add RTEMS_ENDFILE_SPEC. 1226 (LIB_SPECS): Support -nodefaultlibs option. 1227 * config/or1k/rtems.h (RTEMS_STARTFILE_SPEC): Define. 1228 (RTEMS_ENDFILE_SPEC): Likewise. 1229 * config/rs6000/rtems.h (RTEMS_STARTFILE_SPEC): Likewise. 1230 (RTEMS_ENDFILE_SPEC): Likewise. 1231 * config/v850/rtems.h (RTEMS_STARTFILE_SPEC): Likewise. 1232 (RTEMS_ENDFILE_SPEC): Likewise. 1233 12342020-05-11 Martin Liska <mliska@suse.cz> 1235 1236 Backport from mainline 1237 2020-05-11 Martin Liska <mliska@suse.cz> 1238 1239 PR c/95040 1240 * common.opt: Fix typo in option description. 1241 12422020-05-08 Jakub Jelinek <jakub@redhat.com> 1243 1244 PR middle-end/94724 1245 * tree.c (get_narrower): Reuse the op temporary instead of 1246 shadowing it. 1247 12482020-05-07 Uroš Bizjak <ubizjak@gmail.com> 1249 1250 * config/alpha/alpha.c (alpha_atomic_assign_expand_fenv): Use 1251 TARGET_EXPR instead of MODIFY_EXPR for the first assignments to 1252 fenv_var and new_fenv_var. 1253 12542020-05-07 Martin Liska <mliska@suse.cz> 1255 1256 Backport from mainline 1257 2020-05-07 Martin Liska <mliska@suse.cz> 1258 1259 * doc/invoke.texi: Fix 2 optindex entries. 1260 12612020-05-07 Jakub Jelinek <jakub@redhat.com> 1262 1263 Backported from mainline 1264 2020-05-06 Jakub Jelinek <jakub@redhat.com> 1265 1266 PR target/94950 1267 * config/riscv/riscv-builtins.c (riscv_atomic_assign_expand_fenv): Use 1268 TARGET_EXPR instead of MODIFY_EXPR for first assignment to old_flags. 1269 1270 PR rtl-optimization/94873 1271 * combine.c (combine_instructions): Don't optimize using REG_EQUAL 1272 note if SET_SRC (set) has side-effects. 1273 1274 2020-05-05 Jakub Jelinek <jakub@redhat.com> 1275 1276 PR target/94942 1277 * config/i386/mmx.md (*vec_dupv4hi): Use xYw constraints instead of Yv. 1278 1279 2020-05-04 Jakub Jelinek <jakub@redhat.com> 1280 1281 * opts.c (get_option_html_page): Instead of hardcoding a list of 1282 options common between C/C++ and Fortran only use gfortran/ 1283 documentation for warnings that have CL_Fortran set but not 1284 CL_C or CL_CXX. 1285 12862020-05-07 Jakub Jelinek <jakub@redhat.com> 1287 1288 * BASE-VER: Set to 10.1.1. 1289 12902020-05-07 Release Manager 1291 1292 * GCC 10.1.0 released. 1293 12942020-05-06 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> 1295 1296 * doc/install.texi: Replace Sun with Solaris as appropriate. 1297 (Tools/packages necessary for building GCC, Perl version between 1298 5.6.1 and 5.6.24): Remove Solaris 8 reference. 1299 (Installing GCC: Binaries, Solaris 2 (SPARC, Intel)): Remove 1300 TGCware reference. 1301 (Specific, i?86-*-solaris2*): Update version references for 1302 Solaris 11.3 and later. Remove gas 2.26 caveat. 1303 (Specific, *-*-solaris2*): Update version references for 1304 Solaris 11.3 and later. Remove boehm-gc reference. 1305 Document GMP, MPFR caveats on Solaris 11.3. 1306 (Specific, sparc-sun-solaris2*): Update Solaris 9 references. 1307 (Specific, sparc64-*-solaris2*): Likewise. 1308 Document --build requirement. 1309 13102020-05-05 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> 1311 1312 * configure.ac <i[34567]86-*-*>: Add --32 to tls_as_opt on Solaris. 1313 * configure: Regenerate. 1314 13152020-05-04 Richard Sandiford <richard.sandiford@arm.com> 1316 1317 PR middle-end/94941 1318 * internal-fn.c (expand_load_lanes_optab_fn): Emit a move if the 1319 chosen lhs is different from the gcall lhs. 1320 (expand_mask_load_optab_fn): Likewise. 1321 (expand_gather_load_optab_fn): Likewise. 1322 13232020-05-04 Marek Polacek <polacek@redhat.com> 1324 1325 Revert: 1326 2020-04-30 Marek Polacek <polacek@redhat.com> 1327 1328 PR c++/94775 1329 * tree.c (check_base_type): Return true only if TYPE_USER_ALIGN match. 1330 (check_aligned_type): Check if TYPE_USER_ALIGN match. 1331 13322020-05-02 Jakub Jelinek <jakub@redhat.com> 1333 1334 * config/tilegx/tilegx.md 1335 (insn_stnt<I124MODE:n>_add<I48MODE:bitsuffix>): Use <I124MODE:n> 1336 rather than just <n>. 1337 13382020-04-30 Alexandre Oliva <oliva@adacore.com> 1339 1340 * doc/sourcebuild.texi (Effective-Target Keywords): Document 1341 the newly-introduced fileio effective target. 1342 13432020-04-30 Richard Sandiford <richard.sandiford@arm.com> 1344 1345 PR rtl-optimization/94740 1346 * cse.c (cse_process_notes_1): Replace with... 1347 (cse_process_note_1): ...this new function, acting as a 1348 simplify_replace_fn_rtx callback to process_note. Handle only 1349 REGs and MEMs directly. Validate the MEM if cse_process_note 1350 changes its address. 1351 (cse_process_notes): Replace with... 1352 (cse_process_note): ...this new function. 1353 (cse_extended_basic_block): Update accordingly, iterating over 1354 the register notes and passing individual notes to cse_process_note. 1355 13562020-04-30 Martin Jambor <mjambor@suse.cz> 1357 1358 PR ipa/94856 1359 * cgraph.c (clone_of_p): Also consider thunks whih had their bodies 1360 saved by the inliner and thunks which had their call inlined. 1361 * ipa-inline-transform.c (save_inline_function_body): Fill in 1362 former_clone_of of new body holders. 1363 13642020-04-30 Jakub Jelinek <jakub@redhat.com> 1365 1366 * DEV-PHASE: Set to prerelease. 1367 13682020-04-30 Jonathan Wakely <jwakely@redhat.com> 1369 1370 * pretty-print.c (pp_take_prefix): Fix spelling in comment. 1371 13722020-04-30 Marek Polacek <polacek@redhat.com> 1373 1374 PR c++/94775 1375 * tree.c (check_base_type): Return true only if TYPE_USER_ALIGN match. 1376 (check_aligned_type): Check if TYPE_USER_ALIGN match. 1377 13782020-04-30 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 1379 1380 * config/aarch64/aarch64.h (TARGET_OUTLINE_ATOMICS): Define. 1381 * config/aarch64/aarch64.opt (moutline-atomics): Change to Int variable. 1382 * doc/invoke.texi (moutline-atomics): Document as on by default. 1383 13842020-04-30 Szabolcs Nagy <szabolcs.nagy@arm.com> 1385 1386 PR target/94748 1387 * config/aarch64/aarch64-bti-insert.c (rest_of_insert_bti): Remove 1388 the check for NOTE_INSN_DELETED_LABEL. 1389 13902020-04-30 Jakub Jelinek <jakub@redhat.com> 1391 1392 * configure.ac (--with-documentation-root-url, 1393 --with-changes-root-url): Diagnose URL not ending with /, 1394 use AC_DEFINE_UNQUOTED instead of AC_SUBST. 1395 * opts.h (get_changes_url): Remove. 1396 * opts.c (get_changes_url): Remove. 1397 * Makefile.in (CFLAGS-opts.o): Don't add -DDOCUMENTATION_ROOT_URL 1398 or -DCHANGES_ROOT_URL. 1399 * doc/install.texi (--with-documentation-root-url, 1400 --with-changes-root-url): Document. 1401 * config/arm/arm.c (aapcs_vfp_is_call_or_return_candidate): Don't call 1402 get_changes_url and free, change url variable type to const char * and 1403 set it to CHANGES_ROOT_URL "gcc-10/changes.html#empty_base". 1404 * config/s390/s390.c (s390_function_arg_vector, 1405 s390_function_arg_float): Likewise. 1406 * config/aarch64/aarch64.c (aarch64_vfp_is_call_or_return_candidate): 1407 Likewise. 1408 * config/rs6000/rs6000-call.c (rs6000_discover_homogeneous_aggregate): 1409 Likewise. 1410 * config.in: Regenerate. 1411 * configure: Regenerate. 1412 14132020-04-30 Christophe Lyon <christophe.lyon@linaro.org> 1414 1415 PR target/57002 1416 * config/arm/arm.c (isr_attribute_args): Remove duplicate entries. 1417 14182020-04-30 Andreas Krebbel <krebbel@linux.ibm.com> 1419 1420 * config/s390/constraints.md ("j>f", "jb4"): New constraints. 1421 * config/s390/vecintrin.h (vec_load_len_r, vec_store_len_r): Fix 1422 macro definitions. 1423 * config/s390/vx-builtins.md ("vlrlrv16qi", "vstrlrv16qi"): Add a 1424 separate expander. 1425 ("*vlrlrv16qi", "*vstrlrv16qi"): Add alternative for vl/vst. 1426 Change constraint for vlrl/vstrl to jb4. 1427 14282020-04-30 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> 1429 1430 * var-tracking.c (vt_initialize): Move variables pre and post 1431 into inner block and initialize both in order to fix warning 1432 about uninitialized use. Remove unnecessary checks for 1433 frame_pointer_needed. 1434 14352020-04-30 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> 1436 1437 * toplev.c (output_stack_usage_1): Ensure that first 1438 argument to fprintf is not null. 1439 14402020-04-29 Jakub Jelinek <jakub@redhat.com> 1441 1442 * configure.ac (-with-changes-root-url): New configure option, 1443 defaulting to https://gcc.gnu.org/. 1444 * Makefile.in (CFLAGS-opts.o): Define CHANGES_ROOT_URL for 1445 opts.c. 1446 * pretty-print.c (get_end_url_string): New function. 1447 (pp_format): Handle %{ and %} for URLs. 1448 (pp_begin_url): Use pp_string instead of pp_printf. 1449 (pp_end_url): Use get_end_url_string. 1450 * opts.h (get_changes_url): Declare. 1451 * opts.c (get_changes_url): New function. 1452 * config/rs6000/rs6000-call.c: Include opts.h. 1453 (rs6000_discover_homogeneous_aggregate): Use %{in GCC 10.1%} instead 1454 of just in GCC 10.1 in diagnostics and add URL. 1455 * config/arm/arm.c (aapcs_vfp_is_call_or_return_candidate): Likewise. 1456 * config/aarch64/aarch64.c (aarch64_vfp_is_call_or_return_candidate): 1457 Likewise. 1458 * config/s390/s390.c (s390_function_arg_vector, 1459 s390_function_arg_float): Likewise. 1460 * configure: Regenerated. 1461 1462 PR target/94704 1463 * config/s390/s390.c (s390_function_arg_vector, 1464 s390_function_arg_float): Use DECL_FIELD_ABI_IGNORED instead of 1465 cxx17_empty_base_field_p. In -Wpsabi diagnostics use the type 1466 passed to the function rather than the type of the single element. 1467 Rename cxx17_empty_base_seen variable to empty_base_seen, change 1468 type to int, and adjust diagnostics depending on if the field 1469 has [[no_unique_attribute]] or not. 1470 1471 PR target/94832 1472 * config/i386/avx512bwintrin.h (_mm512_alignr_epi8, 1473 _mm512_mask_alignr_epi8, _mm512_maskz_alignr_epi8): Wrap macro operands 1474 used in casts into parens. 1475 * config/i386/avx512fintrin.h (_mm512_cvt_roundps_ph, _mm512_cvtps_ph, 1476 _mm512_mask_cvt_roundps_ph, _mm512_mask_cvtps_ph, 1477 _mm512_maskz_cvt_roundps_ph, _mm512_maskz_cvtps_ph, 1478 _mm512_mask_cmp_epi64_mask, _mm512_mask_cmp_epi32_mask, 1479 _mm512_mask_cmp_epu64_mask, _mm512_mask_cmp_epu32_mask, 1480 _mm512_mask_cmp_round_pd_mask, _mm512_mask_cmp_round_ps_mask, 1481 _mm512_mask_cmp_pd_mask, _mm512_mask_cmp_ps_mask): Likewise. 1482 * config/i386/avx512vlbwintrin.h (_mm256_mask_alignr_epi8, 1483 _mm256_maskz_alignr_epi8, _mm_mask_alignr_epi8, _mm_maskz_alignr_epi8, 1484 _mm256_mask_cmp_epu8_mask): Likewise. 1485 * config/i386/avx512vlintrin.h (_mm_mask_cvtps_ph, _mm_maskz_cvtps_ph, 1486 _mm256_mask_cvtps_ph, _mm256_maskz_cvtps_ph): Likewise. 1487 * config/i386/f16cintrin.h (_mm_cvtps_ph, _mm256_cvtps_ph): Likewise. 1488 * config/i386/shaintrin.h (_mm_sha1rnds4_epu32): Likewise. 1489 1490 PR target/94832 1491 * config/i386/avx2intrin.h (_mm_mask_i32gather_pd, 1492 _mm256_mask_i32gather_pd, _mm_mask_i64gather_pd, 1493 _mm256_mask_i64gather_pd, _mm_mask_i32gather_ps, 1494 _mm256_mask_i32gather_ps, _mm_mask_i64gather_ps, 1495 _mm256_mask_i64gather_ps, _mm_i32gather_epi64, 1496 _mm_mask_i32gather_epi64, _mm256_i32gather_epi64, 1497 _mm256_mask_i32gather_epi64, _mm_i64gather_epi64, 1498 _mm_mask_i64gather_epi64, _mm256_i64gather_epi64, 1499 _mm256_mask_i64gather_epi64, _mm_i32gather_epi32, 1500 _mm_mask_i32gather_epi32, _mm256_i32gather_epi32, 1501 _mm256_mask_i32gather_epi32, _mm_i64gather_epi32, 1502 _mm_mask_i64gather_epi32, _mm256_i64gather_epi32, 1503 _mm256_mask_i64gather_epi32): Surround macro parameter uses with 1504 parens. 1505 (_mm_i32gather_pd, _mm256_i32gather_pd, _mm_i64gather_pd, 1506 _mm256_i64gather_pd, _mm_i32gather_ps, _mm256_i32gather_ps, 1507 _mm_i64gather_ps, _mm256_i64gather_ps): Likewise. Don't use 1508 as mask vector containing -1.0 or -1.0f elts, but instead vector 1509 with all bits set using _mm*_cmpeq_p? with zero operands. 1510 * config/i386/avx512fintrin.h (_mm512_i32gather_ps, 1511 _mm512_mask_i32gather_ps, _mm512_i32gather_pd, 1512 _mm512_mask_i32gather_pd, _mm512_i64gather_ps, 1513 _mm512_mask_i64gather_ps, _mm512_i64gather_pd, 1514 _mm512_mask_i64gather_pd, _mm512_i32gather_epi32, 1515 _mm512_mask_i32gather_epi32, _mm512_i32gather_epi64, 1516 _mm512_mask_i32gather_epi64, _mm512_i64gather_epi32, 1517 _mm512_mask_i64gather_epi32, _mm512_i64gather_epi64, 1518 _mm512_mask_i64gather_epi64, _mm512_i32scatter_ps, 1519 _mm512_mask_i32scatter_ps, _mm512_i32scatter_pd, 1520 _mm512_mask_i32scatter_pd, _mm512_i64scatter_ps, 1521 _mm512_mask_i64scatter_ps, _mm512_i64scatter_pd, 1522 _mm512_mask_i64scatter_pd, _mm512_i32scatter_epi32, 1523 _mm512_mask_i32scatter_epi32, _mm512_i32scatter_epi64, 1524 _mm512_mask_i32scatter_epi64, _mm512_i64scatter_epi32, 1525 _mm512_mask_i64scatter_epi32, _mm512_i64scatter_epi64, 1526 _mm512_mask_i64scatter_epi64): Surround macro parameter uses with 1527 parens. 1528 * config/i386/avx512pfintrin.h (_mm512_prefetch_i32gather_pd, 1529 _mm512_prefetch_i32gather_ps, _mm512_mask_prefetch_i32gather_pd, 1530 _mm512_mask_prefetch_i32gather_ps, _mm512_prefetch_i64gather_pd, 1531 _mm512_prefetch_i64gather_ps, _mm512_mask_prefetch_i64gather_pd, 1532 _mm512_mask_prefetch_i64gather_ps, _mm512_prefetch_i32scatter_pd, 1533 _mm512_prefetch_i32scatter_ps, _mm512_mask_prefetch_i32scatter_pd, 1534 _mm512_mask_prefetch_i32scatter_ps, _mm512_prefetch_i64scatter_pd, 1535 _mm512_prefetch_i64scatter_ps, _mm512_mask_prefetch_i64scatter_pd, 1536 _mm512_mask_prefetch_i64scatter_ps): Likewise. 1537 * config/i386/avx512vlintrin.h (_mm256_mmask_i32gather_ps, 1538 _mm_mmask_i32gather_ps, _mm256_mmask_i32gather_pd, 1539 _mm_mmask_i32gather_pd, _mm256_mmask_i64gather_ps, 1540 _mm_mmask_i64gather_ps, _mm256_mmask_i64gather_pd, 1541 _mm_mmask_i64gather_pd, _mm256_mmask_i32gather_epi32, 1542 _mm_mmask_i32gather_epi32, _mm256_mmask_i32gather_epi64, 1543 _mm_mmask_i32gather_epi64, _mm256_mmask_i64gather_epi32, 1544 _mm_mmask_i64gather_epi32, _mm256_mmask_i64gather_epi64, 1545 _mm_mmask_i64gather_epi64, _mm256_i32scatter_ps, 1546 _mm256_mask_i32scatter_ps, _mm_i32scatter_ps, _mm_mask_i32scatter_ps, 1547 _mm256_i32scatter_pd, _mm256_mask_i32scatter_pd, _mm_i32scatter_pd, 1548 _mm_mask_i32scatter_pd, _mm256_i64scatter_ps, 1549 _mm256_mask_i64scatter_ps, _mm_i64scatter_ps, _mm_mask_i64scatter_ps, 1550 _mm256_i64scatter_pd, _mm256_mask_i64scatter_pd, _mm_i64scatter_pd, 1551 _mm_mask_i64scatter_pd, _mm256_i32scatter_epi32, 1552 _mm256_mask_i32scatter_epi32, _mm_i32scatter_epi32, 1553 _mm_mask_i32scatter_epi32, _mm256_i32scatter_epi64, 1554 _mm256_mask_i32scatter_epi64, _mm_i32scatter_epi64, 1555 _mm_mask_i32scatter_epi64, _mm256_i64scatter_epi32, 1556 _mm256_mask_i64scatter_epi32, _mm_i64scatter_epi32, 1557 _mm_mask_i64scatter_epi32, _mm256_i64scatter_epi64, 1558 _mm256_mask_i64scatter_epi64, _mm_i64scatter_epi64, 1559 _mm_mask_i64scatter_epi64): Likewise. 1560 15612020-04-29 Jeff Law <law@redhat.com> 1562 1563 * config/h8300/h8300.md (H8/SX div patterns): All H8/SX specific 1564 division instructions are 4 bytes long. 1565 15662020-04-29 Jakub Jelinek <jakub@redhat.com> 1567 1568 PR target/94826 1569 * config/rs6000/rs6000.c (rs6000_atomic_assign_expand_fenv): Use 1570 TARGET_EXPR instead of MODIFY_EXPR for first assignment to 1571 fenv_var, fenv_clear and old_fenv variables. For fenv_addr 1572 take address of TARGET_EXPR of fenv_var with void_node initializer. 1573 Formatting fixes. 1574 15752020-04-29 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> 1576 1577 PR tree-optimization/94774 1578 * gimple-ssa-sprintf.c (try_substitute_return_value): Initialize 1579 variable retval. 1580 15812020-04-29 Richard Sandiford <richard.sandiford@arm.com> 1582 1583 * calls.h (cxx17_empty_base_field_p): Turn into a function declaration. 1584 * calls.c (cxx17_empty_base_field_p): New function. Check 1585 DECL_ARTIFICIAL and RECORD_OR_UNION_TYPE_P in addition to the 1586 previous checks. 1587 15882020-04-29 H.J. Lu <hongjiu.lu@intel.com> 1589 1590 PR target/93654 1591 * config/i386/i386-options.c (ix86_set_indirect_branch_type): 1592 Allow -fcf-protection with -mindirect-branch=thunk-extern and 1593 -mfunction-return=thunk-extern. 1594 * doc/invoke.texi: Update notes for -fcf-protection=branch with 1595 -mindirect-branch=thunk-extern and -mindirect-return=thunk-extern. 1596 15972020-04-29 Richard Sandiford <richard.sandiford@arm.com> 1598 1599 * doc/sourcebuild.texi: Add missing arm_arch_v8a_hard_ok anchor. 1600 16012020-04-29 Richard Sandiford <richard.sandiford@arm.com> 1602 1603 * config/arm/arm-builtins.c (arm_atomic_assign_expand_fenv): Use 1604 TARGET_EXPR instead of MODIFY_EXPR for the first assignments to 1605 fenv_var and new_fenv_var. 1606 16072020-04-29 Richard Sandiford <richard.sandiford@arm.com> 1608 1609 * doc/sourcebuild.texi (arm_arch_v8a_hard_ok): Document new 1610 effective-target keyword. 1611 (arm_arch_v8a_hard_multilib): Likewise. 1612 (arm_arch_v8a_hard): Document new dg-add-options keyword. 1613 * config/arm/arm.c (arm_return_in_memory): Note that the APCS 1614 code is deprecated and has not been updated to handle 1615 DECL_FIELD_ABI_IGNORED. 1616 (WARN_PSABI_EMPTY_CXX17_BASE): New constant. 1617 (WARN_PSABI_NO_UNIQUE_ADDRESS): Likewise. 1618 (aapcs_vfp_sub_candidate): Replace the boolean pointer parameter 1619 avoid_cxx17_empty_base with a pointer to a bitmask. Ignore fields 1620 whose DECL_FIELD_ABI_IGNORED bit is set when determining whether 1621 something actually is a HFA or HVA. Record whether we see a 1622 [[no_unique_address]] field that previous GCCs would not have 1623 ignored in this way. 1624 (aapcs_vfp_is_call_or_return_candidate): Update the calls to 1625 aapcs_vfp_sub_candidate and report a -Wpsabi warning for the 1626 [[no_unique_address]] case. Use TYPE_MAIN_VARIANT in the 1627 diagnostic messages. 1628 (arm_needs_doubleword_align): Add a comment explaining why we 1629 consider even zero-sized fields. 1630 16312020-04-29 Richard Biener <rguenther@suse.de> 1632 Li Zekun <lizekun1@huawei.com> 1633 1634 PR lto/94822 1635 * tree.c (component_ref_size): Guard against error_mark_node 1636 DECL_INITIAL as it happens with LTO. 1637 16382020-04-29 Richard Sandiford <richard.sandiford@arm.com> 1639 1640 * config/aarch64/aarch64.c (aarch64_function_arg_alignment): Add a 1641 comment explaining why we consider even zero-sized fields. 1642 (WARN_PSABI_EMPTY_CXX17_BASE): New constant. 1643 (WARN_PSABI_NO_UNIQUE_ADDRESS): Likewise. 1644 (aapcs_vfp_sub_candidate): Replace the boolean pointer parameter 1645 avoid_cxx17_empty_base with a pointer to a bitmask. Ignore fields 1646 whose DECL_FIELD_ABI_IGNORED bit is set when determining whether 1647 something actually is a HFA or HVA. Record whether we see a 1648 [[no_unique_address]] field that previous GCCs would not have 1649 ignored in this way. 1650 (aarch64_vfp_is_call_or_return_candidate): Add a parameter to say 1651 whether diagnostics should be suppressed. Update the calls to 1652 aapcs_vfp_sub_candidate and report a -Wpsabi warning for the 1653 [[no_unique_address]] case. 1654 (aarch64_return_in_msb): Update call accordingly, never silencing 1655 diagnostics. 1656 (aarch64_function_value): Likewise. 1657 (aarch64_return_in_memory_1): Likewise. 1658 (aarch64_init_cumulative_args): Likewise. 1659 (aarch64_gimplify_va_arg_expr): Likewise. 1660 (aarch64_pass_by_reference_1): Take a CUMULATIVE_ARGS pointer and 1661 use it to decide whether arch64_vfp_is_call_or_return_candidate 1662 should be silent. 1663 (aarch64_pass_by_reference): Update calls accordingly. 1664 (aarch64_vfp_is_call_candidate): Use the CUMULATIVE_ARGS argument 1665 to decide whether arch64_vfp_is_call_or_return_candidate should be 1666 silent. 1667 16682020-04-29 Haijian Zhang <z.zhanghaijian@huawei.com> 1669 1670 PR target/94820 1671 * config/aarch64/aarch64-builtins.c 1672 (aarch64_atomic_assign_expand_fenv): Use TARGET_EXPR instead of 1673 MODIFY_EXPR for first assignment to fenv_cr, fenv_sr and 1674 new_fenv_var. 1675 16762020-04-29 Thomas Schwinge <thomas@codesourcery.com> 1677 1678 * configure.ac <$enable_offload_targets>: Do parsing as done 1679 elsewhere. 1680 * configure: Regenerate. 1681 1682 * configure.ac <$enable_offload_targets>: 'amdgcn' is 'gcn'. 1683 * configure: Regenerate. 1684 1685 PR target/94279 1686 * rtlanal.c (set_noop_p): Handle non-constant selectors. 1687 1688 PR target/94282 1689 * common/config/gcn/gcn-common.c (gcn_except_unwind_info): New 1690 function. 1691 (TARGET_EXCEPT_UNWIND_INFO): Define. 1692 16932020-04-29 Jakub Jelinek <jakub@redhat.com> 1694 1695 PR target/94248 1696 * config/gcn/gcn.md (*mov<mode>_insn): Use 1697 'reg_overlap_mentioned_p' to check for overlap. 1698 1699 PR target/94706 1700 * config/ia64/ia64.c (hfa_element_mode): Use DECL_FIELD_ABI_IGNORED 1701 instead of cxx17_empty_base_field_p. 1702 1703 PR target/94707 1704 * tree-core.h (tree_decl_common): Note decl_flag_0 used for 1705 DECL_FIELD_ABI_IGNORED. 1706 * tree.h (DECL_FIELD_ABI_IGNORED): Define. 1707 * calls.h (cxx17_empty_base_field_p): Change into a temporary 1708 macro, check DECL_FIELD_ABI_IGNORED flag with no "no_unique_address" 1709 attribute. 1710 * calls.c (cxx17_empty_base_field_p): Remove. 1711 * tree-streamer-out.c (pack_ts_decl_common_value_fields): Handle 1712 DECL_FIELD_ABI_IGNORED. 1713 * tree-streamer-in.c (unpack_ts_decl_common_value_fields): Likewise. 1714 * lto-streamer-out.c (hash_tree): Likewise. 1715 * config/rs6000/rs6000-call.c (rs6000_aggregate_candidate): Rename 1716 cxx17_empty_base_seen to empty_base_seen, change type to int *, 1717 adjust recursive calls, use DECL_FIELD_ABI_IGNORED instead of 1718 cxx17_empty_base_field_p, if "no_unique_address" attribute is 1719 present, propagate that to the caller too. 1720 (rs6000_discover_homogeneous_aggregate): Adjust 1721 rs6000_aggregate_candidate caller, emit different diagnostics 1722 when c++17 empty base fields are present and when empty 1723 [[no_unique_address]] fields are present. 1724 * config/rs6000/rs6000.c (rs6000_special_round_type_align, 1725 darwin_rs6000_special_round_type_align): Skip DECL_FIELD_ABI_IGNORED 1726 fields. 1727 17282020-04-29 Richard Biener <rguenther@suse.de> 1729 1730 * tree-ssa-loop-im.c (ref_always_accessed::operator ()): 1731 Just check whether the stmt stores. 1732 17332020-04-28 Alexandre Oliva <oliva@adacore.com> 1734 1735 PR target/94812 1736 * gcc/config/rs6000/rs6000.md (rs6000_mffsl): Copy result to 1737 output operand in emulation. Don't overwrite pseudos. 1738 17392020-04-28 Jeff Law <law@redhat.com> 1740 1741 * config/h8300/h8300.md (H8/SX mult patterns): All H8/SX specific 1742 multiply patterns are 4 bytes long. 1743 17442020-04-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 1745 1746 * config/arm/arm-cpus.in (cortex-m55): Remove +nofp option. 1747 * doc/invoke.texi (Arm Options): Remove -mcpu=cortex-m55 from +nofp option. 1748 17492020-04-28 Matthew Malcomson <matthew.malcomson@arm.com> 1750 Jakub Jelinek <jakub@redhat.com> 1751 1752 PR target/94711 1753 * config/arm/arm.c (aapcs_vfp_sub_candidate): Account for C++17 empty 1754 base class artificial fields. 1755 (aapcs_vfp_is_call_or_return_candidate): Warn when PCS ABI 1756 decision is different after this fix. 1757 17582020-04-28 David Malcolm <dmalcolm@redhat.com> 1759 1760 PR analyzer/94447 1761 PR analyzer/94639 1762 PR analyzer/94732 1763 PR analyzer/94754 1764 * doc/invoke.texi (Static Analyzer Options): Remove 1765 -Wanalyzer-use-of-uninitialized-value. 1766 (-Wno-analyzer-use-of-uninitialized-value): Remove item. 1767 17682020-04-28 Jakub Jelinek <jakub@redhat.com> 1769 1770 PR tree-optimization/94809 1771 * tree.c (build_call_expr_internal_loc_array): Call 1772 process_call_operands. 1773 17742020-04-27 Anton Youdkevitch <anton.youdkevitch@bell-sw.com> 1775 1776 * config/aarch64/aarch64-cores.def (thunderx3t110): Add the chip name. 1777 * config/aarch64/aarch64-tune.md: Regenerate. 1778 * config/aarch64/aarch64.c (thunderx3t110_addrcost_table): Define. 1779 (thunderx3t110_regmove_cost): Likewise. 1780 (thunderx3t110_vector_cost): Likewise. 1781 (thunderx3t110_prefetch_tune): Likewise. 1782 (thunderx3t110_tunings): Likewise. 1783 * config/aarch64/aarch64-cost-tables.h (thunderx3t110_extra_costs): 1784 Define. 1785 * config/aarch64/thunderx3t110.md: New file. 1786 * config/aarch64/aarch64.md: Include thunderx3t110.md. 1787 * doc/invoke.texi (AArch64 options): Add thunderx3t110. 1788 17892020-04-28 Jakub Jelinek <jakub@redhat.com> 1790 1791 PR target/94704 1792 * config/s390/s390.c (s390_function_arg_vector, 1793 s390_function_arg_float): Emit -Wpsabi diagnostics if the ABI changed. 1794 17952020-04-28 Richard Sandiford <richard.sandiford@arm.com> 1796 1797 PR tree-optimization/94727 1798 * tree-vect-stmts.c (vect_is_simple_cond): If both comparison 1799 operands are invariant booleans, use the mask type associated with the 1800 STMT_VINFO_VECTYPE. Use !slp_node instead of !vectype to exclude SLP. 1801 (vectorizable_condition): Pass vectype unconditionally to 1802 vect_is_simple_cond. 1803 18042020-04-27 Jakub Jelinek <jakub@redhat.com> 1805 1806 PR target/94780 1807 * config/i386/i386.c (ix86_atomic_assign_expand_fenv): Use 1808 TARGET_EXPR instead of MODIFY_EXPR for first assignment to 1809 sw_var, exceptions_var, mxcsr_orig_var and mxcsr_mod_var. 1810 18112020-04-27 David Malcolm <dmalcolm@redhat.com> 1812 1813 PR 92830 1814 * configure.ac (DOCUMENTATION_ROOT_URL): Drop trailing "gcc/" from 1815 default value, so that it can by supplied by get_option_html_page. 1816 * configure: Regenerate. 1817 * opts.c: Include "selftest.h". 1818 (get_option_html_page): New function. 1819 (get_option_url): Use it. Reformat to place comments next to the 1820 expressions they refer to. 1821 (selftest::test_get_option_html_page): New. 1822 (selftest::opts_c_tests): New. 1823 * selftest-run-tests.c (selftest::run_tests): Call 1824 selftest::opts_c_tests. 1825 * selftest.h (selftest::opts_c_tests): New decl. 1826 18272020-04-27 Richard Sandiford <richard.sandiford@arm.com> 1828 1829 * config/arm/arm-builtins.c (arm_expand_builtin_args): Only apply 1830 UINTVAL to CONST_INTs. 1831 18322020-04-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 1833 1834 * config/arm/constraints.md (e): Remove constraint. 1835 (Te): Define constraint. 1836 * config/arm/mve.md (vaddvq_<supf><mode>): Modify constraint in 1837 operand 0 from "e" to "Te". 1838 (vaddvaq_<supf><mode>): Likewise. 1839 (vaddvq_p_<supf><mode>): Likewise. 1840 (vmladavq_<supf><mode>): Likewise. 1841 (vmladavxq_s<mode>): Likewise. 1842 (vmlsdavq_s<mode>): Likewise. 1843 (vmlsdavxq_s<mode>): Likewise. 1844 (vaddvaq_p_<supf><mode>): Likewise. 1845 (vmladavaq_<supf><mode>): Likewise. 1846 (vmladavq_p_<supf><mode>): Likewise. 1847 (vmladavxq_p_s<mode>): Likewise. 1848 (vmlsdavq_p_s<mode>): Likewise. 1849 (vmlsdavxq_p_s<mode>): Likewise. 1850 (vmlsdavaxq_s<mode>): Likewise. 1851 (vmlsdavaq_s<mode>): Likewise. 1852 (vmladavaxq_s<mode>): Likewise. 1853 (vmladavaq_p_<supf><mode>): Likewise. 1854 (vmladavaxq_p_s<mode>): Likewise. 1855 (vmlsdavaq_p_s<mode>): Likewise. 1856 (vmlsdavaxq_p_s<mode>): Likewise. 1857 18582020-04-27 Andre Vieira <andre.simoesdiasvieira@arm.com> 1859 1860 * config/arm/arm.c (output_move_neon): Only get the first operand if 1861 addr is PLUS. 1862 18632020-04-27 Felix Yang <felix.yang@huawei.com> 1864 1865 PR tree-optimization/94784 1866 * tree-ssa-forwprop.c (simplify_vector_constructor): Flip the 1867 assert around so that it checks that the two vectors have equal 1868 TYPE_VECTOR_SUBPARTS and that converting the corresponding element 1869 types is a useless_type_conversion_p. 1870 18712020-04-27 Szabolcs Nagy <szabolcs.nagy@arm.com> 1872 1873 PR target/94515 1874 * dwarf2cfi.c (struct GTY): Add ra_mangled. 1875 (cfi_row_equal_p): Check ra_mangled. 1876 (dwarf2out_frame_debug_cfa_window_save): Remove the argument, 1877 this only handles the sparc logic now. 1878 (dwarf2out_frame_debug_cfa_toggle_ra_mangle): New function for 1879 the aarch64 specific logic. 1880 (dwarf2out_frame_debug): Update to use the new subroutines. 1881 (change_cfi_row): Check ra_mangled. 1882 18832020-04-27 Jakub Jelinek <jakub@redhat.com> 1884 1885 PR target/94704 1886 * config/s390/s390.c (s390_function_arg_vector, 1887 s390_function_arg_float): Ignore cxx17_empty_base_field_p fields. 1888 18892020-04-27 Jiufu Guo <guojiufu@cn.ibm.com> 1890 1891 * common/config/rs6000/rs6000-common.c 1892 (rs6000_option_optimization_table) [OPT_LEVELS_ALL]: Remove turn off 1893 -fweb. 1894 * config/rs6000/rs6000.c (rs6000_option_override_internal): Avoid to 1895 set flag_web. 1896 18972020-04-27 Martin Liska <mliska@suse.cz> 1898 1899 PR lto/94659 1900 * cgraph.h (cgraph_node::can_remove_if_no_direct_calls_and_refs_p): 1901 Do not remove ifunc_resolvers in remove unreachable nodes in LTO. 1902 19032020-04-27 Xiong Hu Luo <luoxhu@linux.ibm.com> 1904 1905 PR target/91518 1906 * config/rs6000/rs6000-logue.c (frame_pointer_needed_indeed): 1907 New variable. 1908 (rs6000_emit_prologue_components): 1909 Check with frame_pointer_needed_indeed. 1910 (rs6000_emit_epilogue_components): Likewise. 1911 (rs6000_emit_prologue): Likewise. 1912 (rs6000_emit_epilogue): Set frame_pointer_needed_indeed. 1913 19142020-04-25 David Edelsohn <dje.gcc@gmail.com> 1915 1916 * config/rs6000/rs6000-logue.c (rs6000_stack_info): Don't push a 1917 stack frame when debugging and flag_compare_debug is enabled. 1918 19192020-04-25 Michael Meissner <meissner@linux.ibm.com> 1920 1921 * config/rs6000/linux64.h (PCREL_SUPPORTED_BY_OS): Define to 1922 enable PC-relative addressing for -mcpu=future. 1923 * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Move 1924 after OTHER_FUTURE_MASKS. Use OTHER_FUTURE_MASKS. 1925 * config/rs6000/rs6000.c (PCREL_SUPPORTED_BY_OS): If not defined, 1926 suppress PC-relative addressing. 1927 (rs6000_option_override_internal): Split up error messages 1928 checking for -mprefixed and -mpcrel. Enable -mpcrel if the target 1929 system supports it. 1930 19312020-04-25 Jakub Jelinek <jakub@redhat.com> 1932 Richard Biener <rguenther@suse.de> 1933 1934 PR tree-optimization/94734 1935 PR tree-optimization/89430 1936 * tree-ssa-phiopt.c: Include tree-eh.h. 1937 (cond_store_replacement): Return false if an automatic variable 1938 access could trap. If -fstore-data-races, don't return false 1939 just because an automatic variable is addressable. 1940 19412020-04-24 Andrew Stubbs <ams@codesourcery.com> 1942 1943 * config/gcn/gcn-valu.md (add<mode>_zext_dup2_exec): Fix merge 1944 of high-part. 1945 (add<mode>_sext_dup2_exec): Likewise. 1946 19472020-04-24 Segher Boessenkool <segher@kernel.crashing.org> 1948 1949 PR target/94710 1950 * config/rs6000/vector.md (vec_shr_<mode> for VEC_L): Correct little 1951 endian byteshift_val calculation. 1952 19532020-04-24 Andrew Stubbs <ams@codesourcery.com> 1954 1955 * config/gcn/gcn.md (*mov<mode>_insn): Only split post-reload. 1956 19572020-04-24 Richard Sandiford <richard.sandiford@arm.com> 1958 1959 * config/aarch64/arm_sve.h: Add a comment. 1960 19612020-04-24 Haijian Zhang <z.zhanghaijian@huawei.com> 1962 1963 PR rtl-optimization/94708 1964 * combine.c (simplify_if_then_else): Add check for 1965 !HONOR_NANS (mode) && !HONOR_SIGNED_ZEROS (mode). 1966 19672020-04-23 Martin Sebor <msebor@redhat.com> 1968 1969 PR driver/90983 1970 * common.opt (-Wno-frame-larger-than): New option. 1971 (-Wno-larger-than, -Wno-stack-usage): Same. 1972 19732020-04-23 Andrew Stubbs <ams@codesourcery.com> 1974 1975 * config/gcn/gcn-valu.md (mov<mode>_exec): Swap the numbers on operands 1976 2 and 3. 1977 (mov<mode>_exec): Likewise. 1978 (trunc<vndi><mode>2_exec): Swap parameters to gen_mov<mode>_exec. 1979 (<convop><mode><vndi>2_exec): Likewise. 1980 19812019-04-23 Eric Botcazou <ebotcazou@adacore.com> 1982 1983 PR tree-optimization/94717 1984 * gimple-ssa-store-merging.c (try_coalesce_bswap): Return false if one 1985 of the stores doesn't have the same landing pad number as the first. 1986 (coalesce_immediate_stores): Do not try to coalesce the store using 1987 bswap if it doesn't have the same landing pad number as the first. 1988 19892020-04-23 Bill Schmidt <wschmidt@linux.ibm.com> 1990 1991 * gcc/doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): 1992 Replace outdated link to ELFv2 ABI. 1993 19942020-04-23 Jakub Jelinek <jakub@redhat.com> 1995 1996 PR target/94710 1997 * optabs.c (expand_vec_perm_const): For shift_amt const0_rtx 1998 just return v2. 1999 2000 PR middle-end/94724 2001 * tree.c (get_narrower): Instead of creating COMPOUND_EXPRs 2002 temporarily with non-final second operand and updating it later, 2003 push COMPOUND_EXPRs into a vector and process it in reverse, 2004 creating COMPOUND_EXPRs with the final operands. 2005 20062020-04-23 Szabolcs Nagy <szabolcs.nagy@arm.com> 2007 2008 PR target/94697 2009 * config/aarch64/aarch64-bti-insert.c (rest_of_insert_bti): Swap 2010 bti c and bti j handling. 2011 20122020-04-23 Andrew Stubbs <ams@codesourcery.com> 2013 Thomas Schwinge <thomas@codesourcery.com> 2014 2015 PR middle-end/93488 2016 2017 * omp-expand.c (expand_omp_target): Use force_gimple_operand_gsi on 2018 t_async and the wait arguments. 2019 20202020-04-23 Richard Sandiford <richard.sandiford@arm.com> 2021 2022 PR tree-optimization/94727 2023 * tree-vect-stmts.c (vectorizable_comparison): Use mask_type when 2024 comparing invariant scalar booleans. 2025 20262020-04-23 Matthew Malcomson <matthew.malcomson@arm.com> 2027 Jakub Jelinek <jakub@redhat.com> 2028 2029 PR target/94383 2030 * config/aarch64/aarch64.c (aapcs_vfp_sub_candidate): Account for C++17 2031 empty base class artificial fields. 2032 (aarch64_vfp_is_call_or_return_candidate): Warn when ABI PCS decision is 2033 different after this fix. 2034 20352020-04-23 Jakub Jelinek <jakub@redhat.com> 2036 2037 PR target/94707 2038 * config/rs6000/rs6000-call.c (rs6000_discover_homogeneous_aggregate): 2039 Use TYPE_UID (TYPE_MAIN_VARIANT (type)) instead of type to check 2040 if the same type has been diagnosed most recently already. 2041 20422020-04-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 2043 2044 * config/arm/arm_mve.h (__arm_vbicq_n_u16): Modify function parameter's 2045 datatype. 2046 (__arm_vbicq_n_s16): Likewise. 2047 (__arm_vbicq_n_u32): Likewise. 2048 (__arm_vbicq_n_s32): Likewise. 2049 (__arm_vbicq): Likewise. 2050 (__arm_vbicq_n_s16): Modify MVE polymorphic variant argument's datatype. 2051 (__arm_vbicq_n_s32): Likewise. 2052 (__arm_vbicq_n_u16): Likewise. 2053 (__arm_vbicq_n_u32): Likewise. 2054 (__arm_vdupq_m_n_s8): Likewise. 2055 (__arm_vdupq_m_n_s16): Likewise. 2056 (__arm_vdupq_m_n_s32): Likewise. 2057 (__arm_vdupq_m_n_u8): Likewise. 2058 (__arm_vdupq_m_n_u16): Likewise. 2059 (__arm_vdupq_m_n_u32): Likewise. 2060 (__arm_vdupq_m_n_f16): Likewise. 2061 (__arm_vdupq_m_n_f32): Likewise. 2062 (__arm_vldrhq_gather_offset_s16): Likewise. 2063 (__arm_vldrhq_gather_offset_s32): Likewise. 2064 (__arm_vldrhq_gather_offset_u16): Likewise. 2065 (__arm_vldrhq_gather_offset_u32): Likewise. 2066 (__arm_vldrhq_gather_offset_f16): Likewise. 2067 (__arm_vldrhq_gather_offset_z_s16): Likewise. 2068 (__arm_vldrhq_gather_offset_z_s32): Likewise. 2069 (__arm_vldrhq_gather_offset_z_u16): Likewise. 2070 (__arm_vldrhq_gather_offset_z_u32): Likewise. 2071 (__arm_vldrhq_gather_offset_z_f16): Likewise. 2072 (__arm_vldrhq_gather_shifted_offset_s16): Likewise. 2073 (__arm_vldrhq_gather_shifted_offset_s32): Likewise. 2074 (__arm_vldrhq_gather_shifted_offset_u16): Likewise. 2075 (__arm_vldrhq_gather_shifted_offset_u32): Likewise. 2076 (__arm_vldrhq_gather_shifted_offset_f16): Likewise. 2077 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise. 2078 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise. 2079 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise. 2080 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise. 2081 (__arm_vldrhq_gather_shifted_offset_z_f16): Likewise. 2082 (__arm_vldrwq_gather_offset_s32): Likewise. 2083 (__arm_vldrwq_gather_offset_u32): Likewise. 2084 (__arm_vldrwq_gather_offset_f32): Likewise. 2085 (__arm_vldrwq_gather_offset_z_s32): Likewise. 2086 (__arm_vldrwq_gather_offset_z_u32): Likewise. 2087 (__arm_vldrwq_gather_offset_z_f32): Likewise. 2088 (__arm_vldrwq_gather_shifted_offset_s32): Likewise. 2089 (__arm_vldrwq_gather_shifted_offset_u32): Likewise. 2090 (__arm_vldrwq_gather_shifted_offset_f32): Likewise. 2091 (__arm_vldrwq_gather_shifted_offset_z_s32): Likewise. 2092 (__arm_vldrwq_gather_shifted_offset_z_u32): Likewise. 2093 (__arm_vldrwq_gather_shifted_offset_z_f32): Likewise. 2094 (__arm_vdwdupq_x_n_u8): Likewise. 2095 (__arm_vdwdupq_x_n_u16): Likewise. 2096 (__arm_vdwdupq_x_n_u32): Likewise. 2097 (__arm_viwdupq_x_n_u8): Likewise. 2098 (__arm_viwdupq_x_n_u16): Likewise. 2099 (__arm_viwdupq_x_n_u32): Likewise. 2100 (__arm_vidupq_x_n_u8): Likewise. 2101 (__arm_vddupq_x_n_u8): Likewise. 2102 (__arm_vidupq_x_n_u16): Likewise. 2103 (__arm_vddupq_x_n_u16): Likewise. 2104 (__arm_vidupq_x_n_u32): Likewise. 2105 (__arm_vddupq_x_n_u32): Likewise. 2106 (__arm_vldrdq_gather_offset_s64): Likewise. 2107 (__arm_vldrdq_gather_offset_u64): Likewise. 2108 (__arm_vldrdq_gather_offset_z_s64): Likewise. 2109 (__arm_vldrdq_gather_offset_z_u64): Likewise. 2110 (__arm_vldrdq_gather_shifted_offset_s64): Likewise. 2111 (__arm_vldrdq_gather_shifted_offset_u64): Likewise. 2112 (__arm_vldrdq_gather_shifted_offset_z_s64): Likewise. 2113 (__arm_vldrdq_gather_shifted_offset_z_u64): Likewise. 2114 (__arm_vidupq_m_n_u8): Likewise. 2115 (__arm_vidupq_m_n_u16): Likewise. 2116 (__arm_vidupq_m_n_u32): Likewise. 2117 (__arm_vddupq_m_n_u8): Likewise. 2118 (__arm_vddupq_m_n_u16): Likewise. 2119 (__arm_vddupq_m_n_u32): Likewise. 2120 (__arm_vidupq_n_u16): Likewise. 2121 (__arm_vidupq_n_u32): Likewise. 2122 (__arm_vidupq_n_u8): Likewise. 2123 (__arm_vddupq_n_u16): Likewise. 2124 (__arm_vddupq_n_u32): Likewise. 2125 (__arm_vddupq_n_u8): Likewise. 2126 21272020-04-23 Iain Buclaw <ibuclaw@gdcproject.org> 2128 2129 * doc/install.texi (D-Specific Options): Document 2130 --enable-libphobos-checking and --with-libphobos-druntime-only. 2131 21322020-04-23 Jakub Jelinek <jakub@redhat.com> 2133 2134 PR target/94707 2135 * config/rs6000/rs6000-call.c (rs6000_aggregate_candidate): Add 2136 cxx17_empty_base_seen argument. Pass it to recursive calls. 2137 Ignore cxx17_empty_base_field_p fields after setting 2138 *cxx17_empty_base_seen to true. 2139 (rs6000_discover_homogeneous_aggregate): Adjust 2140 rs6000_aggregate_candidate caller. With -Wpsabi, diagnose homogeneous 2141 aggregates with C++17 empty base fields. 2142 2143 PR c/94705 2144 * attribs.c (decl_attribute): Don't diagnose attribute exclusions 2145 if last_decl is error_mark_node or has such a TREE_TYPE. 2146 2147 PR c/94705 2148 * attribs.c (decl_attribute): Don't diagnose attribute exclusions 2149 if last_decl is error_mark_node or has such a TREE_TYPE. 2150 21512020-04-22 Felix Yang <felix.yang@huawei.com> 2152 2153 PR target/94678 2154 * config/aarch64/aarch64.h (TARGET_SVE): 2155 Add && !TARGET_GENERAL_REGS_ONLY. 2156 (TARGET_SVE2): Add && TARGET_SVE. 2157 (TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3, 2158 TARGET_SVE2_SM4): Add && TARGET_SVE2. 2159 * config/aarch64/aarch64-sve-builtins.h 2160 (sve_switcher::m_old_general_regs_only): New member. 2161 * config/aarch64/aarch64-sve-builtins.cc (check_required_registers): 2162 New function. 2163 (reported_missing_registers_p): New variable. 2164 (check_required_extensions): Call check_required_registers before 2165 return if all required extenstions are present. 2166 (sve_switcher::sve_switcher): Save TARGET_GENERAL_REGS_ONLY in 2167 m_old_general_regs_only and clear MASK_GENERAL_REGS_ONLY in 2168 global_options.x_target_flags. 2169 (sve_switcher::~sve_switcher): Set MASK_GENERAL_REGS_ONLY in 2170 global_options.x_target_flags if m_old_general_regs_only is true. 2171 21722020-04-22 Zackery Spytz <zspytz@gmail.com> 2173 2174 * doc/extend.exi: Add "free" to list of other builtin functions 2175 supported by GCC. 2176 21772020-04-20 Aaron Sawdey <acsawdey@linux.ibm.com> 2178 2179 PR target/94622 2180 * config/rs6000/sync.md (load_quadpti): Add attr "prefixed" 2181 if TARGET_PREFIXED. 2182 (store_quadpti): Ditto. 2183 (atomic_load<mode>): Do not swap doublewords if TARGET_PREFIXED as 2184 plq will be used and doesn't need it. 2185 (atomic_store<mode>): Ditto, for pstq. 2186 21872020-04-22 Erick Ochoa <erick.ochoa@theobroma-systems.com> 2188 2189 * doc/invoke.texi: Update flags turned on by -O3. 2190 21912020-04-22 Jakub Jelinek <jakub@redhat.com> 2192 2193 PR target/94706 2194 * config/ia64/ia64.c (hfa_element_mode): Ignore 2195 cxx17_empty_base_field_p fields. 2196 2197 PR target/94383 2198 * calls.h (cxx17_empty_base_field_p): Declare. 2199 * calls.c (cxx17_empty_base_field_p): Define. 2200 22012020-04-22 Christophe Lyon <christophe.lyon@linaro.org> 2202 2203 * doc/sourcebuild.texi (arm_softfp_ok, arm_hard_ok): Document. 2204 22052020-04-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 2206 Andre Vieira <andre.simoesdiasvieira@arm.com> 2207 Mihail Ionescu <mihail.ionescu@arm.com> 2208 2209 * config/arm/arm.c (arm_file_start): Handle isa_bit_quirk_no_asmcpu. 2210 * config/arm/arm-cpus.in (quirk_no_asmcpu): Define. 2211 (ALL_QUIRKS): Add quirk_no_asmcpu. 2212 (cortex-m55): Define new cpu. 2213 * config/arm/arm-tables.opt: Regenerate. 2214 * config/arm/arm-tune.md: Likewise. 2215 * doc/invoke.texi (Arm Options): Document -mcpu=cortex-m55. 2216 22172020-04-22 Richard Sandiford <richard.sandiford@arm.com> 2218 2219 PR tree-optimization/94700 2220 * tree-ssa-forwprop.c (simplify_vector_constructor): When processing 2221 an identity constructor, use a VIEW_CONVERT_EXPR to handle mixtures 2222 of similarly-structured but distinct vector types. 2223 22242020-04-21 Martin Sebor <msebor@redhat.com> 2225 2226 PR middle-end/94647 2227 * gimple-ssa-warn-restrict.c (builtin_access::builtin_access): Correct 2228 the computation of the lower bound of the source access size. 2229 (builtin_access::generic_overlap): Remove a hack for setting ranges 2230 of overlap offsets. 2231 22322020-04-21 John David Anglin <danglin@gcc.gnu.org> 2233 2234 * config/pa/som.h (ASM_WEAKEN_LABEL): Delete. 2235 (ASM_WEAKEN_DECL): New define. 2236 (HAVE_GAS_WEAKREF): Undefine. 2237 22382020-04-21 Richard Sandiford <richard.sandiford@arm.com> 2239 2240 PR tree-optimization/94683 2241 * tree-ssa-forwprop.c (simplify_vector_constructor): Use a 2242 VIEW_CONVERT_EXPR to handle mixtures of similarly-structured 2243 but distinct vector types. 2244 22452020-04-21 Jakub Jelinek <jakub@redhat.com> 2246 2247 PR c/94641 2248 * stor-layout.c (place_field, finalize_record_size): Don't emit 2249 -Wpadded warning on TYPE_ARTIFICIAL rli->t. 2250 * ubsan.c (ubsan_get_type_descriptor_type, 2251 ubsan_get_source_location_type, ubsan_create_data): Set 2252 TYPE_ARTIFICIAL. 2253 * asan.c (asan_global_struct): Likewise. 2254 22552020-04-21 Duan bo <duanbo3@huawei.com> 2256 2257 PR target/94577 2258 * config/aarch64/aarch64.c: Add an error message for option conflict. 2259 * doc/invoke.texi (-mcmodel=large): Mention that -mcmodel=large is 2260 incompatible with -fpic, -fPIC and -mabi=ilp32. 2261 22622020-04-21 Frederik Harwath <frederik@codesourcery.com> 2263 2264 PR other/94629 2265 * omp-low.c (new_omp_context): Remove assignments to 2266 ctx->outer_reduction_clauses and ctx->local_reduction_clauses. 2267 22682020-04-20 Andreas Krebbel <krebbel@linux.ibm.com> 2269 2270 * config/s390/vector.md ("popcountv8hi2_vx", "popcountv4si2_vx") 2271 ("popcountv2di2_vx"): Use simplify_gen_subreg. 2272 22732020-04-20 Andreas Krebbel <krebbel@linux.ibm.com> 2274 2275 PR target/94613 2276 * config/s390/s390-builtin-types.def: Add 3 new function modes. 2277 * config/s390/s390-builtins.def: Add mode dependent low-level 2278 builtin and map the overloaded builtins to these. 2279 * config/s390/vx-builtins.md ("vec_selV_HW"): Rename to ... 2280 ("vsel<V_HW"): ... this and rewrite the pattern with bitops. 2281 22822020-04-20 Richard Sandiford <richard.sandiford@arm.com> 2283 2284 * tree-vect-loop.c (vect_better_loop_vinfo_p): If old_loop_vinfo 2285 has a variable VF, prefer new_loop_vinfo if it is cheaper for the 2286 estimated VF and is no worse at double the estimated VF. 2287 22882020-04-20 Richard Sandiford <richard.sandiford@arm.com> 2289 2290 PR target/94668 2291 * config/aarch64/aarch64.c (aarch64_sve_expand_vector_init): Fix 2292 order of arguments to rtx_vector_builder. 2293 (aarch64_sve_expand_vector_init_handle_trailing_constants): Likewise. 2294 When extending the trailing constants to a full vector, replace any 2295 variables with zeros. 2296 22972020-04-20 Jan Hubicka <hubicka@ucw.cz> 2298 2299 PR ipa/94582 2300 * tree-inline.c (optimize_inline_calls): Recompute calls_comdat_local 2301 flag. 2302 23032020-04-20 Martin Liska <mliska@suse.cz> 2304 2305 * symtab.c (symtab_node::dump_references): Add space after 2306 one entry. 2307 (symtab_node::dump_referring): Likewise. 2308 23092020-04-18 Jeff Law <law@redhat.com> 2310 2311 PR debug/94439 2312 * regrename.c (check_new_reg_p): Ignore DEBUG_INSNs when walking 2313 the chain. 2314 23152020-04-18 Iain Buclaw <ibuclaw@gdcproject.org> 2316 2317 * doc/sourcebuild.texi (Effective-Target Keywords, Environment 2318 attributes): Document d_runtime_has_std_library. 2319 23202020-04-17 Jeff Law <law@redhat.com> 2321 2322 PR rtl-optimization/90275 2323 * cse.c (cse_insn): Avoid recording nop sets in multi-set parallels 2324 when the destination has a REG_UNUSED note. 2325 23262020-04-17 Tobias Burnus <tobias@codesourcery.com> 2327 2328 PR middle-end/94635 2329 * gimplify.c (gimplify_scan_omp_clauses): Turn MAP_TO_PSET to 2330 MAP_DELETE. 2331 23322020-04-17 Richard Sandiford <richard.sandiford@arm.com> 2333 2334 * config/aarch64/aarch64.c (aarch64_advsimd_ldp_stp_p): New function. 2335 (aarch64_sve_adjust_stmt_cost): Add a vectype parameter. Double the 2336 cost of load and store insns if one loop iteration has enough scalar 2337 elements to use an Advanced SIMD LDP or STP. 2338 (aarch64_add_stmt_cost): Update call accordingly. 2339 23402020-04-17 Jakub Jelinek <jakub@redhat.com> 2341 Jeff Law <law@redhat.com> 2342 2343 PR target/94567 2344 * config/i386/i386.md (*testqi_ext_3): Use CCZmode rather than 2345 CCNOmode in ix86_match_ccmode if len is equal to <MODE>mode precision, 2346 or pos + len >= 32, or pos + len is equal to operands[2] precision 2347 and operands[2] is not a register operand. During splitting perform 2348 SImode AND if operands[0] doesn't have CCZmode and pos + len is 2349 equal to mode precision. 2350 23512020-04-17 Richard Biener <rguenther@suse.de> 2352 2353 PR other/94629 2354 * cgraphclones.c (cgraph_node::create_clone): Remove duplicate 2355 initialization. 2356 * dwarf2out.c (dw_val_equal_p): Fix pasto in 2357 dw_val_class_vms_delta comparison. 2358 * optabs.c (expand_binop_directly): Fix pasto in commutation 2359 check. 2360 * tree-ssa-sccvn.c (vn_reference_lookup_pieces): Fix pasto in 2361 initialization. 2362 23632020-04-17 Jakub Jelinek <jakub@redhat.com> 2364 2365 PR rtl-optimization/94618 2366 * cfgrtl.c (delete_insn_and_edges): Set purge not just when 2367 insn is the BB_END of its block, but also when it is only followed 2368 by DEBUG_INSNs in its block. 2369 2370 PR tree-optimization/94621 2371 * tree-inline.c (remap_type_1): Don't dereference NULL TYPE_DOMAIN. 2372 Move id->adjust_array_error_bounds check first in the condition. 2373 23742020-04-17 Martin Liska <mliska@suse.cz> 2375 Jonathan Yong <10walls@gmail.com> 2376 2377 PR gcov-profile/94570 2378 * coverage.c (coverage_init): Use separator properly. 2379 23802020-04-16 Peter Bergner <bergner@linux.ibm.com> 2381 2382 PR rtl-optimization/93974 2383 * config/rs6000/rs6000.c (TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P): Define. 2384 (rs6000_cannot_substitute_mem_equiv_p): New function. 2385 23862020-04-16 Martin Jambor <mjambor@suse.cz> 2387 2388 PR ipa/93621 2389 * ipa-inline.h (ipa_saved_clone_sources): Declare. 2390 * ipa-inline-transform.c (ipa_saved_clone_sources): New variable. 2391 (save_inline_function_body): Link the new body holder with the 2392 previous one. 2393 * cgraph.c: Include ipa-inline.h. 2394 (cgraph_edge::redirect_call_stmt_to_callee): Try to find the decl from 2395 the statement in ipa_saved_clone_sources. 2396 * cgraphunit.c: Include ipa-inline.h. 2397 (expand_all_functions): Free ipa_saved_clone_sources. 2398 23992020-04-16 Richard Sandiford <richard.sandiford@arm.com> 2400 2401 PR target/94606 2402 * config/aarch64/aarch64.c (aarch64_expand_sve_const_pred_eor): Take 2403 the VNx16BI lowpart of the recursively-generated constant. 2404 24052020-04-16 Martin Liska <mliska@suse.cz> 2406 Jakub Jelinek <jakub@redhat.com> 2407 2408 PR c++/94314 2409 * cgraphclones.c (set_new_clone_decl_and_node_flags): Drop 2410 DECL_IS_REPLACEABLE_OPERATOR during cloning. 2411 * tree-ssa-dce.c (valid_new_delete_pair_p): New function. 2412 (propagate_necessity): Check operator names. 2413 24142020-04-16 Richard Sandiford <richard.sandiford@arm.com> 2415 2416 PR rtl-optimization/94605 2417 * early-remat.c (early_remat::process_block): Handle insns that 2418 set multiple candidate registers. 24192020-04-16 Jan Hubicka <hubicka@ucw.cz> 2420 2421 PR gcov-profile/93401 2422 * common.opt (profile-prefix-path): New option. 2423 * coverae.c: Include diagnostics.h. 2424 (coverage_init): Strip profile prefix path. 2425 * doc/invoke.texi (-fprofile-prefix-path): Document. 2426 24272020-04-16 Richard Biener <rguenther@suse.de> 2428 2429 PR middle-end/94614 2430 * expr.c (emit_move_multi_word): Do not generate code when 2431 the destination part is undefined_operand_subword_p. 2432 * lower-subreg.c (resolve_clobber): Look through a paradoxica 2433 subreg. 2434 24352020-04-16 Martin Jambor <mjambor@suse.cz> 2436 2437 PR tree-optimization/94598 2438 * tree-sra.c (verify_sra_access_forest): Fix verification of total 2439 scalarization accesses under access to one-element arrays. 2440 24412020-04-16 Jakub Jelinek <jakub@redhat.com> 2442 2443 PR bootstrap/89494 2444 * function.c (assign_parm_find_data_types): Add workaround for 2445 BROKEN_VALUE_INITIALIZATION compilers. 2446 24472020-04-16 Richard Biener <rguenther@suse.de> 2448 2449 * gdbhooks.py (TreePrinter): Print SSA_NAME_VERSION of SSA_NAME 2450 nodes. 2451 24522020-04-15 Uroš Bizjak <ubizjak@gmail.com> 2453 2454 PR target/94603 2455 * config/i386/i386-builtin.def (__builtin_ia32_movq128): 2456 Require OPTION_MASK_ISA_SSE2. 2457 24582020-04-15 Gustavo Romero <gromero@linux.ibm.com> 2459 2460 PR bootstrap/89494 2461 * dumpfile.c (selftest::temp_dump_context::temp_dump_context): 2462 Don't construct a dump_context temporary to call static method. 2463 24642020-04-15 Andrea Corallo <andrea.corallo@arm.com> 2465 2466 * config/aarch64/falkor-tag-collision-avoidance.c 2467 (valid_src_p): Check for aarch64_address_info type before 2468 accessing base field. 2469 24702020-04-15 Andre Vieira <andre.simoesdiasvieira@arm.com> 2471 2472 * config/arm/mve.md (mve_vec_duplicate<mode>): New pattern. 2473 (V_sz_elem2): Remove unused mode attribute. 2474 24752020-04-15 Matthew Malcomson <matthew.malcomson@arm.com> 2476 2477 * config/arm/arm.md (arm_movdi): Disallow for MVE. 2478 24792020-04-15 Richard Biener <rguenther@suse.de> 2480 2481 PR middle-end/94539 2482 * tree-ssa-alias.c (same_type_for_tbaa): Defer to 2483 alias_sets_conflict_p for pointers. 2484 24852020-04-14 Max Filippov <jcmvbkbc@gmail.com> 2486 2487 PR target/94584 2488 * config/xtensa/xtensa.md (zero_extendhisi2, zero_extendqisi2) 2489 (extendhisi2_internal): Add %v1 before the load instructions. 2490 24912020-04-14 Aaron Sawdey <acsawdey@linux.ibm.com> 2492 2493 PR target/94542 2494 * config/rs6000/rs6000.c (address_to_insn_form): Do not attempt to 2495 use PC-relative addressing for TLS references. 2496 24972020-04-14 Martin Jambor <mjambor@suse.cz> 2498 2499 PR ipa/94434 2500 * ipa-sra.c: Include internal-fn.h. 2501 (enum isra_scan_context): Update comment. 2502 (scan_function): Treat calls to internal_functions like loads or stores. 2503 25042020-04-14 Yang Yang <yangyang305@huawei.com> 2505 2506 PR tree-optimization/94574 2507 * tree-ssa.c (non_rewritable_lvalue_p): Add size check when analyzing 2508 whether a vector-insert is rewritable using a BIT_INSERT_EXPR. 2509 25102020-04-14 H.J. Lu <hongjiu.lu@intel.com> 2511 2512 PR target/94561 2513 * config/i386/i386.c (ix86_get_ssemov): Remove mode size check. 2514 25152020-04-13 Martin Sebor <msebor@redhat.com> 2516 2517 * doc/extend.texi (-Wall): Mention -Wformat-overflow and 2518 -Wformat-truncation. Move -Wzero-length-bounds last. 2519 (-Wrestrict): Document positive form of option enabled by -Wall. 2520 25212020-04-13 Zachary Spytz <zspytz@gmail.com> 2522 2523 * doc/extend.texi: Add realloc to list of built-in functions 2524 are recognized by the compiler. 2525 25262020-04-13 H.J. Lu <hongjiu.lu@intel.com> 2527 2528 PR target/94556 2529 * config/i386/i386.c (ix86_expand_epilogue): Restore the frame 2530 pointer in word_mode for eh_return epilogues. 2531 25322020-04-13 Jozef Lawrynowicz <jozef.l@mittosystems.com> 2533 2534 * config/msp430/msp430.c (msp430_print_operand): Don't add offsets to 2535 memory references in %B, %C and %D operand selectors when the inner 2536 operand is a post increment address. 2537 25382020-04-13 Jozef Lawrynowicz <jozef.l@mittosystems.com> 2539 2540 * config/msp430/msp430.c (msp430_print_operand): Offset a %C memory 2541 reference by 4 bytes, and %D memory reference by 6 bytes. 2542 25432020-04-11 Uroš Bizjak <ubizjak@gmail.com> 2544 2545 PR target/94494 2546 * config/i386/sse.md (REDUC_SSE_SMINMAX_MODE): Use TARGET_SSE2 2547 condition for V4SI, V8HI and V16QI modes. 2548 25492020-04-11 Jakub Jelinek <jakub@redhat.com> 2550 2551 PR debug/94495 2552 PR target/94551 2553 * cselib.c (cselib_record_sp_cfa_base_equiv): Set PRESERVED_VALUE_P on 2554 val->val_rtx. 2555 25562020-04-10 Thomas Schwinge <thomas@codesourcery.com> 2557 2558 PR middle-end/89433 2559 PR middle-end/93465 2560 * omp-general.c (oacc_verify_routine_clauses): Diagnose if 2561 "#pragma omp declare target" has also been applied. 2562 25632020-04-09 Jozef Lawrynowicz <jozef.l@mittosystems.com> 2564 2565 * config/msp430/msp430.c (msp430_expand_epilogue): Use emit_jump_insn 2566 when to emit the epilogue_helper insn. 2567 * config/msp430/msp430.md (epilogue_helper): Add a return insn to the 2568 RTL pattern. 2569 25702020-04-09 Jakub Jelinek <jakub@redhat.com> 2571 2572 PR debug/94495 2573 * cselib.h (cselib_record_sp_cfa_base_equiv, 2574 cselib_sp_derived_value_p): Declare. 2575 * cselib.c (cselib_record_sp_cfa_base_equiv, 2576 cselib_sp_derived_value_p): New functions. 2577 * var-tracking.c (add_stores): Don't record MO_VAL_SET for 2578 cselib_sp_derived_value_p values. 2579 (vt_initialize): Call cselib_record_sp_cfa_base_equiv at the 2580 start of extended basic blocks other than the first one 2581 for !frame_pointer_needed functions. 2582 25832020-04-09 Richard Sandiford <richard.sandiford@arm.com> 2584 2585 * doc/sourcebuild.texi (aarch64_sve_hw, aarch64_sve128_hw) 2586 (aarch64_sve256_hw, aarch64_sve512_hw, aarch64_sve1024_hw) 2587 (aarch64_sve2048_hw): Document. 2588 * config/aarch64/aarch64-protos.h 2589 (aarch64_sve::handle_arm_sve_vector_bits_attribute): Declare. 2590 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define 2591 __ARM_FEATURE_SVE_VECTOR_OPERATIONS when SVE is enabled. 2592 * config/aarch64/aarch64-sve-builtins.cc (matches_type_p): New 2593 function. 2594 (find_type_suffix_for_scalar_type): Use it instead of comparing 2595 TYPE_MAIN_VARIANTs. 2596 (function_resolver::infer_vector_or_tuple_type): Likewise. 2597 (function_resolver::require_vector_type): Likewise. 2598 (handle_arm_sve_vector_bits_attribute): New function. 2599 * config/aarch64/aarch64.c (pure_scalable_type_info): New class. 2600 (aarch64_attribute_table): Add arm_sve_vector_bits. 2601 (aarch64_return_in_memory_1): 2602 (pure_scalable_type_info::piece::get_rtx): New function. 2603 (pure_scalable_type_info::num_zr): Likewise. 2604 (pure_scalable_type_info::num_pr): Likewise. 2605 (pure_scalable_type_info::get_rtx): Likewise. 2606 (pure_scalable_type_info::analyze): Likewise. 2607 (pure_scalable_type_info::analyze_registers): Likewise. 2608 (pure_scalable_type_info::analyze_array): Likewise. 2609 (pure_scalable_type_info::analyze_record): Likewise. 2610 (pure_scalable_type_info::add_piece): Likewise. 2611 (aarch64_some_values_include_pst_objects_p): Likewise. 2612 (aarch64_returns_value_in_sve_regs_p): Use pure_scalable_type_info 2613 to analyze whether the type is returned in SVE registers. 2614 (aarch64_takes_arguments_in_sve_regs_p): Likwise whether the type 2615 is passed in SVE registers. 2616 (aarch64_pass_by_reference_1): New function, extracted from... 2617 (aarch64_pass_by_reference): ...here. Use pure_scalable_type_info 2618 to analyze whether the type is a pure scalable type and, if so, 2619 whether it should be passed by reference. 2620 (aarch64_return_in_msb): Return false for pure scalable types. 2621 (aarch64_function_value_1): Fold back into... 2622 (aarch64_function_value): ...this function. Use 2623 pure_scalable_type_info to analyze whether the type is a pure 2624 scalable type and, if so, which registers it should use. Handle 2625 types that include pure scalable types but are not themselves 2626 pure scalable types. 2627 (aarch64_return_in_memory_1): New function, split out from... 2628 (aarch64_return_in_memory): ...here. Use pure_scalable_type_info 2629 to analyze whether the type is a pure scalable type and, if so, 2630 whether it should be returned by reference. 2631 (aarch64_layout_arg): Remove orig_mode argument. Use 2632 pure_scalable_type_info to analyze whether the type is a pure 2633 scalable type and, if so, which registers it should use. Handle 2634 types that include pure scalable types but are not themselves 2635 pure scalable types. 2636 (aarch64_function_arg): Update call accordingly. 2637 (aarch64_function_arg_advance): Likewise. 2638 (aarch64_pad_reg_upward): On big-endian targets, return false for 2639 pure scalable types that are smaller than 16 bytes. 2640 (aarch64_member_type_forces_blk): New function. 2641 (aapcs_vfp_sub_candidate): Exit early for built-in SVE types. 2642 (aarch64_short_vector_p): Return false for VECTOR_TYPEs that 2643 correspond to built-in SVE types. Do not rely on a vector mode 2644 if the type includes an pure scalable type. When returning true, 2645 assert that the mode is not an SVE mode. 2646 (aarch64_vfp_is_call_or_return_candidate): Do not check for SVE 2647 built-in types here. When returning true, assert that the type 2648 does not have an SVE mode. 2649 (aarch64_can_change_mode_class): Don't allow anything to change 2650 between a predicate mode and a non-predicate mode. Also don't 2651 allow changes between SVE vector modes and other modes that 2652 might be bigger than 128 bits. 2653 (aarch64_invalid_binary_op): Reject binary operations that mix 2654 SVE and GNU vector types. 2655 (TARGET_MEMBER_TYPE_FORCES_BLK): Define. 2656 26572020-04-09 Richard Sandiford <richard.sandiford@arm.com> 2658 2659 * config/aarch64/aarch64.c (aarch64_attribute_table): Add 2660 "SVE sizeless type". 2661 * config/aarch64/aarch64-sve-builtins.cc (make_type_sizeless) 2662 (sizeless_type_p): New functions. 2663 (register_builtin_types): Apply make_type_sizeless to the type. 2664 (register_tuple_type): Likewise. 2665 (verify_type_context): Use sizeless_type_p instead of builin_type_p. 2666 26672020-04-09 Matthew Malcomson <matthew.malcomson@arm.com> 2668 2669 * config/arm/arm_cde.h: Remove `extern "C"` when compiling for 2670 C++. 2671 26722020-04-09 Martin Jambor <mjambor@suse.cz> 2673 Richard Biener <rguenther@suse.de> 2674 2675 PR tree-optimization/94482 2676 * tree-sra.c (create_access_replacement): Dump new replacement with 2677 TDF_UID. 2678 (sra_modify_expr): Fix handling of cases when the original EXPR writes 2679 to only part of the replacement. 2680 * tree-ssa-forwprop.c (pass_forwprop::execute): Properly verify 2681 the first operand of combinations into REAL/IMAGPART_EXPR and 2682 BIT_FIELD_REF. 2683 26842020-04-09 Richard Sandiford <richard.sandiford@arm.com> 2685 2686 * doc/sourcebuild.texi (check-function-bodies): Treat the third 2687 parameter as a list of option regexps and require each regexp 2688 to match. 2689 26902020-04-09 Andrea Corallo <andrea.corallo@arm.com> 2691 2692 PR target/94530 2693 * config/aarch64/falkor-tag-collision-avoidance.c 2694 (valid_src_p): Fix missing rtx type check. 2695 26962020-04-09 Bin Cheng <bin.cheng@linux.alibaba.com> 2697 Richard Biener <rguenther@suse.de> 2698 2699 PR tree-optimization/93674 2700 * tree-ssa-loop-ivopts.c (langhooks.h): New include. 2701 (add_iv_candidate_for_use): For iv_use of non integer or pointer type, 2702 or non-mode precision type, add candidate in unsigned type with the 2703 same precision. 2704 27052020-04-08 Clement Chigot <clement.chigot@atos.net> 2706 2707 * config/rs6000/aix61.h (LIB_SPEC): Add -lc128 with -mlong-double-128. 2708 * config/rs6000/aix71.h (LIB_SPEC): Likewise. 2709 * config/rs6000/aix72.h (LIB_SPEC): Likewise. 2710 27112020-04-08 Jakub Jelinek <jakub@redhat.com> 2712 2713 PR middle-end/94526 2714 * cselib.c (autoinc_split): Handle e->val_rtx being SP_DERIVED_VALUE_P 2715 with zero offset. 2716 * reload1.c (eliminate_regs_1): Avoid creating 2717 (plus (reg) (const_int 0)) in DEBUG_INSNs. 2718 2719 PR tree-optimization/94524 2720 * tree-vect-generic.c (expand_vector_divmod): If any elt of op1 is 2721 negative for signed TRUNC_MOD_EXPR, multiply with absolute value of 2722 op1 rather than op1 itself at the end. Punt for signed modulo by 2723 most negative constant. 2724 * tree-vect-patterns.c (vect_recog_divmod_pattern): Punt for signed 2725 modulo by most negative constant. 2726 27272020-04-08 Richard Biener <rguenther@suse.de> 2728 2729 PR rtl-optimization/93946 2730 * cse.c (cse_insn): Record the tabled expression in 2731 src_related. Verify a redundant store removal is valid. 2732 27332020-04-08 H.J. Lu <hongjiu.lu@intel.com> 2734 2735 PR target/94417 2736 * config/i386/i386-features.c (rest_of_insert_endbranch): Insert 2737 ENDBR at function entry if function will be called indirectly. 2738 27392020-04-08 Jakub Jelinek <jakub@redhat.com> 2740 2741 PR target/94438 2742 * config/i386/i386.c (ix86_get_mask_mode): Only use int mask for elem_size 2743 1, 2, 4 and 8. 2744 27452020-04-08 Martin Liska <mliska@suse.cz> 2746 2747 PR c++/94314 2748 * gimple.c (gimple_call_operator_delete_p): Rename to... 2749 (gimple_call_replaceable_operator_delete_p): ... this. 2750 Use DECL_IS_REPLACEABLE_OPERATOR_DELETE_P. 2751 * gimple.h (gimple_call_operator_delete_p): Rename to ... 2752 (gimple_call_replaceable_operator_delete_p): ... this. 2753 * tree-core.h (tree_function_decl): Add replaceable_operator 2754 flag. 2755 * tree-ssa-dce.c (mark_all_reaching_defs_necessary_1): 2756 Use DECL_IS_REPLACEABLE_OPERATOR_DELETE_P. 2757 (propagate_necessity): Use gimple_call_replaceable_operator_delete_p. 2758 (eliminate_unnecessary_stmts): Likewise. 2759 * tree-streamer-in.c (unpack_ts_function_decl_value_fields): 2760 Pack DECL_IS_REPLACEABLE_OPERATOR. 2761 * tree-streamer-out.c (pack_ts_function_decl_value_fields): 2762 Unpack the field here. 2763 * tree.h (DECL_IS_REPLACEABLE_OPERATOR): New. 2764 (DECL_IS_REPLACEABLE_OPERATOR_NEW_P): New. 2765 (DECL_IS_REPLACEABLE_OPERATOR_DELETE_P): New. 2766 * cgraph.c (cgraph_node::dump): Dump if an operator is replaceable. 2767 * ipa-icf.c (sem_item::compare_referenced_symbol_properties): Compare 2768 replaceable operator flags. 2769 27702020-04-08 Dennis Zhang <dennis.zhang@arm.com> 2771 Matthew Malcomson <matthew.malcomson@arm.com> 2772 2773 * config/arm/arm-builtins.c (CX_IMM_QUALIFIERS): New macro. 2774 (CX_UNARY_QUALIFIERS, CX_BINARY_QUALIFIERS): Likewise. 2775 (CX_TERNARY_QUALIFIERS): Likewise. 2776 (ARM_BUILTIN_CDE_PATTERN_START): Likewise. 2777 (ARM_BUILTIN_CDE_PATTERN_END): Likewise. 2778 (arm_init_acle_builtins): Initialize CDE builtins. 2779 (arm_expand_acle_builtin): Check CDE constant operands. 2780 * config/arm/arm.h (ARM_CDE_CONST_COPROC): New macro to set the range 2781 of CDE constant operand. 2782 * config/arm/arm.c (arm_hard_regno_mode_ok): Support DImode for 2783 TARGET_VFP_BASE. 2784 (ARM_VCDE_CONST_1, ARM_VCDE_CONST_2, ARM_VCDE_CONST_3): Likewise. 2785 * config/arm/arm_cde.h (__arm_vcx1_u32): New macro of ACLE interface. 2786 (__arm_vcx1a_u32, __arm_vcx2_u32, __arm_vcx2a_u32): Likewise. 2787 (__arm_vcx3_u32, __arm_vcx3a_u32, __arm_vcx1d_u64): Likewise. 2788 (__arm_vcx1da_u64, __arm_vcx2d_u64, __arm_vcx2da_u64): Likewise. 2789 (__arm_vcx3d_u64, __arm_vcx3da_u64): Likewise. 2790 * config/arm/arm_cde_builtins.def: New file. 2791 * config/arm/iterators.md (V_reg): New attribute of SI. 2792 * config/arm/predicates.md (const_int_coproc_operand): New. 2793 (const_int_vcde1_operand, const_int_vcde2_operand): New. 2794 (const_int_vcde3_operand): New. 2795 * config/arm/unspecs.md (UNSPEC_VCDE, UNSPEC_VCDEA): New. 2796 * config/arm/vfp.md (arm_vcx1<mode>): New entry. 2797 (arm_vcx1a<mode>, arm_vcx2<mode>, arm_vcx2a<mode>): Likewise. 2798 (arm_vcx3<mode>, arm_vcx3a<mode>): Likewise. 2799 28002020-04-08 Dennis Zhang <dennis.zhang@arm.com> 2801 2802 * config.gcc: Add arm_cde.h. 2803 * config/arm/arm-c.c (arm_cpu_builtins): Define or undefine 2804 __ARM_FEATURE_CDE and __ARM_FEATURE_CDE_COPROC. 2805 * config/arm/arm-cpus.in (cdecp0, cdecp1, ..., cdecp7): New options. 2806 * config/arm/arm.c (arm_option_reconfigure_globals): Configure 2807 arm_arch_cde and arm_arch_cde_coproc to store the feature bits. 2808 * config/arm/arm.h (TARGET_CDE): New macro. 2809 * config/arm/arm_cde.h: New file. 2810 * doc/invoke.texi: Document CDE options +cdecp[0-7]. 2811 * doc/sourcebuild.texi (arm_v8m_main_cde_ok): Document new target 2812 supports option. 2813 (arm_v8m_main_cde_fp, arm_v8_1m_main_cde_mve): Likewise. 2814 28152020-04-08 Jakub Jelinek <jakub@redhat.com> 2816 2817 PR rtl-optimization/94516 2818 * postreload.c: Include rtl-iter.h. 2819 (reload_cse_move2add): Handle SP autoinc here by FOR_EACH_SUBRTX_VAR 2820 looking for all MEMs with RTX_AUTOINC operand. 2821 (move2add_note_store): Remove {PRE,POST}_{INC,DEC} handling. 2822 28232020-04-08 Tobias Burnus <tobias@codesourcery.com> 2824 2825 * omp-grid.c (grid_eliminate_combined_simd_part): Use 2826 OMP_CLAUSE_CODE to access the omp clause code. 2827 28282020-04-07 Jeff Law <law@redhat.com> 2829 2830 PR rtl-optimization/92264 2831 * config/h8300/h8300.md (mov;add peephole2): Avoid applying when 2832 the destination is the stack pointer. 2833 28342020-04-07 Jakub Jelinek <jakub@redhat.com> 2835 2836 PR rtl-optimization/94291 2837 PR rtl-optimization/84169 2838 * combine.c (try_combine): For split_i2i3, don't assume SET_DEST 2839 must be a REG or SUBREG of REG; if it is not one of these, don't 2840 update LOG_LINKs. 2841 28422020-04-07 Richard Biener <rguenther@suse.de> 2843 2844 PR middle-end/94479 2845 * gimplify.c (gimplify_addr_expr): Also consider generated 2846 MEM_REFs. 2847 28482020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com> 2849 2850 * config/arm/arm_mve.h: Add C++ polymorphism and fix preserve MACROs. 2851 28522020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com> 2853 2854 * config/arm/arm_mve.h: Cast some pointers to expected types. 2855 28562020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com> 2857 2858 * config/arm/arm_mve.h: Replace all uses of vuninitializedq_* with the 2859 same with '__arm_' prefix. 2860 28612020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com> 2862 2863 * config/arm/mve.md (mve_vec_extract*): Allow memory operands in set. 2864 28652020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com> 2866 2867 * config/arm/arm.c (arm_mve_immediate_check): Removed. 2868 * config/arm/mve.md (MVE_pred2, MVE_constraint2): Added FP types. 2869 (mve_vcvtq_n_to_f_*, mve_vcvtq_n_from_f_*, mve_vqshrnbq_n_*, 2870 mve_vqshrntq_n_*, mve_vqshrunbq_n_s*, mve_vqshruntq_n_s*, 2871 mve_vcvtq_m_n_from_f_*, mve_vcvtq_m_n_to_f_*, mve_vqshrnbq_m_n_*, 2872 mve_vqrshruntq_m_n_s*, mve_vqshrunbq_m_n_s*, 2873 mve_vqshruntq_m_n_s*): Fixed immediate constraints. 2874 28752020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com> 2876 2877 * config/arm/arm.d (ashldi3): Don't use lsll for constant 32-bit shifts. 2878 28792020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com> 2880 2881 * config/arm/arm_mve.h: Fix v[id]wdup intrinsics. 2882 * config/arm/mve/md: Fix v[id]wdup patterns. 2883 28842020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com> 2885 2886 * config/arm/arm.c (output_move_neon): Deal with label + offset cases. 2887 * config/arm/mve.md (*mve_mov<mode>): Handle const vectors. 2888 28892020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com> 2890 2891 * config/arm/arm_mve.h: Remove use of typeof for addr pointer parameters 2892 and remove const_ptr enums. 2893 28942020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com> 2895 2896 * config/arm/arm_mve.h (vsubq_n): Merge with... 2897 (vsubq): ... this. 2898 (vmulq_n): Merge with... 2899 (vmulq): ... this. 2900 (__ARM_mve_typeid): Simplify scalar and constant detection. 2901 29022020-04-07 Jakub Jelinek <jakub@redhat.com> 2903 2904 PR target/94509 2905 * config/i386/i386-expand.c (expand_vec_perm_pshufb): Fix the check 2906 for inter-lane permutation for 64-byte modes. 2907 2908 PR target/94488 2909 * config/aarch64/aarch64-simd.md (ashl<mode>3, lshr<mode>3, 2910 ashr<mode>3): Force operands[2] into reg whenever it is not CONST_INT. 2911 Assume it is a REG after that instead of testing it and doing FAIL 2912 otherwise. Formatting fix. 2913 29142020-04-07 Sebastian Huber <sebastian.huber@embedded-brains.de> 2915 2916 * config/rs6000/t-rtems: Delete mcpu=8540 multilib. 2917 29182020-04-07 Jakub Jelinek <jakub@redhat.com> 2919 2920 PR target/94500 2921 * config/i386/i386-expand.c (emit_reduc_half): For V{64QI,32HI}mode 2922 handle i < 64 using avx512bw_lshrv4ti3. Formatting fixes. 2923 29242020-04-06 Jakub Jelinek <jakub@redhat.com> 2925 2926 * cselib.c (cselib_subst_to_values): For SP_DERIVED_VALUE_P 2927 + const0_rtx return the SP_DERIVED_VALUE_P. 2928 29292020-04-06 Richard Sandiford <richard.sandiford@arm.com> 2930 2931 PR rtl-optimization/92989 2932 * lra-lives.c (process_bb_lives): Do not treat eh_return data 2933 registers as being live at the beginning of the EH receiver. 2934 29352020-04-05 Zachary Spytz <zspytz@gmail.com> 2936 2937 * extend.texi: Add free to list of ISO C90 functions that 2938 are recognized by the compiler. 2939 29402020-04-05 Nagaraju Mekala <nmekala@xilix.com> 2941 2942 * config/microblaze/microblaze.c (microblaze_must_save_register): Check 2943 for fast_interrupt. 2944 2945 * config/microblaze/microblaze.md (trap): Update output pattern. 2946 29472020-04-04 Hannes Domani <ssbssa@yahoo.de> 2948 Jakub Jelinek <jakub@redhat.com> 2949 2950 PR debug/94459 2951 * dwarf2out.c (gen_subprogram_die): Look through references, pointers, 2952 arrays, pointer-to-members, function types and qualifiers when 2953 checking if in-class DIE had an 'auto' or 'decltype(auto)' return type 2954 to emit type again on definition. 2955 29562020-04-04 Jan Hubicka <hubicka@ucw.cz> 2957 2958 PR ipa/93940 2959 * ipa-fnsummary.c (vrp_will_run_p): New function. 2960 (fre_will_run_p): New function. 2961 (evaluate_properties_for_edge): Use it. 2962 * ipa-inline.c (can_inline_edge_by_limits_p): Do not inline 2963 !optimize_debug to optimize_debug. 2964 29652020-04-04 Jakub Jelinek <jakub@redhat.com> 2966 2967 PR rtl-optimization/94468 2968 * cselib.c (references_value_p): Formatting fix. 2969 (cselib_useless_value_p): New function. 2970 (discard_useless_locs, discard_useless_values, 2971 cselib_invalidate_regno_val, cselib_invalidate_mem, 2972 cselib_record_set): Use it instead of 2973 v->locs == 0 && !PRESERVED_VALUE_P (v->val_rtx). 2974 2975 PR debug/94441 2976 * tree-iterator.h (expr_single): Declare. 2977 * tree-iterator.c (expr_single): New function. 2978 * tree.h (protected_set_expr_location_if_unset): Declare. 2979 * tree.c (protected_set_expr_location): Use expr_single. 2980 (protected_set_expr_location_if_unset): New function. 2981 29822020-04-03 Jeff Law <law@redhat.com> 2983 2984 PR rtl-optimization/92264 2985 * config/stormy16/stormy16.c (xstormy16_preferred_reload_class): Handle 2986 reloading of auto-increment addressing modes. 2987 29882020-04-03 H.J. Lu <hongjiu.lu@intel.com> 2989 2990 PR target/94467 2991 * config/i386/sse.md (ssse3_pshufbv8qi3): Mark scratch operand 2992 as earlyclobber. 2993 29942020-04-03 Jeff Law <law@redhat.com> 2995 2996 PR rtl-optimization/92264 2997 * config/m32r/m32r.c (m32r_output_block_move): Properly account for 2998 post-increment addressing of source operands as well as residuals 2999 when computing any adjustments to the input pointer. 3000 30012020-04-03 Jakub Jelinek <jakub@redhat.com> 3002 3003 PR target/94460 3004 * config/i386/sse.md (avx2_ph<plusminus_mnemonic>wv16hi3, 3005 avx2_ph<plusminus_mnemonic>dv8si3): Fix up RTL pattern to do 3006 second half of first lane from first lane of second operand and 3007 first half of second lane from second lane of first operand. 3008 30092020-04-03 Andre Vieira <andre.simoesdiasvieira@arm.com> 3010 3011 * config/arm/arm_mve.h: Condition the header file on __ARM_FEATURE_MVE. 3012 30132020-04-03 Tamar Christina <tamar.christina@arm.com> 3014 3015 PR target/94396 3016 * common/config/aarch64/aarch64-common.c 3017 (aarch64_get_extension_string_for_isa_flags): Handle default flags. 3018 30192020-04-03 Richard Biener <rguenther@suse.de> 3020 3021 PR middle-end/94465 3022 * tree.c (array_ref_low_bound): Deal with released SSA names 3023 in index position. 3024 30252020-04-03 Kwok Cheung Yeung <kcy@codesourcery.com> 3026 3027 * config/gcn/gcn.c (print_operand): Handle unordered comparison 3028 operators. 3029 * config/gcn/predicates.md (gcn_fp_compare_operator): Add unordered 3030 comparison operators. 3031 30322020-04-03 Kewen Lin <linkw@gcc.gnu.org> 3033 3034 PR tree-optimization/94443 3035 * tree-vect-loop.c (vectorizable_live_operation): Use 3036 gsi_insert_seq_before to replace gsi_insert_before. 3037 30382020-04-03 Martin Liska <mliska@suse.cz> 3039 3040 PR ipa/94445 3041 * ipa-icf-gimple.c (func_checker::compare_gimple_call): 3042 Compare type attributes for gimple_call_fntypes. 3043 30442020-04-02 Sandra Loosemore <sandra@codesourcery.com> 3045 3046 * alias.c (get_alias_set): Fix comment typos. 3047 30482020-04-02 Fritz Reese <foreese@gcc.gnu.org> 3049 3050 PR fortran/85982 3051 * fortran/decl.c (match_attr_spec): Lump COMP_STRUCTURE/COMP_MAP into 3052 attribute checking used by TYPE. 3053 30542020-04-02 Martin Jambor <mjambor@suse.cz> 3055 3056 PR ipa/92676 3057 * ipa-sra.c (struct caller_issues): New fields candidate and 3058 call_from_outside_comdat. 3059 (check_for_caller_issues): Check for calls from outsied of 3060 candidate's same_comdat_group. 3061 (check_all_callers_for_issues): Set up issues.candidate, check result 3062 of the new check. 3063 (mark_callers_calls_comdat_local): New function. 3064 (process_isra_node_results): Set calls_comdat_local of callers if 3065 appropriate. 3066 30672020-04-02 Richard Biener <rguenther@suse.de> 3068 3069 PR c/94392 3070 * common.opt (ffinite-loops): Initialize to zero. 3071 * opts.c (default_options_table): Remove OPT_ffinite_loops 3072 entry. 3073 * cfgloop.h (loop::finite_p): New member. 3074 * cfgloopmanip.c (copy_loop_info): Copy finite_p. 3075 * ipa-icf-gimple.c (func_checker::compare_loops): Compare 3076 finite_p. 3077 * lto-streamer-in.c (input_cfg): Stream finite_p. 3078 * lto-streamer-out.c (output_cfg): Likewise. 3079 * tree-cfg.c (replace_loop_annotate): Initialize finite_p 3080 from flag_finite_loops at CFG build time. 3081 * tree-ssa-loop-niter.c (finite_loop_p): Check the loops 3082 finite_p flag instead of flag_finite_loops. 3083 * doc/invoke.texi (ffinite-loops): Adjust documentation of 3084 default setting. 3085 30862020-04-02 Richard Biener <rguenther@suse.de> 3087 3088 PR debug/94450 3089 * dwarf2out.c (dwarf2out_early_finish): Remove code emitting 3090 DW_TAG_imported_unit. 3091 30922020-04-02 Maciej W. Rozycki <macro@wdc.com> 3093 3094 * doc/install.texi (Specific) <riscv32-*-elf, riscv32-*-linux> 3095 <riscv64-*-elf, riscv64-*-linux>: Update binutils requirement to 3096 2.30. 3097 30982020-04-02 Kewen Lin <linkw@gcc.gnu.org> 3099 3100 PR tree-optimization/94401 3101 * tree-vect-loop.c (vectorizable_load): Handle VMAT_CONTIGUOUS_REVERSE 3102 access type when loading halves of vector to avoid peeling for gaps. 3103 31042020-04-02 Jakub Jelinek <jakub@redhat.com> 3105 3106 * config/mips/mti-linux.h (SYSROOT_SUFFIX_SPEC): Add a space in 3107 between a string literal and MIPS_SYSVERSION_SPEC macro. 3108 31092020-04-02 Martin Jambor <mjambor@suse.cz> 3110 3111 * doc/invoke.texi (Optimize Options): Document sra-max-propagations. 3112 31132020-04-02 Jakub Jelinek <jakub@redhat.com> 3114 3115 PR rtl-optimization/92264 3116 * params.opt (-param=max-find-base-term-values=): Decrease default 3117 from 2000 to 200. 3118 3119 PR rtl-optimization/92264 3120 * rtl.h (struct rtx_def): Mention that call bit is used as 3121 SP_DERIVED_VALUE_P in cselib.c. 3122 * cselib.c (SP_DERIVED_VALUE_P): Define. 3123 (PRESERVED_VALUE_P, SP_BASED_VALUE_P): Move definitions earlier. 3124 (cselib_hasher::equal): Handle equality between SP_DERIVED_VALUE_P 3125 val_rtx and sp based expression where offsets cancel each other. 3126 (preserve_constants_and_equivs): Formatting fix. 3127 (cselib_reset_table): Add reverse op loc to SP_DERIVED_VALUE_P 3128 locs list for cfa_base_preserved_val if needed. Formatting fix. 3129 (autoinc_split): If the to be returned value is a REG, MEM or 3130 VALUE which has SP_DERIVED_VALUE_P + CONST_INT as one of its 3131 locs, return the SP_DERIVED_VALUE_P VALUE and adjust *off. 3132 (rtx_equal_for_cselib_1): Call autoinc_split even if both 3133 expressions are PLUS in Pmode with CONST_INT second operands. 3134 Handle SP_DERIVED_VALUE_P cases. 3135 (cselib_hash_plus_const_int): New function. 3136 (cselib_hash_rtx): Use it for PLUS in Pmode with CONST_INT 3137 second operand, as well as for PRE_DEC etc. that ought to be 3138 hashed the same way. 3139 (cselib_subst_to_values): Substitute PLUS with Pmode and 3140 CONST_INT operand if the first operand is a VALUE which has 3141 SP_DERIVED_VALUE_P + CONST_INT as one of its locs for the 3142 SP_DERIVED_VALUE_P + adjusted offset. 3143 (cselib_lookup_1): When creating a new VALUE for stack_pointer_rtx, 3144 set SP_DERIVED_VALUE_P on it. Set PRESERVED_VALUE_P when adding 3145 SP_DERIVED_VALUE_P PRESERVED_VALUE_P subseted VALUE location. 3146 * var-tracking.c (vt_initialize): Call cselib_add_permanent_equiv 3147 on the sp value before calling cselib_add_permanent_equiv on the 3148 cfa_base value. 3149 * dse.c (check_for_inc_dec_1, check_for_inc_dec): Punt on RTX_AUTOINC 3150 in the insn without REG_INC note. 3151 (replace_read): Punt on RTX_AUTOINC in the *loc being replaced. 3152 Punt on invalid insns added by copy_to_mode_reg. Formatting fixes. 3153 3154 PR target/94435 3155 * config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): For 3156 y_mode E_[QH]Imode and y being a CONST_INT, change y_mode to SImode. 3157 31582020-04-02 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 3159 3160 PR target/94317 3161 * config/arm/arm-builtins.c (LDRGBWBXU_QUALIFIERS): Define. 3162 (LDRGBWBXU_Z_QUALIFIERS): Likewise. 3163 * config/arm/arm_mve.h (__arm_vldrdq_gather_base_wb_s64): Modify 3164 intrinsic defintion by adding a new builtin call to writeback into base 3165 address. 3166 (__arm_vldrdq_gather_base_wb_u64): Likewise. 3167 (__arm_vldrdq_gather_base_wb_z_s64): Likewise. 3168 (__arm_vldrdq_gather_base_wb_z_u64): Likewise. 3169 (__arm_vldrwq_gather_base_wb_s32): Likewise. 3170 (__arm_vldrwq_gather_base_wb_u32): Likewise. 3171 (__arm_vldrwq_gather_base_wb_z_s32): Likewise. 3172 (__arm_vldrwq_gather_base_wb_z_u32): Likewise. 3173 (__arm_vldrwq_gather_base_wb_f32): Likewise. 3174 (__arm_vldrwq_gather_base_wb_z_f32): Likewise. 3175 * config/arm/arm_mve_builtins.def (vldrwq_gather_base_wb_z_u): Modify 3176 builtin's qualifier. 3177 (vldrdq_gather_base_wb_z_u): Likewise. 3178 (vldrwq_gather_base_wb_u): Likewise. 3179 (vldrdq_gather_base_wb_u): Likewise. 3180 (vldrwq_gather_base_wb_z_s): Likewise. 3181 (vldrwq_gather_base_wb_z_f): Likewise. 3182 (vldrdq_gather_base_wb_z_s): Likewise. 3183 (vldrwq_gather_base_wb_s): Likewise. 3184 (vldrwq_gather_base_wb_f): Likewise. 3185 (vldrdq_gather_base_wb_s): Likewise. 3186 (vldrwq_gather_base_nowb_z_u): Define builtin. 3187 (vldrdq_gather_base_nowb_z_u): Likewise. 3188 (vldrwq_gather_base_nowb_u): Likewise. 3189 (vldrdq_gather_base_nowb_u): Likewise. 3190 (vldrwq_gather_base_nowb_z_s): Likewise. 3191 (vldrwq_gather_base_nowb_z_f): Likewise. 3192 (vldrdq_gather_base_nowb_z_s): Likewise. 3193 (vldrwq_gather_base_nowb_s): Likewise. 3194 (vldrwq_gather_base_nowb_f): Likewise. 3195 (vldrdq_gather_base_nowb_s): Likewise. 3196 * config/arm/mve.md (mve_vldrwq_gather_base_nowb_<supf>v4si): Define RTL 3197 pattern. 3198 (mve_vldrwq_gather_base_wb_<supf>v4si): Modify RTL pattern. 3199 (mve_vldrwq_gather_base_nowb_z_<supf>v4si): Define RTL pattern. 3200 (mve_vldrwq_gather_base_wb_z_<supf>v4si): Modify RTL pattern. 3201 (mve_vldrwq_gather_base_wb_fv4sf): Modify RTL pattern. 3202 (mve_vldrwq_gather_base_nowb_fv4sf): Define RTL pattern. 3203 (mve_vldrwq_gather_base_wb_z_fv4sf): Modify RTL pattern. 3204 (mve_vldrwq_gather_base_nowb_z_fv4sf): Define RTL pattern. 3205 (mve_vldrdq_gather_base_nowb_<supf>v4di): Define RTL pattern. 3206 (mve_vldrdq_gather_base_wb_<supf>v4di): Modify RTL pattern. 3207 (mve_vldrdq_gather_base_nowb_z_<supf>v4di): Define RTL pattern. 3208 (mve_vldrdq_gather_base_wb_z_<supf>v4di): Modify RTL pattern. 3209 32102020-04-02 Andreas Krebbel <krebbel@linux.ibm.com> 3211 3212 * config/s390/vector.md ("<ti*>add<mode>3", "mul<mode>3") 3213 ("and<mode>3", "notand<mode>3", "ior<mode>3", "ior_not<mode>3") 3214 ("xor<mode>3", "notxor<mode>3", "smin<mode>3", "smax<mode>3") 3215 ("umin<mode>3", "umax<mode>3", "vec_widen_smult_even_<mode>") 3216 ("vec_widen_umult_even_<mode>", "vec_widen_smult_odd_<mode>") 3217 ("vec_widen_umult_odd_<mode>", "add<mode>3", "sub<mode>3") 3218 ("mul<mode>3", "fma<mode>4", "fms<mode>4", "neg_fma<mode>4") 3219 ("neg_fms<mode>4", "*smax<mode>3_vxe", "*smaxv2df3_vx") 3220 ("*smin<mode>3_vxe", "*sminv2df3_vx"): Remove % constraint 3221 modifier. 3222 ("vec_widen_umult_lo_<mode>", "vec_widen_umult_hi_<mode>") 3223 ("vec_widen_smult_lo_<mode>", "vec_widen_smult_hi_<mode>"): 3224 Remove constraints from expander. 3225 * config/s390/vx-builtins.md ("vacc<bhfgq>_<mode>", "vacq") 3226 ("vacccq", "vec_avg<mode>", "vec_avgu<mode>", "vec_vmal<mode>") 3227 ("vec_vmah<mode>", "vec_vmalh<mode>", "vec_vmae<mode>") 3228 ("vec_vmale<mode>", "vec_vmao<mode>", "vec_vmalo<mode>") 3229 ("vec_smulh<mode>", "vec_umulh<mode>", "vec_nor<mode>3") 3230 ("vfmin<mode>", "vfmax<mode>"): Remove % constraint modifier. 3231 32322020-04-01 Peter Bergner <bergner@linux.ibm.com> 3233 3234 PR rtl-optimization/94123 3235 * lower-subreg.c (pass_lower_subreg3::gate): Remove test for 3236 flag_split_wide_types_early. 3237 32382020-04-01 Joerg Sonnenberger <joerg@bec.de> 3239 3240 * doc/extend.texi (Common Function Attributes): Fix typo. 3241 32422020-04-01 Segher Boessenkool <segher@kernel.crashing.org> 3243 3244 PR target/94420 3245 * config/rs6000/rs6000.md (*tocref<mode> for P): Add insn condition 3246 on operands[1]. 3247 32482020-04-01 Zackery Spytz <zspytz@gmail.com> 3249 3250 * doc/extend.texi: Fix a typo in the documentation of the 3251 copy function attribute. 3252 32532020-04-01 Jakub Jelinek <jakub@redhat.com> 3254 3255 PR middle-end/94423 3256 * tree-object-size.c (pass_object_sizes::execute): Don't call 3257 replace_uses_by for SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs, instead 3258 call replace_call_with_value. 3259 32602020-04-01 Kewen Lin <linkw@gcc.gnu.org> 3261 3262 PR tree-optimization/94043 3263 * tree-vect-loop.c (vectorizable_live_operation): Generate loop-closed 3264 phi for vec_lhs and use it for lane extraction. 3265 32662020-03-31 Felix Yang <felix.yang@huawei.com> 3267 3268 PR tree-optimization/94398 3269 * tree-vect-stmts.c (vectorizable_store): Instead of calling 3270 vect_supportable_dr_alignment, set alignment_support_scheme to 3271 dr_unaligned_supported for gather-scatter accesses. 3272 (vectorizable_load): Likewise. 3273 32742020-03-31 Andrew Stubbs <ams@codesourcery.com> 3275 3276 * config/gcn/gcn-valu.md (V_QI, V_HI, V_HF, V_SI, V_SF, V_DI, V_DF): 3277 New mode iterators. 3278 (vnsi, VnSI, vndi, VnDI): New mode attributes. 3279 (mov<mode>): Use <VnDI> in place of V64DI. 3280 (mov<mode>_exec): Likewise. 3281 (mov<mode>_sgprbase): Likewise. 3282 (reload_out<mode>): Likewise. 3283 (*vec_set<mode>_1): Use GET_MODE_NUNITS instead of constant 64. 3284 (gather_load<mode>v64si): Rename to ... 3285 (gather_load<mode><vnsi>): ... this, and use <VnSI> in place of V64SI, 3286 and <VnDI> in place of V64DI. 3287 (gather<mode>_insn_1offset<exec>): Use <VnDI> in place of V64DI. 3288 (gather<mode>_insn_1offset_ds<exec>): Use <VnSI> in place of V64SI. 3289 (gather<mode>_insn_2offsets<exec>): Use <VnSI> and <VnDI>. 3290 (scatter_store<mode>v64si): Rename to ... 3291 (scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>. 3292 (scatter<mode>_expr<exec_scatter>): Use <VnSI> and <VnDI>. 3293 (scatter<mode>_insn_1offset<exec_scatter>): Likewise. 3294 (scatter<mode>_insn_1offset_ds<exec_scatter>): Likewise. 3295 (scatter<mode>_insn_2offsets<exec_scatter>): Likewise. 3296 (ds_bpermute<mode>): Use <VnSI>. 3297 (addv64si3_vcc<exec_vcc>): Rename to ... 3298 (add<mode>3_vcc<exec_vcc>): ... this, and use V_SI. 3299 (addv64si3_vcc_dup<exec_vcc>): Rename to ... 3300 (add<mode>3_vcc_dup<exec_vcc>): ... this, and use V_SI. 3301 (addcv64si3<exec_vcc>): Rename to ... 3302 (addc<mode>3<exec_vcc>): ... this, and use V_SI. 3303 (subv64si3_vcc<exec_vcc>): Rename to ... 3304 (sub<mode>3_vcc<exec_vcc>): ... this, and use V_SI. 3305 (subcv64si3<exec_vcc>): Rename to ... 3306 (subc<mode>3<exec_vcc>): ... this, and use V_SI. 3307 (addv64di3): Rename to ... 3308 (add<mode>3): ... this, and use V_DI. 3309 (addv64di3_exec): Rename to ... 3310 (add<mode>3_exec): ... this, and use V_DI. 3311 (subv64di3): Rename to ... 3312 (sub<mode>3): ... this, and use V_DI. 3313 (subv64di3_exec): Rename to ... 3314 (sub<mode>3_exec): ... this, and use V_DI. 3315 (addv64di3_zext): Rename to ... 3316 (add<mode>3_zext): ... this, and use V_DI and <VnSI>. 3317 (addv64di3_zext_exec): Rename to ... 3318 (add<mode>3_zext_exec): ... this, and use V_DI and <VnSI>. 3319 (addv64di3_zext_dup): Rename to ... 3320 (add<mode>3_zext_dup): ... this, and use V_DI and <VnSI>. 3321 (addv64di3_zext_dup_exec): Rename to ... 3322 (add<mode>3_zext_dup_exec): ... this, and use V_DI and <VnSI>. 3323 (addv64di3_zext_dup2): Rename to ... 3324 (add<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>. 3325 (addv64di3_zext_dup2_exec): Rename to ... 3326 (add<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>. 3327 (addv64di3_sext_dup2): Rename to ... 3328 (add<mode>3_sext_dup2): ... this, and use V_DI and <VnSI>. 3329 (addv64di3_sext_dup2_exec): Rename to ... 3330 (add<mode>3_sext_dup2_exec): ... this, and use V_DI and <VnSI>. 3331 (<su>mulv64si3_highpart<exec>): Rename to ... 3332 (<su>mul<mode>3_highpart<exec>): ... this and use V_SI and <VnDI>. 3333 (mulv64di3): Rename to ... 3334 (mul<mode>3): ... this, and use V_DI and <VnSI>. 3335 (mulv64di3_exec): Rename to ... 3336 (mul<mode>3_exec): ... this, and use V_DI and <VnSI>. 3337 (mulv64di3_zext): Rename to ... 3338 (mul<mode>3_zext): ... this, and use V_DI and <VnSI>. 3339 (mulv64di3_zext_exec): Rename to ... 3340 (mul<mode>3_zext_exec): ... this, and use V_DI and <VnSI>. 3341 (mulv64di3_zext_dup2): Rename to ... 3342 (mul<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>. 3343 (mulv64di3_zext_dup2_exec): Rename to ... 3344 (mul<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>. 3345 (<expander>v64di3): Rename to ... 3346 (<expander><mode>3): ... this, and use V_DI and <VnSI>. 3347 (<expander>v64di3_exec): Rename to ... 3348 (<expander><mode>3_exec): ... this, and use V_DI and <VnSI>. 3349 (<expander>v64si3<exec>): Rename to ... 3350 (<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>. 3351 (v<expander>v64si3<exec>): Rename to ... 3352 (v<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>. 3353 (<expander>v64si3<exec>): Rename to ... 3354 (<expander><vnsi>3<exec>): ... this, and use V_SI. 3355 (subv64df3<exec>): Rename to ... 3356 (sub<mode>3<exec>): ... this, and use V_DF. 3357 (truncv64di<mode>2): Rename to ... 3358 (trunc<vndi><mode>2): ... this, and use <VnDI>. 3359 (truncv64di<mode>2_exec): Rename to ... 3360 (trunc<vndi><mode>2_exec): ... this, and use <VnDI>. 3361 (<convop><mode>v64di2): Rename to ... 3362 (<convop><mode><vndi>2): ... this, and use <VnDI>. 3363 (<convop><mode>v64di2_exec): Rename to ... 3364 (<convop><mode><vndi>2_exec): ... this, and use <VnDI>. 3365 (vec_cmp<u>v64qidi): Rename to ... 3366 (vec_cmp<u><mode>di): ... this, and use <VnSI>. 3367 (vec_cmp<u>v64qidi_exec): Rename to ... 3368 (vec_cmp<u><mode>di_exec): ... this, and use <VnSI>. 3369 (vcond_mask_<mode>di): Use <VnDI>. 3370 (maskload<mode>di): Likewise. 3371 (maskstore<mode>di): Likewise. 3372 (mask_gather_load<mode>v64si): Rename to ... 3373 (mask_gather_load<mode><vnsi>): ... this, and use <VnSI> and <VnDI>. 3374 (mask_scatter_store<mode>v64si): Rename to ... 3375 (mask_scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>. 3376 (*<reduc_op>_dpp_shr_v64di): Rename to ... 3377 (*<reduc_op>_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>. 3378 (*plus_carry_in_dpp_shr_v64si): Rename to ... 3379 (*plus_carry_in_dpp_shr_<mode>): ... this, and use V_SI. 3380 (*plus_carry_dpp_shr_v64di): Rename to ... 3381 (*plus_carry_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>. 3382 (vec_seriesv64si): Rename to ... 3383 (vec_series<mode>): ... this, and use V_SI. 3384 (vec_seriesv64di): Rename to ... 3385 (vec_series<mode>): ... this, and use V_DI. 3386 33872020-03-31 Claudiu Zissulescu <claziss@synopsys.com> 3388 3389 * config/arc/arc.c (arc_print_operand): Use 3390 HOST_WIDE_INT_PRINT_DEC macro. 3391 33922020-03-31 Claudiu Zissulescu <claziss@synopsys.com> 3393 3394 * config/arc/arc.h (ASM_FORMAT_PRIVATE_NAME): Fix it. 3395 33962020-03-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 3397 3398 * config/arm/arm_mve.h (vbicq): Define MVE intrinsic polymorphic 3399 variant. 3400 (__arm_vbicq): Likewise. 3401 34022020-03-31 Vineet Gupta <vgupta@synopsys.com> 3403 3404 * config/arc/linux.h: GLIBC_DYNAMIC_LINKER support BE/arc700. 3405 34062020-03-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 3407 3408 * config/arm/arm_mve.h (vaddlvq): Move the polymorphic variant to the 3409 common section of both MVE Integer and MVE Floating Point. 3410 (vaddvq): Likewise. 3411 (vaddlvq_p): Likewise. 3412 (vaddvaq): Likewise. 3413 (vaddvq_p): Likewise. 3414 (vcmpcsq): Likewise. 3415 (vmlsdavxq): Likewise. 3416 (vmlsdavq): Likewise. 3417 (vmladavxq): Likewise. 3418 (vmladavq): Likewise. 3419 (vminvq): Likewise. 3420 (vminavq): Likewise. 3421 (vmaxvq): Likewise. 3422 (vmaxavq): Likewise. 3423 (vmlaldavq): Likewise. 3424 (vcmphiq): Likewise. 3425 (vaddlvaq): Likewise. 3426 (vrmlaldavhq): Likewise. 3427 (vrmlaldavhxq): Likewise. 3428 (vrmlsldavhq): Likewise. 3429 (vrmlsldavhxq): Likewise. 3430 (vmlsldavxq): Likewise. 3431 (vmlsldavq): Likewise. 3432 (vabavq): Likewise. 3433 (vrmlaldavhaq): Likewise. 3434 (vcmpgeq_m_n): Likewise. 3435 (vmlsdavxq_p): Likewise. 3436 (vmlsdavq_p): Likewise. 3437 (vmlsdavaxq): Likewise. 3438 (vmlsdavaq): Likewise. 3439 (vaddvaq_p): Likewise. 3440 (vcmpcsq_m_n): Likewise. 3441 (vcmpcsq_m): Likewise. 3442 (vmladavxq_p): Likewise. 3443 (vmladavq_p): Likewise. 3444 (vmladavaxq): Likewise. 3445 (vmladavaq): Likewise. 3446 (vminvq_p): Likewise. 3447 (vminavq_p): Likewise. 3448 (vmaxvq_p): Likewise. 3449 (vmaxavq_p): Likewise. 3450 (vcmphiq_m): Likewise. 3451 (vaddlvaq_p): Likewise. 3452 (vmlaldavaq): Likewise. 3453 (vmlaldavaxq): Likewise. 3454 (vmlaldavq_p): Likewise. 3455 (vmlaldavxq_p): Likewise. 3456 (vmlsldavaq): Likewise. 3457 (vmlsldavaxq): Likewise. 3458 (vmlsldavq_p): Likewise. 3459 (vmlsldavxq_p): Likewise. 3460 (vrmlaldavhaxq): Likewise. 3461 (vrmlaldavhq_p): Likewise. 3462 (vrmlaldavhxq_p): Likewise. 3463 (vrmlsldavhaq): Likewise. 3464 (vrmlsldavhaxq): Likewise. 3465 (vrmlsldavhq_p): Likewise. 3466 (vrmlsldavhxq_p): Likewise. 3467 (vabavq_p): Likewise. 3468 (vmladavaq_p): Likewise. 3469 (vstrbq_scatter_offset): Likewise. 3470 (vstrbq_p): Likewise. 3471 (vstrbq_scatter_offset_p): Likewise. 3472 (vstrdq_scatter_base_p): Likewise. 3473 (vstrdq_scatter_base): Likewise. 3474 (vstrdq_scatter_offset_p): Likewise. 3475 (vstrdq_scatter_offset): Likewise. 3476 (vstrdq_scatter_shifted_offset_p): Likewise. 3477 (vstrdq_scatter_shifted_offset): Likewise. 3478 (vmaxq_x): Likewise. 3479 (vminq_x): Likewise. 3480 (vmovlbq_x): Likewise. 3481 (vmovltq_x): Likewise. 3482 (vmulhq_x): Likewise. 3483 (vmullbq_int_x): Likewise. 3484 (vmullbq_poly_x): Likewise. 3485 (vmulltq_int_x): Likewise. 3486 (vmulltq_poly_x): Likewise. 3487 (vstrbq): Likewise. 3488 34892020-03-31 Jakub Jelinek <jakub@redhat.com> 3490 3491 PR target/94368 3492 * config/aarch64/constraints.md (Uph): New constraint. 3493 * config/aarch64/atomics.md (cas_short_expected_imm): New mode attr. 3494 (@aarch64_compare_and_swap<mode>): Use it instead of n in operand 2's 3495 constraint. 3496 34972020-03-31 Marc Glisse <marc.glisse@inria.fr> 3498 Jakub Jelinek <jakub@redhat.com> 3499 3500 PR middle-end/94412 3501 * fold-const.c (fold_binary_loc) <case TRUNC_DIV_EXPR>: Use 3502 ANY_INTEGRAL_TYPE_P instead of INTEGRAL_TYPE_P. 3503 35042020-03-31 Jakub Jelinek <jakub@redhat.com> 3505 3506 PR tree-optimization/94403 3507 * gimple-ssa-store-merging.c (verify_symbolic_number_p): Allow also 3508 ENUMERAL_TYPE lhs_type. 3509 3510 PR rtl-optimization/94344 3511 * tree-ssa-forwprop.c (simplify_rotate): Handle also same precision 3512 conversions, either on both operands of |^+ or just one. Handle 3513 also extra same precision conversion on RSHIFT_EXPR first operand 3514 provided RSHIFT_EXPR is performed in unsigned type. 3515 35162020-03-30 David Malcolm <dmalcolm@redhat.com> 3517 3518 * lra.c (finish_insn_code_data_once): Set the array elements 3519 to NULL after freeing them. 3520 35212020-03-30 Andreas Schwab <schwab@suse.de> 3522 3523 * config/host-linux.c (TRY_EMPTY_VM_SPACE) [__riscv && __LP64__]: 3524 Define. 3525 35262020-03-30 Will Schmidt <will_schmidt@vnet.ibm.com> 3527 3528 * config/rs6000/rs6000-call.c altivec_init_builtins(): Remove code 3529 to skip defining builtins based on builtin_mask. 3530 35312020-03-30 Jakub Jelinek <jakub@redhat.com> 3532 3533 PR target/94343 3534 * config/i386/sse.md (<mask_codefor>one_cmpl<mode>2<mask_name>): If 3535 !TARGET_AVX512VL, use 512-bit vpternlog and make sure the input 3536 operand is a register. Don't enable masked variants for V*[QH]Imode. 3537 3538 PR target/93069 3539 * config/i386/sse.md (vec_extract_lo_<mode><mask_name>): Use 3540 <store_mask_constraint> instead of m in output operand constraint. 3541 (vec_extract_hi_<mode><mask_name>): Use <mask_operand2> instead of 3542 %{%3%}. 3543 35442020-03-30 Alan Modra <amodra@gmail.com> 3545 3546 * config/rs6000/rs6000.c (rs6000_call_aix): Emit cookie to pattern. 3547 (rs6000_indirect_call_template_1): Adjust to suit. 3548 * config/rs6000/rs6000.md (call_local): Merge call_local32, 3549 call_local64, and call_local_aix. 3550 (call_value_local): Simlarly. 3551 (call_nonlocal_aix, call_value_nonlocal_aix): Adjust rtl to suit, 3552 and disable pattern when CALL_LONG. 3553 (call_indirect_aix, call_value_indirect_aix): Adjust rtl. 3554 (call_indirect_elfv2, call_indirect_pcrel): Likewise. 3555 (call_value_indirect_elfv2, call_value_indirect_pcrel): Likewise. 3556 35572020-03-29 H.J. Lu <hongjiu.lu@intel.com> 3558 3559 PR driver/94381 3560 * doc/invoke.texi: Update -falign-functions, -falign-loops and 3561 -falign-jumps documentation. 3562 35632020-03-29 Martin Liska <mliska@suse.cz> 3564 3565 PR ipa/94363 3566 * cgraphunit.c (process_function_and_variable_attributes): Remove 3567 double 'attribute' words. 3568 35692020-03-29 John David Anglin <dave.anglin@bell.net> 3570 3571 * gcc/config/pa/pa.c (pa_asm_output_aligned_bss): Delete duplicate 3572 .align output. 3573 35742020-03-28 Jakub Jelinek <jakub@redhat.com> 3575 3576 PR c/93573 3577 * c-decl.c (grokdeclarator): After issuing errors, set size_int_const 3578 to true after setting size to integer_one_node. 3579 3580 PR tree-optimization/94329 3581 * tree-ssa-reassoc.c (reassociate_bb): When calling reassoc_remove_stmt 3582 on the last stmt in a bb, make sure gsi_prev isn't done immediately 3583 after gsi_last_bb. 3584 35852020-03-27 Alan Modra <amodra@gmail.com> 3586 3587 PR target/94145 3588 * config/rs6000/rs6000.c (rs6000_longcall_ref): Use unspec_volatile 3589 for PLT16_LO and PLT_PCREL. 3590 * config/rs6000/rs6000.md (UNSPEC_PLT16_LO, UNSPEC_PLT_PCREL): Remove. 3591 (UNSPECV_PLT16_LO, UNSPECV_PLT_PCREL): Define. 3592 (pltseq_plt16_lo_, pltseq_plt_pcrel): Use unspec_volatile. 3593 35942020-03-27 Martin Sebor <msebor@redhat.com> 3595 3596 PR c++/94098 3597 * calls.c (init_attr_rdwr_indices): Iterate over all access attributes. 3598 35992020-03-27 Andrew Stubbs <ams@codesourcery.com> 3600 3601 * config/gcn/gcn-valu.md: 3602 (VEC_SUBDWORD_MODE): Rename to V_QIHI throughout. 3603 (VEC_1REG_MODE): Delete. 3604 (VEC_1REG_ALT): Delete. 3605 (VEC_ALL1REG_MODE): Rename to V_1REG throughout. 3606 (VEC_1REG_INT_MODE): Delete. 3607 (VEC_ALL1REG_INT_MODE): Rename to V_INT_1REG throughout. 3608 (VEC_ALL1REG_INT_ALT): Rename to V_INT_1REG_ALT throughout. 3609 (VEC_2REG_MODE): Rename to V_2REG throughout. 3610 (VEC_REG_MODE): Rename to V_noHI throughout. 3611 (VEC_ALLREG_MODE): Rename to V_ALL throughout. 3612 (VEC_ALLREG_ALT): Rename to V_ALL_ALT throughout. 3613 (VEC_ALLREG_INT_MODE): Rename to V_INT throughout. 3614 (VEC_INT_MODE): Delete. 3615 (VEC_FP_MODE): Rename to V_FP throughout and move to top. 3616 (VEC_FP_1REG_MODE): Rename to V_FP_1REG throughout and move to top. 3617 (FP_MODE): Delete and replace with FP throughout. 3618 (FP_1REG_MODE): Delete and replace with FP_1REG throughout. 3619 (VCMP_MODE): Rename to V_noQI throughout and move to top. 3620 (VCMP_MODE_INT): Rename to V_INT_noQI throughout and move to top. 3621 * config/gcn/gcn.md (FP): New mode iterator. 3622 (FP_1REG): New mode iterator. 3623 36242020-03-27 David Malcolm <dmalcolm@redhat.com> 3625 3626 * doc/invoke.texi (-fdump-analyzer-supergraph): Document that this 3627 now emits two .dot files. 3628 * graphviz.cc (graphviz_out::begin_tr): Only emit a TR, not a TD. 3629 (graphviz_out::end_tr): Only close a TR, not a TD. 3630 (graphviz_out::begin_td): New. 3631 (graphviz_out::end_td): New. 3632 (graphviz_out::begin_trtd): New, replacing the old implementation 3633 of graphviz_out::begin_tr. 3634 (graphviz_out::end_tdtr): New, replacing the old implementation 3635 of graphviz_out::end_tr. 3636 * graphviz.h (graphviz_out::begin_td): New decl. 3637 (graphviz_out::end_td): New decl. 3638 (graphviz_out::begin_trtd): New decl. 3639 (graphviz_out::end_tdtr): New decl. 3640 36412020-03-27 Richard Biener <rguenther@suse.de> 3642 3643 PR debug/94273 3644 * dwarf2out.c (should_emit_struct_debug): Return false for 3645 DINFO_LEVEL_TERSE. 3646 36472020-03-27 Richard Biener <rguenther@suse.de> 3648 3649 PR tree-optimization/94352 3650 * tree-ssa-propagate.c (ssa_prop_init): Move seeding of the 3651 worklist ... 3652 (ssa_propagation_engine::ssa_propagate): ... here after 3653 initializing curr_order. 3654 36552020-03-27 Kewen Lin <linkw@gcc.gnu.org> 3656 3657 PR tree-optimization/90332 3658 * tree-vect-stmts.c (vector_vector_composition_type): New function. 3659 (get_group_load_store_type): Adjust to call 3660 vector_vector_composition_type, extend it to construct with scalar 3661 types. 3662 (vectorizable_load): Likewise. 3663 36642020-03-27 Roman Zhuykov <zhroma@ispras.ru> 3665 3666 * ddg.c (create_ddg_dep_from_intra_loop_link): Remove assertions. 3667 (create_ddg_dep_no_link): Likewise. 3668 (add_cross_iteration_register_deps): Move debug instruction check. 3669 Other minor refactoring. 3670 (add_intra_loop_mem_dep): Do not check for debug instructions. 3671 (add_inter_loop_mem_dep): Likewise. 3672 (build_intra_loop_deps): Likewise. 3673 (create_ddg): Do not include debug insns into the graph. 3674 * ddg.h (struct ddg): Remove num_debug field. 3675 * modulo-sched.c (doloop_register_get): Adjust condition. 3676 (res_MII): Remove DDG num_debug field usage. 3677 (sms_schedule_by_order): Use assertion against debug insns. 3678 (ps_has_conflicts): Drop debug insn check. 3679 36802020-03-26 Jakub Jelinek <jakub@redhat.com> 3681 3682 PR debug/94323 3683 * tree.c (protected_set_expr_location): Recurse on STATEMENT_LIST 3684 that contains exactly one non-DEBUG_BEGIN_STMT statement. 3685 3686 PR debug/94281 3687 * gimple.h (gimple_seq_first_nondebug_stmt): New function. 3688 (gimple_seq_last_nondebug_stmt): Don't return NULL if seq contains 3689 a single non-debug stmt followed by one or more debug stmts. 3690 * gimplify.c (gimplify_body): Use gimple_seq_first_nondebug_stmt 3691 instead of gimple_seq_first_stmt, use gimple_seq_first_nondebug_stmt 3692 and gimple_seq_last_nondebug_stmt instead of gimple_seq_first and 3693 gimple_seq_last to check if outer_stmt gbind could be reused and 3694 if yes and it is surrounded by any debug stmts, move them into the 3695 gbind body. 3696 3697 PR rtl-optimization/92264 3698 * var-tracking.c (add_stores): Call cselib_set_value_sp_based even 3699 for sp based values in !frame_pointer_needed 3700 && !ACCUMULATE_OUTGOING_ARGS functions. 3701 37022020-03-26 Felix Yang <felix.yang@huawei.com> 3703 3704 PR tree-optimization/94269 3705 * tree-ssa-math-opts.c (convert_plusminus_to_widen): Restrict 3706 this 3707 operation to single basic block. 3708 37092020-03-25 Jeff Law <law@redhat.com> 3710 3711 PR rtl-optimization/90275 3712 * config/sh/sh.md (mov_neg_si_t): Clobber the T register in the 3713 pattern. 3714 37152020-03-25 Jakub Jelinek <jakub@redhat.com> 3716 3717 PR target/94292 3718 * config/arm/arm.c (arm_gen_dicompare_reg): Set mode of COMPARE to 3719 mode rather than VOIDmode. 3720 37212020-03-25 Martin Sebor <msebor@redhat.com> 3722 3723 PR middle-end/94004 3724 * gimple-ssa-warn-alloca.c (pass_walloca::execute): Issue warnings 3725 even for alloca calls resulting from system macro expansion. 3726 Include inlining context in all warnings. 3727 37282020-03-25 Richard Sandiford <richard.sandiford@arm.com> 3729 3730 PR target/94254 3731 * config/rs6000/rs6000.c (rs6000_can_change_mode_class): Allow 3732 FPRs to change between SDmode and DDmode. 3733 37342020-03-25 Martin Sebor <msebor@redhat.com> 3735 3736 PR tree-optimization/94131 3737 * gimple-fold.c (get_range_strlen_tree): Fail for variable-length 3738 types and decls. 3739 * tree-ssa-strlen.c (get_range_strlen_dynamic): Avoid assuming 3740 types have constant sizes. 3741 37422020-03-25 Martin Liska <mliska@suse.cz> 3743 3744 PR lto/94259 3745 * configure.ac: Report error only when --with-zstd 3746 is used. 3747 * configure: Regenerate. 3748 37492020-03-25 Jakub Jelinek <jakub@redhat.com> 3750 3751 PR target/94308 3752 * config/i386/i386-features.c (ix86_add_reg_usage_to_vzeroupper): Set 3753 INSN_CODE (insn) to -1 when changing the pattern. 3754 37552020-03-25 Martin Liska <mliska@suse.cz> 3756 3757 PR target/93274 3758 PR ipa/94271 3759 * config/i386/i386-features.c (make_resolver_func): Drop 3760 public flag for resolver. 3761 * config/rs6000/rs6000.c (make_resolver_func): Add comdat 3762 group for resolver and drop public flag if possible. 3763 * multiple_target.c (create_dispatcher_calls): Drop unique_name 3764 and resolution as we want to enable LTO privatization of the default 3765 symbol. 3766 37672020-03-25 Martin Liska <mliska@suse.cz> 3768 3769 PR lto/94259 3770 * configure.ac: Respect --without-zstd and report 3771 error when we can't find header file with --with-zstd. 3772 * configure: Regenerate. 3773 37742020-03-25 Jakub Jelinek <jakub@redhat.com> 3775 3776 PR middle-end/94303 3777 * varasm.c (output_constructor_array_range): If local->index 3778 RANGE_EXPR doesn't start at the current location in the constructor, 3779 skip needed number of bytes using assemble_zeros or assert we don't 3780 go backwards. 3781 3782 PR c++/94223 3783 * langhooks.c (lhd_set_decl_assembler_name): Use a static ulong 3784 counter instead of DECL_UID. 3785 3786 PR tree-optimization/94300 3787 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): If pd.offset 3788 is positive, make sure that off + size isn't larger than needed_len. 3789 37902020-03-25 Richard Biener <rguenther@suse.de> 3791 Jakub Jelinek <jakub@redhat.com> 3792 3793 PR debug/94283 3794 * tree-if-conv.c (ifcvt_local_dce): Delete dead statements backwards. 3795 37962020-03-24 Christophe Lyon <christophe.lyon@linaro.org> 3797 3798 * doc/sourcebuild.texi (ARM-specific attributes): Add 3799 arm_fp_dp_ok. 3800 (Features for dg-add-options): Add arm_fp_dp. 3801 38022020-03-24 John David Anglin <danglin@gcc.gnu.org> 3803 3804 PR lto/94249 3805 * config/pa/pa.h (TARGET_CPU_CPP_BUILTINS): Define __BIG_ENDIAN__. 3806 38072020-03-24 Tobias Burnus <tobias@codesourcery.com> 3808 3809 PR libgomp/81689 3810 * omp-offload.c (omp_finish_file): Fix target-link handling if 3811 targetm_common.have_named_sections is false. 3812 38132020-03-24 Jakub Jelinek <jakub@redhat.com> 3814 3815 PR target/94286 3816 * config/arm/arm.md (subvdi4, usubvsi4, usubvdi4): Use gen_int_mode 3817 instead of GEN_INT. 3818 3819 PR debug/94285 3820 * tree-ssa-loop-manip.c (create_iv): If after, set stmt location to 3821 e->goto_locus even if gsi_bb (*incr_pos) contains only debug stmts. 3822 If not after and at *incr_pos is a debug stmt, set stmt location to 3823 location of next non-debug stmt after it if any. 3824 3825 PR debug/94283 3826 * tree-if-conv.c (ifcvt_local_dce): For gimple debug stmts, just set 3827 GF_PLF_2, but don't add them to worklist. Don't add an assigment to 3828 worklist or set GF_PLF_2 just because it is used in a debug stmt in 3829 another bb. Formatting improvements. 3830 3831 PR debug/94277 3832 * cgraphunit.c (check_global_declaration): For DECL_EXTERNAL and 3833 non-TREE_PUBLIC non-DECL_ARTIFICIAL FUNCTION_DECLs, set TREE_PUBLIC 3834 regardless of whether TREE_NO_WARNING is set on it or whether 3835 warn_unused_function is true or not. 3836 38372020-03-23 Jeff Law <law@redhat.com> 3838 3839 PR rtl-optimization/90275 3840 PR target/94238 3841 PR target/94144 3842 * simplify-rtx.c (comparison_code_valid_for_mode): New function. 3843 (simplify_logical_relational_operation): Use it. 3844 38452020-03-23 Jakub Jelinek <jakub@redhat.com> 3846 3847 PR c++/91993 3848 * tree.c (get_narrower): Handle COMPOUND_EXPR by recursing on 3849 ultimate rhs and if returned something different, reconstructing 3850 the COMPOUND_EXPRs. 3851 38522020-03-23 Lewis Hyatt <lhyatt@gmail.com> 3853 3854 * opts.c (print_filtered_help): Improve the help text for alias options. 3855 38562020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 3857 Andre Vieira <andre.simoesdiasvieira@arm.com> 3858 Mihail Ionescu <mihail.ionescu@arm.com> 3859 3860 * config/arm/arm_mve.h (vshlcq_m_s8): Define macro. 3861 (vshlcq_m_u8): Likewise. 3862 (vshlcq_m_s16): Likewise. 3863 (vshlcq_m_u16): Likewise. 3864 (vshlcq_m_s32): Likewise. 3865 (vshlcq_m_u32): Likewise. 3866 (__arm_vshlcq_m_s8): Define intrinsic. 3867 (__arm_vshlcq_m_u8): Likewise. 3868 (__arm_vshlcq_m_s16): Likewise. 3869 (__arm_vshlcq_m_u16): Likewise. 3870 (__arm_vshlcq_m_s32): Likewise. 3871 (__arm_vshlcq_m_u32): Likewise. 3872 (vshlcq_m): Define polymorphic variant. 3873 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_UNONE_IMM_UNONE): 3874 Use builtin qualifier. 3875 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise. 3876 * config/arm/mve.md (mve_vshlcq_m_vec_<supf><mode>): Define RTL pattern. 3877 (mve_vshlcq_m_carry_<supf><mode>): Likewise. 3878 (mve_vshlcq_m_<supf><mode>): Likewise. 3879 38802020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 3881 3882 * config/arm/arm-builtins.c (LSLL_QUALIFIERS): Define builtin qualifier. 3883 (UQSHL_QUALIFIERS): Likewise. 3884 (ASRL_QUALIFIERS): Likewise. 3885 (SQSHL_QUALIFIERS): Likewise. 3886 * config/arm/arm_mve.h (__ARM_BIG_ENDIAN): Check to not support MVE in 3887 Big-Endian Mode. 3888 (sqrshr): Define macro. 3889 (sqrshrl): Likewise. 3890 (sqrshrl_sat48): Likewise. 3891 (sqshl): Likewise. 3892 (sqshll): Likewise. 3893 (srshr): Likewise. 3894 (srshrl): Likewise. 3895 (uqrshl): Likewise. 3896 (uqrshll): Likewise. 3897 (uqrshll_sat48): Likewise. 3898 (uqshl): Likewise. 3899 (uqshll): Likewise. 3900 (urshr): Likewise. 3901 (urshrl): Likewise. 3902 (lsll): Likewise. 3903 (asrl): Likewise. 3904 (__arm_lsll): Define intrinsic. 3905 (__arm_asrl): Likewise. 3906 (__arm_uqrshll): Likewise. 3907 (__arm_uqrshll_sat48): Likewise. 3908 (__arm_sqrshrl): Likewise. 3909 (__arm_sqrshrl_sat48): Likewise. 3910 (__arm_uqshll): Likewise. 3911 (__arm_urshrl): Likewise. 3912 (__arm_srshrl): Likewise. 3913 (__arm_sqshll): Likewise. 3914 (__arm_uqrshl): Likewise. 3915 (__arm_sqrshr): Likewise. 3916 (__arm_uqshl): Likewise. 3917 (__arm_urshr): Likewise. 3918 (__arm_sqshl): Likewise. 3919 (__arm_srshr): Likewise. 3920 * config/arm/arm_mve_builtins.def (LSLL_QUALIFIERS): Use builtin 3921 qualifier. 3922 (UQSHL_QUALIFIERS): Likewise. 3923 (ASRL_QUALIFIERS): Likewise. 3924 (SQSHL_QUALIFIERS): Likewise. 3925 * config/arm/mve.md (mve_uqrshll_sat<supf>_di): Define RTL pattern. 3926 (mve_sqrshrl_sat<supf>_di): Likewise. 3927 (mve_uqrshl_si): Likewise. 3928 (mve_sqrshr_si): Likewise. 3929 (mve_uqshll_di): Likewise. 3930 (mve_urshrl_di): Likewise. 3931 (mve_uqshl_si): Likewise. 3932 (mve_urshr_si): Likewise. 3933 (mve_sqshl_si): Likewise. 3934 (mve_srshr_si): Likewise. 3935 (mve_srshrl_di): Likewise. 3936 (mve_sqshll_di): Likewise. 3937 39382020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 3939 Andre Vieira <andre.simoesdiasvieira@arm.com> 3940 Mihail Ionescu <mihail.ionescu@arm.com> 3941 3942 * config/arm/arm_mve.h (vsetq_lane_f16): Define macro. 3943 (vsetq_lane_f32): Likewise. 3944 (vsetq_lane_s16): Likewise. 3945 (vsetq_lane_s32): Likewise. 3946 (vsetq_lane_s8): Likewise. 3947 (vsetq_lane_s64): Likewise. 3948 (vsetq_lane_u8): Likewise. 3949 (vsetq_lane_u16): Likewise. 3950 (vsetq_lane_u32): Likewise. 3951 (vsetq_lane_u64): Likewise. 3952 (vgetq_lane_f16): Likewise. 3953 (vgetq_lane_f32): Likewise. 3954 (vgetq_lane_s16): Likewise. 3955 (vgetq_lane_s32): Likewise. 3956 (vgetq_lane_s8): Likewise. 3957 (vgetq_lane_s64): Likewise. 3958 (vgetq_lane_u8): Likewise. 3959 (vgetq_lane_u16): Likewise. 3960 (vgetq_lane_u32): Likewise. 3961 (vgetq_lane_u64): Likewise. 3962 (__ARM_NUM_LANES): Likewise. 3963 (__ARM_LANEQ): Likewise. 3964 (__ARM_CHECK_LANEQ): Likewise. 3965 (__arm_vsetq_lane_s16): Define intrinsic. 3966 (__arm_vsetq_lane_s32): Likewise. 3967 (__arm_vsetq_lane_s8): Likewise. 3968 (__arm_vsetq_lane_s64): Likewise. 3969 (__arm_vsetq_lane_u8): Likewise. 3970 (__arm_vsetq_lane_u16): Likewise. 3971 (__arm_vsetq_lane_u32): Likewise. 3972 (__arm_vsetq_lane_u64): Likewise. 3973 (__arm_vgetq_lane_s16): Likewise. 3974 (__arm_vgetq_lane_s32): Likewise. 3975 (__arm_vgetq_lane_s8): Likewise. 3976 (__arm_vgetq_lane_s64): Likewise. 3977 (__arm_vgetq_lane_u8): Likewise. 3978 (__arm_vgetq_lane_u16): Likewise. 3979 (__arm_vgetq_lane_u32): Likewise. 3980 (__arm_vgetq_lane_u64): Likewise. 3981 (__arm_vsetq_lane_f16): Likewise. 3982 (__arm_vsetq_lane_f32): Likewise. 3983 (__arm_vgetq_lane_f16): Likewise. 3984 (__arm_vgetq_lane_f32): Likewise. 3985 (vgetq_lane): Define polymorphic variant. 3986 (vsetq_lane): Likewise. 3987 * config/arm/mve.md (mve_vec_extract<mode><V_elem_l>): Define RTL 3988 pattern. 3989 (mve_vec_extractv2didi): Likewise. 3990 (mve_vec_extract_sext_internal<mode>): Likewise. 3991 (mve_vec_extract_zext_internal<mode>): Likewise. 3992 (mve_vec_set<mode>_internal): Likewise. 3993 (mve_vec_setv2di_internal): Likewise. 3994 * config/arm/neon.md (vec_set<mode>): Move RTL pattern to vec-common.md 3995 file. 3996 (vec_extract<mode><V_elem_l>): Rename to 3997 "neon_vec_extract<mode><V_elem_l>". 3998 (vec_extractv2didi): Rename to "neon_vec_extractv2didi". 3999 * config/arm/vec-common.md (vec_extract<mode><V_elem_l>): Define RTL 4000 pattern common for MVE and NEON. 4001 (vec_set<mode>): Move RTL pattern from neon.md and modify to accept both 4002 MVE and NEON. 4003 40042020-03-23 Andre Vieira <andre.simoesdiasvieira@arm.com> 4005 4006 * config/arm/mve.md (earlyclobber_32): New mode attribute. 4007 (mve_vrev64q_*, mve_vcaddq*, mve_vhcaddq_*, mve_vcmulq_*, 4008 mve_vmull[bt]q_*, mve_vqdmull[bt]q_*): Add appropriate early clobbers. 4009 40102020-03-23 Richard Biener <rguenther@suse.de> 4011 4012 PR tree-optimization/94261 4013 * tree-vect-slp.c (vect_get_and_check_slp_defs): Remove 4014 IL operand swapping code. 4015 (vect_slp_rearrange_stmts): Do not arrange isomorphic 4016 nodes that would need operation code adjustments. 4017 40182020-03-23 Tobias Burnus <tobias@codesourcery.com> 4019 4020 * doc/install.texi (amdgcn-*-amdhsa): Renamed 4021 from amdgcn-unknown-amdhsa; change 4022 amdgcn-unknown-amdhsa to amdgcn-amdhsa. 4023 40242020-03-23 Richard Biener <rguenther@suse.de> 4025 4026 PR ipa/94245 4027 * ipa-prop.c (ipa_read_jump_function): Build the ADDR_EXRP 4028 directly rather than also folding it via build_fold_addr_expr. 4029 40302020-03-23 Richard Biener <rguenther@suse.de> 4031 4032 PR tree-optimization/94266 4033 * tree-ssa-forwprop.c (pass_forwprop::execute): Do not propagate 4034 addresses of TARGET_MEM_REFs. 4035 40362020-03-23 Martin Liska <mliska@suse.cz> 4037 4038 PR ipa/94250 4039 * symtab.c (symtab_node::clone_references): Save speculative_id 4040 as ref may be overwritten by create_reference. 4041 (symtab_node::clone_referring): Likewise. 4042 (symtab_node::clone_reference): Likewise. 4043 40442020-03-22 Iain Sandoe <iain@sandoe.co.uk> 4045 4046 * config/i386/darwin.h (JUMP_TABLES_IN_TEXT_SECTION): Remove 4047 references to Darwin. 4048 * config/i386/i386.h (JUMP_TABLES_IN_TEXT_SECTION): Define this 4049 unconditionally and comment on why. 4050 40512020-03-21 Iain Sandoe <iain@sandoe.co.uk> 4052 4053 * config/darwin.c (darwin_mergeable_constant_section): Collect 4054 section anchor checks into the caller. 4055 (machopic_select_section): Collect section anchor checks into 4056 the determination of 'effective zero-size' objects. When the 4057 size is unknown, assume it is non-zero, and thus return the 4058 'generic' section for the DECL. 4059 40602020-03-21 Iain Sandoe <iain@sandoe.co.uk> 4061 4062 PR target/93694 4063 * gcc/config/darwin.opt: Amend options descriptions. 4064 40652020-03-21 Richard Sandiford <richard.sandiford@arm.com> 4066 4067 PR rtl-optimization/94052 4068 * lra-constraints.c (simplify_operand_subreg): Reload the inner 4069 register of a paradoxical subreg if simplify_subreg_regno fails 4070 to give a valid hard register for the outer mode. 4071 40722020-03-20 Martin Jambor <mjambor@suse.cz> 4073 4074 PR tree-optimization/93435 4075 * params.opt (sra-max-propagations): New parameter. 4076 * tree-sra.c (propagation_budget): New variable. 4077 (budget_for_propagation_access): New function. 4078 (propagate_subaccesses_from_rhs): Use it. 4079 (propagate_subaccesses_from_lhs): Likewise. 4080 (propagate_all_subaccesses): Set up and destroy propagation_budget. 4081 40822020-03-20 Carl Love <cel@us.ibm.com> 4083 4084 PR/target 87583 4085 * gcc/config/rs6000/rs6000.c (rs6000_option_override_internal): 4086 Add check for TARGET_FPRND for Power 7 or newer. 4087 40882020-03-20 Jan Hubicka <hubicka@ucw.cz> 4089 4090 PR ipa/93347 4091 * cgraph.c (symbol_table::create_edge): Update calls_comdat_local flag. 4092 (cgraph_edge::redirect_callee): Move here; likewise. 4093 (cgraph_node::remove_callees): Update calls_comdat_local flag. 4094 (cgraph_node::verify_node): Verify that calls_comdat_local flag match 4095 reality. 4096 (cgraph_node::check_calls_comdat_local_p): New member function. 4097 * cgraph.h (cgraph_node::check_calls_comdat_local_p): Declare. 4098 (cgraph_edge::redirect_callee): Move offline. 4099 * ipa-fnsummary.c (compute_fn_summary): Do not compute 4100 calls_comdat_local flag here. 4101 * ipa-inline-transform.c (inline_call): Fix updating of 4102 calls_comdat_local flag. 4103 * ipa-split.c (split_function): Use true instead of 1 to set the flag. 4104 * symtab.c (symtab_node::add_to_same_comdat_group): Update 4105 calls_comdat_local flag. 4106 41072020-03-20 Richard Biener <rguenther@suse.de> 4108 4109 * tree-vect-slp.c (vect_analyze_slp_instance): Dump SLP tree 4110 from the possibly modified root. 4111 41122020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 4113 Andre Vieira <andre.simoesdiasvieira@arm.com> 4114 Mihail Ionescu <mihail.ionescu@arm.com> 4115 4116 * config/arm/arm_mve.h (vst1q_p_u8): Define macro. 4117 (vst1q_p_s8): Likewise. 4118 (vst2q_s8): Likewise. 4119 (vst2q_u8): Likewise. 4120 (vld1q_z_u8): Likewise. 4121 (vld1q_z_s8): Likewise. 4122 (vld2q_s8): Likewise. 4123 (vld2q_u8): Likewise. 4124 (vld4q_s8): Likewise. 4125 (vld4q_u8): Likewise. 4126 (vst1q_p_u16): Likewise. 4127 (vst1q_p_s16): Likewise. 4128 (vst2q_s16): Likewise. 4129 (vst2q_u16): Likewise. 4130 (vld1q_z_u16): Likewise. 4131 (vld1q_z_s16): Likewise. 4132 (vld2q_s16): Likewise. 4133 (vld2q_u16): Likewise. 4134 (vld4q_s16): Likewise. 4135 (vld4q_u16): Likewise. 4136 (vst1q_p_u32): Likewise. 4137 (vst1q_p_s32): Likewise. 4138 (vst2q_s32): Likewise. 4139 (vst2q_u32): Likewise. 4140 (vld1q_z_u32): Likewise. 4141 (vld1q_z_s32): Likewise. 4142 (vld2q_s32): Likewise. 4143 (vld2q_u32): Likewise. 4144 (vld4q_s32): Likewise. 4145 (vld4q_u32): Likewise. 4146 (vld4q_f16): Likewise. 4147 (vld2q_f16): Likewise. 4148 (vld1q_z_f16): Likewise. 4149 (vst2q_f16): Likewise. 4150 (vst1q_p_f16): Likewise. 4151 (vld4q_f32): Likewise. 4152 (vld2q_f32): Likewise. 4153 (vld1q_z_f32): Likewise. 4154 (vst2q_f32): Likewise. 4155 (vst1q_p_f32): Likewise. 4156 (__arm_vst1q_p_u8): Define intrinsic. 4157 (__arm_vst1q_p_s8): Likewise. 4158 (__arm_vst2q_s8): Likewise. 4159 (__arm_vst2q_u8): Likewise. 4160 (__arm_vld1q_z_u8): Likewise. 4161 (__arm_vld1q_z_s8): Likewise. 4162 (__arm_vld2q_s8): Likewise. 4163 (__arm_vld2q_u8): Likewise. 4164 (__arm_vld4q_s8): Likewise. 4165 (__arm_vld4q_u8): Likewise. 4166 (__arm_vst1q_p_u16): Likewise. 4167 (__arm_vst1q_p_s16): Likewise. 4168 (__arm_vst2q_s16): Likewise. 4169 (__arm_vst2q_u16): Likewise. 4170 (__arm_vld1q_z_u16): Likewise. 4171 (__arm_vld1q_z_s16): Likewise. 4172 (__arm_vld2q_s16): Likewise. 4173 (__arm_vld2q_u16): Likewise. 4174 (__arm_vld4q_s16): Likewise. 4175 (__arm_vld4q_u16): Likewise. 4176 (__arm_vst1q_p_u32): Likewise. 4177 (__arm_vst1q_p_s32): Likewise. 4178 (__arm_vst2q_s32): Likewise. 4179 (__arm_vst2q_u32): Likewise. 4180 (__arm_vld1q_z_u32): Likewise. 4181 (__arm_vld1q_z_s32): Likewise. 4182 (__arm_vld2q_s32): Likewise. 4183 (__arm_vld2q_u32): Likewise. 4184 (__arm_vld4q_s32): Likewise. 4185 (__arm_vld4q_u32): Likewise. 4186 (__arm_vld4q_f16): Likewise. 4187 (__arm_vld2q_f16): Likewise. 4188 (__arm_vld1q_z_f16): Likewise. 4189 (__arm_vst2q_f16): Likewise. 4190 (__arm_vst1q_p_f16): Likewise. 4191 (__arm_vld4q_f32): Likewise. 4192 (__arm_vld2q_f32): Likewise. 4193 (__arm_vld1q_z_f32): Likewise. 4194 (__arm_vst2q_f32): Likewise. 4195 (__arm_vst1q_p_f32): Likewise. 4196 (vld1q_z): Define polymorphic variant. 4197 (vld2q): Likewise. 4198 (vld4q): Likewise. 4199 (vst1q_p): Likewise. 4200 (vst2q): Likewise. 4201 * config/arm/arm_mve_builtins.def (STORE1): Use builtin qualifier. 4202 (LOAD1): Likewise. 4203 * config/arm/mve.md (mve_vst2q<mode>): Define RTL pattern. 4204 (mve_vld2q<mode>): Likewise. 4205 (mve_vld4q<mode>): Likewise. 4206 42072020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 4208 Andre Vieira <andre.simoesdiasvieira@arm.com> 4209 Mihail Ionescu <mihail.ionescu@arm.com> 4210 4211 * config/arm/arm-builtins.c (ARM_BUILTIN_GET_FPSCR_NZCVQC): Define. 4212 (ARM_BUILTIN_SET_FPSCR_NZCVQC): Likewise. 4213 (arm_init_mve_builtins): Add "__builtin_arm_get_fpscr_nzcvqc" and 4214 "__builtin_arm_set_fpscr_nzcvqc" to arm_builtin_decls array. 4215 (arm_expand_builtin): Define case ARM_BUILTIN_GET_FPSCR_NZCVQC 4216 and ARM_BUILTIN_SET_FPSCR_NZCVQC. 4217 * config/arm/arm_mve.h (vadciq_s32): Define macro. 4218 (vadciq_u32): Likewise. 4219 (vadciq_m_s32): Likewise. 4220 (vadciq_m_u32): Likewise. 4221 (vadcq_s32): Likewise. 4222 (vadcq_u32): Likewise. 4223 (vadcq_m_s32): Likewise. 4224 (vadcq_m_u32): Likewise. 4225 (vsbciq_s32): Likewise. 4226 (vsbciq_u32): Likewise. 4227 (vsbciq_m_s32): Likewise. 4228 (vsbciq_m_u32): Likewise. 4229 (vsbcq_s32): Likewise. 4230 (vsbcq_u32): Likewise. 4231 (vsbcq_m_s32): Likewise. 4232 (vsbcq_m_u32): Likewise. 4233 (__arm_vadciq_s32): Define intrinsic. 4234 (__arm_vadciq_u32): Likewise. 4235 (__arm_vadciq_m_s32): Likewise. 4236 (__arm_vadciq_m_u32): Likewise. 4237 (__arm_vadcq_s32): Likewise. 4238 (__arm_vadcq_u32): Likewise. 4239 (__arm_vadcq_m_s32): Likewise. 4240 (__arm_vadcq_m_u32): Likewise. 4241 (__arm_vsbciq_s32): Likewise. 4242 (__arm_vsbciq_u32): Likewise. 4243 (__arm_vsbciq_m_s32): Likewise. 4244 (__arm_vsbciq_m_u32): Likewise. 4245 (__arm_vsbcq_s32): Likewise. 4246 (__arm_vsbcq_u32): Likewise. 4247 (__arm_vsbcq_m_s32): Likewise. 4248 (__arm_vsbcq_m_u32): Likewise. 4249 (vadciq_m): Define polymorphic variant. 4250 (vadciq): Likewise. 4251 (vadcq_m): Likewise. 4252 (vadcq): Likewise. 4253 (vsbciq_m): Likewise. 4254 (vsbciq): Likewise. 4255 (vsbcq_m): Likewise. 4256 (vsbcq): Likewise. 4257 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_NONE): Use builtin 4258 qualifier. 4259 (BINOP_UNONE_UNONE_UNONE): Likewise. 4260 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise. 4261 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise. 4262 * config/arm/mve.md (VADCIQ): Define iterator. 4263 (VADCIQ_M): Likewise. 4264 (VSBCQ): Likewise. 4265 (VSBCQ_M): Likewise. 4266 (VSBCIQ): Likewise. 4267 (VSBCIQ_M): Likewise. 4268 (VADCQ): Likewise. 4269 (VADCQ_M): Likewise. 4270 (mve_vadciq_m_<supf>v4si): Define RTL pattern. 4271 (mve_vadciq_<supf>v4si): Likewise. 4272 (mve_vadcq_m_<supf>v4si): Likewise. 4273 (mve_vadcq_<supf>v4si): Likewise. 4274 (mve_vsbciq_m_<supf>v4si): Likewise. 4275 (mve_vsbciq_<supf>v4si): Likewise. 4276 (mve_vsbcq_m_<supf>v4si): Likewise. 4277 (mve_vsbcq_<supf>v4si): Likewise. 4278 (get_fpscr_nzcvqc): Define isns. 4279 (set_fpscr_nzcvqc): Define isns. 4280 * config/arm/unspecs.md (UNSPEC_GET_FPSCR_NZCVQC): Define. 4281 (UNSPEC_SET_FPSCR_NZCVQC): Define. 4282 42832020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 4284 4285 * config/arm/arm_mve.h (vddupq_x_n_u8): Define macro. 4286 (vddupq_x_n_u16): Likewise. 4287 (vddupq_x_n_u32): Likewise. 4288 (vddupq_x_wb_u8): Likewise. 4289 (vddupq_x_wb_u16): Likewise. 4290 (vddupq_x_wb_u32): Likewise. 4291 (vdwdupq_x_n_u8): Likewise. 4292 (vdwdupq_x_n_u16): Likewise. 4293 (vdwdupq_x_n_u32): Likewise. 4294 (vdwdupq_x_wb_u8): Likewise. 4295 (vdwdupq_x_wb_u16): Likewise. 4296 (vdwdupq_x_wb_u32): Likewise. 4297 (vidupq_x_n_u8): Likewise. 4298 (vidupq_x_n_u16): Likewise. 4299 (vidupq_x_n_u32): Likewise. 4300 (vidupq_x_wb_u8): Likewise. 4301 (vidupq_x_wb_u16): Likewise. 4302 (vidupq_x_wb_u32): Likewise. 4303 (viwdupq_x_n_u8): Likewise. 4304 (viwdupq_x_n_u16): Likewise. 4305 (viwdupq_x_n_u32): Likewise. 4306 (viwdupq_x_wb_u8): Likewise. 4307 (viwdupq_x_wb_u16): Likewise. 4308 (viwdupq_x_wb_u32): Likewise. 4309 (vdupq_x_n_s8): Likewise. 4310 (vdupq_x_n_s16): Likewise. 4311 (vdupq_x_n_s32): Likewise. 4312 (vdupq_x_n_u8): Likewise. 4313 (vdupq_x_n_u16): Likewise. 4314 (vdupq_x_n_u32): Likewise. 4315 (vminq_x_s8): Likewise. 4316 (vminq_x_s16): Likewise. 4317 (vminq_x_s32): Likewise. 4318 (vminq_x_u8): Likewise. 4319 (vminq_x_u16): Likewise. 4320 (vminq_x_u32): Likewise. 4321 (vmaxq_x_s8): Likewise. 4322 (vmaxq_x_s16): Likewise. 4323 (vmaxq_x_s32): Likewise. 4324 (vmaxq_x_u8): Likewise. 4325 (vmaxq_x_u16): Likewise. 4326 (vmaxq_x_u32): Likewise. 4327 (vabdq_x_s8): Likewise. 4328 (vabdq_x_s16): Likewise. 4329 (vabdq_x_s32): Likewise. 4330 (vabdq_x_u8): Likewise. 4331 (vabdq_x_u16): Likewise. 4332 (vabdq_x_u32): Likewise. 4333 (vabsq_x_s8): Likewise. 4334 (vabsq_x_s16): Likewise. 4335 (vabsq_x_s32): Likewise. 4336 (vaddq_x_s8): Likewise. 4337 (vaddq_x_s16): Likewise. 4338 (vaddq_x_s32): Likewise. 4339 (vaddq_x_n_s8): Likewise. 4340 (vaddq_x_n_s16): Likewise. 4341 (vaddq_x_n_s32): Likewise. 4342 (vaddq_x_u8): Likewise. 4343 (vaddq_x_u16): Likewise. 4344 (vaddq_x_u32): Likewise. 4345 (vaddq_x_n_u8): Likewise. 4346 (vaddq_x_n_u16): Likewise. 4347 (vaddq_x_n_u32): Likewise. 4348 (vclsq_x_s8): Likewise. 4349 (vclsq_x_s16): Likewise. 4350 (vclsq_x_s32): Likewise. 4351 (vclzq_x_s8): Likewise. 4352 (vclzq_x_s16): Likewise. 4353 (vclzq_x_s32): Likewise. 4354 (vclzq_x_u8): Likewise. 4355 (vclzq_x_u16): Likewise. 4356 (vclzq_x_u32): Likewise. 4357 (vnegq_x_s8): Likewise. 4358 (vnegq_x_s16): Likewise. 4359 (vnegq_x_s32): Likewise. 4360 (vmulhq_x_s8): Likewise. 4361 (vmulhq_x_s16): Likewise. 4362 (vmulhq_x_s32): Likewise. 4363 (vmulhq_x_u8): Likewise. 4364 (vmulhq_x_u16): Likewise. 4365 (vmulhq_x_u32): Likewise. 4366 (vmullbq_poly_x_p8): Likewise. 4367 (vmullbq_poly_x_p16): Likewise. 4368 (vmullbq_int_x_s8): Likewise. 4369 (vmullbq_int_x_s16): Likewise. 4370 (vmullbq_int_x_s32): Likewise. 4371 (vmullbq_int_x_u8): Likewise. 4372 (vmullbq_int_x_u16): Likewise. 4373 (vmullbq_int_x_u32): Likewise. 4374 (vmulltq_poly_x_p8): Likewise. 4375 (vmulltq_poly_x_p16): Likewise. 4376 (vmulltq_int_x_s8): Likewise. 4377 (vmulltq_int_x_s16): Likewise. 4378 (vmulltq_int_x_s32): Likewise. 4379 (vmulltq_int_x_u8): Likewise. 4380 (vmulltq_int_x_u16): Likewise. 4381 (vmulltq_int_x_u32): Likewise. 4382 (vmulq_x_s8): Likewise. 4383 (vmulq_x_s16): Likewise. 4384 (vmulq_x_s32): Likewise. 4385 (vmulq_x_n_s8): Likewise. 4386 (vmulq_x_n_s16): Likewise. 4387 (vmulq_x_n_s32): Likewise. 4388 (vmulq_x_u8): Likewise. 4389 (vmulq_x_u16): Likewise. 4390 (vmulq_x_u32): Likewise. 4391 (vmulq_x_n_u8): Likewise. 4392 (vmulq_x_n_u16): Likewise. 4393 (vmulq_x_n_u32): Likewise. 4394 (vsubq_x_s8): Likewise. 4395 (vsubq_x_s16): Likewise. 4396 (vsubq_x_s32): Likewise. 4397 (vsubq_x_n_s8): Likewise. 4398 (vsubq_x_n_s16): Likewise. 4399 (vsubq_x_n_s32): Likewise. 4400 (vsubq_x_u8): Likewise. 4401 (vsubq_x_u16): Likewise. 4402 (vsubq_x_u32): Likewise. 4403 (vsubq_x_n_u8): Likewise. 4404 (vsubq_x_n_u16): Likewise. 4405 (vsubq_x_n_u32): Likewise. 4406 (vcaddq_rot90_x_s8): Likewise. 4407 (vcaddq_rot90_x_s16): Likewise. 4408 (vcaddq_rot90_x_s32): Likewise. 4409 (vcaddq_rot90_x_u8): Likewise. 4410 (vcaddq_rot90_x_u16): Likewise. 4411 (vcaddq_rot90_x_u32): Likewise. 4412 (vcaddq_rot270_x_s8): Likewise. 4413 (vcaddq_rot270_x_s16): Likewise. 4414 (vcaddq_rot270_x_s32): Likewise. 4415 (vcaddq_rot270_x_u8): Likewise. 4416 (vcaddq_rot270_x_u16): Likewise. 4417 (vcaddq_rot270_x_u32): Likewise. 4418 (vhaddq_x_n_s8): Likewise. 4419 (vhaddq_x_n_s16): Likewise. 4420 (vhaddq_x_n_s32): Likewise. 4421 (vhaddq_x_n_u8): Likewise. 4422 (vhaddq_x_n_u16): Likewise. 4423 (vhaddq_x_n_u32): Likewise. 4424 (vhaddq_x_s8): Likewise. 4425 (vhaddq_x_s16): Likewise. 4426 (vhaddq_x_s32): Likewise. 4427 (vhaddq_x_u8): Likewise. 4428 (vhaddq_x_u16): Likewise. 4429 (vhaddq_x_u32): Likewise. 4430 (vhcaddq_rot90_x_s8): Likewise. 4431 (vhcaddq_rot90_x_s16): Likewise. 4432 (vhcaddq_rot90_x_s32): Likewise. 4433 (vhcaddq_rot270_x_s8): Likewise. 4434 (vhcaddq_rot270_x_s16): Likewise. 4435 (vhcaddq_rot270_x_s32): Likewise. 4436 (vhsubq_x_n_s8): Likewise. 4437 (vhsubq_x_n_s16): Likewise. 4438 (vhsubq_x_n_s32): Likewise. 4439 (vhsubq_x_n_u8): Likewise. 4440 (vhsubq_x_n_u16): Likewise. 4441 (vhsubq_x_n_u32): Likewise. 4442 (vhsubq_x_s8): Likewise. 4443 (vhsubq_x_s16): Likewise. 4444 (vhsubq_x_s32): Likewise. 4445 (vhsubq_x_u8): Likewise. 4446 (vhsubq_x_u16): Likewise. 4447 (vhsubq_x_u32): Likewise. 4448 (vrhaddq_x_s8): Likewise. 4449 (vrhaddq_x_s16): Likewise. 4450 (vrhaddq_x_s32): Likewise. 4451 (vrhaddq_x_u8): Likewise. 4452 (vrhaddq_x_u16): Likewise. 4453 (vrhaddq_x_u32): Likewise. 4454 (vrmulhq_x_s8): Likewise. 4455 (vrmulhq_x_s16): Likewise. 4456 (vrmulhq_x_s32): Likewise. 4457 (vrmulhq_x_u8): Likewise. 4458 (vrmulhq_x_u16): Likewise. 4459 (vrmulhq_x_u32): Likewise. 4460 (vandq_x_s8): Likewise. 4461 (vandq_x_s16): Likewise. 4462 (vandq_x_s32): Likewise. 4463 (vandq_x_u8): Likewise. 4464 (vandq_x_u16): Likewise. 4465 (vandq_x_u32): Likewise. 4466 (vbicq_x_s8): Likewise. 4467 (vbicq_x_s16): Likewise. 4468 (vbicq_x_s32): Likewise. 4469 (vbicq_x_u8): Likewise. 4470 (vbicq_x_u16): Likewise. 4471 (vbicq_x_u32): Likewise. 4472 (vbrsrq_x_n_s8): Likewise. 4473 (vbrsrq_x_n_s16): Likewise. 4474 (vbrsrq_x_n_s32): Likewise. 4475 (vbrsrq_x_n_u8): Likewise. 4476 (vbrsrq_x_n_u16): Likewise. 4477 (vbrsrq_x_n_u32): Likewise. 4478 (veorq_x_s8): Likewise. 4479 (veorq_x_s16): Likewise. 4480 (veorq_x_s32): Likewise. 4481 (veorq_x_u8): Likewise. 4482 (veorq_x_u16): Likewise. 4483 (veorq_x_u32): Likewise. 4484 (vmovlbq_x_s8): Likewise. 4485 (vmovlbq_x_s16): Likewise. 4486 (vmovlbq_x_u8): Likewise. 4487 (vmovlbq_x_u16): Likewise. 4488 (vmovltq_x_s8): Likewise. 4489 (vmovltq_x_s16): Likewise. 4490 (vmovltq_x_u8): Likewise. 4491 (vmovltq_x_u16): Likewise. 4492 (vmvnq_x_s8): Likewise. 4493 (vmvnq_x_s16): Likewise. 4494 (vmvnq_x_s32): Likewise. 4495 (vmvnq_x_u8): Likewise. 4496 (vmvnq_x_u16): Likewise. 4497 (vmvnq_x_u32): Likewise. 4498 (vmvnq_x_n_s16): Likewise. 4499 (vmvnq_x_n_s32): Likewise. 4500 (vmvnq_x_n_u16): Likewise. 4501 (vmvnq_x_n_u32): Likewise. 4502 (vornq_x_s8): Likewise. 4503 (vornq_x_s16): Likewise. 4504 (vornq_x_s32): Likewise. 4505 (vornq_x_u8): Likewise. 4506 (vornq_x_u16): Likewise. 4507 (vornq_x_u32): Likewise. 4508 (vorrq_x_s8): Likewise. 4509 (vorrq_x_s16): Likewise. 4510 (vorrq_x_s32): Likewise. 4511 (vorrq_x_u8): Likewise. 4512 (vorrq_x_u16): Likewise. 4513 (vorrq_x_u32): Likewise. 4514 (vrev16q_x_s8): Likewise. 4515 (vrev16q_x_u8): Likewise. 4516 (vrev32q_x_s8): Likewise. 4517 (vrev32q_x_s16): Likewise. 4518 (vrev32q_x_u8): Likewise. 4519 (vrev32q_x_u16): Likewise. 4520 (vrev64q_x_s8): Likewise. 4521 (vrev64q_x_s16): Likewise. 4522 (vrev64q_x_s32): Likewise. 4523 (vrev64q_x_u8): Likewise. 4524 (vrev64q_x_u16): Likewise. 4525 (vrev64q_x_u32): Likewise. 4526 (vrshlq_x_s8): Likewise. 4527 (vrshlq_x_s16): Likewise. 4528 (vrshlq_x_s32): Likewise. 4529 (vrshlq_x_u8): Likewise. 4530 (vrshlq_x_u16): Likewise. 4531 (vrshlq_x_u32): Likewise. 4532 (vshllbq_x_n_s8): Likewise. 4533 (vshllbq_x_n_s16): Likewise. 4534 (vshllbq_x_n_u8): Likewise. 4535 (vshllbq_x_n_u16): Likewise. 4536 (vshlltq_x_n_s8): Likewise. 4537 (vshlltq_x_n_s16): Likewise. 4538 (vshlltq_x_n_u8): Likewise. 4539 (vshlltq_x_n_u16): Likewise. 4540 (vshlq_x_s8): Likewise. 4541 (vshlq_x_s16): Likewise. 4542 (vshlq_x_s32): Likewise. 4543 (vshlq_x_u8): Likewise. 4544 (vshlq_x_u16): Likewise. 4545 (vshlq_x_u32): Likewise. 4546 (vshlq_x_n_s8): Likewise. 4547 (vshlq_x_n_s16): Likewise. 4548 (vshlq_x_n_s32): Likewise. 4549 (vshlq_x_n_u8): Likewise. 4550 (vshlq_x_n_u16): Likewise. 4551 (vshlq_x_n_u32): Likewise. 4552 (vrshrq_x_n_s8): Likewise. 4553 (vrshrq_x_n_s16): Likewise. 4554 (vrshrq_x_n_s32): Likewise. 4555 (vrshrq_x_n_u8): Likewise. 4556 (vrshrq_x_n_u16): Likewise. 4557 (vrshrq_x_n_u32): Likewise. 4558 (vshrq_x_n_s8): Likewise. 4559 (vshrq_x_n_s16): Likewise. 4560 (vshrq_x_n_s32): Likewise. 4561 (vshrq_x_n_u8): Likewise. 4562 (vshrq_x_n_u16): Likewise. 4563 (vshrq_x_n_u32): Likewise. 4564 (vdupq_x_n_f16): Likewise. 4565 (vdupq_x_n_f32): Likewise. 4566 (vminnmq_x_f16): Likewise. 4567 (vminnmq_x_f32): Likewise. 4568 (vmaxnmq_x_f16): Likewise. 4569 (vmaxnmq_x_f32): Likewise. 4570 (vabdq_x_f16): Likewise. 4571 (vabdq_x_f32): Likewise. 4572 (vabsq_x_f16): Likewise. 4573 (vabsq_x_f32): Likewise. 4574 (vaddq_x_f16): Likewise. 4575 (vaddq_x_f32): Likewise. 4576 (vaddq_x_n_f16): Likewise. 4577 (vaddq_x_n_f32): Likewise. 4578 (vnegq_x_f16): Likewise. 4579 (vnegq_x_f32): Likewise. 4580 (vmulq_x_f16): Likewise. 4581 (vmulq_x_f32): Likewise. 4582 (vmulq_x_n_f16): Likewise. 4583 (vmulq_x_n_f32): Likewise. 4584 (vsubq_x_f16): Likewise. 4585 (vsubq_x_f32): Likewise. 4586 (vsubq_x_n_f16): Likewise. 4587 (vsubq_x_n_f32): Likewise. 4588 (vcaddq_rot90_x_f16): Likewise. 4589 (vcaddq_rot90_x_f32): Likewise. 4590 (vcaddq_rot270_x_f16): Likewise. 4591 (vcaddq_rot270_x_f32): Likewise. 4592 (vcmulq_x_f16): Likewise. 4593 (vcmulq_x_f32): Likewise. 4594 (vcmulq_rot90_x_f16): Likewise. 4595 (vcmulq_rot90_x_f32): Likewise. 4596 (vcmulq_rot180_x_f16): Likewise. 4597 (vcmulq_rot180_x_f32): Likewise. 4598 (vcmulq_rot270_x_f16): Likewise. 4599 (vcmulq_rot270_x_f32): Likewise. 4600 (vcvtaq_x_s16_f16): Likewise. 4601 (vcvtaq_x_s32_f32): Likewise. 4602 (vcvtaq_x_u16_f16): Likewise. 4603 (vcvtaq_x_u32_f32): Likewise. 4604 (vcvtnq_x_s16_f16): Likewise. 4605 (vcvtnq_x_s32_f32): Likewise. 4606 (vcvtnq_x_u16_f16): Likewise. 4607 (vcvtnq_x_u32_f32): Likewise. 4608 (vcvtpq_x_s16_f16): Likewise. 4609 (vcvtpq_x_s32_f32): Likewise. 4610 (vcvtpq_x_u16_f16): Likewise. 4611 (vcvtpq_x_u32_f32): Likewise. 4612 (vcvtmq_x_s16_f16): Likewise. 4613 (vcvtmq_x_s32_f32): Likewise. 4614 (vcvtmq_x_u16_f16): Likewise. 4615 (vcvtmq_x_u32_f32): Likewise. 4616 (vcvtbq_x_f32_f16): Likewise. 4617 (vcvttq_x_f32_f16): Likewise. 4618 (vcvtq_x_f16_u16): Likewise. 4619 (vcvtq_x_f16_s16): Likewise. 4620 (vcvtq_x_f32_s32): Likewise. 4621 (vcvtq_x_f32_u32): Likewise. 4622 (vcvtq_x_n_f16_s16): Likewise. 4623 (vcvtq_x_n_f16_u16): Likewise. 4624 (vcvtq_x_n_f32_s32): Likewise. 4625 (vcvtq_x_n_f32_u32): Likewise. 4626 (vcvtq_x_s16_f16): Likewise. 4627 (vcvtq_x_s32_f32): Likewise. 4628 (vcvtq_x_u16_f16): Likewise. 4629 (vcvtq_x_u32_f32): Likewise. 4630 (vcvtq_x_n_s16_f16): Likewise. 4631 (vcvtq_x_n_s32_f32): Likewise. 4632 (vcvtq_x_n_u16_f16): Likewise. 4633 (vcvtq_x_n_u32_f32): Likewise. 4634 (vrndq_x_f16): Likewise. 4635 (vrndq_x_f32): Likewise. 4636 (vrndnq_x_f16): Likewise. 4637 (vrndnq_x_f32): Likewise. 4638 (vrndmq_x_f16): Likewise. 4639 (vrndmq_x_f32): Likewise. 4640 (vrndpq_x_f16): Likewise. 4641 (vrndpq_x_f32): Likewise. 4642 (vrndaq_x_f16): Likewise. 4643 (vrndaq_x_f32): Likewise. 4644 (vrndxq_x_f16): Likewise. 4645 (vrndxq_x_f32): Likewise. 4646 (vandq_x_f16): Likewise. 4647 (vandq_x_f32): Likewise. 4648 (vbicq_x_f16): Likewise. 4649 (vbicq_x_f32): Likewise. 4650 (vbrsrq_x_n_f16): Likewise. 4651 (vbrsrq_x_n_f32): Likewise. 4652 (veorq_x_f16): Likewise. 4653 (veorq_x_f32): Likewise. 4654 (vornq_x_f16): Likewise. 4655 (vornq_x_f32): Likewise. 4656 (vorrq_x_f16): Likewise. 4657 (vorrq_x_f32): Likewise. 4658 (vrev32q_x_f16): Likewise. 4659 (vrev64q_x_f16): Likewise. 4660 (vrev64q_x_f32): Likewise. 4661 (__arm_vddupq_x_n_u8): Define intrinsic. 4662 (__arm_vddupq_x_n_u16): Likewise. 4663 (__arm_vddupq_x_n_u32): Likewise. 4664 (__arm_vddupq_x_wb_u8): Likewise. 4665 (__arm_vddupq_x_wb_u16): Likewise. 4666 (__arm_vddupq_x_wb_u32): Likewise. 4667 (__arm_vdwdupq_x_n_u8): Likewise. 4668 (__arm_vdwdupq_x_n_u16): Likewise. 4669 (__arm_vdwdupq_x_n_u32): Likewise. 4670 (__arm_vdwdupq_x_wb_u8): Likewise. 4671 (__arm_vdwdupq_x_wb_u16): Likewise. 4672 (__arm_vdwdupq_x_wb_u32): Likewise. 4673 (__arm_vidupq_x_n_u8): Likewise. 4674 (__arm_vidupq_x_n_u16): Likewise. 4675 (__arm_vidupq_x_n_u32): Likewise. 4676 (__arm_vidupq_x_wb_u8): Likewise. 4677 (__arm_vidupq_x_wb_u16): Likewise. 4678 (__arm_vidupq_x_wb_u32): Likewise. 4679 (__arm_viwdupq_x_n_u8): Likewise. 4680 (__arm_viwdupq_x_n_u16): Likewise. 4681 (__arm_viwdupq_x_n_u32): Likewise. 4682 (__arm_viwdupq_x_wb_u8): Likewise. 4683 (__arm_viwdupq_x_wb_u16): Likewise. 4684 (__arm_viwdupq_x_wb_u32): Likewise. 4685 (__arm_vdupq_x_n_s8): Likewise. 4686 (__arm_vdupq_x_n_s16): Likewise. 4687 (__arm_vdupq_x_n_s32): Likewise. 4688 (__arm_vdupq_x_n_u8): Likewise. 4689 (__arm_vdupq_x_n_u16): Likewise. 4690 (__arm_vdupq_x_n_u32): Likewise. 4691 (__arm_vminq_x_s8): Likewise. 4692 (__arm_vminq_x_s16): Likewise. 4693 (__arm_vminq_x_s32): Likewise. 4694 (__arm_vminq_x_u8): Likewise. 4695 (__arm_vminq_x_u16): Likewise. 4696 (__arm_vminq_x_u32): Likewise. 4697 (__arm_vmaxq_x_s8): Likewise. 4698 (__arm_vmaxq_x_s16): Likewise. 4699 (__arm_vmaxq_x_s32): Likewise. 4700 (__arm_vmaxq_x_u8): Likewise. 4701 (__arm_vmaxq_x_u16): Likewise. 4702 (__arm_vmaxq_x_u32): Likewise. 4703 (__arm_vabdq_x_s8): Likewise. 4704 (__arm_vabdq_x_s16): Likewise. 4705 (__arm_vabdq_x_s32): Likewise. 4706 (__arm_vabdq_x_u8): Likewise. 4707 (__arm_vabdq_x_u16): Likewise. 4708 (__arm_vabdq_x_u32): Likewise. 4709 (__arm_vabsq_x_s8): Likewise. 4710 (__arm_vabsq_x_s16): Likewise. 4711 (__arm_vabsq_x_s32): Likewise. 4712 (__arm_vaddq_x_s8): Likewise. 4713 (__arm_vaddq_x_s16): Likewise. 4714 (__arm_vaddq_x_s32): Likewise. 4715 (__arm_vaddq_x_n_s8): Likewise. 4716 (__arm_vaddq_x_n_s16): Likewise. 4717 (__arm_vaddq_x_n_s32): Likewise. 4718 (__arm_vaddq_x_u8): Likewise. 4719 (__arm_vaddq_x_u16): Likewise. 4720 (__arm_vaddq_x_u32): Likewise. 4721 (__arm_vaddq_x_n_u8): Likewise. 4722 (__arm_vaddq_x_n_u16): Likewise. 4723 (__arm_vaddq_x_n_u32): Likewise. 4724 (__arm_vclsq_x_s8): Likewise. 4725 (__arm_vclsq_x_s16): Likewise. 4726 (__arm_vclsq_x_s32): Likewise. 4727 (__arm_vclzq_x_s8): Likewise. 4728 (__arm_vclzq_x_s16): Likewise. 4729 (__arm_vclzq_x_s32): Likewise. 4730 (__arm_vclzq_x_u8): Likewise. 4731 (__arm_vclzq_x_u16): Likewise. 4732 (__arm_vclzq_x_u32): Likewise. 4733 (__arm_vnegq_x_s8): Likewise. 4734 (__arm_vnegq_x_s16): Likewise. 4735 (__arm_vnegq_x_s32): Likewise. 4736 (__arm_vmulhq_x_s8): Likewise. 4737 (__arm_vmulhq_x_s16): Likewise. 4738 (__arm_vmulhq_x_s32): Likewise. 4739 (__arm_vmulhq_x_u8): Likewise. 4740 (__arm_vmulhq_x_u16): Likewise. 4741 (__arm_vmulhq_x_u32): Likewise. 4742 (__arm_vmullbq_poly_x_p8): Likewise. 4743 (__arm_vmullbq_poly_x_p16): Likewise. 4744 (__arm_vmullbq_int_x_s8): Likewise. 4745 (__arm_vmullbq_int_x_s16): Likewise. 4746 (__arm_vmullbq_int_x_s32): Likewise. 4747 (__arm_vmullbq_int_x_u8): Likewise. 4748 (__arm_vmullbq_int_x_u16): Likewise. 4749 (__arm_vmullbq_int_x_u32): Likewise. 4750 (__arm_vmulltq_poly_x_p8): Likewise. 4751 (__arm_vmulltq_poly_x_p16): Likewise. 4752 (__arm_vmulltq_int_x_s8): Likewise. 4753 (__arm_vmulltq_int_x_s16): Likewise. 4754 (__arm_vmulltq_int_x_s32): Likewise. 4755 (__arm_vmulltq_int_x_u8): Likewise. 4756 (__arm_vmulltq_int_x_u16): Likewise. 4757 (__arm_vmulltq_int_x_u32): Likewise. 4758 (__arm_vmulq_x_s8): Likewise. 4759 (__arm_vmulq_x_s16): Likewise. 4760 (__arm_vmulq_x_s32): Likewise. 4761 (__arm_vmulq_x_n_s8): Likewise. 4762 (__arm_vmulq_x_n_s16): Likewise. 4763 (__arm_vmulq_x_n_s32): Likewise. 4764 (__arm_vmulq_x_u8): Likewise. 4765 (__arm_vmulq_x_u16): Likewise. 4766 (__arm_vmulq_x_u32): Likewise. 4767 (__arm_vmulq_x_n_u8): Likewise. 4768 (__arm_vmulq_x_n_u16): Likewise. 4769 (__arm_vmulq_x_n_u32): Likewise. 4770 (__arm_vsubq_x_s8): Likewise. 4771 (__arm_vsubq_x_s16): Likewise. 4772 (__arm_vsubq_x_s32): Likewise. 4773 (__arm_vsubq_x_n_s8): Likewise. 4774 (__arm_vsubq_x_n_s16): Likewise. 4775 (__arm_vsubq_x_n_s32): Likewise. 4776 (__arm_vsubq_x_u8): Likewise. 4777 (__arm_vsubq_x_u16): Likewise. 4778 (__arm_vsubq_x_u32): Likewise. 4779 (__arm_vsubq_x_n_u8): Likewise. 4780 (__arm_vsubq_x_n_u16): Likewise. 4781 (__arm_vsubq_x_n_u32): Likewise. 4782 (__arm_vcaddq_rot90_x_s8): Likewise. 4783 (__arm_vcaddq_rot90_x_s16): Likewise. 4784 (__arm_vcaddq_rot90_x_s32): Likewise. 4785 (__arm_vcaddq_rot90_x_u8): Likewise. 4786 (__arm_vcaddq_rot90_x_u16): Likewise. 4787 (__arm_vcaddq_rot90_x_u32): Likewise. 4788 (__arm_vcaddq_rot270_x_s8): Likewise. 4789 (__arm_vcaddq_rot270_x_s16): Likewise. 4790 (__arm_vcaddq_rot270_x_s32): Likewise. 4791 (__arm_vcaddq_rot270_x_u8): Likewise. 4792 (__arm_vcaddq_rot270_x_u16): Likewise. 4793 (__arm_vcaddq_rot270_x_u32): Likewise. 4794 (__arm_vhaddq_x_n_s8): Likewise. 4795 (__arm_vhaddq_x_n_s16): Likewise. 4796 (__arm_vhaddq_x_n_s32): Likewise. 4797 (__arm_vhaddq_x_n_u8): Likewise. 4798 (__arm_vhaddq_x_n_u16): Likewise. 4799 (__arm_vhaddq_x_n_u32): Likewise. 4800 (__arm_vhaddq_x_s8): Likewise. 4801 (__arm_vhaddq_x_s16): Likewise. 4802 (__arm_vhaddq_x_s32): Likewise. 4803 (__arm_vhaddq_x_u8): Likewise. 4804 (__arm_vhaddq_x_u16): Likewise. 4805 (__arm_vhaddq_x_u32): Likewise. 4806 (__arm_vhcaddq_rot90_x_s8): Likewise. 4807 (__arm_vhcaddq_rot90_x_s16): Likewise. 4808 (__arm_vhcaddq_rot90_x_s32): Likewise. 4809 (__arm_vhcaddq_rot270_x_s8): Likewise. 4810 (__arm_vhcaddq_rot270_x_s16): Likewise. 4811 (__arm_vhcaddq_rot270_x_s32): Likewise. 4812 (__arm_vhsubq_x_n_s8): Likewise. 4813 (__arm_vhsubq_x_n_s16): Likewise. 4814 (__arm_vhsubq_x_n_s32): Likewise. 4815 (__arm_vhsubq_x_n_u8): Likewise. 4816 (__arm_vhsubq_x_n_u16): Likewise. 4817 (__arm_vhsubq_x_n_u32): Likewise. 4818 (__arm_vhsubq_x_s8): Likewise. 4819 (__arm_vhsubq_x_s16): Likewise. 4820 (__arm_vhsubq_x_s32): Likewise. 4821 (__arm_vhsubq_x_u8): Likewise. 4822 (__arm_vhsubq_x_u16): Likewise. 4823 (__arm_vhsubq_x_u32): Likewise. 4824 (__arm_vrhaddq_x_s8): Likewise. 4825 (__arm_vrhaddq_x_s16): Likewise. 4826 (__arm_vrhaddq_x_s32): Likewise. 4827 (__arm_vrhaddq_x_u8): Likewise. 4828 (__arm_vrhaddq_x_u16): Likewise. 4829 (__arm_vrhaddq_x_u32): Likewise. 4830 (__arm_vrmulhq_x_s8): Likewise. 4831 (__arm_vrmulhq_x_s16): Likewise. 4832 (__arm_vrmulhq_x_s32): Likewise. 4833 (__arm_vrmulhq_x_u8): Likewise. 4834 (__arm_vrmulhq_x_u16): Likewise. 4835 (__arm_vrmulhq_x_u32): Likewise. 4836 (__arm_vandq_x_s8): Likewise. 4837 (__arm_vandq_x_s16): Likewise. 4838 (__arm_vandq_x_s32): Likewise. 4839 (__arm_vandq_x_u8): Likewise. 4840 (__arm_vandq_x_u16): Likewise. 4841 (__arm_vandq_x_u32): Likewise. 4842 (__arm_vbicq_x_s8): Likewise. 4843 (__arm_vbicq_x_s16): Likewise. 4844 (__arm_vbicq_x_s32): Likewise. 4845 (__arm_vbicq_x_u8): Likewise. 4846 (__arm_vbicq_x_u16): Likewise. 4847 (__arm_vbicq_x_u32): Likewise. 4848 (__arm_vbrsrq_x_n_s8): Likewise. 4849 (__arm_vbrsrq_x_n_s16): Likewise. 4850 (__arm_vbrsrq_x_n_s32): Likewise. 4851 (__arm_vbrsrq_x_n_u8): Likewise. 4852 (__arm_vbrsrq_x_n_u16): Likewise. 4853 (__arm_vbrsrq_x_n_u32): Likewise. 4854 (__arm_veorq_x_s8): Likewise. 4855 (__arm_veorq_x_s16): Likewise. 4856 (__arm_veorq_x_s32): Likewise. 4857 (__arm_veorq_x_u8): Likewise. 4858 (__arm_veorq_x_u16): Likewise. 4859 (__arm_veorq_x_u32): Likewise. 4860 (__arm_vmovlbq_x_s8): Likewise. 4861 (__arm_vmovlbq_x_s16): Likewise. 4862 (__arm_vmovlbq_x_u8): Likewise. 4863 (__arm_vmovlbq_x_u16): Likewise. 4864 (__arm_vmovltq_x_s8): Likewise. 4865 (__arm_vmovltq_x_s16): Likewise. 4866 (__arm_vmovltq_x_u8): Likewise. 4867 (__arm_vmovltq_x_u16): Likewise. 4868 (__arm_vmvnq_x_s8): Likewise. 4869 (__arm_vmvnq_x_s16): Likewise. 4870 (__arm_vmvnq_x_s32): Likewise. 4871 (__arm_vmvnq_x_u8): Likewise. 4872 (__arm_vmvnq_x_u16): Likewise. 4873 (__arm_vmvnq_x_u32): Likewise. 4874 (__arm_vmvnq_x_n_s16): Likewise. 4875 (__arm_vmvnq_x_n_s32): Likewise. 4876 (__arm_vmvnq_x_n_u16): Likewise. 4877 (__arm_vmvnq_x_n_u32): Likewise. 4878 (__arm_vornq_x_s8): Likewise. 4879 (__arm_vornq_x_s16): Likewise. 4880 (__arm_vornq_x_s32): Likewise. 4881 (__arm_vornq_x_u8): Likewise. 4882 (__arm_vornq_x_u16): Likewise. 4883 (__arm_vornq_x_u32): Likewise. 4884 (__arm_vorrq_x_s8): Likewise. 4885 (__arm_vorrq_x_s16): Likewise. 4886 (__arm_vorrq_x_s32): Likewise. 4887 (__arm_vorrq_x_u8): Likewise. 4888 (__arm_vorrq_x_u16): Likewise. 4889 (__arm_vorrq_x_u32): Likewise. 4890 (__arm_vrev16q_x_s8): Likewise. 4891 (__arm_vrev16q_x_u8): Likewise. 4892 (__arm_vrev32q_x_s8): Likewise. 4893 (__arm_vrev32q_x_s16): Likewise. 4894 (__arm_vrev32q_x_u8): Likewise. 4895 (__arm_vrev32q_x_u16): Likewise. 4896 (__arm_vrev64q_x_s8): Likewise. 4897 (__arm_vrev64q_x_s16): Likewise. 4898 (__arm_vrev64q_x_s32): Likewise. 4899 (__arm_vrev64q_x_u8): Likewise. 4900 (__arm_vrev64q_x_u16): Likewise. 4901 (__arm_vrev64q_x_u32): Likewise. 4902 (__arm_vrshlq_x_s8): Likewise. 4903 (__arm_vrshlq_x_s16): Likewise. 4904 (__arm_vrshlq_x_s32): Likewise. 4905 (__arm_vrshlq_x_u8): Likewise. 4906 (__arm_vrshlq_x_u16): Likewise. 4907 (__arm_vrshlq_x_u32): Likewise. 4908 (__arm_vshllbq_x_n_s8): Likewise. 4909 (__arm_vshllbq_x_n_s16): Likewise. 4910 (__arm_vshllbq_x_n_u8): Likewise. 4911 (__arm_vshllbq_x_n_u16): Likewise. 4912 (__arm_vshlltq_x_n_s8): Likewise. 4913 (__arm_vshlltq_x_n_s16): Likewise. 4914 (__arm_vshlltq_x_n_u8): Likewise. 4915 (__arm_vshlltq_x_n_u16): Likewise. 4916 (__arm_vshlq_x_s8): Likewise. 4917 (__arm_vshlq_x_s16): Likewise. 4918 (__arm_vshlq_x_s32): Likewise. 4919 (__arm_vshlq_x_u8): Likewise. 4920 (__arm_vshlq_x_u16): Likewise. 4921 (__arm_vshlq_x_u32): Likewise. 4922 (__arm_vshlq_x_n_s8): Likewise. 4923 (__arm_vshlq_x_n_s16): Likewise. 4924 (__arm_vshlq_x_n_s32): Likewise. 4925 (__arm_vshlq_x_n_u8): Likewise. 4926 (__arm_vshlq_x_n_u16): Likewise. 4927 (__arm_vshlq_x_n_u32): Likewise. 4928 (__arm_vrshrq_x_n_s8): Likewise. 4929 (__arm_vrshrq_x_n_s16): Likewise. 4930 (__arm_vrshrq_x_n_s32): Likewise. 4931 (__arm_vrshrq_x_n_u8): Likewise. 4932 (__arm_vrshrq_x_n_u16): Likewise. 4933 (__arm_vrshrq_x_n_u32): Likewise. 4934 (__arm_vshrq_x_n_s8): Likewise. 4935 (__arm_vshrq_x_n_s16): Likewise. 4936 (__arm_vshrq_x_n_s32): Likewise. 4937 (__arm_vshrq_x_n_u8): Likewise. 4938 (__arm_vshrq_x_n_u16): Likewise. 4939 (__arm_vshrq_x_n_u32): Likewise. 4940 (__arm_vdupq_x_n_f16): Likewise. 4941 (__arm_vdupq_x_n_f32): Likewise. 4942 (__arm_vminnmq_x_f16): Likewise. 4943 (__arm_vminnmq_x_f32): Likewise. 4944 (__arm_vmaxnmq_x_f16): Likewise. 4945 (__arm_vmaxnmq_x_f32): Likewise. 4946 (__arm_vabdq_x_f16): Likewise. 4947 (__arm_vabdq_x_f32): Likewise. 4948 (__arm_vabsq_x_f16): Likewise. 4949 (__arm_vabsq_x_f32): Likewise. 4950 (__arm_vaddq_x_f16): Likewise. 4951 (__arm_vaddq_x_f32): Likewise. 4952 (__arm_vaddq_x_n_f16): Likewise. 4953 (__arm_vaddq_x_n_f32): Likewise. 4954 (__arm_vnegq_x_f16): Likewise. 4955 (__arm_vnegq_x_f32): Likewise. 4956 (__arm_vmulq_x_f16): Likewise. 4957 (__arm_vmulq_x_f32): Likewise. 4958 (__arm_vmulq_x_n_f16): Likewise. 4959 (__arm_vmulq_x_n_f32): Likewise. 4960 (__arm_vsubq_x_f16): Likewise. 4961 (__arm_vsubq_x_f32): Likewise. 4962 (__arm_vsubq_x_n_f16): Likewise. 4963 (__arm_vsubq_x_n_f32): Likewise. 4964 (__arm_vcaddq_rot90_x_f16): Likewise. 4965 (__arm_vcaddq_rot90_x_f32): Likewise. 4966 (__arm_vcaddq_rot270_x_f16): Likewise. 4967 (__arm_vcaddq_rot270_x_f32): Likewise. 4968 (__arm_vcmulq_x_f16): Likewise. 4969 (__arm_vcmulq_x_f32): Likewise. 4970 (__arm_vcmulq_rot90_x_f16): Likewise. 4971 (__arm_vcmulq_rot90_x_f32): Likewise. 4972 (__arm_vcmulq_rot180_x_f16): Likewise. 4973 (__arm_vcmulq_rot180_x_f32): Likewise. 4974 (__arm_vcmulq_rot270_x_f16): Likewise. 4975 (__arm_vcmulq_rot270_x_f32): Likewise. 4976 (__arm_vcvtaq_x_s16_f16): Likewise. 4977 (__arm_vcvtaq_x_s32_f32): Likewise. 4978 (__arm_vcvtaq_x_u16_f16): Likewise. 4979 (__arm_vcvtaq_x_u32_f32): Likewise. 4980 (__arm_vcvtnq_x_s16_f16): Likewise. 4981 (__arm_vcvtnq_x_s32_f32): Likewise. 4982 (__arm_vcvtnq_x_u16_f16): Likewise. 4983 (__arm_vcvtnq_x_u32_f32): Likewise. 4984 (__arm_vcvtpq_x_s16_f16): Likewise. 4985 (__arm_vcvtpq_x_s32_f32): Likewise. 4986 (__arm_vcvtpq_x_u16_f16): Likewise. 4987 (__arm_vcvtpq_x_u32_f32): Likewise. 4988 (__arm_vcvtmq_x_s16_f16): Likewise. 4989 (__arm_vcvtmq_x_s32_f32): Likewise. 4990 (__arm_vcvtmq_x_u16_f16): Likewise. 4991 (__arm_vcvtmq_x_u32_f32): Likewise. 4992 (__arm_vcvtbq_x_f32_f16): Likewise. 4993 (__arm_vcvttq_x_f32_f16): Likewise. 4994 (__arm_vcvtq_x_f16_u16): Likewise. 4995 (__arm_vcvtq_x_f16_s16): Likewise. 4996 (__arm_vcvtq_x_f32_s32): Likewise. 4997 (__arm_vcvtq_x_f32_u32): Likewise. 4998 (__arm_vcvtq_x_n_f16_s16): Likewise. 4999 (__arm_vcvtq_x_n_f16_u16): Likewise. 5000 (__arm_vcvtq_x_n_f32_s32): Likewise. 5001 (__arm_vcvtq_x_n_f32_u32): Likewise. 5002 (__arm_vcvtq_x_s16_f16): Likewise. 5003 (__arm_vcvtq_x_s32_f32): Likewise. 5004 (__arm_vcvtq_x_u16_f16): Likewise. 5005 (__arm_vcvtq_x_u32_f32): Likewise. 5006 (__arm_vcvtq_x_n_s16_f16): Likewise. 5007 (__arm_vcvtq_x_n_s32_f32): Likewise. 5008 (__arm_vcvtq_x_n_u16_f16): Likewise. 5009 (__arm_vcvtq_x_n_u32_f32): Likewise. 5010 (__arm_vrndq_x_f16): Likewise. 5011 (__arm_vrndq_x_f32): Likewise. 5012 (__arm_vrndnq_x_f16): Likewise. 5013 (__arm_vrndnq_x_f32): Likewise. 5014 (__arm_vrndmq_x_f16): Likewise. 5015 (__arm_vrndmq_x_f32): Likewise. 5016 (__arm_vrndpq_x_f16): Likewise. 5017 (__arm_vrndpq_x_f32): Likewise. 5018 (__arm_vrndaq_x_f16): Likewise. 5019 (__arm_vrndaq_x_f32): Likewise. 5020 (__arm_vrndxq_x_f16): Likewise. 5021 (__arm_vrndxq_x_f32): Likewise. 5022 (__arm_vandq_x_f16): Likewise. 5023 (__arm_vandq_x_f32): Likewise. 5024 (__arm_vbicq_x_f16): Likewise. 5025 (__arm_vbicq_x_f32): Likewise. 5026 (__arm_vbrsrq_x_n_f16): Likewise. 5027 (__arm_vbrsrq_x_n_f32): Likewise. 5028 (__arm_veorq_x_f16): Likewise. 5029 (__arm_veorq_x_f32): Likewise. 5030 (__arm_vornq_x_f16): Likewise. 5031 (__arm_vornq_x_f32): Likewise. 5032 (__arm_vorrq_x_f16): Likewise. 5033 (__arm_vorrq_x_f32): Likewise. 5034 (__arm_vrev32q_x_f16): Likewise. 5035 (__arm_vrev64q_x_f16): Likewise. 5036 (__arm_vrev64q_x_f32): Likewise. 5037 (vabdq_x): Define polymorphic variant. 5038 (vabsq_x): Likewise. 5039 (vaddq_x): Likewise. 5040 (vandq_x): Likewise. 5041 (vbicq_x): Likewise. 5042 (vbrsrq_x): Likewise. 5043 (vcaddq_rot270_x): Likewise. 5044 (vcaddq_rot90_x): Likewise. 5045 (vcmulq_rot180_x): Likewise. 5046 (vcmulq_rot270_x): Likewise. 5047 (vcmulq_x): Likewise. 5048 (vcvtq_x): Likewise. 5049 (vcvtq_x_n): Likewise. 5050 (vcvtnq_m): Likewise. 5051 (veorq_x): Likewise. 5052 (vmaxnmq_x): Likewise. 5053 (vminnmq_x): Likewise. 5054 (vmulq_x): Likewise. 5055 (vnegq_x): Likewise. 5056 (vornq_x): Likewise. 5057 (vorrq_x): Likewise. 5058 (vrev32q_x): Likewise. 5059 (vrev64q_x): Likewise. 5060 (vrndaq_x): Likewise. 5061 (vrndmq_x): Likewise. 5062 (vrndnq_x): Likewise. 5063 (vrndpq_x): Likewise. 5064 (vrndq_x): Likewise. 5065 (vrndxq_x): Likewise. 5066 (vsubq_x): Likewise. 5067 (vcmulq_rot90_x): Likewise. 5068 (vadciq): Likewise. 5069 (vclsq_x): Likewise. 5070 (vclzq_x): Likewise. 5071 (vhaddq_x): Likewise. 5072 (vhcaddq_rot270_x): Likewise. 5073 (vhcaddq_rot90_x): Likewise. 5074 (vhsubq_x): Likewise. 5075 (vmaxq_x): Likewise. 5076 (vminq_x): Likewise. 5077 (vmovlbq_x): Likewise. 5078 (vmovltq_x): Likewise. 5079 (vmulhq_x): Likewise. 5080 (vmullbq_int_x): Likewise. 5081 (vmullbq_poly_x): Likewise. 5082 (vmulltq_int_x): Likewise. 5083 (vmulltq_poly_x): Likewise. 5084 (vmvnq_x): Likewise. 5085 (vrev16q_x): Likewise. 5086 (vrhaddq_x): Likewise. 5087 (vrmulhq_x): Likewise. 5088 (vrshlq_x): Likewise. 5089 (vrshrq_x): Likewise. 5090 (vshllbq_x): Likewise. 5091 (vshlltq_x): Likewise. 5092 (vshlq_x_n): Likewise. 5093 (vshlq_x): Likewise. 5094 (vdwdupq_x_u8): Likewise. 5095 (vdwdupq_x_u16): Likewise. 5096 (vdwdupq_x_u32): Likewise. 5097 (viwdupq_x_u8): Likewise. 5098 (viwdupq_x_u16): Likewise. 5099 (viwdupq_x_u32): Likewise. 5100 (vidupq_x_u8): Likewise. 5101 (vddupq_x_u8): Likewise. 5102 (vidupq_x_u16): Likewise. 5103 (vddupq_x_u16): Likewise. 5104 (vidupq_x_u32): Likewise. 5105 (vddupq_x_u32): Likewise. 5106 (vshrq_x): Likewise. 5107 51082020-03-20 Richard Biener <rguenther@suse.de> 5109 5110 * tree-vect-slp.c (vect_analyze_slp_instance): Push the stmts 5111 to vectorize for CTOR defs. 5112 51132020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 5114 Andre Vieira <andre.simoesdiasvieira@arm.com> 5115 Mihail Ionescu <mihail.ionescu@arm.com> 5116 5117 * config/arm/arm-builtins.c (LDRGBWBS_QUALIFIERS): Define builtin 5118 qualifier. 5119 (LDRGBWBU_QUALIFIERS): Likewise. 5120 (LDRGBWBS_Z_QUALIFIERS): Likewise. 5121 (LDRGBWBU_Z_QUALIFIERS): Likewise. 5122 (STRSBWBS_QUALIFIERS): Likewise. 5123 (STRSBWBU_QUALIFIERS): Likewise. 5124 (STRSBWBS_P_QUALIFIERS): Likewise. 5125 (STRSBWBU_P_QUALIFIERS): Likewise. 5126 * config/arm/arm_mve.h (vldrdq_gather_base_wb_s64): Define macro. 5127 (vldrdq_gather_base_wb_u64): Likewise. 5128 (vldrdq_gather_base_wb_z_s64): Likewise. 5129 (vldrdq_gather_base_wb_z_u64): Likewise. 5130 (vldrwq_gather_base_wb_f32): Likewise. 5131 (vldrwq_gather_base_wb_s32): Likewise. 5132 (vldrwq_gather_base_wb_u32): Likewise. 5133 (vldrwq_gather_base_wb_z_f32): Likewise. 5134 (vldrwq_gather_base_wb_z_s32): Likewise. 5135 (vldrwq_gather_base_wb_z_u32): Likewise. 5136 (vstrdq_scatter_base_wb_p_s64): Likewise. 5137 (vstrdq_scatter_base_wb_p_u64): Likewise. 5138 (vstrdq_scatter_base_wb_s64): Likewise. 5139 (vstrdq_scatter_base_wb_u64): Likewise. 5140 (vstrwq_scatter_base_wb_p_s32): Likewise. 5141 (vstrwq_scatter_base_wb_p_f32): Likewise. 5142 (vstrwq_scatter_base_wb_p_u32): Likewise. 5143 (vstrwq_scatter_base_wb_s32): Likewise. 5144 (vstrwq_scatter_base_wb_u32): Likewise. 5145 (vstrwq_scatter_base_wb_f32): Likewise. 5146 (__arm_vldrdq_gather_base_wb_s64): Define intrinsic. 5147 (__arm_vldrdq_gather_base_wb_u64): Likewise. 5148 (__arm_vldrdq_gather_base_wb_z_s64): Likewise. 5149 (__arm_vldrdq_gather_base_wb_z_u64): Likewise. 5150 (__arm_vldrwq_gather_base_wb_s32): Likewise. 5151 (__arm_vldrwq_gather_base_wb_u32): Likewise. 5152 (__arm_vldrwq_gather_base_wb_z_s32): Likewise. 5153 (__arm_vldrwq_gather_base_wb_z_u32): Likewise. 5154 (__arm_vstrdq_scatter_base_wb_s64): Likewise. 5155 (__arm_vstrdq_scatter_base_wb_u64): Likewise. 5156 (__arm_vstrdq_scatter_base_wb_p_s64): Likewise. 5157 (__arm_vstrdq_scatter_base_wb_p_u64): Likewise. 5158 (__arm_vstrwq_scatter_base_wb_p_s32): Likewise. 5159 (__arm_vstrwq_scatter_base_wb_p_u32): Likewise. 5160 (__arm_vstrwq_scatter_base_wb_s32): Likewise. 5161 (__arm_vstrwq_scatter_base_wb_u32): Likewise. 5162 (__arm_vldrwq_gather_base_wb_f32): Likewise. 5163 (__arm_vldrwq_gather_base_wb_z_f32): Likewise. 5164 (__arm_vstrwq_scatter_base_wb_f32): Likewise. 5165 (__arm_vstrwq_scatter_base_wb_p_f32): Likewise. 5166 (vstrwq_scatter_base_wb): Define polymorphic variant. 5167 (vstrwq_scatter_base_wb_p): Likewise. 5168 (vstrdq_scatter_base_wb_p): Likewise. 5169 (vstrdq_scatter_base_wb): Likewise. 5170 * config/arm/arm_mve_builtins.def (LDRGBWBS_QUALIFIERS): Use builtin 5171 qualifier. 5172 * config/arm/mve.md (mve_vstrwq_scatter_base_wb_<supf>v4si): Define RTL 5173 pattern. 5174 (mve_vstrwq_scatter_base_wb_add_<supf>v4si): Likewise. 5175 (mve_vstrwq_scatter_base_wb_<supf>v4si_insn): Likewise. 5176 (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise. 5177 (mve_vstrwq_scatter_base_wb_p_add_<supf>v4si): Likewise. 5178 (mve_vstrwq_scatter_base_wb_p_<supf>v4si_insn): Likewise. 5179 (mve_vstrwq_scatter_base_wb_fv4sf): Likewise. 5180 (mve_vstrwq_scatter_base_wb_add_fv4sf): Likewise. 5181 (mve_vstrwq_scatter_base_wb_fv4sf_insn): Likewise. 5182 (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise. 5183 (mve_vstrwq_scatter_base_wb_p_add_fv4sf): Likewise. 5184 (mve_vstrwq_scatter_base_wb_p_fv4sf_insn): Likewise. 5185 (mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise. 5186 (mve_vstrdq_scatter_base_wb_add_<supf>v2di): Likewise. 5187 (mve_vstrdq_scatter_base_wb_<supf>v2di_insn): Likewise. 5188 (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise. 5189 (mve_vstrdq_scatter_base_wb_p_add_<supf>v2di): Likewise. 5190 (mve_vstrdq_scatter_base_wb_p_<supf>v2di_insn): Likewise. 5191 (mve_vldrwq_gather_base_wb_<supf>v4si): Likewise. 5192 (mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise. 5193 (mve_vldrwq_gather_base_wb_z_<supf>v4si): Likewise. 5194 (mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise. 5195 (mve_vldrwq_gather_base_wb_fv4sf): Likewise. 5196 (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise. 5197 (mve_vldrwq_gather_base_wb_z_fv4sf): Likewise. 5198 (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise. 5199 (mve_vldrdq_gather_base_wb_<supf>v2di): Likewise. 5200 (mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise. 5201 (mve_vldrdq_gather_base_wb_z_<supf>v2di): Likewise. 5202 (mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise. 5203 52042020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 5205 Andre Vieira <andre.simoesdiasvieira@arm.com> 5206 Mihail Ionescu <mihail.ionescu@arm.com> 5207 5208 * config/arm/arm-builtins.c 5209 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Define quinary 5210 builtin qualifier. 5211 * config/arm/arm_mve.h (vddupq_m_n_u8): Define macro. 5212 (vddupq_m_n_u32): Likewise. 5213 (vddupq_m_n_u16): Likewise. 5214 (vddupq_m_wb_u8): Likewise. 5215 (vddupq_m_wb_u16): Likewise. 5216 (vddupq_m_wb_u32): Likewise. 5217 (vddupq_n_u8): Likewise. 5218 (vddupq_n_u32): Likewise. 5219 (vddupq_n_u16): Likewise. 5220 (vddupq_wb_u8): Likewise. 5221 (vddupq_wb_u16): Likewise. 5222 (vddupq_wb_u32): Likewise. 5223 (vdwdupq_m_n_u8): Likewise. 5224 (vdwdupq_m_n_u32): Likewise. 5225 (vdwdupq_m_n_u16): Likewise. 5226 (vdwdupq_m_wb_u8): Likewise. 5227 (vdwdupq_m_wb_u32): Likewise. 5228 (vdwdupq_m_wb_u16): Likewise. 5229 (vdwdupq_n_u8): Likewise. 5230 (vdwdupq_n_u32): Likewise. 5231 (vdwdupq_n_u16): Likewise. 5232 (vdwdupq_wb_u8): Likewise. 5233 (vdwdupq_wb_u32): Likewise. 5234 (vdwdupq_wb_u16): Likewise. 5235 (vidupq_m_n_u8): Likewise. 5236 (vidupq_m_n_u32): Likewise. 5237 (vidupq_m_n_u16): Likewise. 5238 (vidupq_m_wb_u8): Likewise. 5239 (vidupq_m_wb_u16): Likewise. 5240 (vidupq_m_wb_u32): Likewise. 5241 (vidupq_n_u8): Likewise. 5242 (vidupq_n_u32): Likewise. 5243 (vidupq_n_u16): Likewise. 5244 (vidupq_wb_u8): Likewise. 5245 (vidupq_wb_u16): Likewise. 5246 (vidupq_wb_u32): Likewise. 5247 (viwdupq_m_n_u8): Likewise. 5248 (viwdupq_m_n_u32): Likewise. 5249 (viwdupq_m_n_u16): Likewise. 5250 (viwdupq_m_wb_u8): Likewise. 5251 (viwdupq_m_wb_u32): Likewise. 5252 (viwdupq_m_wb_u16): Likewise. 5253 (viwdupq_n_u8): Likewise. 5254 (viwdupq_n_u32): Likewise. 5255 (viwdupq_n_u16): Likewise. 5256 (viwdupq_wb_u8): Likewise. 5257 (viwdupq_wb_u32): Likewise. 5258 (viwdupq_wb_u16): Likewise. 5259 (__arm_vddupq_m_n_u8): Define intrinsic. 5260 (__arm_vddupq_m_n_u32): Likewise. 5261 (__arm_vddupq_m_n_u16): Likewise. 5262 (__arm_vddupq_m_wb_u8): Likewise. 5263 (__arm_vddupq_m_wb_u16): Likewise. 5264 (__arm_vddupq_m_wb_u32): Likewise. 5265 (__arm_vddupq_n_u8): Likewise. 5266 (__arm_vddupq_n_u32): Likewise. 5267 (__arm_vddupq_n_u16): Likewise. 5268 (__arm_vdwdupq_m_n_u8): Likewise. 5269 (__arm_vdwdupq_m_n_u32): Likewise. 5270 (__arm_vdwdupq_m_n_u16): Likewise. 5271 (__arm_vdwdupq_m_wb_u8): Likewise. 5272 (__arm_vdwdupq_m_wb_u32): Likewise. 5273 (__arm_vdwdupq_m_wb_u16): Likewise. 5274 (__arm_vdwdupq_n_u8): Likewise. 5275 (__arm_vdwdupq_n_u32): Likewise. 5276 (__arm_vdwdupq_n_u16): Likewise. 5277 (__arm_vdwdupq_wb_u8): Likewise. 5278 (__arm_vdwdupq_wb_u32): Likewise. 5279 (__arm_vdwdupq_wb_u16): Likewise. 5280 (__arm_vidupq_m_n_u8): Likewise. 5281 (__arm_vidupq_m_n_u32): Likewise. 5282 (__arm_vidupq_m_n_u16): Likewise. 5283 (__arm_vidupq_n_u8): Likewise. 5284 (__arm_vidupq_m_wb_u8): Likewise. 5285 (__arm_vidupq_m_wb_u16): Likewise. 5286 (__arm_vidupq_m_wb_u32): Likewise. 5287 (__arm_vidupq_n_u32): Likewise. 5288 (__arm_vidupq_n_u16): Likewise. 5289 (__arm_vidupq_wb_u8): Likewise. 5290 (__arm_vidupq_wb_u16): Likewise. 5291 (__arm_vidupq_wb_u32): Likewise. 5292 (__arm_vddupq_wb_u8): Likewise. 5293 (__arm_vddupq_wb_u16): Likewise. 5294 (__arm_vddupq_wb_u32): Likewise. 5295 (__arm_viwdupq_m_n_u8): Likewise. 5296 (__arm_viwdupq_m_n_u32): Likewise. 5297 (__arm_viwdupq_m_n_u16): Likewise. 5298 (__arm_viwdupq_m_wb_u8): Likewise. 5299 (__arm_viwdupq_m_wb_u32): Likewise. 5300 (__arm_viwdupq_m_wb_u16): Likewise. 5301 (__arm_viwdupq_n_u8): Likewise. 5302 (__arm_viwdupq_n_u32): Likewise. 5303 (__arm_viwdupq_n_u16): Likewise. 5304 (__arm_viwdupq_wb_u8): Likewise. 5305 (__arm_viwdupq_wb_u32): Likewise. 5306 (__arm_viwdupq_wb_u16): Likewise. 5307 (vidupq_m): Define polymorphic variant. 5308 (vddupq_m): Likewise. 5309 (vidupq_u16): Likewise. 5310 (vidupq_u32): Likewise. 5311 (vidupq_u8): Likewise. 5312 (vddupq_u16): Likewise. 5313 (vddupq_u32): Likewise. 5314 (vddupq_u8): Likewise. 5315 (viwdupq_m): Likewise. 5316 (viwdupq_u16): Likewise. 5317 (viwdupq_u32): Likewise. 5318 (viwdupq_u8): Likewise. 5319 (vdwdupq_m): Likewise. 5320 (vdwdupq_u16): Likewise. 5321 (vdwdupq_u32): Likewise. 5322 (vdwdupq_u8): Likewise. 5323 * config/arm/arm_mve_builtins.def 5324 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Use builtin 5325 qualifier. 5326 * config/arm/mve.md (mve_vidupq_n_u<mode>): Define RTL pattern. 5327 (mve_vidupq_u<mode>_insn): Likewise. 5328 (mve_vidupq_m_n_u<mode>): Likewise. 5329 (mve_vidupq_m_wb_u<mode>_insn): Likewise. 5330 (mve_vddupq_n_u<mode>): Likewise. 5331 (mve_vddupq_u<mode>_insn): Likewise. 5332 (mve_vddupq_m_n_u<mode>): Likewise. 5333 (mve_vddupq_m_wb_u<mode>_insn): Likewise. 5334 (mve_vdwdupq_n_u<mode>): Likewise. 5335 (mve_vdwdupq_wb_u<mode>): Likewise. 5336 (mve_vdwdupq_wb_u<mode>_insn): Likewise. 5337 (mve_vdwdupq_m_n_u<mode>): Likewise. 5338 (mve_vdwdupq_m_wb_u<mode>): Likewise. 5339 (mve_vdwdupq_m_wb_u<mode>_insn): Likewise. 5340 (mve_viwdupq_n_u<mode>): Likewise. 5341 (mve_viwdupq_wb_u<mode>): Likewise. 5342 (mve_viwdupq_wb_u<mode>_insn): Likewise. 5343 (mve_viwdupq_m_n_u<mode>): Likewise. 5344 (mve_viwdupq_m_wb_u<mode>): Likewise. 5345 (mve_viwdupq_m_wb_u<mode>_insn): Likewise. 5346 53472020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 5348 5349 * config/arm/arm_mve.h (vreinterpretq_s16_s32): Define macro. 5350 (vreinterpretq_s16_s64): Likewise. 5351 (vreinterpretq_s16_s8): Likewise. 5352 (vreinterpretq_s16_u16): Likewise. 5353 (vreinterpretq_s16_u32): Likewise. 5354 (vreinterpretq_s16_u64): Likewise. 5355 (vreinterpretq_s16_u8): Likewise. 5356 (vreinterpretq_s32_s16): Likewise. 5357 (vreinterpretq_s32_s64): Likewise. 5358 (vreinterpretq_s32_s8): Likewise. 5359 (vreinterpretq_s32_u16): Likewise. 5360 (vreinterpretq_s32_u32): Likewise. 5361 (vreinterpretq_s32_u64): Likewise. 5362 (vreinterpretq_s32_u8): Likewise. 5363 (vreinterpretq_s64_s16): Likewise. 5364 (vreinterpretq_s64_s32): Likewise. 5365 (vreinterpretq_s64_s8): Likewise. 5366 (vreinterpretq_s64_u16): Likewise. 5367 (vreinterpretq_s64_u32): Likewise. 5368 (vreinterpretq_s64_u64): Likewise. 5369 (vreinterpretq_s64_u8): Likewise. 5370 (vreinterpretq_s8_s16): Likewise. 5371 (vreinterpretq_s8_s32): Likewise. 5372 (vreinterpretq_s8_s64): Likewise. 5373 (vreinterpretq_s8_u16): Likewise. 5374 (vreinterpretq_s8_u32): Likewise. 5375 (vreinterpretq_s8_u64): Likewise. 5376 (vreinterpretq_s8_u8): Likewise. 5377 (vreinterpretq_u16_s16): Likewise. 5378 (vreinterpretq_u16_s32): Likewise. 5379 (vreinterpretq_u16_s64): Likewise. 5380 (vreinterpretq_u16_s8): Likewise. 5381 (vreinterpretq_u16_u32): Likewise. 5382 (vreinterpretq_u16_u64): Likewise. 5383 (vreinterpretq_u16_u8): Likewise. 5384 (vreinterpretq_u32_s16): Likewise. 5385 (vreinterpretq_u32_s32): Likewise. 5386 (vreinterpretq_u32_s64): Likewise. 5387 (vreinterpretq_u32_s8): Likewise. 5388 (vreinterpretq_u32_u16): Likewise. 5389 (vreinterpretq_u32_u64): Likewise. 5390 (vreinterpretq_u32_u8): Likewise. 5391 (vreinterpretq_u64_s16): Likewise. 5392 (vreinterpretq_u64_s32): Likewise. 5393 (vreinterpretq_u64_s64): Likewise. 5394 (vreinterpretq_u64_s8): Likewise. 5395 (vreinterpretq_u64_u16): Likewise. 5396 (vreinterpretq_u64_u32): Likewise. 5397 (vreinterpretq_u64_u8): Likewise. 5398 (vreinterpretq_u8_s16): Likewise. 5399 (vreinterpretq_u8_s32): Likewise. 5400 (vreinterpretq_u8_s64): Likewise. 5401 (vreinterpretq_u8_s8): Likewise. 5402 (vreinterpretq_u8_u16): Likewise. 5403 (vreinterpretq_u8_u32): Likewise. 5404 (vreinterpretq_u8_u64): Likewise. 5405 (vreinterpretq_s32_f16): Likewise. 5406 (vreinterpretq_s32_f32): Likewise. 5407 (vreinterpretq_u16_f16): Likewise. 5408 (vreinterpretq_u16_f32): Likewise. 5409 (vreinterpretq_u32_f16): Likewise. 5410 (vreinterpretq_u32_f32): Likewise. 5411 (vreinterpretq_u64_f16): Likewise. 5412 (vreinterpretq_u64_f32): Likewise. 5413 (vreinterpretq_u8_f16): Likewise. 5414 (vreinterpretq_u8_f32): Likewise. 5415 (vreinterpretq_f16_f32): Likewise. 5416 (vreinterpretq_f16_s16): Likewise. 5417 (vreinterpretq_f16_s32): Likewise. 5418 (vreinterpretq_f16_s64): Likewise. 5419 (vreinterpretq_f16_s8): Likewise. 5420 (vreinterpretq_f16_u16): Likewise. 5421 (vreinterpretq_f16_u32): Likewise. 5422 (vreinterpretq_f16_u64): Likewise. 5423 (vreinterpretq_f16_u8): Likewise. 5424 (vreinterpretq_f32_f16): Likewise. 5425 (vreinterpretq_f32_s16): Likewise. 5426 (vreinterpretq_f32_s32): Likewise. 5427 (vreinterpretq_f32_s64): Likewise. 5428 (vreinterpretq_f32_s8): Likewise. 5429 (vreinterpretq_f32_u16): Likewise. 5430 (vreinterpretq_f32_u32): Likewise. 5431 (vreinterpretq_f32_u64): Likewise. 5432 (vreinterpretq_f32_u8): Likewise. 5433 (vreinterpretq_s16_f16): Likewise. 5434 (vreinterpretq_s16_f32): Likewise. 5435 (vreinterpretq_s64_f16): Likewise. 5436 (vreinterpretq_s64_f32): Likewise. 5437 (vreinterpretq_s8_f16): Likewise. 5438 (vreinterpretq_s8_f32): Likewise. 5439 (vuninitializedq_u8): Likewise. 5440 (vuninitializedq_u16): Likewise. 5441 (vuninitializedq_u32): Likewise. 5442 (vuninitializedq_u64): Likewise. 5443 (vuninitializedq_s8): Likewise. 5444 (vuninitializedq_s16): Likewise. 5445 (vuninitializedq_s32): Likewise. 5446 (vuninitializedq_s64): Likewise. 5447 (vuninitializedq_f16): Likewise. 5448 (vuninitializedq_f32): Likewise. 5449 (__arm_vuninitializedq_u8): Define intrinsic. 5450 (__arm_vuninitializedq_u16): Likewise. 5451 (__arm_vuninitializedq_u32): Likewise. 5452 (__arm_vuninitializedq_u64): Likewise. 5453 (__arm_vuninitializedq_s8): Likewise. 5454 (__arm_vuninitializedq_s16): Likewise. 5455 (__arm_vuninitializedq_s32): Likewise. 5456 (__arm_vuninitializedq_s64): Likewise. 5457 (__arm_vreinterpretq_s16_s32): Likewise. 5458 (__arm_vreinterpretq_s16_s64): Likewise. 5459 (__arm_vreinterpretq_s16_s8): Likewise. 5460 (__arm_vreinterpretq_s16_u16): Likewise. 5461 (__arm_vreinterpretq_s16_u32): Likewise. 5462 (__arm_vreinterpretq_s16_u64): Likewise. 5463 (__arm_vreinterpretq_s16_u8): Likewise. 5464 (__arm_vreinterpretq_s32_s16): Likewise. 5465 (__arm_vreinterpretq_s32_s64): Likewise. 5466 (__arm_vreinterpretq_s32_s8): Likewise. 5467 (__arm_vreinterpretq_s32_u16): Likewise. 5468 (__arm_vreinterpretq_s32_u32): Likewise. 5469 (__arm_vreinterpretq_s32_u64): Likewise. 5470 (__arm_vreinterpretq_s32_u8): Likewise. 5471 (__arm_vreinterpretq_s64_s16): Likewise. 5472 (__arm_vreinterpretq_s64_s32): Likewise. 5473 (__arm_vreinterpretq_s64_s8): Likewise. 5474 (__arm_vreinterpretq_s64_u16): Likewise. 5475 (__arm_vreinterpretq_s64_u32): Likewise. 5476 (__arm_vreinterpretq_s64_u64): Likewise. 5477 (__arm_vreinterpretq_s64_u8): Likewise. 5478 (__arm_vreinterpretq_s8_s16): Likewise. 5479 (__arm_vreinterpretq_s8_s32): Likewise. 5480 (__arm_vreinterpretq_s8_s64): Likewise. 5481 (__arm_vreinterpretq_s8_u16): Likewise. 5482 (__arm_vreinterpretq_s8_u32): Likewise. 5483 (__arm_vreinterpretq_s8_u64): Likewise. 5484 (__arm_vreinterpretq_s8_u8): Likewise. 5485 (__arm_vreinterpretq_u16_s16): Likewise. 5486 (__arm_vreinterpretq_u16_s32): Likewise. 5487 (__arm_vreinterpretq_u16_s64): Likewise. 5488 (__arm_vreinterpretq_u16_s8): Likewise. 5489 (__arm_vreinterpretq_u16_u32): Likewise. 5490 (__arm_vreinterpretq_u16_u64): Likewise. 5491 (__arm_vreinterpretq_u16_u8): Likewise. 5492 (__arm_vreinterpretq_u32_s16): Likewise. 5493 (__arm_vreinterpretq_u32_s32): Likewise. 5494 (__arm_vreinterpretq_u32_s64): Likewise. 5495 (__arm_vreinterpretq_u32_s8): Likewise. 5496 (__arm_vreinterpretq_u32_u16): Likewise. 5497 (__arm_vreinterpretq_u32_u64): Likewise. 5498 (__arm_vreinterpretq_u32_u8): Likewise. 5499 (__arm_vreinterpretq_u64_s16): Likewise. 5500 (__arm_vreinterpretq_u64_s32): Likewise. 5501 (__arm_vreinterpretq_u64_s64): Likewise. 5502 (__arm_vreinterpretq_u64_s8): Likewise. 5503 (__arm_vreinterpretq_u64_u16): Likewise. 5504 (__arm_vreinterpretq_u64_u32): Likewise. 5505 (__arm_vreinterpretq_u64_u8): Likewise. 5506 (__arm_vreinterpretq_u8_s16): Likewise. 5507 (__arm_vreinterpretq_u8_s32): Likewise. 5508 (__arm_vreinterpretq_u8_s64): Likewise. 5509 (__arm_vreinterpretq_u8_s8): Likewise. 5510 (__arm_vreinterpretq_u8_u16): Likewise. 5511 (__arm_vreinterpretq_u8_u32): Likewise. 5512 (__arm_vreinterpretq_u8_u64): Likewise. 5513 (__arm_vuninitializedq_f16): Likewise. 5514 (__arm_vuninitializedq_f32): Likewise. 5515 (__arm_vreinterpretq_s32_f16): Likewise. 5516 (__arm_vreinterpretq_s32_f32): Likewise. 5517 (__arm_vreinterpretq_s16_f16): Likewise. 5518 (__arm_vreinterpretq_s16_f32): Likewise. 5519 (__arm_vreinterpretq_s64_f16): Likewise. 5520 (__arm_vreinterpretq_s64_f32): Likewise. 5521 (__arm_vreinterpretq_s8_f16): Likewise. 5522 (__arm_vreinterpretq_s8_f32): Likewise. 5523 (__arm_vreinterpretq_u16_f16): Likewise. 5524 (__arm_vreinterpretq_u16_f32): Likewise. 5525 (__arm_vreinterpretq_u32_f16): Likewise. 5526 (__arm_vreinterpretq_u32_f32): Likewise. 5527 (__arm_vreinterpretq_u64_f16): Likewise. 5528 (__arm_vreinterpretq_u64_f32): Likewise. 5529 (__arm_vreinterpretq_u8_f16): Likewise. 5530 (__arm_vreinterpretq_u8_f32): Likewise. 5531 (__arm_vreinterpretq_f16_f32): Likewise. 5532 (__arm_vreinterpretq_f16_s16): Likewise. 5533 (__arm_vreinterpretq_f16_s32): Likewise. 5534 (__arm_vreinterpretq_f16_s64): Likewise. 5535 (__arm_vreinterpretq_f16_s8): Likewise. 5536 (__arm_vreinterpretq_f16_u16): Likewise. 5537 (__arm_vreinterpretq_f16_u32): Likewise. 5538 (__arm_vreinterpretq_f16_u64): Likewise. 5539 (__arm_vreinterpretq_f16_u8): Likewise. 5540 (__arm_vreinterpretq_f32_f16): Likewise. 5541 (__arm_vreinterpretq_f32_s16): Likewise. 5542 (__arm_vreinterpretq_f32_s32): Likewise. 5543 (__arm_vreinterpretq_f32_s64): Likewise. 5544 (__arm_vreinterpretq_f32_s8): Likewise. 5545 (__arm_vreinterpretq_f32_u16): Likewise. 5546 (__arm_vreinterpretq_f32_u32): Likewise. 5547 (__arm_vreinterpretq_f32_u64): Likewise. 5548 (__arm_vreinterpretq_f32_u8): Likewise. 5549 (vuninitializedq): Define polymorphic variant. 5550 (vreinterpretq_f16): Likewise. 5551 (vreinterpretq_f32): Likewise. 5552 (vreinterpretq_s16): Likewise. 5553 (vreinterpretq_s32): Likewise. 5554 (vreinterpretq_s64): Likewise. 5555 (vreinterpretq_s8): Likewise. 5556 (vreinterpretq_u16): Likewise. 5557 (vreinterpretq_u32): Likewise. 5558 (vreinterpretq_u64): Likewise. 5559 (vreinterpretq_u8): Likewise. 5560 55612020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 5562 Andre Vieira <andre.simoesdiasvieira@arm.com> 5563 Mihail Ionescu <mihail.ionescu@arm.com> 5564 5565 * config/arm/arm_mve.h (vaddq_s8): Define macro. 5566 (vaddq_s16): Likewise. 5567 (vaddq_s32): Likewise. 5568 (vaddq_u8): Likewise. 5569 (vaddq_u16): Likewise. 5570 (vaddq_u32): Likewise. 5571 (vaddq_f16): Likewise. 5572 (vaddq_f32): Likewise. 5573 (__arm_vaddq_s8): Define intrinsic. 5574 (__arm_vaddq_s16): Likewise. 5575 (__arm_vaddq_s32): Likewise. 5576 (__arm_vaddq_u8): Likewise. 5577 (__arm_vaddq_u16): Likewise. 5578 (__arm_vaddq_u32): Likewise. 5579 (__arm_vaddq_f16): Likewise. 5580 (__arm_vaddq_f32): Likewise. 5581 (vaddq): Define polymorphic variant. 5582 * config/arm/iterators.md (VNIM): Define mode iterator for common types 5583 Neon, IWMMXT and MVE. 5584 (VNINOTM): Likewise. 5585 * config/arm/mve.md (mve_vaddq<mode>): Define RTL pattern. 5586 (mve_vaddq_f<mode>): Define RTL pattern. 5587 * config/arm/neon.md (add<mode>3): Rename to addv4hf3 RTL pattern. 5588 (addv8hf3_neon): Define RTL pattern. 5589 * config/arm/vec-common.md (add<mode>3): Modify standard add RTL pattern 5590 to support MVE. 5591 (addv8hf3): Define standard RTL pattern for MVE and Neon. 5592 (add<mode>3): Modify existing standard add RTL pattern for Neon and IWMMXT. 5593 55942020-03-20 Martin Liska <mliska@suse.cz> 5595 5596 PR ipa/94232 5597 * ipa-cp.c (ipa_get_jf_ancestor_result): Use offset in bytes. Previously 5598 build_ref_for_offset function was used and it transforms off to bytes 5599 from bits. 5600 56012020-03-20 Richard Biener <rguenther@suse.de> 5602 5603 PR tree-optimization/94266 5604 * gimple-ssa-sprintf.c (get_origin_and_offset): Use the 5605 type of the underlying object to adjust for the containing 5606 field if available. 5607 56082020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com> 5609 5610 * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Rename this to ... 5611 (VUNSPEC_GET_FPSCR): ... this, and move it to vunspec. 5612 * config/arm/vfp.md: (get_fpscr, set_fpscr): Revert to old patterns. 5613 56142020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com> 5615 5616 * config/arm/mve.md (mve_mov<mode>): Fix R->R case. 5617 56182020-03-20 Jakub Jelinek <jakub@redhat.com> 5619 5620 PR tree-optimization/94224 5621 * gimple-ssa-store-merging.c 5622 (imm_store_chain_info::coalesce_immediate): Don't consider overlapping 5623 or adjacent INTEGER_CST rhs_code stores as mergeable if they have 5624 different lp_nr. 5625 56262020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com> 5627 5628 * config/arm/arm.md (define_attr "conds"): Fix logic for neon and mve. 5629 56302020-03-19 Jan Hubicka <hubicka@ucw.cz> 5631 5632 PR ipa/94202 5633 * cgraph.c (cgraph_node::function_symbol): Fix availability computation. 5634 (cgraph_node::function_or_virtual_thunk_symbol): Likewise. 5635 56362020-03-19 Jan Hubicka <hubicka@ucw.cz> 5637 5638 PR ipa/92372 5639 * cgraphunit.c (process_function_and_variable_attributes): warn 5640 for flatten attribute on alias. 5641 * ipa-inline.c (ipa_inline): Do not ICE on flatten attribute on alias. 5642 56432020-03-19 Martin Liska <mliska@suse.cz> 5644 5645 * lto-section-in.c: Add ext_symtab. 5646 * lto-streamer-out.c (write_symbol_extension_info): New. 5647 (produce_symtab_extension): New. 5648 (produce_asm_for_decls): Stream also produce_symtab_extension. 5649 * lto-streamer.h (enum lto_section_type): New section. 5650 56512020-03-19 Jakub Jelinek <jakub@redhat.com> 5652 5653 PR tree-optimization/94211 5654 * tree-ssa-phiopt.c (value_replacement): Use estimate_num_insns_seq 5655 instead of estimate_num_insns for bb_seq (middle_bb). Rename 5656 emtpy_or_with_defined_p variable to empty_or_with_defined_p, adjust 5657 all uses. 5658 56592020-03-19 Richard Biener <rguenther@suse.de> 5660 5661 PR ipa/94217 5662 * ipa-cp.c (ipa_get_jf_ancestor_result): Avoid build_fold_addr_expr 5663 and build_ref_for_offset. 5664 56652020-03-19 Richard Biener <rguenther@suse.de> 5666 5667 PR middle-end/94216 5668 * fold-const.c (fold_binary_loc): Avoid using 5669 build_fold_addr_expr when we really want an ADDR_EXPR. 5670 56712020-03-18 Segher Boessenkool <segher@kernel.crashing.org> 5672 5673 * config/rs6000/constraints.md (wd, wf, wi, ws, ww): New undocumented 5674 aliases for "wa". 5675 56762020-03-12 Richard Sandiford <richard.sandiford@arm.com> 5677 5678 PR rtl-optimization/90275 5679 * cse.c (cse_insn): Delete no-op register moves too. 5680 56812020-03-18 Martin Sebor <msebor@redhat.com> 5682 5683 PR ipa/92799 5684 * cgraphunit.c (process_function_and_variable_attributes): Also 5685 complain about weakref function definitions and drop all effects 5686 of the attribute. 5687 56882020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> 5689 Mihail Ionescu <mihail.ionescu@arm.com> 5690 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 5691 5692 * config/arm/arm_mve.h (vstrdq_scatter_base_p_s64): Define macro. 5693 (vstrdq_scatter_base_p_u64): Likewise. 5694 (vstrdq_scatter_base_s64): Likewise. 5695 (vstrdq_scatter_base_u64): Likewise. 5696 (vstrdq_scatter_offset_p_s64): Likewise. 5697 (vstrdq_scatter_offset_p_u64): Likewise. 5698 (vstrdq_scatter_offset_s64): Likewise. 5699 (vstrdq_scatter_offset_u64): Likewise. 5700 (vstrdq_scatter_shifted_offset_p_s64): Likewise. 5701 (vstrdq_scatter_shifted_offset_p_u64): Likewise. 5702 (vstrdq_scatter_shifted_offset_s64): Likewise. 5703 (vstrdq_scatter_shifted_offset_u64): Likewise. 5704 (vstrhq_scatter_offset_f16): Likewise. 5705 (vstrhq_scatter_offset_p_f16): Likewise. 5706 (vstrhq_scatter_shifted_offset_f16): Likewise. 5707 (vstrhq_scatter_shifted_offset_p_f16): Likewise. 5708 (vstrwq_scatter_base_f32): Likewise. 5709 (vstrwq_scatter_base_p_f32): Likewise. 5710 (vstrwq_scatter_offset_f32): Likewise. 5711 (vstrwq_scatter_offset_p_f32): Likewise. 5712 (vstrwq_scatter_offset_p_s32): Likewise. 5713 (vstrwq_scatter_offset_p_u32): Likewise. 5714 (vstrwq_scatter_offset_s32): Likewise. 5715 (vstrwq_scatter_offset_u32): Likewise. 5716 (vstrwq_scatter_shifted_offset_f32): Likewise. 5717 (vstrwq_scatter_shifted_offset_p_f32): Likewise. 5718 (vstrwq_scatter_shifted_offset_p_s32): Likewise. 5719 (vstrwq_scatter_shifted_offset_p_u32): Likewise. 5720 (vstrwq_scatter_shifted_offset_s32): Likewise. 5721 (vstrwq_scatter_shifted_offset_u32): Likewise. 5722 (__arm_vstrdq_scatter_base_p_s64): Define intrinsic. 5723 (__arm_vstrdq_scatter_base_p_u64): Likewise. 5724 (__arm_vstrdq_scatter_base_s64): Likewise. 5725 (__arm_vstrdq_scatter_base_u64): Likewise. 5726 (__arm_vstrdq_scatter_offset_p_s64): Likewise. 5727 (__arm_vstrdq_scatter_offset_p_u64): Likewise. 5728 (__arm_vstrdq_scatter_offset_s64): Likewise. 5729 (__arm_vstrdq_scatter_offset_u64): Likewise. 5730 (__arm_vstrdq_scatter_shifted_offset_p_s64): Likewise. 5731 (__arm_vstrdq_scatter_shifted_offset_p_u64): Likewise. 5732 (__arm_vstrdq_scatter_shifted_offset_s64): Likewise. 5733 (__arm_vstrdq_scatter_shifted_offset_u64): Likewise. 5734 (__arm_vstrwq_scatter_offset_p_s32): Likewise. 5735 (__arm_vstrwq_scatter_offset_p_u32): Likewise. 5736 (__arm_vstrwq_scatter_offset_s32): Likewise. 5737 (__arm_vstrwq_scatter_offset_u32): Likewise. 5738 (__arm_vstrwq_scatter_shifted_offset_p_s32): Likewise. 5739 (__arm_vstrwq_scatter_shifted_offset_p_u32): Likewise. 5740 (__arm_vstrwq_scatter_shifted_offset_s32): Likewise. 5741 (__arm_vstrwq_scatter_shifted_offset_u32): Likewise. 5742 (__arm_vstrhq_scatter_offset_f16): Likewise. 5743 (__arm_vstrhq_scatter_offset_p_f16): Likewise. 5744 (__arm_vstrhq_scatter_shifted_offset_f16): Likewise. 5745 (__arm_vstrhq_scatter_shifted_offset_p_f16): Likewise. 5746 (__arm_vstrwq_scatter_base_f32): Likewise. 5747 (__arm_vstrwq_scatter_base_p_f32): Likewise. 5748 (__arm_vstrwq_scatter_offset_f32): Likewise. 5749 (__arm_vstrwq_scatter_offset_p_f32): Likewise. 5750 (__arm_vstrwq_scatter_shifted_offset_f32): Likewise. 5751 (__arm_vstrwq_scatter_shifted_offset_p_f32): Likewise. 5752 (vstrhq_scatter_offset): Define polymorphic variant. 5753 (vstrhq_scatter_offset_p): Likewise. 5754 (vstrhq_scatter_shifted_offset): Likewise. 5755 (vstrhq_scatter_shifted_offset_p): Likewise. 5756 (vstrwq_scatter_base): Likewise. 5757 (vstrwq_scatter_base_p): Likewise. 5758 (vstrwq_scatter_offset): Likewise. 5759 (vstrwq_scatter_offset_p): Likewise. 5760 (vstrwq_scatter_shifted_offset): Likewise. 5761 (vstrwq_scatter_shifted_offset_p): Likewise. 5762 (vstrdq_scatter_base_p): Likewise. 5763 (vstrdq_scatter_base): Likewise. 5764 (vstrdq_scatter_offset_p): Likewise. 5765 (vstrdq_scatter_offset): Likewise. 5766 (vstrdq_scatter_shifted_offset_p): Likewise. 5767 (vstrdq_scatter_shifted_offset): Likewise. 5768 * config/arm/arm_mve_builtins.def (STRSBS): Use builtin qualifier. 5769 (STRSBS_P): Likewise. 5770 (STRSBU): Likewise. 5771 (STRSBU_P): Likewise. 5772 (STRSS): Likewise. 5773 (STRSS_P): Likewise. 5774 (STRSU): Likewise. 5775 (STRSU_P): Likewise. 5776 * config/arm/constraints.md (Ri): Define. 5777 * config/arm/mve.md (VSTRDSBQ): Define iterator. 5778 (VSTRDSOQ): Likewise. 5779 (VSTRDSSOQ): Likewise. 5780 (VSTRWSOQ): Likewise. 5781 (VSTRWSSOQ): Likewise. 5782 (mve_vstrdq_scatter_base_p_<supf>v2di): Define RTL pattern. 5783 (mve_vstrdq_scatter_base_<supf>v2di): Likewise. 5784 (mve_vstrdq_scatter_offset_p_<supf>v2di): Likewise. 5785 (mve_vstrdq_scatter_offset_<supf>v2di): Likewise. 5786 (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di): Likewise. 5787 (mve_vstrdq_scatter_shifted_offset_<supf>v2di): Likewise. 5788 (mve_vstrhq_scatter_offset_fv8hf): Likewise. 5789 (mve_vstrhq_scatter_offset_p_fv8hf): Likewise. 5790 (mve_vstrhq_scatter_shifted_offset_fv8hf): Likewise. 5791 (mve_vstrhq_scatter_shifted_offset_p_fv8hf): Likewise. 5792 (mve_vstrwq_scatter_base_fv4sf): Likewise. 5793 (mve_vstrwq_scatter_base_p_fv4sf): Likewise. 5794 (mve_vstrwq_scatter_offset_fv4sf): Likewise. 5795 (mve_vstrwq_scatter_offset_p_fv4sf): Likewise. 5796 (mve_vstrwq_scatter_offset_p_<supf>v4si): Likewise. 5797 (mve_vstrwq_scatter_offset_<supf>v4si): Likewise. 5798 (mve_vstrwq_scatter_shifted_offset_fv4sf): Likewise. 5799 (mve_vstrwq_scatter_shifted_offset_p_fv4sf): Likewise. 5800 (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si): Likewise. 5801 (mve_vstrwq_scatter_shifted_offset_<supf>v4si): Likewise. 5802 * config/arm/predicates.md (Ri): Define predicate to check immediate 5803 is the range +/-1016 and multiple of 8. 5804 58052020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> 5806 Mihail Ionescu <mihail.ionescu@arm.com> 5807 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 5808 5809 * config/arm/arm_mve.h (vst1q_f32): Define macro. 5810 (vst1q_f16): Likewise. 5811 (vst1q_s8): Likewise. 5812 (vst1q_s32): Likewise. 5813 (vst1q_s16): Likewise. 5814 (vst1q_u8): Likewise. 5815 (vst1q_u32): Likewise. 5816 (vst1q_u16): Likewise. 5817 (vstrhq_f16): Likewise. 5818 (vstrhq_scatter_offset_s32): Likewise. 5819 (vstrhq_scatter_offset_s16): Likewise. 5820 (vstrhq_scatter_offset_u32): Likewise. 5821 (vstrhq_scatter_offset_u16): Likewise. 5822 (vstrhq_scatter_offset_p_s32): Likewise. 5823 (vstrhq_scatter_offset_p_s16): Likewise. 5824 (vstrhq_scatter_offset_p_u32): Likewise. 5825 (vstrhq_scatter_offset_p_u16): Likewise. 5826 (vstrhq_scatter_shifted_offset_s32): Likewise. 5827 (vstrhq_scatter_shifted_offset_s16): Likewise. 5828 (vstrhq_scatter_shifted_offset_u32): Likewise. 5829 (vstrhq_scatter_shifted_offset_u16): Likewise. 5830 (vstrhq_scatter_shifted_offset_p_s32): Likewise. 5831 (vstrhq_scatter_shifted_offset_p_s16): Likewise. 5832 (vstrhq_scatter_shifted_offset_p_u32): Likewise. 5833 (vstrhq_scatter_shifted_offset_p_u16): Likewise. 5834 (vstrhq_s32): Likewise. 5835 (vstrhq_s16): Likewise. 5836 (vstrhq_u32): Likewise. 5837 (vstrhq_u16): Likewise. 5838 (vstrhq_p_f16): Likewise. 5839 (vstrhq_p_s32): Likewise. 5840 (vstrhq_p_s16): Likewise. 5841 (vstrhq_p_u32): Likewise. 5842 (vstrhq_p_u16): Likewise. 5843 (vstrwq_f32): Likewise. 5844 (vstrwq_s32): Likewise. 5845 (vstrwq_u32): Likewise. 5846 (vstrwq_p_f32): Likewise. 5847 (vstrwq_p_s32): Likewise. 5848 (vstrwq_p_u32): Likewise. 5849 (__arm_vst1q_s8): Define intrinsic. 5850 (__arm_vst1q_s32): Likewise. 5851 (__arm_vst1q_s16): Likewise. 5852 (__arm_vst1q_u8): Likewise. 5853 (__arm_vst1q_u32): Likewise. 5854 (__arm_vst1q_u16): Likewise. 5855 (__arm_vstrhq_scatter_offset_s32): Likewise. 5856 (__arm_vstrhq_scatter_offset_s16): Likewise. 5857 (__arm_vstrhq_scatter_offset_u32): Likewise. 5858 (__arm_vstrhq_scatter_offset_u16): Likewise. 5859 (__arm_vstrhq_scatter_offset_p_s32): Likewise. 5860 (__arm_vstrhq_scatter_offset_p_s16): Likewise. 5861 (__arm_vstrhq_scatter_offset_p_u32): Likewise. 5862 (__arm_vstrhq_scatter_offset_p_u16): Likewise. 5863 (__arm_vstrhq_scatter_shifted_offset_s32): Likewise. 5864 (__arm_vstrhq_scatter_shifted_offset_s16): Likewise. 5865 (__arm_vstrhq_scatter_shifted_offset_u32): Likewise. 5866 (__arm_vstrhq_scatter_shifted_offset_u16): Likewise. 5867 (__arm_vstrhq_scatter_shifted_offset_p_s32): Likewise. 5868 (__arm_vstrhq_scatter_shifted_offset_p_s16): Likewise. 5869 (__arm_vstrhq_scatter_shifted_offset_p_u32): Likewise. 5870 (__arm_vstrhq_scatter_shifted_offset_p_u16): Likewise. 5871 (__arm_vstrhq_s32): Likewise. 5872 (__arm_vstrhq_s16): Likewise. 5873 (__arm_vstrhq_u32): Likewise. 5874 (__arm_vstrhq_u16): Likewise. 5875 (__arm_vstrhq_p_s32): Likewise. 5876 (__arm_vstrhq_p_s16): Likewise. 5877 (__arm_vstrhq_p_u32): Likewise. 5878 (__arm_vstrhq_p_u16): Likewise. 5879 (__arm_vstrwq_s32): Likewise. 5880 (__arm_vstrwq_u32): Likewise. 5881 (__arm_vstrwq_p_s32): Likewise. 5882 (__arm_vstrwq_p_u32): Likewise. 5883 (__arm_vstrwq_p_f32): Likewise. 5884 (__arm_vstrwq_f32): Likewise. 5885 (__arm_vst1q_f32): Likewise. 5886 (__arm_vst1q_f16): Likewise. 5887 (__arm_vstrhq_f16): Likewise. 5888 (__arm_vstrhq_p_f16): Likewise. 5889 (vst1q): Define polymorphic variant. 5890 (vstrhq): Likewise. 5891 (vstrhq_p): Likewise. 5892 (vstrhq_scatter_offset_p): Likewise. 5893 (vstrhq_scatter_offset): Likewise. 5894 (vstrhq_scatter_shifted_offset_p): Likewise. 5895 (vstrhq_scatter_shifted_offset): Likewise. 5896 (vstrwq_p): Likewise. 5897 (vstrwq): Likewise. 5898 * config/arm/arm_mve_builtins.def (STRS): Use builtin qualifier. 5899 (STRS_P): Likewise. 5900 (STRSS): Likewise. 5901 (STRSS_P): Likewise. 5902 (STRSU): Likewise. 5903 (STRSU_P): Likewise. 5904 (STRU): Likewise. 5905 (STRU_P): Likewise. 5906 * config/arm/mve.md (VST1Q): Define iterator. 5907 (VSTRHSOQ): Likewise. 5908 (VSTRHSSOQ): Likewise. 5909 (VSTRHQ): Likewise. 5910 (VSTRWQ): Likewise. 5911 (mve_vstrhq_fv8hf): Define RTL pattern. 5912 (mve_vstrhq_p_fv8hf): Likewise. 5913 (mve_vstrhq_p_<supf><mode>): Likewise. 5914 (mve_vstrhq_scatter_offset_p_<supf><mode>): Likewise. 5915 (mve_vstrhq_scatter_offset_<supf><mode>): Likewise. 5916 (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>): Likewise. 5917 (mve_vstrhq_scatter_shifted_offset_<supf><mode>): Likewise. 5918 (mve_vstrhq_<supf><mode>): Likewise. 5919 (mve_vstrwq_fv4sf): Likewise. 5920 (mve_vstrwq_p_fv4sf): Likewise. 5921 (mve_vstrwq_p_<supf>v4si): Likewise. 5922 (mve_vstrwq_<supf>v4si): Likewise. 5923 (mve_vst1q_f<mode>): Define expand. 5924 (mve_vst1q_<supf><mode>): Likewise. 5925 59262020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> 5927 Mihail Ionescu <mihail.ionescu@arm.com> 5928 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 5929 5930 * config/arm/arm_mve.h (vld1q_s8): Define macro. 5931 (vld1q_s32): Likewise. 5932 (vld1q_s16): Likewise. 5933 (vld1q_u8): Likewise. 5934 (vld1q_u32): Likewise. 5935 (vld1q_u16): Likewise. 5936 (vldrhq_gather_offset_s32): Likewise. 5937 (vldrhq_gather_offset_s16): Likewise. 5938 (vldrhq_gather_offset_u32): Likewise. 5939 (vldrhq_gather_offset_u16): Likewise. 5940 (vldrhq_gather_offset_z_s32): Likewise. 5941 (vldrhq_gather_offset_z_s16): Likewise. 5942 (vldrhq_gather_offset_z_u32): Likewise. 5943 (vldrhq_gather_offset_z_u16): Likewise. 5944 (vldrhq_gather_shifted_offset_s32): Likewise. 5945 (vldrhq_gather_shifted_offset_s16): Likewise. 5946 (vldrhq_gather_shifted_offset_u32): Likewise. 5947 (vldrhq_gather_shifted_offset_u16): Likewise. 5948 (vldrhq_gather_shifted_offset_z_s32): Likewise. 5949 (vldrhq_gather_shifted_offset_z_s16): Likewise. 5950 (vldrhq_gather_shifted_offset_z_u32): Likewise. 5951 (vldrhq_gather_shifted_offset_z_u16): Likewise. 5952 (vldrhq_s32): Likewise. 5953 (vldrhq_s16): Likewise. 5954 (vldrhq_u32): Likewise. 5955 (vldrhq_u16): Likewise. 5956 (vldrhq_z_s32): Likewise. 5957 (vldrhq_z_s16): Likewise. 5958 (vldrhq_z_u32): Likewise. 5959 (vldrhq_z_u16): Likewise. 5960 (vldrwq_s32): Likewise. 5961 (vldrwq_u32): Likewise. 5962 (vldrwq_z_s32): Likewise. 5963 (vldrwq_z_u32): Likewise. 5964 (vld1q_f32): Likewise. 5965 (vld1q_f16): Likewise. 5966 (vldrhq_f16): Likewise. 5967 (vldrhq_z_f16): Likewise. 5968 (vldrwq_f32): Likewise. 5969 (vldrwq_z_f32): Likewise. 5970 (__arm_vld1q_s8): Define intrinsic. 5971 (__arm_vld1q_s32): Likewise. 5972 (__arm_vld1q_s16): Likewise. 5973 (__arm_vld1q_u8): Likewise. 5974 (__arm_vld1q_u32): Likewise. 5975 (__arm_vld1q_u16): Likewise. 5976 (__arm_vldrhq_gather_offset_s32): Likewise. 5977 (__arm_vldrhq_gather_offset_s16): Likewise. 5978 (__arm_vldrhq_gather_offset_u32): Likewise. 5979 (__arm_vldrhq_gather_offset_u16): Likewise. 5980 (__arm_vldrhq_gather_offset_z_s32): Likewise. 5981 (__arm_vldrhq_gather_offset_z_s16): Likewise. 5982 (__arm_vldrhq_gather_offset_z_u32): Likewise. 5983 (__arm_vldrhq_gather_offset_z_u16): Likewise. 5984 (__arm_vldrhq_gather_shifted_offset_s32): Likewise. 5985 (__arm_vldrhq_gather_shifted_offset_s16): Likewise. 5986 (__arm_vldrhq_gather_shifted_offset_u32): Likewise. 5987 (__arm_vldrhq_gather_shifted_offset_u16): Likewise. 5988 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise. 5989 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise. 5990 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise. 5991 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise. 5992 (__arm_vldrhq_s32): Likewise. 5993 (__arm_vldrhq_s16): Likewise. 5994 (__arm_vldrhq_u32): Likewise. 5995 (__arm_vldrhq_u16): Likewise. 5996 (__arm_vldrhq_z_s32): Likewise. 5997 (__arm_vldrhq_z_s16): Likewise. 5998 (__arm_vldrhq_z_u32): Likewise. 5999 (__arm_vldrhq_z_u16): Likewise. 6000 (__arm_vldrwq_s32): Likewise. 6001 (__arm_vldrwq_u32): Likewise. 6002 (__arm_vldrwq_z_s32): Likewise. 6003 (__arm_vldrwq_z_u32): Likewise. 6004 (__arm_vld1q_f32): Likewise. 6005 (__arm_vld1q_f16): Likewise. 6006 (__arm_vldrwq_f32): Likewise. 6007 (__arm_vldrwq_z_f32): Likewise. 6008 (__arm_vldrhq_z_f16): Likewise. 6009 (__arm_vldrhq_f16): Likewise. 6010 (vld1q): Define polymorphic variant. 6011 (vldrhq_gather_offset): Likewise. 6012 (vldrhq_gather_offset_z): Likewise. 6013 (vldrhq_gather_shifted_offset): Likewise. 6014 (vldrhq_gather_shifted_offset_z): Likewise. 6015 * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier. 6016 (LDRS): Likewise. 6017 (LDRU_Z): Likewise. 6018 (LDRS_Z): Likewise. 6019 (LDRGU_Z): Likewise. 6020 (LDRGU): Likewise. 6021 (LDRGS_Z): Likewise. 6022 (LDRGS): Likewise. 6023 * config/arm/mve.md (MVE_H_ELEM): Define mode iterator. 6024 (V_sz_elem1): Likewise. 6025 (VLD1Q): Define iterator. 6026 (VLDRHGOQ): Likewise. 6027 (VLDRHGSOQ): Likewise. 6028 (VLDRHQ): Likewise. 6029 (VLDRWQ): Likewise. 6030 (mve_vldrhq_fv8hf): Define RTL pattern. 6031 (mve_vldrhq_gather_offset_<supf><mode>): Likewise. 6032 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise. 6033 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise. 6034 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise. 6035 (mve_vldrhq_<supf><mode>): Likewise. 6036 (mve_vldrhq_z_fv8hf): Likewise. 6037 (mve_vldrhq_z_<supf><mode>): Likewise. 6038 (mve_vldrwq_fv4sf): Likewise. 6039 (mve_vldrwq_<supf>v4si): Likewise. 6040 (mve_vldrwq_z_fv4sf): Likewise. 6041 (mve_vldrwq_z_<supf>v4si): Likewise. 6042 (mve_vld1q_f<mode>): Define RTL expand pattern. 6043 (mve_vld1q_<supf><mode>): Likewise. 6044 60452020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> 6046 Mihail Ionescu <mihail.ionescu@arm.com> 6047 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 6048 6049 * config/arm/arm_mve.h (vld1q_s8): Define macro. 6050 (vld1q_s32): Likewise. 6051 (vld1q_s16): Likewise. 6052 (vld1q_u8): Likewise. 6053 (vld1q_u32): Likewise. 6054 (vld1q_u16): Likewise. 6055 (vldrhq_gather_offset_s32): Likewise. 6056 (vldrhq_gather_offset_s16): Likewise. 6057 (vldrhq_gather_offset_u32): Likewise. 6058 (vldrhq_gather_offset_u16): Likewise. 6059 (vldrhq_gather_offset_z_s32): Likewise. 6060 (vldrhq_gather_offset_z_s16): Likewise. 6061 (vldrhq_gather_offset_z_u32): Likewise. 6062 (vldrhq_gather_offset_z_u16): Likewise. 6063 (vldrhq_gather_shifted_offset_s32): Likewise. 6064 (vldrhq_gather_shifted_offset_s16): Likewise. 6065 (vldrhq_gather_shifted_offset_u32): Likewise. 6066 (vldrhq_gather_shifted_offset_u16): Likewise. 6067 (vldrhq_gather_shifted_offset_z_s32): Likewise. 6068 (vldrhq_gather_shifted_offset_z_s16): Likewise. 6069 (vldrhq_gather_shifted_offset_z_u32): Likewise. 6070 (vldrhq_gather_shifted_offset_z_u16): Likewise. 6071 (vldrhq_s32): Likewise. 6072 (vldrhq_s16): Likewise. 6073 (vldrhq_u32): Likewise. 6074 (vldrhq_u16): Likewise. 6075 (vldrhq_z_s32): Likewise. 6076 (vldrhq_z_s16): Likewise. 6077 (vldrhq_z_u32): Likewise. 6078 (vldrhq_z_u16): Likewise. 6079 (vldrwq_s32): Likewise. 6080 (vldrwq_u32): Likewise. 6081 (vldrwq_z_s32): Likewise. 6082 (vldrwq_z_u32): Likewise. 6083 (vld1q_f32): Likewise. 6084 (vld1q_f16): Likewise. 6085 (vldrhq_f16): Likewise. 6086 (vldrhq_z_f16): Likewise. 6087 (vldrwq_f32): Likewise. 6088 (vldrwq_z_f32): Likewise. 6089 (__arm_vld1q_s8): Define intrinsic. 6090 (__arm_vld1q_s32): Likewise. 6091 (__arm_vld1q_s16): Likewise. 6092 (__arm_vld1q_u8): Likewise. 6093 (__arm_vld1q_u32): Likewise. 6094 (__arm_vld1q_u16): Likewise. 6095 (__arm_vldrhq_gather_offset_s32): Likewise. 6096 (__arm_vldrhq_gather_offset_s16): Likewise. 6097 (__arm_vldrhq_gather_offset_u32): Likewise. 6098 (__arm_vldrhq_gather_offset_u16): Likewise. 6099 (__arm_vldrhq_gather_offset_z_s32): Likewise. 6100 (__arm_vldrhq_gather_offset_z_s16): Likewise. 6101 (__arm_vldrhq_gather_offset_z_u32): Likewise. 6102 (__arm_vldrhq_gather_offset_z_u16): Likewise. 6103 (__arm_vldrhq_gather_shifted_offset_s32): Likewise. 6104 (__arm_vldrhq_gather_shifted_offset_s16): Likewise. 6105 (__arm_vldrhq_gather_shifted_offset_u32): Likewise. 6106 (__arm_vldrhq_gather_shifted_offset_u16): Likewise. 6107 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise. 6108 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise. 6109 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise. 6110 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise. 6111 (__arm_vldrhq_s32): Likewise. 6112 (__arm_vldrhq_s16): Likewise. 6113 (__arm_vldrhq_u32): Likewise. 6114 (__arm_vldrhq_u16): Likewise. 6115 (__arm_vldrhq_z_s32): Likewise. 6116 (__arm_vldrhq_z_s16): Likewise. 6117 (__arm_vldrhq_z_u32): Likewise. 6118 (__arm_vldrhq_z_u16): Likewise. 6119 (__arm_vldrwq_s32): Likewise. 6120 (__arm_vldrwq_u32): Likewise. 6121 (__arm_vldrwq_z_s32): Likewise. 6122 (__arm_vldrwq_z_u32): Likewise. 6123 (__arm_vld1q_f32): Likewise. 6124 (__arm_vld1q_f16): Likewise. 6125 (__arm_vldrwq_f32): Likewise. 6126 (__arm_vldrwq_z_f32): Likewise. 6127 (__arm_vldrhq_z_f16): Likewise. 6128 (__arm_vldrhq_f16): Likewise. 6129 (vld1q): Define polymorphic variant. 6130 (vldrhq_gather_offset): Likewise. 6131 (vldrhq_gather_offset_z): Likewise. 6132 (vldrhq_gather_shifted_offset): Likewise. 6133 (vldrhq_gather_shifted_offset_z): Likewise. 6134 * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier. 6135 (LDRS): Likewise. 6136 (LDRU_Z): Likewise. 6137 (LDRS_Z): Likewise. 6138 (LDRGU_Z): Likewise. 6139 (LDRGU): Likewise. 6140 (LDRGS_Z): Likewise. 6141 (LDRGS): Likewise. 6142 * config/arm/mve.md (MVE_H_ELEM): Define mode iterator. 6143 (V_sz_elem1): Likewise. 6144 (VLD1Q): Define iterator. 6145 (VLDRHGOQ): Likewise. 6146 (VLDRHGSOQ): Likewise. 6147 (VLDRHQ): Likewise. 6148 (VLDRWQ): Likewise. 6149 (mve_vldrhq_fv8hf): Define RTL pattern. 6150 (mve_vldrhq_gather_offset_<supf><mode>): Likewise. 6151 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise. 6152 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise. 6153 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise. 6154 (mve_vldrhq_<supf><mode>): Likewise. 6155 (mve_vldrhq_z_fv8hf): Likewise. 6156 (mve_vldrhq_z_<supf><mode>): Likewise. 6157 (mve_vldrwq_fv4sf): Likewise. 6158 (mve_vldrwq_<supf>v4si): Likewise. 6159 (mve_vldrwq_z_fv4sf): Likewise. 6160 (mve_vldrwq_z_<supf>v4si): Likewise. 6161 (mve_vld1q_f<mode>): Define RTL expand pattern. 6162 (mve_vld1q_<supf><mode>): Likewise. 6163 61642020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> 6165 Mihail Ionescu <mihail.ionescu@arm.com> 6166 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 6167 6168 * config/arm/arm-builtins.c (LDRGBS_Z_QUALIFIERS): Define builtin 6169 qualifier. 6170 (LDRGBU_Z_QUALIFIERS): Likewise. 6171 (LDRGS_Z_QUALIFIERS): Likewise. 6172 (LDRGU_Z_QUALIFIERS): Likewise. 6173 (LDRS_Z_QUALIFIERS): Likewise. 6174 (LDRU_Z_QUALIFIERS): Likewise. 6175 * config/arm/arm_mve.h (vldrbq_gather_offset_z_s16): Define macro. 6176 (vldrbq_gather_offset_z_u8): Likewise. 6177 (vldrbq_gather_offset_z_s32): Likewise. 6178 (vldrbq_gather_offset_z_u16): Likewise. 6179 (vldrbq_gather_offset_z_u32): Likewise. 6180 (vldrbq_gather_offset_z_s8): Likewise. 6181 (vldrbq_z_s16): Likewise. 6182 (vldrbq_z_u8): Likewise. 6183 (vldrbq_z_s8): Likewise. 6184 (vldrbq_z_s32): Likewise. 6185 (vldrbq_z_u16): Likewise. 6186 (vldrbq_z_u32): Likewise. 6187 (vldrwq_gather_base_z_u32): Likewise. 6188 (vldrwq_gather_base_z_s32): Likewise. 6189 (__arm_vldrbq_gather_offset_z_s8): Define intrinsic. 6190 (__arm_vldrbq_gather_offset_z_s32): Likewise. 6191 (__arm_vldrbq_gather_offset_z_s16): Likewise. 6192 (__arm_vldrbq_gather_offset_z_u8): Likewise. 6193 (__arm_vldrbq_gather_offset_z_u32): Likewise. 6194 (__arm_vldrbq_gather_offset_z_u16): Likewise. 6195 (__arm_vldrbq_z_s8): Likewise. 6196 (__arm_vldrbq_z_s32): Likewise. 6197 (__arm_vldrbq_z_s16): Likewise. 6198 (__arm_vldrbq_z_u8): Likewise. 6199 (__arm_vldrbq_z_u32): Likewise. 6200 (__arm_vldrbq_z_u16): Likewise. 6201 (__arm_vldrwq_gather_base_z_s32): Likewise. 6202 (__arm_vldrwq_gather_base_z_u32): Likewise. 6203 (vldrbq_gather_offset_z): Define polymorphic variant. 6204 * config/arm/arm_mve_builtins.def (LDRGBS_Z_QUALIFIERS): Use builtin 6205 qualifier. 6206 (LDRGBU_Z_QUALIFIERS): Likewise. 6207 (LDRGS_Z_QUALIFIERS): Likewise. 6208 (LDRGU_Z_QUALIFIERS): Likewise. 6209 (LDRS_Z_QUALIFIERS): Likewise. 6210 (LDRU_Z_QUALIFIERS): Likewise. 6211 * config/arm/mve.md (mve_vldrbq_gather_offset_z_<supf><mode>): Define 6212 RTL pattern. 6213 (mve_vldrbq_z_<supf><mode>): Likewise. 6214 (mve_vldrwq_gather_base_z_<supf>v4si): Likewise. 6215 62162020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> 6217 Mihail Ionescu <mihail.ionescu@arm.com> 6218 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 6219 6220 * config/arm/arm-builtins.c (STRS_P_QUALIFIERS): Define builtin 6221 qualifier. 6222 (STRU_P_QUALIFIERS): Likewise. 6223 (STRSU_P_QUALIFIERS): Likewise. 6224 (STRSS_P_QUALIFIERS): Likewise. 6225 (STRSBS_P_QUALIFIERS): Likewise. 6226 (STRSBU_P_QUALIFIERS): Likewise. 6227 * config/arm/arm_mve.h (vstrbq_p_s8): Define macro. 6228 (vstrbq_p_s32): Likewise. 6229 (vstrbq_p_s16): Likewise. 6230 (vstrbq_p_u8): Likewise. 6231 (vstrbq_p_u32): Likewise. 6232 (vstrbq_p_u16): Likewise. 6233 (vstrbq_scatter_offset_p_s8): Likewise. 6234 (vstrbq_scatter_offset_p_s32): Likewise. 6235 (vstrbq_scatter_offset_p_s16): Likewise. 6236 (vstrbq_scatter_offset_p_u8): Likewise. 6237 (vstrbq_scatter_offset_p_u32): Likewise. 6238 (vstrbq_scatter_offset_p_u16): Likewise. 6239 (vstrwq_scatter_base_p_s32): Likewise. 6240 (vstrwq_scatter_base_p_u32): Likewise. 6241 (__arm_vstrbq_p_s8): Define intrinsic. 6242 (__arm_vstrbq_p_s32): Likewise. 6243 (__arm_vstrbq_p_s16): Likewise. 6244 (__arm_vstrbq_p_u8): Likewise. 6245 (__arm_vstrbq_p_u32): Likewise. 6246 (__arm_vstrbq_p_u16): Likewise. 6247 (__arm_vstrbq_scatter_offset_p_s8): Likewise. 6248 (__arm_vstrbq_scatter_offset_p_s32): Likewise. 6249 (__arm_vstrbq_scatter_offset_p_s16): Likewise. 6250 (__arm_vstrbq_scatter_offset_p_u8): Likewise. 6251 (__arm_vstrbq_scatter_offset_p_u32): Likewise. 6252 (__arm_vstrbq_scatter_offset_p_u16): Likewise. 6253 (__arm_vstrwq_scatter_base_p_s32): Likewise. 6254 (__arm_vstrwq_scatter_base_p_u32): Likewise. 6255 (vstrbq_p): Define polymorphic variant. 6256 (vstrbq_scatter_offset_p): Likewise. 6257 (vstrwq_scatter_base_p): Likewise. 6258 * config/arm/arm_mve_builtins.def (STRS_P_QUALIFIERS): Use builtin 6259 qualifier. 6260 (STRU_P_QUALIFIERS): Likewise. 6261 (STRSU_P_QUALIFIERS): Likewise. 6262 (STRSS_P_QUALIFIERS): Likewise. 6263 (STRSBS_P_QUALIFIERS): Likewise. 6264 (STRSBU_P_QUALIFIERS): Likewise. 6265 * config/arm/mve.md (mve_vstrbq_scatter_offset_p_<supf><mode>): Define 6266 RTL pattern. 6267 (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise. 6268 (mve_vstrbq_p_<supf><mode>): Likewise. 6269 62702020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> 6271 Mihail Ionescu <mihail.ionescu@arm.com> 6272 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 6273 6274 * config/arm/arm-builtins.c (LDRGU_QUALIFIERS): Define builtin 6275 qualifier. 6276 (LDRGS_QUALIFIERS): Likewise. 6277 (LDRS_QUALIFIERS): Likewise. 6278 (LDRU_QUALIFIERS): Likewise. 6279 (LDRGBS_QUALIFIERS): Likewise. 6280 (LDRGBU_QUALIFIERS): Likewise. 6281 * config/arm/arm_mve.h (vldrbq_gather_offset_u8): Define macro. 6282 (vldrbq_gather_offset_s8): Likewise. 6283 (vldrbq_s8): Likewise. 6284 (vldrbq_u8): Likewise. 6285 (vldrbq_gather_offset_u16): Likewise. 6286 (vldrbq_gather_offset_s16): Likewise. 6287 (vldrbq_s16): Likewise. 6288 (vldrbq_u16): Likewise. 6289 (vldrbq_gather_offset_u32): Likewise. 6290 (vldrbq_gather_offset_s32): Likewise. 6291 (vldrbq_s32): Likewise. 6292 (vldrbq_u32): Likewise. 6293 (vldrwq_gather_base_s32): Likewise. 6294 (vldrwq_gather_base_u32): Likewise. 6295 (__arm_vldrbq_gather_offset_u8): Define intrinsic. 6296 (__arm_vldrbq_gather_offset_s8): Likewise. 6297 (__arm_vldrbq_s8): Likewise. 6298 (__arm_vldrbq_u8): Likewise. 6299 (__arm_vldrbq_gather_offset_u16): Likewise. 6300 (__arm_vldrbq_gather_offset_s16): Likewise. 6301 (__arm_vldrbq_s16): Likewise. 6302 (__arm_vldrbq_u16): Likewise. 6303 (__arm_vldrbq_gather_offset_u32): Likewise. 6304 (__arm_vldrbq_gather_offset_s32): Likewise. 6305 (__arm_vldrbq_s32): Likewise. 6306 (__arm_vldrbq_u32): Likewise. 6307 (__arm_vldrwq_gather_base_s32): Likewise. 6308 (__arm_vldrwq_gather_base_u32): Likewise. 6309 (vldrbq_gather_offset): Define polymorphic variant. 6310 * config/arm/arm_mve_builtins.def (LDRGU_QUALIFIERS): Use builtin 6311 qualifier. 6312 (LDRGS_QUALIFIERS): Likewise. 6313 (LDRS_QUALIFIERS): Likewise. 6314 (LDRU_QUALIFIERS): Likewise. 6315 (LDRGBS_QUALIFIERS): Likewise. 6316 (LDRGBU_QUALIFIERS): Likewise. 6317 * config/arm/mve.md (VLDRBGOQ): Define iterator. 6318 (VLDRBQ): Likewise. 6319 (VLDRWGBQ): Likewise. 6320 (mve_vldrbq_gather_offset_<supf><mode>): Define RTL pattern. 6321 (mve_vldrbq_<supf><mode>): Likewise. 6322 (mve_vldrwq_gather_base_<supf>v4si): Likewise. 6323 63242020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> 6325 Mihail Ionescu <mihail.ionescu@arm.com> 6326 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 6327 6328 * config/arm/arm-builtins.c (STRS_QUALIFIERS): Define builtin qualifier. 6329 (STRU_QUALIFIERS): Likewise. 6330 (STRSS_QUALIFIERS): Likewise. 6331 (STRSU_QUALIFIERS): Likewise. 6332 (STRSBS_QUALIFIERS): Likewise. 6333 (STRSBU_QUALIFIERS): Likewise. 6334 * config/arm/arm_mve.h (vstrbq_s8): Define macro. 6335 (vstrbq_u8): Likewise. 6336 (vstrbq_u16): Likewise. 6337 (vstrbq_scatter_offset_s8): Likewise. 6338 (vstrbq_scatter_offset_u8): Likewise. 6339 (vstrbq_scatter_offset_u16): Likewise. 6340 (vstrbq_s16): Likewise. 6341 (vstrbq_u32): Likewise. 6342 (vstrbq_scatter_offset_s16): Likewise. 6343 (vstrbq_scatter_offset_u32): Likewise. 6344 (vstrbq_s32): Likewise. 6345 (vstrbq_scatter_offset_s32): Likewise. 6346 (vstrwq_scatter_base_s32): Likewise. 6347 (vstrwq_scatter_base_u32): Likewise. 6348 (__arm_vstrbq_scatter_offset_s8): Define intrinsic. 6349 (__arm_vstrbq_scatter_offset_s32): Likewise. 6350 (__arm_vstrbq_scatter_offset_s16): Likewise. 6351 (__arm_vstrbq_scatter_offset_u8): Likewise. 6352 (__arm_vstrbq_scatter_offset_u32): Likewise. 6353 (__arm_vstrbq_scatter_offset_u16): Likewise. 6354 (__arm_vstrbq_s8): Likewise. 6355 (__arm_vstrbq_s32): Likewise. 6356 (__arm_vstrbq_s16): Likewise. 6357 (__arm_vstrbq_u8): Likewise. 6358 (__arm_vstrbq_u32): Likewise. 6359 (__arm_vstrbq_u16): Likewise. 6360 (__arm_vstrwq_scatter_base_s32): Likewise. 6361 (__arm_vstrwq_scatter_base_u32): Likewise. 6362 (vstrbq): Define polymorphic variant. 6363 (vstrbq_scatter_offset): Likewise. 6364 (vstrwq_scatter_base): Likewise. 6365 * config/arm/arm_mve_builtins.def (STRS_QUALIFIERS): Use builtin 6366 qualifier. 6367 (STRU_QUALIFIERS): Likewise. 6368 (STRSS_QUALIFIERS): Likewise. 6369 (STRSU_QUALIFIERS): Likewise. 6370 (STRSBS_QUALIFIERS): Likewise. 6371 (STRSBU_QUALIFIERS): Likewise. 6372 * config/arm/mve.md (MVE_B_ELEM): Define mode attribute iterator. 6373 (VSTRWSBQ): Define iterators. 6374 (VSTRBSOQ): Likewise. 6375 (VSTRBQ): Likewise. 6376 (mve_vstrbq_<supf><mode>): Define RTL pattern. 6377 (mve_vstrbq_scatter_offset_<supf><mode>): Likewise. 6378 (mve_vstrwq_scatter_base_<supf>v4si): Likewise. 6379 63802020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> 6381 Mihail Ionescu <mihail.ionescu@arm.com> 6382 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 6383 6384 * config/arm/arm_mve.h (vabdq_m_f32): Define macro. 6385 (vabdq_m_f16): Likewise. 6386 (vaddq_m_f32): Likewise. 6387 (vaddq_m_f16): Likewise. 6388 (vaddq_m_n_f32): Likewise. 6389 (vaddq_m_n_f16): Likewise. 6390 (vandq_m_f32): Likewise. 6391 (vandq_m_f16): Likewise. 6392 (vbicq_m_f32): Likewise. 6393 (vbicq_m_f16): Likewise. 6394 (vbrsrq_m_n_f32): Likewise. 6395 (vbrsrq_m_n_f16): Likewise. 6396 (vcaddq_rot270_m_f32): Likewise. 6397 (vcaddq_rot270_m_f16): Likewise. 6398 (vcaddq_rot90_m_f32): Likewise. 6399 (vcaddq_rot90_m_f16): Likewise. 6400 (vcmlaq_m_f32): Likewise. 6401 (vcmlaq_m_f16): Likewise. 6402 (vcmlaq_rot180_m_f32): Likewise. 6403 (vcmlaq_rot180_m_f16): Likewise. 6404 (vcmlaq_rot270_m_f32): Likewise. 6405 (vcmlaq_rot270_m_f16): Likewise. 6406 (vcmlaq_rot90_m_f32): Likewise. 6407 (vcmlaq_rot90_m_f16): Likewise. 6408 (vcmulq_m_f32): Likewise. 6409 (vcmulq_m_f16): Likewise. 6410 (vcmulq_rot180_m_f32): Likewise. 6411 (vcmulq_rot180_m_f16): Likewise. 6412 (vcmulq_rot270_m_f32): Likewise. 6413 (vcmulq_rot270_m_f16): Likewise. 6414 (vcmulq_rot90_m_f32): Likewise. 6415 (vcmulq_rot90_m_f16): Likewise. 6416 (vcvtq_m_n_s32_f32): Likewise. 6417 (vcvtq_m_n_s16_f16): Likewise. 6418 (vcvtq_m_n_u32_f32): Likewise. 6419 (vcvtq_m_n_u16_f16): Likewise. 6420 (veorq_m_f32): Likewise. 6421 (veorq_m_f16): Likewise. 6422 (vfmaq_m_f32): Likewise. 6423 (vfmaq_m_f16): Likewise. 6424 (vfmaq_m_n_f32): Likewise. 6425 (vfmaq_m_n_f16): Likewise. 6426 (vfmasq_m_n_f32): Likewise. 6427 (vfmasq_m_n_f16): Likewise. 6428 (vfmsq_m_f32): Likewise. 6429 (vfmsq_m_f16): Likewise. 6430 (vmaxnmq_m_f32): Likewise. 6431 (vmaxnmq_m_f16): Likewise. 6432 (vminnmq_m_f32): Likewise. 6433 (vminnmq_m_f16): Likewise. 6434 (vmulq_m_f32): Likewise. 6435 (vmulq_m_f16): Likewise. 6436 (vmulq_m_n_f32): Likewise. 6437 (vmulq_m_n_f16): Likewise. 6438 (vornq_m_f32): Likewise. 6439 (vornq_m_f16): Likewise. 6440 (vorrq_m_f32): Likewise. 6441 (vorrq_m_f16): Likewise. 6442 (vsubq_m_f32): Likewise. 6443 (vsubq_m_f16): Likewise. 6444 (vsubq_m_n_f32): Likewise. 6445 (vsubq_m_n_f16): Likewise. 6446 (__attribute__): Likewise. 6447 (__arm_vabdq_m_f32): Likewise. 6448 (__arm_vabdq_m_f16): Likewise. 6449 (__arm_vaddq_m_f32): Likewise. 6450 (__arm_vaddq_m_f16): Likewise. 6451 (__arm_vaddq_m_n_f32): Likewise. 6452 (__arm_vaddq_m_n_f16): Likewise. 6453 (__arm_vandq_m_f32): Likewise. 6454 (__arm_vandq_m_f16): Likewise. 6455 (__arm_vbicq_m_f32): Likewise. 6456 (__arm_vbicq_m_f16): Likewise. 6457 (__arm_vbrsrq_m_n_f32): Likewise. 6458 (__arm_vbrsrq_m_n_f16): Likewise. 6459 (__arm_vcaddq_rot270_m_f32): Likewise. 6460 (__arm_vcaddq_rot270_m_f16): Likewise. 6461 (__arm_vcaddq_rot90_m_f32): Likewise. 6462 (__arm_vcaddq_rot90_m_f16): Likewise. 6463 (__arm_vcmlaq_m_f32): Likewise. 6464 (__arm_vcmlaq_m_f16): Likewise. 6465 (__arm_vcmlaq_rot180_m_f32): Likewise. 6466 (__arm_vcmlaq_rot180_m_f16): Likewise. 6467 (__arm_vcmlaq_rot270_m_f32): Likewise. 6468 (__arm_vcmlaq_rot270_m_f16): Likewise. 6469 (__arm_vcmlaq_rot90_m_f32): Likewise. 6470 (__arm_vcmlaq_rot90_m_f16): Likewise. 6471 (__arm_vcmulq_m_f32): Likewise. 6472 (__arm_vcmulq_m_f16): Likewise. 6473 (__arm_vcmulq_rot180_m_f32): Define intrinsic. 6474 (__arm_vcmulq_rot180_m_f16): Likewise. 6475 (__arm_vcmulq_rot270_m_f32): Likewise. 6476 (__arm_vcmulq_rot270_m_f16): Likewise. 6477 (__arm_vcmulq_rot90_m_f32): Likewise. 6478 (__arm_vcmulq_rot90_m_f16): Likewise. 6479 (__arm_vcvtq_m_n_s32_f32): Likewise. 6480 (__arm_vcvtq_m_n_s16_f16): Likewise. 6481 (__arm_vcvtq_m_n_u32_f32): Likewise. 6482 (__arm_vcvtq_m_n_u16_f16): Likewise. 6483 (__arm_veorq_m_f32): Likewise. 6484 (__arm_veorq_m_f16): Likewise. 6485 (__arm_vfmaq_m_f32): Likewise. 6486 (__arm_vfmaq_m_f16): Likewise. 6487 (__arm_vfmaq_m_n_f32): Likewise. 6488 (__arm_vfmaq_m_n_f16): Likewise. 6489 (__arm_vfmasq_m_n_f32): Likewise. 6490 (__arm_vfmasq_m_n_f16): Likewise. 6491 (__arm_vfmsq_m_f32): Likewise. 6492 (__arm_vfmsq_m_f16): Likewise. 6493 (__arm_vmaxnmq_m_f32): Likewise. 6494 (__arm_vmaxnmq_m_f16): Likewise. 6495 (__arm_vminnmq_m_f32): Likewise. 6496 (__arm_vminnmq_m_f16): Likewise. 6497 (__arm_vmulq_m_f32): Likewise. 6498 (__arm_vmulq_m_f16): Likewise. 6499 (__arm_vmulq_m_n_f32): Likewise. 6500 (__arm_vmulq_m_n_f16): Likewise. 6501 (__arm_vornq_m_f32): Likewise. 6502 (__arm_vornq_m_f16): Likewise. 6503 (__arm_vorrq_m_f32): Likewise. 6504 (__arm_vorrq_m_f16): Likewise. 6505 (__arm_vsubq_m_f32): Likewise. 6506 (__arm_vsubq_m_f16): Likewise. 6507 (__arm_vsubq_m_n_f32): Likewise. 6508 (__arm_vsubq_m_n_f16): Likewise. 6509 (vabdq_m): Define polymorphic variant. 6510 (vaddq_m): Likewise. 6511 (vaddq_m_n): Likewise. 6512 (vandq_m): Likewise. 6513 (vbicq_m): Likewise. 6514 (vbrsrq_m_n): Likewise. 6515 (vcaddq_rot270_m): Likewise. 6516 (vcaddq_rot90_m): Likewise. 6517 (vcmlaq_m): Likewise. 6518 (vcmlaq_rot180_m): Likewise. 6519 (vcmlaq_rot270_m): Likewise. 6520 (vcmlaq_rot90_m): Likewise. 6521 (vcmulq_m): Likewise. 6522 (vcmulq_rot180_m): Likewise. 6523 (vcmulq_rot270_m): Likewise. 6524 (vcmulq_rot90_m): Likewise. 6525 (veorq_m): Likewise. 6526 (vfmaq_m): Likewise. 6527 (vfmaq_m_n): Likewise. 6528 (vfmasq_m_n): Likewise. 6529 (vfmsq_m): Likewise. 6530 (vmaxnmq_m): Likewise. 6531 (vminnmq_m): Likewise. 6532 (vmulq_m): Likewise. 6533 (vmulq_m_n): Likewise. 6534 (vornq_m): Likewise. 6535 (vsubq_m): Likewise. 6536 (vsubq_m_n): Likewise. 6537 (vorrq_m): Likewise. 6538 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use 6539 builtin qualifier. 6540 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise. 6541 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise. 6542 * config/arm/mve.md (mve_vabdq_m_f<mode>): Define RTL pattern. 6543 (mve_vaddq_m_f<mode>): Likewise. 6544 (mve_vaddq_m_n_f<mode>): Likewise. 6545 (mve_vandq_m_f<mode>): Likewise. 6546 (mve_vbicq_m_f<mode>): Likewise. 6547 (mve_vbrsrq_m_n_f<mode>): Likewise. 6548 (mve_vcaddq_rot270_m_f<mode>): Likewise. 6549 (mve_vcaddq_rot90_m_f<mode>): Likewise. 6550 (mve_vcmlaq_m_f<mode>): Likewise. 6551 (mve_vcmlaq_rot180_m_f<mode>): Likewise. 6552 (mve_vcmlaq_rot270_m_f<mode>): Likewise. 6553 (mve_vcmlaq_rot90_m_f<mode>): Likewise. 6554 (mve_vcmulq_m_f<mode>): Likewise. 6555 (mve_vcmulq_rot180_m_f<mode>): Likewise. 6556 (mve_vcmulq_rot270_m_f<mode>): Likewise. 6557 (mve_vcmulq_rot90_m_f<mode>): Likewise. 6558 (mve_veorq_m_f<mode>): Likewise. 6559 (mve_vfmaq_m_f<mode>): Likewise. 6560 (mve_vfmaq_m_n_f<mode>): Likewise. 6561 (mve_vfmasq_m_n_f<mode>): Likewise. 6562 (mve_vfmsq_m_f<mode>): Likewise. 6563 (mve_vmaxnmq_m_f<mode>): Likewise. 6564 (mve_vminnmq_m_f<mode>): Likewise. 6565 (mve_vmulq_m_f<mode>): Likewise. 6566 (mve_vmulq_m_n_f<mode>): Likewise. 6567 (mve_vornq_m_f<mode>): Likewise. 6568 (mve_vorrq_m_f<mode>): Likewise. 6569 (mve_vsubq_m_f<mode>): Likewise. 6570 (mve_vsubq_m_n_f<mode>): Likewise. 6571 65722020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> 6573 Mihail Ionescu <mihail.ionescu@arm.com> 6574 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 6575 6576 * config/arm/arm-protos.h (arm_mve_immediate_check): 6577 * config/arm/arm.c (arm_mve_immediate_check): Define fuction to check 6578 mode and interger value. 6579 * config/arm/arm_mve.h (vmlaldavaq_p_s32): Define macro. 6580 (vmlaldavaq_p_s16): Likewise. 6581 (vmlaldavaq_p_u32): Likewise. 6582 (vmlaldavaq_p_u16): Likewise. 6583 (vmlaldavaxq_p_s32): Likewise. 6584 (vmlaldavaxq_p_s16): Likewise. 6585 (vmlaldavaxq_p_u32): Likewise. 6586 (vmlaldavaxq_p_u16): Likewise. 6587 (vmlsldavaq_p_s32): Likewise. 6588 (vmlsldavaq_p_s16): Likewise. 6589 (vmlsldavaxq_p_s32): Likewise. 6590 (vmlsldavaxq_p_s16): Likewise. 6591 (vmullbq_poly_m_p8): Likewise. 6592 (vmullbq_poly_m_p16): Likewise. 6593 (vmulltq_poly_m_p8): Likewise. 6594 (vmulltq_poly_m_p16): Likewise. 6595 (vqdmullbq_m_n_s32): Likewise. 6596 (vqdmullbq_m_n_s16): Likewise. 6597 (vqdmullbq_m_s32): Likewise. 6598 (vqdmullbq_m_s16): Likewise. 6599 (vqdmulltq_m_n_s32): Likewise. 6600 (vqdmulltq_m_n_s16): Likewise. 6601 (vqdmulltq_m_s32): Likewise. 6602 (vqdmulltq_m_s16): Likewise. 6603 (vqrshrnbq_m_n_s32): Likewise. 6604 (vqrshrnbq_m_n_s16): Likewise. 6605 (vqrshrnbq_m_n_u32): Likewise. 6606 (vqrshrnbq_m_n_u16): Likewise. 6607 (vqrshrntq_m_n_s32): Likewise. 6608 (vqrshrntq_m_n_s16): Likewise. 6609 (vqrshrntq_m_n_u32): Likewise. 6610 (vqrshrntq_m_n_u16): Likewise. 6611 (vqrshrunbq_m_n_s32): Likewise. 6612 (vqrshrunbq_m_n_s16): Likewise. 6613 (vqrshruntq_m_n_s32): Likewise. 6614 (vqrshruntq_m_n_s16): Likewise. 6615 (vqshrnbq_m_n_s32): Likewise. 6616 (vqshrnbq_m_n_s16): Likewise. 6617 (vqshrnbq_m_n_u32): Likewise. 6618 (vqshrnbq_m_n_u16): Likewise. 6619 (vqshrntq_m_n_s32): Likewise. 6620 (vqshrntq_m_n_s16): Likewise. 6621 (vqshrntq_m_n_u32): Likewise. 6622 (vqshrntq_m_n_u16): Likewise. 6623 (vqshrunbq_m_n_s32): Likewise. 6624 (vqshrunbq_m_n_s16): Likewise. 6625 (vqshruntq_m_n_s32): Likewise. 6626 (vqshruntq_m_n_s16): Likewise. 6627 (vrmlaldavhaq_p_s32): Likewise. 6628 (vrmlaldavhaq_p_u32): Likewise. 6629 (vrmlaldavhaxq_p_s32): Likewise. 6630 (vrmlsldavhaq_p_s32): Likewise. 6631 (vrmlsldavhaxq_p_s32): Likewise. 6632 (vrshrnbq_m_n_s32): Likewise. 6633 (vrshrnbq_m_n_s16): Likewise. 6634 (vrshrnbq_m_n_u32): Likewise. 6635 (vrshrnbq_m_n_u16): Likewise. 6636 (vrshrntq_m_n_s32): Likewise. 6637 (vrshrntq_m_n_s16): Likewise. 6638 (vrshrntq_m_n_u32): Likewise. 6639 (vrshrntq_m_n_u16): Likewise. 6640 (vshllbq_m_n_s8): Likewise. 6641 (vshllbq_m_n_s16): Likewise. 6642 (vshllbq_m_n_u8): Likewise. 6643 (vshllbq_m_n_u16): Likewise. 6644 (vshlltq_m_n_s8): Likewise. 6645 (vshlltq_m_n_s16): Likewise. 6646 (vshlltq_m_n_u8): Likewise. 6647 (vshlltq_m_n_u16): Likewise. 6648 (vshrnbq_m_n_s32): Likewise. 6649 (vshrnbq_m_n_s16): Likewise. 6650 (vshrnbq_m_n_u32): Likewise. 6651 (vshrnbq_m_n_u16): Likewise. 6652 (vshrntq_m_n_s32): Likewise. 6653 (vshrntq_m_n_s16): Likewise. 6654 (vshrntq_m_n_u32): Likewise. 6655 (vshrntq_m_n_u16): Likewise. 6656 (__arm_vmlaldavaq_p_s32): Define intrinsic. 6657 (__arm_vmlaldavaq_p_s16): Likewise. 6658 (__arm_vmlaldavaq_p_u32): Likewise. 6659 (__arm_vmlaldavaq_p_u16): Likewise. 6660 (__arm_vmlaldavaxq_p_s32): Likewise. 6661 (__arm_vmlaldavaxq_p_s16): Likewise. 6662 (__arm_vmlaldavaxq_p_u32): Likewise. 6663 (__arm_vmlaldavaxq_p_u16): Likewise. 6664 (__arm_vmlsldavaq_p_s32): Likewise. 6665 (__arm_vmlsldavaq_p_s16): Likewise. 6666 (__arm_vmlsldavaxq_p_s32): Likewise. 6667 (__arm_vmlsldavaxq_p_s16): Likewise. 6668 (__arm_vmullbq_poly_m_p8): Likewise. 6669 (__arm_vmullbq_poly_m_p16): Likewise. 6670 (__arm_vmulltq_poly_m_p8): Likewise. 6671 (__arm_vmulltq_poly_m_p16): Likewise. 6672 (__arm_vqdmullbq_m_n_s32): Likewise. 6673 (__arm_vqdmullbq_m_n_s16): Likewise. 6674 (__arm_vqdmullbq_m_s32): Likewise. 6675 (__arm_vqdmullbq_m_s16): Likewise. 6676 (__arm_vqdmulltq_m_n_s32): Likewise. 6677 (__arm_vqdmulltq_m_n_s16): Likewise. 6678 (__arm_vqdmulltq_m_s32): Likewise. 6679 (__arm_vqdmulltq_m_s16): Likewise. 6680 (__arm_vqrshrnbq_m_n_s32): Likewise. 6681 (__arm_vqrshrnbq_m_n_s16): Likewise. 6682 (__arm_vqrshrnbq_m_n_u32): Likewise. 6683 (__arm_vqrshrnbq_m_n_u16): Likewise. 6684 (__arm_vqrshrntq_m_n_s32): Likewise. 6685 (__arm_vqrshrntq_m_n_s16): Likewise. 6686 (__arm_vqrshrntq_m_n_u32): Likewise. 6687 (__arm_vqrshrntq_m_n_u16): Likewise. 6688 (__arm_vqrshrunbq_m_n_s32): Likewise. 6689 (__arm_vqrshrunbq_m_n_s16): Likewise. 6690 (__arm_vqrshruntq_m_n_s32): Likewise. 6691 (__arm_vqrshruntq_m_n_s16): Likewise. 6692 (__arm_vqshrnbq_m_n_s32): Likewise. 6693 (__arm_vqshrnbq_m_n_s16): Likewise. 6694 (__arm_vqshrnbq_m_n_u32): Likewise. 6695 (__arm_vqshrnbq_m_n_u16): Likewise. 6696 (__arm_vqshrntq_m_n_s32): Likewise. 6697 (__arm_vqshrntq_m_n_s16): Likewise. 6698 (__arm_vqshrntq_m_n_u32): Likewise. 6699 (__arm_vqshrntq_m_n_u16): Likewise. 6700 (__arm_vqshrunbq_m_n_s32): Likewise. 6701 (__arm_vqshrunbq_m_n_s16): Likewise. 6702 (__arm_vqshruntq_m_n_s32): Likewise. 6703 (__arm_vqshruntq_m_n_s16): Likewise. 6704 (__arm_vrmlaldavhaq_p_s32): Likewise. 6705 (__arm_vrmlaldavhaq_p_u32): Likewise. 6706 (__arm_vrmlaldavhaxq_p_s32): Likewise. 6707 (__arm_vrmlsldavhaq_p_s32): Likewise. 6708 (__arm_vrmlsldavhaxq_p_s32): Likewise. 6709 (__arm_vrshrnbq_m_n_s32): Likewise. 6710 (__arm_vrshrnbq_m_n_s16): Likewise. 6711 (__arm_vrshrnbq_m_n_u32): Likewise. 6712 (__arm_vrshrnbq_m_n_u16): Likewise. 6713 (__arm_vrshrntq_m_n_s32): Likewise. 6714 (__arm_vrshrntq_m_n_s16): Likewise. 6715 (__arm_vrshrntq_m_n_u32): Likewise. 6716 (__arm_vrshrntq_m_n_u16): Likewise. 6717 (__arm_vshllbq_m_n_s8): Likewise. 6718 (__arm_vshllbq_m_n_s16): Likewise. 6719 (__arm_vshllbq_m_n_u8): Likewise. 6720 (__arm_vshllbq_m_n_u16): Likewise. 6721 (__arm_vshlltq_m_n_s8): Likewise. 6722 (__arm_vshlltq_m_n_s16): Likewise. 6723 (__arm_vshlltq_m_n_u8): Likewise. 6724 (__arm_vshlltq_m_n_u16): Likewise. 6725 (__arm_vshrnbq_m_n_s32): Likewise. 6726 (__arm_vshrnbq_m_n_s16): Likewise. 6727 (__arm_vshrnbq_m_n_u32): Likewise. 6728 (__arm_vshrnbq_m_n_u16): Likewise. 6729 (__arm_vshrntq_m_n_s32): Likewise. 6730 (__arm_vshrntq_m_n_s16): Likewise. 6731 (__arm_vshrntq_m_n_u32): Likewise. 6732 (__arm_vshrntq_m_n_u16): Likewise. 6733 (vmullbq_poly_m): Define polymorphic variant. 6734 (vmulltq_poly_m): Likewise. 6735 (vshllbq_m): Likewise. 6736 (vshrntq_m_n): Likewise. 6737 (vshrnbq_m_n): Likewise. 6738 (vshlltq_m_n): Likewise. 6739 (vshllbq_m_n): Likewise. 6740 (vrshrntq_m_n): Likewise. 6741 (vrshrnbq_m_n): Likewise. 6742 (vqshruntq_m_n): Likewise. 6743 (vqshrunbq_m_n): Likewise. 6744 (vqdmullbq_m_n): Likewise. 6745 (vqdmullbq_m): Likewise. 6746 (vqdmulltq_m_n): Likewise. 6747 (vqdmulltq_m): Likewise. 6748 (vqrshrnbq_m_n): Likewise. 6749 (vqrshrntq_m_n): Likewise. 6750 (vqrshrunbq_m_n): Likewise. 6751 (vqrshruntq_m_n): Likewise. 6752 (vqshrnbq_m_n): Likewise. 6753 (vqshrntq_m_n): Likewise. 6754 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use 6755 builtin qualifiers. 6756 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise. 6757 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise. 6758 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise. 6759 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise. 6760 * config/arm/mve.md (VMLALDAVAQ_P): Define iterator. 6761 (VMLALDAVAXQ_P): Likewise. 6762 (VQRSHRNBQ_M_N): Likewise. 6763 (VQRSHRNTQ_M_N): Likewise. 6764 (VQSHRNBQ_M_N): Likewise. 6765 (VQSHRNTQ_M_N): Likewise. 6766 (VRSHRNBQ_M_N): Likewise. 6767 (VRSHRNTQ_M_N): Likewise. 6768 (VSHLLBQ_M_N): Likewise. 6769 (VSHLLTQ_M_N): Likewise. 6770 (VSHRNBQ_M_N): Likewise. 6771 (VSHRNTQ_M_N): Likewise. 6772 (mve_vmlaldavaq_p_<supf><mode>): Define RTL pattern. 6773 (mve_vmlaldavaxq_p_<supf><mode>): Likewise. 6774 (mve_vqrshrnbq_m_n_<supf><mode>): Likewise. 6775 (mve_vqrshrntq_m_n_<supf><mode>): Likewise. 6776 (mve_vqshrnbq_m_n_<supf><mode>): Likewise. 6777 (mve_vqshrntq_m_n_<supf><mode>): Likewise. 6778 (mve_vrmlaldavhaq_p_sv4si): Likewise. 6779 (mve_vrshrnbq_m_n_<supf><mode>): Likewise. 6780 (mve_vrshrntq_m_n_<supf><mode>): Likewise. 6781 (mve_vshllbq_m_n_<supf><mode>): Likewise. 6782 (mve_vshlltq_m_n_<supf><mode>): Likewise. 6783 (mve_vshrnbq_m_n_<supf><mode>): Likewise. 6784 (mve_vshrntq_m_n_<supf><mode>): Likewise. 6785 (mve_vmlsldavaq_p_s<mode>): Likewise. 6786 (mve_vmlsldavaxq_p_s<mode>): Likewise. 6787 (mve_vmullbq_poly_m_p<mode>): Likewise. 6788 (mve_vmulltq_poly_m_p<mode>): Likewise. 6789 (mve_vqdmullbq_m_n_s<mode>): Likewise. 6790 (mve_vqdmullbq_m_s<mode>): Likewise. 6791 (mve_vqdmulltq_m_n_s<mode>): Likewise. 6792 (mve_vqdmulltq_m_s<mode>): Likewise. 6793 (mve_vqrshrunbq_m_n_s<mode>): Likewise. 6794 (mve_vqrshruntq_m_n_s<mode>): Likewise. 6795 (mve_vqshrunbq_m_n_s<mode>): Likewise. 6796 (mve_vqshruntq_m_n_s<mode>): Likewise. 6797 (mve_vrmlaldavhaq_p_uv4si): Likewise. 6798 (mve_vrmlaldavhaxq_p_sv4si): Likewise. 6799 (mve_vrmlsldavhaq_p_sv4si): Likewise. 6800 (mve_vrmlsldavhaxq_p_sv4si): Likewise. 6801 68022020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> 6803 Mihail Ionescu <mihail.ionescu@arm.com> 6804 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 6805 6806 * config/arm/arm_mve.h (vabdq_m_s8): Define macro. 6807 (vabdq_m_s32): Likewise. 6808 (vabdq_m_s16): Likewise. 6809 (vabdq_m_u8): Likewise. 6810 (vabdq_m_u32): Likewise. 6811 (vabdq_m_u16): Likewise. 6812 (vaddq_m_n_s8): Likewise. 6813 (vaddq_m_n_s32): Likewise. 6814 (vaddq_m_n_s16): Likewise. 6815 (vaddq_m_n_u8): Likewise. 6816 (vaddq_m_n_u32): Likewise. 6817 (vaddq_m_n_u16): Likewise. 6818 (vaddq_m_s8): Likewise. 6819 (vaddq_m_s32): Likewise. 6820 (vaddq_m_s16): Likewise. 6821 (vaddq_m_u8): Likewise. 6822 (vaddq_m_u32): Likewise. 6823 (vaddq_m_u16): Likewise. 6824 (vandq_m_s8): Likewise. 6825 (vandq_m_s32): Likewise. 6826 (vandq_m_s16): Likewise. 6827 (vandq_m_u8): Likewise. 6828 (vandq_m_u32): Likewise. 6829 (vandq_m_u16): Likewise. 6830 (vbicq_m_s8): Likewise. 6831 (vbicq_m_s32): Likewise. 6832 (vbicq_m_s16): Likewise. 6833 (vbicq_m_u8): Likewise. 6834 (vbicq_m_u32): Likewise. 6835 (vbicq_m_u16): Likewise. 6836 (vbrsrq_m_n_s8): Likewise. 6837 (vbrsrq_m_n_s32): Likewise. 6838 (vbrsrq_m_n_s16): Likewise. 6839 (vbrsrq_m_n_u8): Likewise. 6840 (vbrsrq_m_n_u32): Likewise. 6841 (vbrsrq_m_n_u16): Likewise. 6842 (vcaddq_rot270_m_s8): Likewise. 6843 (vcaddq_rot270_m_s32): Likewise. 6844 (vcaddq_rot270_m_s16): Likewise. 6845 (vcaddq_rot270_m_u8): Likewise. 6846 (vcaddq_rot270_m_u32): Likewise. 6847 (vcaddq_rot270_m_u16): Likewise. 6848 (vcaddq_rot90_m_s8): Likewise. 6849 (vcaddq_rot90_m_s32): Likewise. 6850 (vcaddq_rot90_m_s16): Likewise. 6851 (vcaddq_rot90_m_u8): Likewise. 6852 (vcaddq_rot90_m_u32): Likewise. 6853 (vcaddq_rot90_m_u16): Likewise. 6854 (veorq_m_s8): Likewise. 6855 (veorq_m_s32): Likewise. 6856 (veorq_m_s16): Likewise. 6857 (veorq_m_u8): Likewise. 6858 (veorq_m_u32): Likewise. 6859 (veorq_m_u16): Likewise. 6860 (vhaddq_m_n_s8): Likewise. 6861 (vhaddq_m_n_s32): Likewise. 6862 (vhaddq_m_n_s16): Likewise. 6863 (vhaddq_m_n_u8): Likewise. 6864 (vhaddq_m_n_u32): Likewise. 6865 (vhaddq_m_n_u16): Likewise. 6866 (vhaddq_m_s8): Likewise. 6867 (vhaddq_m_s32): Likewise. 6868 (vhaddq_m_s16): Likewise. 6869 (vhaddq_m_u8): Likewise. 6870 (vhaddq_m_u32): Likewise. 6871 (vhaddq_m_u16): Likewise. 6872 (vhcaddq_rot270_m_s8): Likewise. 6873 (vhcaddq_rot270_m_s32): Likewise. 6874 (vhcaddq_rot270_m_s16): Likewise. 6875 (vhcaddq_rot90_m_s8): Likewise. 6876 (vhcaddq_rot90_m_s32): Likewise. 6877 (vhcaddq_rot90_m_s16): Likewise. 6878 (vhsubq_m_n_s8): Likewise. 6879 (vhsubq_m_n_s32): Likewise. 6880 (vhsubq_m_n_s16): Likewise. 6881 (vhsubq_m_n_u8): Likewise. 6882 (vhsubq_m_n_u32): Likewise. 6883 (vhsubq_m_n_u16): Likewise. 6884 (vhsubq_m_s8): Likewise. 6885 (vhsubq_m_s32): Likewise. 6886 (vhsubq_m_s16): Likewise. 6887 (vhsubq_m_u8): Likewise. 6888 (vhsubq_m_u32): Likewise. 6889 (vhsubq_m_u16): Likewise. 6890 (vmaxq_m_s8): Likewise. 6891 (vmaxq_m_s32): Likewise. 6892 (vmaxq_m_s16): Likewise. 6893 (vmaxq_m_u8): Likewise. 6894 (vmaxq_m_u32): Likewise. 6895 (vmaxq_m_u16): Likewise. 6896 (vminq_m_s8): Likewise. 6897 (vminq_m_s32): Likewise. 6898 (vminq_m_s16): Likewise. 6899 (vminq_m_u8): Likewise. 6900 (vminq_m_u32): Likewise. 6901 (vminq_m_u16): Likewise. 6902 (vmladavaq_p_s8): Likewise. 6903 (vmladavaq_p_s32): Likewise. 6904 (vmladavaq_p_s16): Likewise. 6905 (vmladavaq_p_u8): Likewise. 6906 (vmladavaq_p_u32): Likewise. 6907 (vmladavaq_p_u16): Likewise. 6908 (vmladavaxq_p_s8): Likewise. 6909 (vmladavaxq_p_s32): Likewise. 6910 (vmladavaxq_p_s16): Likewise. 6911 (vmlaq_m_n_s8): Likewise. 6912 (vmlaq_m_n_s32): Likewise. 6913 (vmlaq_m_n_s16): Likewise. 6914 (vmlaq_m_n_u8): Likewise. 6915 (vmlaq_m_n_u32): Likewise. 6916 (vmlaq_m_n_u16): Likewise. 6917 (vmlasq_m_n_s8): Likewise. 6918 (vmlasq_m_n_s32): Likewise. 6919 (vmlasq_m_n_s16): Likewise. 6920 (vmlasq_m_n_u8): Likewise. 6921 (vmlasq_m_n_u32): Likewise. 6922 (vmlasq_m_n_u16): Likewise. 6923 (vmlsdavaq_p_s8): Likewise. 6924 (vmlsdavaq_p_s32): Likewise. 6925 (vmlsdavaq_p_s16): Likewise. 6926 (vmlsdavaxq_p_s8): Likewise. 6927 (vmlsdavaxq_p_s32): Likewise. 6928 (vmlsdavaxq_p_s16): Likewise. 6929 (vmulhq_m_s8): Likewise. 6930 (vmulhq_m_s32): Likewise. 6931 (vmulhq_m_s16): Likewise. 6932 (vmulhq_m_u8): Likewise. 6933 (vmulhq_m_u32): Likewise. 6934 (vmulhq_m_u16): Likewise. 6935 (vmullbq_int_m_s8): Likewise. 6936 (vmullbq_int_m_s32): Likewise. 6937 (vmullbq_int_m_s16): Likewise. 6938 (vmullbq_int_m_u8): Likewise. 6939 (vmullbq_int_m_u32): Likewise. 6940 (vmullbq_int_m_u16): Likewise. 6941 (vmulltq_int_m_s8): Likewise. 6942 (vmulltq_int_m_s32): Likewise. 6943 (vmulltq_int_m_s16): Likewise. 6944 (vmulltq_int_m_u8): Likewise. 6945 (vmulltq_int_m_u32): Likewise. 6946 (vmulltq_int_m_u16): Likewise. 6947 (vmulq_m_n_s8): Likewise. 6948 (vmulq_m_n_s32): Likewise. 6949 (vmulq_m_n_s16): Likewise. 6950 (vmulq_m_n_u8): Likewise. 6951 (vmulq_m_n_u32): Likewise. 6952 (vmulq_m_n_u16): Likewise. 6953 (vmulq_m_s8): Likewise. 6954 (vmulq_m_s32): Likewise. 6955 (vmulq_m_s16): Likewise. 6956 (vmulq_m_u8): Likewise. 6957 (vmulq_m_u32): Likewise. 6958 (vmulq_m_u16): Likewise. 6959 (vornq_m_s8): Likewise. 6960 (vornq_m_s32): Likewise. 6961 (vornq_m_s16): Likewise. 6962 (vornq_m_u8): Likewise. 6963 (vornq_m_u32): Likewise. 6964 (vornq_m_u16): Likewise. 6965 (vorrq_m_s8): Likewise. 6966 (vorrq_m_s32): Likewise. 6967 (vorrq_m_s16): Likewise. 6968 (vorrq_m_u8): Likewise. 6969 (vorrq_m_u32): Likewise. 6970 (vorrq_m_u16): Likewise. 6971 (vqaddq_m_n_s8): Likewise. 6972 (vqaddq_m_n_s32): Likewise. 6973 (vqaddq_m_n_s16): Likewise. 6974 (vqaddq_m_n_u8): Likewise. 6975 (vqaddq_m_n_u32): Likewise. 6976 (vqaddq_m_n_u16): Likewise. 6977 (vqaddq_m_s8): Likewise. 6978 (vqaddq_m_s32): Likewise. 6979 (vqaddq_m_s16): Likewise. 6980 (vqaddq_m_u8): Likewise. 6981 (vqaddq_m_u32): Likewise. 6982 (vqaddq_m_u16): Likewise. 6983 (vqdmladhq_m_s8): Likewise. 6984 (vqdmladhq_m_s32): Likewise. 6985 (vqdmladhq_m_s16): Likewise. 6986 (vqdmladhxq_m_s8): Likewise. 6987 (vqdmladhxq_m_s32): Likewise. 6988 (vqdmladhxq_m_s16): Likewise. 6989 (vqdmlahq_m_n_s8): Likewise. 6990 (vqdmlahq_m_n_s32): Likewise. 6991 (vqdmlahq_m_n_s16): Likewise. 6992 (vqdmlahq_m_n_u8): Likewise. 6993 (vqdmlahq_m_n_u32): Likewise. 6994 (vqdmlahq_m_n_u16): Likewise. 6995 (vqdmlsdhq_m_s8): Likewise. 6996 (vqdmlsdhq_m_s32): Likewise. 6997 (vqdmlsdhq_m_s16): Likewise. 6998 (vqdmlsdhxq_m_s8): Likewise. 6999 (vqdmlsdhxq_m_s32): Likewise. 7000 (vqdmlsdhxq_m_s16): Likewise. 7001 (vqdmulhq_m_n_s8): Likewise. 7002 (vqdmulhq_m_n_s32): Likewise. 7003 (vqdmulhq_m_n_s16): Likewise. 7004 (vqdmulhq_m_s8): Likewise. 7005 (vqdmulhq_m_s32): Likewise. 7006 (vqdmulhq_m_s16): Likewise. 7007 (vqrdmladhq_m_s8): Likewise. 7008 (vqrdmladhq_m_s32): Likewise. 7009 (vqrdmladhq_m_s16): Likewise. 7010 (vqrdmladhxq_m_s8): Likewise. 7011 (vqrdmladhxq_m_s32): Likewise. 7012 (vqrdmladhxq_m_s16): Likewise. 7013 (vqrdmlahq_m_n_s8): Likewise. 7014 (vqrdmlahq_m_n_s32): Likewise. 7015 (vqrdmlahq_m_n_s16): Likewise. 7016 (vqrdmlahq_m_n_u8): Likewise. 7017 (vqrdmlahq_m_n_u32): Likewise. 7018 (vqrdmlahq_m_n_u16): Likewise. 7019 (vqrdmlashq_m_n_s8): Likewise. 7020 (vqrdmlashq_m_n_s32): Likewise. 7021 (vqrdmlashq_m_n_s16): Likewise. 7022 (vqrdmlashq_m_n_u8): Likewise. 7023 (vqrdmlashq_m_n_u32): Likewise. 7024 (vqrdmlashq_m_n_u16): Likewise. 7025 (vqrdmlsdhq_m_s8): Likewise. 7026 (vqrdmlsdhq_m_s32): Likewise. 7027 (vqrdmlsdhq_m_s16): Likewise. 7028 (vqrdmlsdhxq_m_s8): Likewise. 7029 (vqrdmlsdhxq_m_s32): Likewise. 7030 (vqrdmlsdhxq_m_s16): Likewise. 7031 (vqrdmulhq_m_n_s8): Likewise. 7032 (vqrdmulhq_m_n_s32): Likewise. 7033 (vqrdmulhq_m_n_s16): Likewise. 7034 (vqrdmulhq_m_s8): Likewise. 7035 (vqrdmulhq_m_s32): Likewise. 7036 (vqrdmulhq_m_s16): Likewise. 7037 (vqrshlq_m_s8): Likewise. 7038 (vqrshlq_m_s32): Likewise. 7039 (vqrshlq_m_s16): Likewise. 7040 (vqrshlq_m_u8): Likewise. 7041 (vqrshlq_m_u32): Likewise. 7042 (vqrshlq_m_u16): Likewise. 7043 (vqshlq_m_n_s8): Likewise. 7044 (vqshlq_m_n_s32): Likewise. 7045 (vqshlq_m_n_s16): Likewise. 7046 (vqshlq_m_n_u8): Likewise. 7047 (vqshlq_m_n_u32): Likewise. 7048 (vqshlq_m_n_u16): Likewise. 7049 (vqshlq_m_s8): Likewise. 7050 (vqshlq_m_s32): Likewise. 7051 (vqshlq_m_s16): Likewise. 7052 (vqshlq_m_u8): Likewise. 7053 (vqshlq_m_u32): Likewise. 7054 (vqshlq_m_u16): Likewise. 7055 (vqsubq_m_n_s8): Likewise. 7056 (vqsubq_m_n_s32): Likewise. 7057 (vqsubq_m_n_s16): Likewise. 7058 (vqsubq_m_n_u8): Likewise. 7059 (vqsubq_m_n_u32): Likewise. 7060 (vqsubq_m_n_u16): Likewise. 7061 (vqsubq_m_s8): Likewise. 7062 (vqsubq_m_s32): Likewise. 7063 (vqsubq_m_s16): Likewise. 7064 (vqsubq_m_u8): Likewise. 7065 (vqsubq_m_u32): Likewise. 7066 (vqsubq_m_u16): Likewise. 7067 (vrhaddq_m_s8): Likewise. 7068 (vrhaddq_m_s32): Likewise. 7069 (vrhaddq_m_s16): Likewise. 7070 (vrhaddq_m_u8): Likewise. 7071 (vrhaddq_m_u32): Likewise. 7072 (vrhaddq_m_u16): Likewise. 7073 (vrmulhq_m_s8): Likewise. 7074 (vrmulhq_m_s32): Likewise. 7075 (vrmulhq_m_s16): Likewise. 7076 (vrmulhq_m_u8): Likewise. 7077 (vrmulhq_m_u32): Likewise. 7078 (vrmulhq_m_u16): Likewise. 7079 (vrshlq_m_s8): Likewise. 7080 (vrshlq_m_s32): Likewise. 7081 (vrshlq_m_s16): Likewise. 7082 (vrshlq_m_u8): Likewise. 7083 (vrshlq_m_u32): Likewise. 7084 (vrshlq_m_u16): Likewise. 7085 (vrshrq_m_n_s8): Likewise. 7086 (vrshrq_m_n_s32): Likewise. 7087 (vrshrq_m_n_s16): Likewise. 7088 (vrshrq_m_n_u8): Likewise. 7089 (vrshrq_m_n_u32): Likewise. 7090 (vrshrq_m_n_u16): Likewise. 7091 (vshlq_m_n_s8): Likewise. 7092 (vshlq_m_n_s32): Likewise. 7093 (vshlq_m_n_s16): Likewise. 7094 (vshlq_m_n_u8): Likewise. 7095 (vshlq_m_n_u32): Likewise. 7096 (vshlq_m_n_u16): Likewise. 7097 (vshrq_m_n_s8): Likewise. 7098 (vshrq_m_n_s32): Likewise. 7099 (vshrq_m_n_s16): Likewise. 7100 (vshrq_m_n_u8): Likewise. 7101 (vshrq_m_n_u32): Likewise. 7102 (vshrq_m_n_u16): Likewise. 7103 (vsliq_m_n_s8): Likewise. 7104 (vsliq_m_n_s32): Likewise. 7105 (vsliq_m_n_s16): Likewise. 7106 (vsliq_m_n_u8): Likewise. 7107 (vsliq_m_n_u32): Likewise. 7108 (vsliq_m_n_u16): Likewise. 7109 (vsubq_m_n_s8): Likewise. 7110 (vsubq_m_n_s32): Likewise. 7111 (vsubq_m_n_s16): Likewise. 7112 (vsubq_m_n_u8): Likewise. 7113 (vsubq_m_n_u32): Likewise. 7114 (vsubq_m_n_u16): Likewise. 7115 (__arm_vabdq_m_s8): Define intrinsic. 7116 (__arm_vabdq_m_s32): Likewise. 7117 (__arm_vabdq_m_s16): Likewise. 7118 (__arm_vabdq_m_u8): Likewise. 7119 (__arm_vabdq_m_u32): Likewise. 7120 (__arm_vabdq_m_u16): Likewise. 7121 (__arm_vaddq_m_n_s8): Likewise. 7122 (__arm_vaddq_m_n_s32): Likewise. 7123 (__arm_vaddq_m_n_s16): Likewise. 7124 (__arm_vaddq_m_n_u8): Likewise. 7125 (__arm_vaddq_m_n_u32): Likewise. 7126 (__arm_vaddq_m_n_u16): Likewise. 7127 (__arm_vaddq_m_s8): Likewise. 7128 (__arm_vaddq_m_s32): Likewise. 7129 (__arm_vaddq_m_s16): Likewise. 7130 (__arm_vaddq_m_u8): Likewise. 7131 (__arm_vaddq_m_u32): Likewise. 7132 (__arm_vaddq_m_u16): Likewise. 7133 (__arm_vandq_m_s8): Likewise. 7134 (__arm_vandq_m_s32): Likewise. 7135 (__arm_vandq_m_s16): Likewise. 7136 (__arm_vandq_m_u8): Likewise. 7137 (__arm_vandq_m_u32): Likewise. 7138 (__arm_vandq_m_u16): Likewise. 7139 (__arm_vbicq_m_s8): Likewise. 7140 (__arm_vbicq_m_s32): Likewise. 7141 (__arm_vbicq_m_s16): Likewise. 7142 (__arm_vbicq_m_u8): Likewise. 7143 (__arm_vbicq_m_u32): Likewise. 7144 (__arm_vbicq_m_u16): Likewise. 7145 (__arm_vbrsrq_m_n_s8): Likewise. 7146 (__arm_vbrsrq_m_n_s32): Likewise. 7147 (__arm_vbrsrq_m_n_s16): Likewise. 7148 (__arm_vbrsrq_m_n_u8): Likewise. 7149 (__arm_vbrsrq_m_n_u32): Likewise. 7150 (__arm_vbrsrq_m_n_u16): Likewise. 7151 (__arm_vcaddq_rot270_m_s8): Likewise. 7152 (__arm_vcaddq_rot270_m_s32): Likewise. 7153 (__arm_vcaddq_rot270_m_s16): Likewise. 7154 (__arm_vcaddq_rot270_m_u8): Likewise. 7155 (__arm_vcaddq_rot270_m_u32): Likewise. 7156 (__arm_vcaddq_rot270_m_u16): Likewise. 7157 (__arm_vcaddq_rot90_m_s8): Likewise. 7158 (__arm_vcaddq_rot90_m_s32): Likewise. 7159 (__arm_vcaddq_rot90_m_s16): Likewise. 7160 (__arm_vcaddq_rot90_m_u8): Likewise. 7161 (__arm_vcaddq_rot90_m_u32): Likewise. 7162 (__arm_vcaddq_rot90_m_u16): Likewise. 7163 (__arm_veorq_m_s8): Likewise. 7164 (__arm_veorq_m_s32): Likewise. 7165 (__arm_veorq_m_s16): Likewise. 7166 (__arm_veorq_m_u8): Likewise. 7167 (__arm_veorq_m_u32): Likewise. 7168 (__arm_veorq_m_u16): Likewise. 7169 (__arm_vhaddq_m_n_s8): Likewise. 7170 (__arm_vhaddq_m_n_s32): Likewise. 7171 (__arm_vhaddq_m_n_s16): Likewise. 7172 (__arm_vhaddq_m_n_u8): Likewise. 7173 (__arm_vhaddq_m_n_u32): Likewise. 7174 (__arm_vhaddq_m_n_u16): Likewise. 7175 (__arm_vhaddq_m_s8): Likewise. 7176 (__arm_vhaddq_m_s32): Likewise. 7177 (__arm_vhaddq_m_s16): Likewise. 7178 (__arm_vhaddq_m_u8): Likewise. 7179 (__arm_vhaddq_m_u32): Likewise. 7180 (__arm_vhaddq_m_u16): Likewise. 7181 (__arm_vhcaddq_rot270_m_s8): Likewise. 7182 (__arm_vhcaddq_rot270_m_s32): Likewise. 7183 (__arm_vhcaddq_rot270_m_s16): Likewise. 7184 (__arm_vhcaddq_rot90_m_s8): Likewise. 7185 (__arm_vhcaddq_rot90_m_s32): Likewise. 7186 (__arm_vhcaddq_rot90_m_s16): Likewise. 7187 (__arm_vhsubq_m_n_s8): Likewise. 7188 (__arm_vhsubq_m_n_s32): Likewise. 7189 (__arm_vhsubq_m_n_s16): Likewise. 7190 (__arm_vhsubq_m_n_u8): Likewise. 7191 (__arm_vhsubq_m_n_u32): Likewise. 7192 (__arm_vhsubq_m_n_u16): Likewise. 7193 (__arm_vhsubq_m_s8): Likewise. 7194 (__arm_vhsubq_m_s32): Likewise. 7195 (__arm_vhsubq_m_s16): Likewise. 7196 (__arm_vhsubq_m_u8): Likewise. 7197 (__arm_vhsubq_m_u32): Likewise. 7198 (__arm_vhsubq_m_u16): Likewise. 7199 (__arm_vmaxq_m_s8): Likewise. 7200 (__arm_vmaxq_m_s32): Likewise. 7201 (__arm_vmaxq_m_s16): Likewise. 7202 (__arm_vmaxq_m_u8): Likewise. 7203 (__arm_vmaxq_m_u32): Likewise. 7204 (__arm_vmaxq_m_u16): Likewise. 7205 (__arm_vminq_m_s8): Likewise. 7206 (__arm_vminq_m_s32): Likewise. 7207 (__arm_vminq_m_s16): Likewise. 7208 (__arm_vminq_m_u8): Likewise. 7209 (__arm_vminq_m_u32): Likewise. 7210 (__arm_vminq_m_u16): Likewise. 7211 (__arm_vmladavaq_p_s8): Likewise. 7212 (__arm_vmladavaq_p_s32): Likewise. 7213 (__arm_vmladavaq_p_s16): Likewise. 7214 (__arm_vmladavaq_p_u8): Likewise. 7215 (__arm_vmladavaq_p_u32): Likewise. 7216 (__arm_vmladavaq_p_u16): Likewise. 7217 (__arm_vmladavaxq_p_s8): Likewise. 7218 (__arm_vmladavaxq_p_s32): Likewise. 7219 (__arm_vmladavaxq_p_s16): Likewise. 7220 (__arm_vmlaq_m_n_s8): Likewise. 7221 (__arm_vmlaq_m_n_s32): Likewise. 7222 (__arm_vmlaq_m_n_s16): Likewise. 7223 (__arm_vmlaq_m_n_u8): Likewise. 7224 (__arm_vmlaq_m_n_u32): Likewise. 7225 (__arm_vmlaq_m_n_u16): Likewise. 7226 (__arm_vmlasq_m_n_s8): Likewise. 7227 (__arm_vmlasq_m_n_s32): Likewise. 7228 (__arm_vmlasq_m_n_s16): Likewise. 7229 (__arm_vmlasq_m_n_u8): Likewise. 7230 (__arm_vmlasq_m_n_u32): Likewise. 7231 (__arm_vmlasq_m_n_u16): Likewise. 7232 (__arm_vmlsdavaq_p_s8): Likewise. 7233 (__arm_vmlsdavaq_p_s32): Likewise. 7234 (__arm_vmlsdavaq_p_s16): Likewise. 7235 (__arm_vmlsdavaxq_p_s8): Likewise. 7236 (__arm_vmlsdavaxq_p_s32): Likewise. 7237 (__arm_vmlsdavaxq_p_s16): Likewise. 7238 (__arm_vmulhq_m_s8): Likewise. 7239 (__arm_vmulhq_m_s32): Likewise. 7240 (__arm_vmulhq_m_s16): Likewise. 7241 (__arm_vmulhq_m_u8): Likewise. 7242 (__arm_vmulhq_m_u32): Likewise. 7243 (__arm_vmulhq_m_u16): Likewise. 7244 (__arm_vmullbq_int_m_s8): Likewise. 7245 (__arm_vmullbq_int_m_s32): Likewise. 7246 (__arm_vmullbq_int_m_s16): Likewise. 7247 (__arm_vmullbq_int_m_u8): Likewise. 7248 (__arm_vmullbq_int_m_u32): Likewise. 7249 (__arm_vmullbq_int_m_u16): Likewise. 7250 (__arm_vmulltq_int_m_s8): Likewise. 7251 (__arm_vmulltq_int_m_s32): Likewise. 7252 (__arm_vmulltq_int_m_s16): Likewise. 7253 (__arm_vmulltq_int_m_u8): Likewise. 7254 (__arm_vmulltq_int_m_u32): Likewise. 7255 (__arm_vmulltq_int_m_u16): Likewise. 7256 (__arm_vmulq_m_n_s8): Likewise. 7257 (__arm_vmulq_m_n_s32): Likewise. 7258 (__arm_vmulq_m_n_s16): Likewise. 7259 (__arm_vmulq_m_n_u8): Likewise. 7260 (__arm_vmulq_m_n_u32): Likewise. 7261 (__arm_vmulq_m_n_u16): Likewise. 7262 (__arm_vmulq_m_s8): Likewise. 7263 (__arm_vmulq_m_s32): Likewise. 7264 (__arm_vmulq_m_s16): Likewise. 7265 (__arm_vmulq_m_u8): Likewise. 7266 (__arm_vmulq_m_u32): Likewise. 7267 (__arm_vmulq_m_u16): Likewise. 7268 (__arm_vornq_m_s8): Likewise. 7269 (__arm_vornq_m_s32): Likewise. 7270 (__arm_vornq_m_s16): Likewise. 7271 (__arm_vornq_m_u8): Likewise. 7272 (__arm_vornq_m_u32): Likewise. 7273 (__arm_vornq_m_u16): Likewise. 7274 (__arm_vorrq_m_s8): Likewise. 7275 (__arm_vorrq_m_s32): Likewise. 7276 (__arm_vorrq_m_s16): Likewise. 7277 (__arm_vorrq_m_u8): Likewise. 7278 (__arm_vorrq_m_u32): Likewise. 7279 (__arm_vorrq_m_u16): Likewise. 7280 (__arm_vqaddq_m_n_s8): Likewise. 7281 (__arm_vqaddq_m_n_s32): Likewise. 7282 (__arm_vqaddq_m_n_s16): Likewise. 7283 (__arm_vqaddq_m_n_u8): Likewise. 7284 (__arm_vqaddq_m_n_u32): Likewise. 7285 (__arm_vqaddq_m_n_u16): Likewise. 7286 (__arm_vqaddq_m_s8): Likewise. 7287 (__arm_vqaddq_m_s32): Likewise. 7288 (__arm_vqaddq_m_s16): Likewise. 7289 (__arm_vqaddq_m_u8): Likewise. 7290 (__arm_vqaddq_m_u32): Likewise. 7291 (__arm_vqaddq_m_u16): Likewise. 7292 (__arm_vqdmladhq_m_s8): Likewise. 7293 (__arm_vqdmladhq_m_s32): Likewise. 7294 (__arm_vqdmladhq_m_s16): Likewise. 7295 (__arm_vqdmladhxq_m_s8): Likewise. 7296 (__arm_vqdmladhxq_m_s32): Likewise. 7297 (__arm_vqdmladhxq_m_s16): Likewise. 7298 (__arm_vqdmlahq_m_n_s8): Likewise. 7299 (__arm_vqdmlahq_m_n_s32): Likewise. 7300 (__arm_vqdmlahq_m_n_s16): Likewise. 7301 (__arm_vqdmlahq_m_n_u8): Likewise. 7302 (__arm_vqdmlahq_m_n_u32): Likewise. 7303 (__arm_vqdmlahq_m_n_u16): Likewise. 7304 (__arm_vqdmlsdhq_m_s8): Likewise. 7305 (__arm_vqdmlsdhq_m_s32): Likewise. 7306 (__arm_vqdmlsdhq_m_s16): Likewise. 7307 (__arm_vqdmlsdhxq_m_s8): Likewise. 7308 (__arm_vqdmlsdhxq_m_s32): Likewise. 7309 (__arm_vqdmlsdhxq_m_s16): Likewise. 7310 (__arm_vqdmulhq_m_n_s8): Likewise. 7311 (__arm_vqdmulhq_m_n_s32): Likewise. 7312 (__arm_vqdmulhq_m_n_s16): Likewise. 7313 (__arm_vqdmulhq_m_s8): Likewise. 7314 (__arm_vqdmulhq_m_s32): Likewise. 7315 (__arm_vqdmulhq_m_s16): Likewise. 7316 (__arm_vqrdmladhq_m_s8): Likewise. 7317 (__arm_vqrdmladhq_m_s32): Likewise. 7318 (__arm_vqrdmladhq_m_s16): Likewise. 7319 (__arm_vqrdmladhxq_m_s8): Likewise. 7320 (__arm_vqrdmladhxq_m_s32): Likewise. 7321 (__arm_vqrdmladhxq_m_s16): Likewise. 7322 (__arm_vqrdmlahq_m_n_s8): Likewise. 7323 (__arm_vqrdmlahq_m_n_s32): Likewise. 7324 (__arm_vqrdmlahq_m_n_s16): Likewise. 7325 (__arm_vqrdmlahq_m_n_u8): Likewise. 7326 (__arm_vqrdmlahq_m_n_u32): Likewise. 7327 (__arm_vqrdmlahq_m_n_u16): Likewise. 7328 (__arm_vqrdmlashq_m_n_s8): Likewise. 7329 (__arm_vqrdmlashq_m_n_s32): Likewise. 7330 (__arm_vqrdmlashq_m_n_s16): Likewise. 7331 (__arm_vqrdmlashq_m_n_u8): Likewise. 7332 (__arm_vqrdmlashq_m_n_u32): Likewise. 7333 (__arm_vqrdmlashq_m_n_u16): Likewise. 7334 (__arm_vqrdmlsdhq_m_s8): Likewise. 7335 (__arm_vqrdmlsdhq_m_s32): Likewise. 7336 (__arm_vqrdmlsdhq_m_s16): Likewise. 7337 (__arm_vqrdmlsdhxq_m_s8): Likewise. 7338 (__arm_vqrdmlsdhxq_m_s32): Likewise. 7339 (__arm_vqrdmlsdhxq_m_s16): Likewise. 7340 (__arm_vqrdmulhq_m_n_s8): Likewise. 7341 (__arm_vqrdmulhq_m_n_s32): Likewise. 7342 (__arm_vqrdmulhq_m_n_s16): Likewise. 7343 (__arm_vqrdmulhq_m_s8): Likewise. 7344 (__arm_vqrdmulhq_m_s32): Likewise. 7345 (__arm_vqrdmulhq_m_s16): Likewise. 7346 (__arm_vqrshlq_m_s8): Likewise. 7347 (__arm_vqrshlq_m_s32): Likewise. 7348 (__arm_vqrshlq_m_s16): Likewise. 7349 (__arm_vqrshlq_m_u8): Likewise. 7350 (__arm_vqrshlq_m_u32): Likewise. 7351 (__arm_vqrshlq_m_u16): Likewise. 7352 (__arm_vqshlq_m_n_s8): Likewise. 7353 (__arm_vqshlq_m_n_s32): Likewise. 7354 (__arm_vqshlq_m_n_s16): Likewise. 7355 (__arm_vqshlq_m_n_u8): Likewise. 7356 (__arm_vqshlq_m_n_u32): Likewise. 7357 (__arm_vqshlq_m_n_u16): Likewise. 7358 (__arm_vqshlq_m_s8): Likewise. 7359 (__arm_vqshlq_m_s32): Likewise. 7360 (__arm_vqshlq_m_s16): Likewise. 7361 (__arm_vqshlq_m_u8): Likewise. 7362 (__arm_vqshlq_m_u32): Likewise. 7363 (__arm_vqshlq_m_u16): Likewise. 7364 (__arm_vqsubq_m_n_s8): Likewise. 7365 (__arm_vqsubq_m_n_s32): Likewise. 7366 (__arm_vqsubq_m_n_s16): Likewise. 7367 (__arm_vqsubq_m_n_u8): Likewise. 7368 (__arm_vqsubq_m_n_u32): Likewise. 7369 (__arm_vqsubq_m_n_u16): Likewise. 7370 (__arm_vqsubq_m_s8): Likewise. 7371 (__arm_vqsubq_m_s32): Likewise. 7372 (__arm_vqsubq_m_s16): Likewise. 7373 (__arm_vqsubq_m_u8): Likewise. 7374 (__arm_vqsubq_m_u32): Likewise. 7375 (__arm_vqsubq_m_u16): Likewise. 7376 (__arm_vrhaddq_m_s8): Likewise. 7377 (__arm_vrhaddq_m_s32): Likewise. 7378 (__arm_vrhaddq_m_s16): Likewise. 7379 (__arm_vrhaddq_m_u8): Likewise. 7380 (__arm_vrhaddq_m_u32): Likewise. 7381 (__arm_vrhaddq_m_u16): Likewise. 7382 (__arm_vrmulhq_m_s8): Likewise. 7383 (__arm_vrmulhq_m_s32): Likewise. 7384 (__arm_vrmulhq_m_s16): Likewise. 7385 (__arm_vrmulhq_m_u8): Likewise. 7386 (__arm_vrmulhq_m_u32): Likewise. 7387 (__arm_vrmulhq_m_u16): Likewise. 7388 (__arm_vrshlq_m_s8): Likewise. 7389 (__arm_vrshlq_m_s32): Likewise. 7390 (__arm_vrshlq_m_s16): Likewise. 7391 (__arm_vrshlq_m_u8): Likewise. 7392 (__arm_vrshlq_m_u32): Likewise. 7393 (__arm_vrshlq_m_u16): Likewise. 7394 (__arm_vrshrq_m_n_s8): Likewise. 7395 (__arm_vrshrq_m_n_s32): Likewise. 7396 (__arm_vrshrq_m_n_s16): Likewise. 7397 (__arm_vrshrq_m_n_u8): Likewise. 7398 (__arm_vrshrq_m_n_u32): Likewise. 7399 (__arm_vrshrq_m_n_u16): Likewise. 7400 (__arm_vshlq_m_n_s8): Likewise. 7401 (__arm_vshlq_m_n_s32): Likewise. 7402 (__arm_vshlq_m_n_s16): Likewise. 7403 (__arm_vshlq_m_n_u8): Likewise. 7404 (__arm_vshlq_m_n_u32): Likewise. 7405 (__arm_vshlq_m_n_u16): Likewise. 7406 (__arm_vshrq_m_n_s8): Likewise. 7407 (__arm_vshrq_m_n_s32): Likewise. 7408 (__arm_vshrq_m_n_s16): Likewise. 7409 (__arm_vshrq_m_n_u8): Likewise. 7410 (__arm_vshrq_m_n_u32): Likewise. 7411 (__arm_vshrq_m_n_u16): Likewise. 7412 (__arm_vsliq_m_n_s8): Likewise. 7413 (__arm_vsliq_m_n_s32): Likewise. 7414 (__arm_vsliq_m_n_s16): Likewise. 7415 (__arm_vsliq_m_n_u8): Likewise. 7416 (__arm_vsliq_m_n_u32): Likewise. 7417 (__arm_vsliq_m_n_u16): Likewise. 7418 (__arm_vsubq_m_n_s8): Likewise. 7419 (__arm_vsubq_m_n_s32): Likewise. 7420 (__arm_vsubq_m_n_s16): Likewise. 7421 (__arm_vsubq_m_n_u8): Likewise. 7422 (__arm_vsubq_m_n_u32): Likewise. 7423 (__arm_vsubq_m_n_u16): Likewise. 7424 (vqdmladhq_m): Define polymorphic variant. 7425 (vqdmladhxq_m): Likewise. 7426 (vqdmlsdhq_m): Likewise. 7427 (vqdmlsdhxq_m): Likewise. 7428 (vabdq_m): Likewise. 7429 (vandq_m): Likewise. 7430 (vbicq_m): Likewise. 7431 (vbrsrq_m_n): Likewise. 7432 (vcaddq_rot270_m): Likewise. 7433 (vcaddq_rot90_m): Likewise. 7434 (veorq_m): Likewise. 7435 (vmaxq_m): Likewise. 7436 (vminq_m): Likewise. 7437 (vmladavaq_p): Likewise. 7438 (vmlaq_m_n): Likewise. 7439 (vmlasq_m_n): Likewise. 7440 (vmulhq_m): Likewise. 7441 (vmullbq_int_m): Likewise. 7442 (vmulltq_int_m): Likewise. 7443 (vornq_m): Likewise. 7444 (vorrq_m): Likewise. 7445 (vqdmlahq_m_n): Likewise. 7446 (vqrdmlahq_m_n): Likewise. 7447 (vqrdmlashq_m_n): Likewise. 7448 (vqrshlq_m): Likewise. 7449 (vqshlq_m_n): Likewise. 7450 (vqshlq_m): Likewise. 7451 (vrhaddq_m): Likewise. 7452 (vrmulhq_m): Likewise. 7453 (vrshlq_m): Likewise. 7454 (vrshrq_m_n): Likewise. 7455 (vshlq_m_n): Likewise. 7456 (vshrq_m_n): Likewise. 7457 (vsliq_m): Likewise. 7458 (vaddq_m_n): Likewise. 7459 (vaddq_m): Likewise. 7460 (vhaddq_m_n): Likewise. 7461 (vhaddq_m): Likewise. 7462 (vhcaddq_rot270_m): Likewise. 7463 (vhcaddq_rot90_m): Likewise. 7464 (vhsubq_m): Likewise. 7465 (vhsubq_m_n): Likewise. 7466 (vmulq_m_n): Likewise. 7467 (vmulq_m): Likewise. 7468 (vqaddq_m_n): Likewise. 7469 (vqaddq_m): Likewise. 7470 (vqdmulhq_m_n): Likewise. 7471 (vqdmulhq_m): Likewise. 7472 (vsubq_m_n): Likewise. 7473 (vsliq_m_n): Likewise. 7474 (vqsubq_m_n): Likewise. 7475 (vqsubq_m): Likewise. 7476 (vqrdmulhq_m): Likewise. 7477 (vqrdmulhq_m_n): Likewise. 7478 (vqrdmlsdhxq_m): Likewise. 7479 (vqrdmlsdhq_m): Likewise. 7480 (vqrdmladhq_m): Likewise. 7481 (vqrdmladhxq_m): Likewise. 7482 (vmlsdavaxq_p): Likewise. 7483 (vmlsdavaq_p): Likewise. 7484 (vmladavaxq_p): Likewise. 7485 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use 7486 builtin qualifier. 7487 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise. 7488 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise. 7489 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE): Likewise. 7490 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise. 7491 * config/arm/mve.md (VHSUBQ_M): Define iterators. 7492 (VSLIQ_M_N): Likewise. 7493 (VQRDMLAHQ_M_N): Likewise. 7494 (VRSHLQ_M): Likewise. 7495 (VMINQ_M): Likewise. 7496 (VMULLBQ_INT_M): Likewise. 7497 (VMULHQ_M): Likewise. 7498 (VMULQ_M): Likewise. 7499 (VHSUBQ_M_N): Likewise. 7500 (VHADDQ_M_N): Likewise. 7501 (VORRQ_M): Likewise. 7502 (VRMULHQ_M): Likewise. 7503 (VQADDQ_M): Likewise. 7504 (VRSHRQ_M_N): Likewise. 7505 (VQSUBQ_M_N): Likewise. 7506 (VADDQ_M): Likewise. 7507 (VORNQ_M): Likewise. 7508 (VQDMLAHQ_M_N): Likewise. 7509 (VRHADDQ_M): Likewise. 7510 (VQSHLQ_M): Likewise. 7511 (VANDQ_M): Likewise. 7512 (VBICQ_M): Likewise. 7513 (VSHLQ_M_N): Likewise. 7514 (VCADDQ_ROT270_M): Likewise. 7515 (VQRSHLQ_M): Likewise. 7516 (VQADDQ_M_N): Likewise. 7517 (VADDQ_M_N): Likewise. 7518 (VMAXQ_M): Likewise. 7519 (VQSUBQ_M): Likewise. 7520 (VMLASQ_M_N): Likewise. 7521 (VMLADAVAQ_P): Likewise. 7522 (VBRSRQ_M_N): Likewise. 7523 (VMULQ_M_N): Likewise. 7524 (VCADDQ_ROT90_M): Likewise. 7525 (VMULLTQ_INT_M): Likewise. 7526 (VEORQ_M): Likewise. 7527 (VSHRQ_M_N): Likewise. 7528 (VSUBQ_M_N): Likewise. 7529 (VHADDQ_M): Likewise. 7530 (VABDQ_M): Likewise. 7531 (VQRDMLASHQ_M_N): Likewise. 7532 (VMLAQ_M_N): Likewise. 7533 (VQSHLQ_M_N): Likewise. 7534 (mve_vabdq_m_<supf><mode>): Define RTL pattern. 7535 (mve_vaddq_m_n_<supf><mode>): Likewise. 7536 (mve_vaddq_m_<supf><mode>): Likewise. 7537 (mve_vandq_m_<supf><mode>): Likewise. 7538 (mve_vbicq_m_<supf><mode>): Likewise. 7539 (mve_vbrsrq_m_n_<supf><mode>): Likewise. 7540 (mve_vcaddq_rot270_m_<supf><mode>): Likewise. 7541 (mve_vcaddq_rot90_m_<supf><mode>): Likewise. 7542 (mve_veorq_m_<supf><mode>): Likewise. 7543 (mve_vhaddq_m_n_<supf><mode>): Likewise. 7544 (mve_vhaddq_m_<supf><mode>): Likewise. 7545 (mve_vhsubq_m_n_<supf><mode>): Likewise. 7546 (mve_vhsubq_m_<supf><mode>): Likewise. 7547 (mve_vmaxq_m_<supf><mode>): Likewise. 7548 (mve_vminq_m_<supf><mode>): Likewise. 7549 (mve_vmladavaq_p_<supf><mode>): Likewise. 7550 (mve_vmlaq_m_n_<supf><mode>): Likewise. 7551 (mve_vmlasq_m_n_<supf><mode>): Likewise. 7552 (mve_vmulhq_m_<supf><mode>): Likewise. 7553 (mve_vmullbq_int_m_<supf><mode>): Likewise. 7554 (mve_vmulltq_int_m_<supf><mode>): Likewise. 7555 (mve_vmulq_m_n_<supf><mode>): Likewise. 7556 (mve_vmulq_m_<supf><mode>): Likewise. 7557 (mve_vornq_m_<supf><mode>): Likewise. 7558 (mve_vorrq_m_<supf><mode>): Likewise. 7559 (mve_vqaddq_m_n_<supf><mode>): Likewise. 7560 (mve_vqaddq_m_<supf><mode>): Likewise. 7561 (mve_vqdmlahq_m_n_<supf><mode>): Likewise. 7562 (mve_vqrdmlahq_m_n_<supf><mode>): Likewise. 7563 (mve_vqrdmlashq_m_n_<supf><mode>): Likewise. 7564 (mve_vqrshlq_m_<supf><mode>): Likewise. 7565 (mve_vqshlq_m_n_<supf><mode>): Likewise. 7566 (mve_vqshlq_m_<supf><mode>): Likewise. 7567 (mve_vqsubq_m_n_<supf><mode>): Likewise. 7568 (mve_vqsubq_m_<supf><mode>): Likewise. 7569 (mve_vrhaddq_m_<supf><mode>): Likewise. 7570 (mve_vrmulhq_m_<supf><mode>): Likewise. 7571 (mve_vrshlq_m_<supf><mode>): Likewise. 7572 (mve_vrshrq_m_n_<supf><mode>): Likewise. 7573 (mve_vshlq_m_n_<supf><mode>): Likewise. 7574 (mve_vshrq_m_n_<supf><mode>): Likewise. 7575 (mve_vsliq_m_n_<supf><mode>): Likewise. 7576 (mve_vsubq_m_n_<supf><mode>): Likewise. 7577 (mve_vhcaddq_rot270_m_s<mode>): Likewise. 7578 (mve_vhcaddq_rot90_m_s<mode>): Likewise. 7579 (mve_vmladavaxq_p_s<mode>): Likewise. 7580 (mve_vmlsdavaq_p_s<mode>): Likewise. 7581 (mve_vmlsdavaxq_p_s<mode>): Likewise. 7582 (mve_vqdmladhq_m_s<mode>): Likewise. 7583 (mve_vqdmladhxq_m_s<mode>): Likewise. 7584 (mve_vqdmlsdhq_m_s<mode>): Likewise. 7585 (mve_vqdmlsdhxq_m_s<mode>): Likewise. 7586 (mve_vqdmulhq_m_n_s<mode>): Likewise. 7587 (mve_vqdmulhq_m_s<mode>): Likewise. 7588 (mve_vqrdmladhq_m_s<mode>): Likewise. 7589 (mve_vqrdmladhxq_m_s<mode>): Likewise. 7590 (mve_vqrdmlsdhq_m_s<mode>): Likewise. 7591 (mve_vqrdmlsdhxq_m_s<mode>): Likewise. 7592 (mve_vqrdmulhq_m_n_s<mode>): Likewise. 7593 (mve_vqrdmulhq_m_s<mode>): Likewise. 7594 75952020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> 7596 Mihail Ionescu <mihail.ionescu@arm.com> 7597 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 7598 7599 * config/arm/arm-builtins.c (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): 7600 Define builtin qualifier. 7601 (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. 7602 (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. 7603 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. 7604 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. 7605 (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. 7606 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. 7607 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise. 7608 * config/arm/arm_mve.h (vsriq_m_n_s8): Define macro. 7609 (vsubq_m_s8): Likewise. 7610 (vcvtq_m_n_f16_u16): Likewise. 7611 (vqshluq_m_n_s8): Likewise. 7612 (vabavq_p_s8): Likewise. 7613 (vsriq_m_n_u8): Likewise. 7614 (vshlq_m_u8): Likewise. 7615 (vsubq_m_u8): Likewise. 7616 (vabavq_p_u8): Likewise. 7617 (vshlq_m_s8): Likewise. 7618 (vcvtq_m_n_f16_s16): Likewise. 7619 (vsriq_m_n_s16): Likewise. 7620 (vsubq_m_s16): Likewise. 7621 (vcvtq_m_n_f32_u32): Likewise. 7622 (vqshluq_m_n_s16): Likewise. 7623 (vabavq_p_s16): Likewise. 7624 (vsriq_m_n_u16): Likewise. 7625 (vshlq_m_u16): Likewise. 7626 (vsubq_m_u16): Likewise. 7627 (vabavq_p_u16): Likewise. 7628 (vshlq_m_s16): Likewise. 7629 (vcvtq_m_n_f32_s32): Likewise. 7630 (vsriq_m_n_s32): Likewise. 7631 (vsubq_m_s32): Likewise. 7632 (vqshluq_m_n_s32): Likewise. 7633 (vabavq_p_s32): Likewise. 7634 (vsriq_m_n_u32): Likewise. 7635 (vshlq_m_u32): Likewise. 7636 (vsubq_m_u32): Likewise. 7637 (vabavq_p_u32): Likewise. 7638 (vshlq_m_s32): Likewise. 7639 (__arm_vsriq_m_n_s8): Define intrinsic. 7640 (__arm_vsubq_m_s8): Likewise. 7641 (__arm_vqshluq_m_n_s8): Likewise. 7642 (__arm_vabavq_p_s8): Likewise. 7643 (__arm_vsriq_m_n_u8): Likewise. 7644 (__arm_vshlq_m_u8): Likewise. 7645 (__arm_vsubq_m_u8): Likewise. 7646 (__arm_vabavq_p_u8): Likewise. 7647 (__arm_vshlq_m_s8): Likewise. 7648 (__arm_vsriq_m_n_s16): Likewise. 7649 (__arm_vsubq_m_s16): Likewise. 7650 (__arm_vqshluq_m_n_s16): Likewise. 7651 (__arm_vabavq_p_s16): Likewise. 7652 (__arm_vsriq_m_n_u16): Likewise. 7653 (__arm_vshlq_m_u16): Likewise. 7654 (__arm_vsubq_m_u16): Likewise. 7655 (__arm_vabavq_p_u16): Likewise. 7656 (__arm_vshlq_m_s16): Likewise. 7657 (__arm_vsriq_m_n_s32): Likewise. 7658 (__arm_vsubq_m_s32): Likewise. 7659 (__arm_vqshluq_m_n_s32): Likewise. 7660 (__arm_vabavq_p_s32): Likewise. 7661 (__arm_vsriq_m_n_u32): Likewise. 7662 (__arm_vshlq_m_u32): Likewise. 7663 (__arm_vsubq_m_u32): Likewise. 7664 (__arm_vabavq_p_u32): Likewise. 7665 (__arm_vshlq_m_s32): Likewise. 7666 (__arm_vcvtq_m_n_f16_u16): Likewise. 7667 (__arm_vcvtq_m_n_f16_s16): Likewise. 7668 (__arm_vcvtq_m_n_f32_u32): Likewise. 7669 (__arm_vcvtq_m_n_f32_s32): Likewise. 7670 (vcvtq_m_n): Define polymorphic variant. 7671 (vqshluq_m_n): Likewise. 7672 (vshlq_m): Likewise. 7673 (vsriq_m_n): Likewise. 7674 (vsubq_m): Likewise. 7675 (vabavq_p): Likewise. 7676 * config/arm/arm_mve_builtins.def 7677 (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): Use builtin qualifier. 7678 (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. 7679 (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. 7680 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. 7681 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. 7682 (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. 7683 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. 7684 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise. 7685 * config/arm/mve.md (VABAVQ_P): Define iterator. 7686 (VSHLQ_M): Likewise. 7687 (VSRIQ_M_N): Likewise. 7688 (VSUBQ_M): Likewise. 7689 (VCVTQ_M_N_TO_F): Likewise. 7690 (mve_vabavq_p_<supf><mode>): Define RTL pattern. 7691 (mve_vqshluq_m_n_s<mode>): Likewise. 7692 (mve_vshlq_m_<supf><mode>): Likewise. 7693 (mve_vsriq_m_n_<supf><mode>): Likewise. 7694 (mve_vsubq_m_<supf><mode>): Likewise. 7695 (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise. 7696 76972020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> 7698 Mihail Ionescu <mihail.ionescu@arm.com> 7699 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 7700 7701 * config/arm/arm_mve.h (vrmlaldavhaxq_s32): Define macro. 7702 (vrmlsldavhaq_s32): Likewise. 7703 (vrmlsldavhaxq_s32): Likewise. 7704 (vaddlvaq_p_s32): Likewise. 7705 (vcvtbq_m_f16_f32): Likewise. 7706 (vcvtbq_m_f32_f16): Likewise. 7707 (vcvttq_m_f16_f32): Likewise. 7708 (vcvttq_m_f32_f16): Likewise. 7709 (vrev16q_m_s8): Likewise. 7710 (vrev32q_m_f16): Likewise. 7711 (vrmlaldavhq_p_s32): Likewise. 7712 (vrmlaldavhxq_p_s32): Likewise. 7713 (vrmlsldavhq_p_s32): Likewise. 7714 (vrmlsldavhxq_p_s32): Likewise. 7715 (vaddlvaq_p_u32): Likewise. 7716 (vrev16q_m_u8): Likewise. 7717 (vrmlaldavhq_p_u32): Likewise. 7718 (vmvnq_m_n_s16): Likewise. 7719 (vorrq_m_n_s16): Likewise. 7720 (vqrshrntq_n_s16): Likewise. 7721 (vqshrnbq_n_s16): Likewise. 7722 (vqshrntq_n_s16): Likewise. 7723 (vrshrnbq_n_s16): Likewise. 7724 (vrshrntq_n_s16): Likewise. 7725 (vshrnbq_n_s16): Likewise. 7726 (vshrntq_n_s16): Likewise. 7727 (vcmlaq_f16): Likewise. 7728 (vcmlaq_rot180_f16): Likewise. 7729 (vcmlaq_rot270_f16): Likewise. 7730 (vcmlaq_rot90_f16): Likewise. 7731 (vfmaq_f16): Likewise. 7732 (vfmaq_n_f16): Likewise. 7733 (vfmasq_n_f16): Likewise. 7734 (vfmsq_f16): Likewise. 7735 (vmlaldavaq_s16): Likewise. 7736 (vmlaldavaxq_s16): Likewise. 7737 (vmlsldavaq_s16): Likewise. 7738 (vmlsldavaxq_s16): Likewise. 7739 (vabsq_m_f16): Likewise. 7740 (vcvtmq_m_s16_f16): Likewise. 7741 (vcvtnq_m_s16_f16): Likewise. 7742 (vcvtpq_m_s16_f16): Likewise. 7743 (vcvtq_m_s16_f16): Likewise. 7744 (vdupq_m_n_f16): Likewise. 7745 (vmaxnmaq_m_f16): Likewise. 7746 (vmaxnmavq_p_f16): Likewise. 7747 (vmaxnmvq_p_f16): Likewise. 7748 (vminnmaq_m_f16): Likewise. 7749 (vminnmavq_p_f16): Likewise. 7750 (vminnmvq_p_f16): Likewise. 7751 (vmlaldavq_p_s16): Likewise. 7752 (vmlaldavxq_p_s16): Likewise. 7753 (vmlsldavq_p_s16): Likewise. 7754 (vmlsldavxq_p_s16): Likewise. 7755 (vmovlbq_m_s8): Likewise. 7756 (vmovltq_m_s8): Likewise. 7757 (vmovnbq_m_s16): Likewise. 7758 (vmovntq_m_s16): Likewise. 7759 (vnegq_m_f16): Likewise. 7760 (vpselq_f16): Likewise. 7761 (vqmovnbq_m_s16): Likewise. 7762 (vqmovntq_m_s16): Likewise. 7763 (vrev32q_m_s8): Likewise. 7764 (vrev64q_m_f16): Likewise. 7765 (vrndaq_m_f16): Likewise. 7766 (vrndmq_m_f16): Likewise. 7767 (vrndnq_m_f16): Likewise. 7768 (vrndpq_m_f16): Likewise. 7769 (vrndq_m_f16): Likewise. 7770 (vrndxq_m_f16): Likewise. 7771 (vcmpeqq_m_n_f16): Likewise. 7772 (vcmpgeq_m_f16): Likewise. 7773 (vcmpgeq_m_n_f16): Likewise. 7774 (vcmpgtq_m_f16): Likewise. 7775 (vcmpgtq_m_n_f16): Likewise. 7776 (vcmpleq_m_f16): Likewise. 7777 (vcmpleq_m_n_f16): Likewise. 7778 (vcmpltq_m_f16): Likewise. 7779 (vcmpltq_m_n_f16): Likewise. 7780 (vcmpneq_m_f16): Likewise. 7781 (vcmpneq_m_n_f16): Likewise. 7782 (vmvnq_m_n_u16): Likewise. 7783 (vorrq_m_n_u16): Likewise. 7784 (vqrshruntq_n_s16): Likewise. 7785 (vqshrunbq_n_s16): Likewise. 7786 (vqshruntq_n_s16): Likewise. 7787 (vcvtmq_m_u16_f16): Likewise. 7788 (vcvtnq_m_u16_f16): Likewise. 7789 (vcvtpq_m_u16_f16): Likewise. 7790 (vcvtq_m_u16_f16): Likewise. 7791 (vqmovunbq_m_s16): Likewise. 7792 (vqmovuntq_m_s16): Likewise. 7793 (vqrshrntq_n_u16): Likewise. 7794 (vqshrnbq_n_u16): Likewise. 7795 (vqshrntq_n_u16): Likewise. 7796 (vrshrnbq_n_u16): Likewise. 7797 (vrshrntq_n_u16): Likewise. 7798 (vshrnbq_n_u16): Likewise. 7799 (vshrntq_n_u16): Likewise. 7800 (vmlaldavaq_u16): Likewise. 7801 (vmlaldavaxq_u16): Likewise. 7802 (vmlaldavq_p_u16): Likewise. 7803 (vmlaldavxq_p_u16): Likewise. 7804 (vmovlbq_m_u8): Likewise. 7805 (vmovltq_m_u8): Likewise. 7806 (vmovnbq_m_u16): Likewise. 7807 (vmovntq_m_u16): Likewise. 7808 (vqmovnbq_m_u16): Likewise. 7809 (vqmovntq_m_u16): Likewise. 7810 (vrev32q_m_u8): Likewise. 7811 (vmvnq_m_n_s32): Likewise. 7812 (vorrq_m_n_s32): Likewise. 7813 (vqrshrntq_n_s32): Likewise. 7814 (vqshrnbq_n_s32): Likewise. 7815 (vqshrntq_n_s32): Likewise. 7816 (vrshrnbq_n_s32): Likewise. 7817 (vrshrntq_n_s32): Likewise. 7818 (vshrnbq_n_s32): Likewise. 7819 (vshrntq_n_s32): Likewise. 7820 (vcmlaq_f32): Likewise. 7821 (vcmlaq_rot180_f32): Likewise. 7822 (vcmlaq_rot270_f32): Likewise. 7823 (vcmlaq_rot90_f32): Likewise. 7824 (vfmaq_f32): Likewise. 7825 (vfmaq_n_f32): Likewise. 7826 (vfmasq_n_f32): Likewise. 7827 (vfmsq_f32): Likewise. 7828 (vmlaldavaq_s32): Likewise. 7829 (vmlaldavaxq_s32): Likewise. 7830 (vmlsldavaq_s32): Likewise. 7831 (vmlsldavaxq_s32): Likewise. 7832 (vabsq_m_f32): Likewise. 7833 (vcvtmq_m_s32_f32): Likewise. 7834 (vcvtnq_m_s32_f32): Likewise. 7835 (vcvtpq_m_s32_f32): Likewise. 7836 (vcvtq_m_s32_f32): Likewise. 7837 (vdupq_m_n_f32): Likewise. 7838 (vmaxnmaq_m_f32): Likewise. 7839 (vmaxnmavq_p_f32): Likewise. 7840 (vmaxnmvq_p_f32): Likewise. 7841 (vminnmaq_m_f32): Likewise. 7842 (vminnmavq_p_f32): Likewise. 7843 (vminnmvq_p_f32): Likewise. 7844 (vmlaldavq_p_s32): Likewise. 7845 (vmlaldavxq_p_s32): Likewise. 7846 (vmlsldavq_p_s32): Likewise. 7847 (vmlsldavxq_p_s32): Likewise. 7848 (vmovlbq_m_s16): Likewise. 7849 (vmovltq_m_s16): Likewise. 7850 (vmovnbq_m_s32): Likewise. 7851 (vmovntq_m_s32): Likewise. 7852 (vnegq_m_f32): Likewise. 7853 (vpselq_f32): Likewise. 7854 (vqmovnbq_m_s32): Likewise. 7855 (vqmovntq_m_s32): Likewise. 7856 (vrev32q_m_s16): Likewise. 7857 (vrev64q_m_f32): Likewise. 7858 (vrndaq_m_f32): Likewise. 7859 (vrndmq_m_f32): Likewise. 7860 (vrndnq_m_f32): Likewise. 7861 (vrndpq_m_f32): Likewise. 7862 (vrndq_m_f32): Likewise. 7863 (vrndxq_m_f32): Likewise. 7864 (vcmpeqq_m_n_f32): Likewise. 7865 (vcmpgeq_m_f32): Likewise. 7866 (vcmpgeq_m_n_f32): Likewise. 7867 (vcmpgtq_m_f32): Likewise. 7868 (vcmpgtq_m_n_f32): Likewise. 7869 (vcmpleq_m_f32): Likewise. 7870 (vcmpleq_m_n_f32): Likewise. 7871 (vcmpltq_m_f32): Likewise. 7872 (vcmpltq_m_n_f32): Likewise. 7873 (vcmpneq_m_f32): Likewise. 7874 (vcmpneq_m_n_f32): Likewise. 7875 (vmvnq_m_n_u32): Likewise. 7876 (vorrq_m_n_u32): Likewise. 7877 (vqrshruntq_n_s32): Likewise. 7878 (vqshrunbq_n_s32): Likewise. 7879 (vqshruntq_n_s32): Likewise. 7880 (vcvtmq_m_u32_f32): Likewise. 7881 (vcvtnq_m_u32_f32): Likewise. 7882 (vcvtpq_m_u32_f32): Likewise. 7883 (vcvtq_m_u32_f32): Likewise. 7884 (vqmovunbq_m_s32): Likewise. 7885 (vqmovuntq_m_s32): Likewise. 7886 (vqrshrntq_n_u32): Likewise. 7887 (vqshrnbq_n_u32): Likewise. 7888 (vqshrntq_n_u32): Likewise. 7889 (vrshrnbq_n_u32): Likewise. 7890 (vrshrntq_n_u32): Likewise. 7891 (vshrnbq_n_u32): Likewise. 7892 (vshrntq_n_u32): Likewise. 7893 (vmlaldavaq_u32): Likewise. 7894 (vmlaldavaxq_u32): Likewise. 7895 (vmlaldavq_p_u32): Likewise. 7896 (vmlaldavxq_p_u32): Likewise. 7897 (vmovlbq_m_u16): Likewise. 7898 (vmovltq_m_u16): Likewise. 7899 (vmovnbq_m_u32): Likewise. 7900 (vmovntq_m_u32): Likewise. 7901 (vqmovnbq_m_u32): Likewise. 7902 (vqmovntq_m_u32): Likewise. 7903 (vrev32q_m_u16): Likewise. 7904 (__arm_vrmlaldavhaxq_s32): Define intrinsic. 7905 (__arm_vrmlsldavhaq_s32): Likewise. 7906 (__arm_vrmlsldavhaxq_s32): Likewise. 7907 (__arm_vaddlvaq_p_s32): Likewise. 7908 (__arm_vrev16q_m_s8): Likewise. 7909 (__arm_vrmlaldavhq_p_s32): Likewise. 7910 (__arm_vrmlaldavhxq_p_s32): Likewise. 7911 (__arm_vrmlsldavhq_p_s32): Likewise. 7912 (__arm_vrmlsldavhxq_p_s32): Likewise. 7913 (__arm_vaddlvaq_p_u32): Likewise. 7914 (__arm_vrev16q_m_u8): Likewise. 7915 (__arm_vrmlaldavhq_p_u32): Likewise. 7916 (__arm_vmvnq_m_n_s16): Likewise. 7917 (__arm_vorrq_m_n_s16): Likewise. 7918 (__arm_vqrshrntq_n_s16): Likewise. 7919 (__arm_vqshrnbq_n_s16): Likewise. 7920 (__arm_vqshrntq_n_s16): Likewise. 7921 (__arm_vrshrnbq_n_s16): Likewise. 7922 (__arm_vrshrntq_n_s16): Likewise. 7923 (__arm_vshrnbq_n_s16): Likewise. 7924 (__arm_vshrntq_n_s16): Likewise. 7925 (__arm_vmlaldavaq_s16): Likewise. 7926 (__arm_vmlaldavaxq_s16): Likewise. 7927 (__arm_vmlsldavaq_s16): Likewise. 7928 (__arm_vmlsldavaxq_s16): Likewise. 7929 (__arm_vmlaldavq_p_s16): Likewise. 7930 (__arm_vmlaldavxq_p_s16): Likewise. 7931 (__arm_vmlsldavq_p_s16): Likewise. 7932 (__arm_vmlsldavxq_p_s16): Likewise. 7933 (__arm_vmovlbq_m_s8): Likewise. 7934 (__arm_vmovltq_m_s8): Likewise. 7935 (__arm_vmovnbq_m_s16): Likewise. 7936 (__arm_vmovntq_m_s16): Likewise. 7937 (__arm_vqmovnbq_m_s16): Likewise. 7938 (__arm_vqmovntq_m_s16): Likewise. 7939 (__arm_vrev32q_m_s8): Likewise. 7940 (__arm_vmvnq_m_n_u16): Likewise. 7941 (__arm_vorrq_m_n_u16): Likewise. 7942 (__arm_vqrshruntq_n_s16): Likewise. 7943 (__arm_vqshrunbq_n_s16): Likewise. 7944 (__arm_vqshruntq_n_s16): Likewise. 7945 (__arm_vqmovunbq_m_s16): Likewise. 7946 (__arm_vqmovuntq_m_s16): Likewise. 7947 (__arm_vqrshrntq_n_u16): Likewise. 7948 (__arm_vqshrnbq_n_u16): Likewise. 7949 (__arm_vqshrntq_n_u16): Likewise. 7950 (__arm_vrshrnbq_n_u16): Likewise. 7951 (__arm_vrshrntq_n_u16): Likewise. 7952 (__arm_vshrnbq_n_u16): Likewise. 7953 (__arm_vshrntq_n_u16): Likewise. 7954 (__arm_vmlaldavaq_u16): Likewise. 7955 (__arm_vmlaldavaxq_u16): Likewise. 7956 (__arm_vmlaldavq_p_u16): Likewise. 7957 (__arm_vmlaldavxq_p_u16): Likewise. 7958 (__arm_vmovlbq_m_u8): Likewise. 7959 (__arm_vmovltq_m_u8): Likewise. 7960 (__arm_vmovnbq_m_u16): Likewise. 7961 (__arm_vmovntq_m_u16): Likewise. 7962 (__arm_vqmovnbq_m_u16): Likewise. 7963 (__arm_vqmovntq_m_u16): Likewise. 7964 (__arm_vrev32q_m_u8): Likewise. 7965 (__arm_vmvnq_m_n_s32): Likewise. 7966 (__arm_vorrq_m_n_s32): Likewise. 7967 (__arm_vqrshrntq_n_s32): Likewise. 7968 (__arm_vqshrnbq_n_s32): Likewise. 7969 (__arm_vqshrntq_n_s32): Likewise. 7970 (__arm_vrshrnbq_n_s32): Likewise. 7971 (__arm_vrshrntq_n_s32): Likewise. 7972 (__arm_vshrnbq_n_s32): Likewise. 7973 (__arm_vshrntq_n_s32): Likewise. 7974 (__arm_vmlaldavaq_s32): Likewise. 7975 (__arm_vmlaldavaxq_s32): Likewise. 7976 (__arm_vmlsldavaq_s32): Likewise. 7977 (__arm_vmlsldavaxq_s32): Likewise. 7978 (__arm_vmlaldavq_p_s32): Likewise. 7979 (__arm_vmlaldavxq_p_s32): Likewise. 7980 (__arm_vmlsldavq_p_s32): Likewise. 7981 (__arm_vmlsldavxq_p_s32): Likewise. 7982 (__arm_vmovlbq_m_s16): Likewise. 7983 (__arm_vmovltq_m_s16): Likewise. 7984 (__arm_vmovnbq_m_s32): Likewise. 7985 (__arm_vmovntq_m_s32): Likewise. 7986 (__arm_vqmovnbq_m_s32): Likewise. 7987 (__arm_vqmovntq_m_s32): Likewise. 7988 (__arm_vrev32q_m_s16): Likewise. 7989 (__arm_vmvnq_m_n_u32): Likewise. 7990 (__arm_vorrq_m_n_u32): Likewise. 7991 (__arm_vqrshruntq_n_s32): Likewise. 7992 (__arm_vqshrunbq_n_s32): Likewise. 7993 (__arm_vqshruntq_n_s32): Likewise. 7994 (__arm_vqmovunbq_m_s32): Likewise. 7995 (__arm_vqmovuntq_m_s32): Likewise. 7996 (__arm_vqrshrntq_n_u32): Likewise. 7997 (__arm_vqshrnbq_n_u32): Likewise. 7998 (__arm_vqshrntq_n_u32): Likewise. 7999 (__arm_vrshrnbq_n_u32): Likewise. 8000 (__arm_vrshrntq_n_u32): Likewise. 8001 (__arm_vshrnbq_n_u32): Likewise. 8002 (__arm_vshrntq_n_u32): Likewise. 8003 (__arm_vmlaldavaq_u32): Likewise. 8004 (__arm_vmlaldavaxq_u32): Likewise. 8005 (__arm_vmlaldavq_p_u32): Likewise. 8006 (__arm_vmlaldavxq_p_u32): Likewise. 8007 (__arm_vmovlbq_m_u16): Likewise. 8008 (__arm_vmovltq_m_u16): Likewise. 8009 (__arm_vmovnbq_m_u32): Likewise. 8010 (__arm_vmovntq_m_u32): Likewise. 8011 (__arm_vqmovnbq_m_u32): Likewise. 8012 (__arm_vqmovntq_m_u32): Likewise. 8013 (__arm_vrev32q_m_u16): Likewise. 8014 (__arm_vcvtbq_m_f16_f32): Likewise. 8015 (__arm_vcvtbq_m_f32_f16): Likewise. 8016 (__arm_vcvttq_m_f16_f32): Likewise. 8017 (__arm_vcvttq_m_f32_f16): Likewise. 8018 (__arm_vrev32q_m_f16): Likewise. 8019 (__arm_vcmlaq_f16): Likewise. 8020 (__arm_vcmlaq_rot180_f16): Likewise. 8021 (__arm_vcmlaq_rot270_f16): Likewise. 8022 (__arm_vcmlaq_rot90_f16): Likewise. 8023 (__arm_vfmaq_f16): Likewise. 8024 (__arm_vfmaq_n_f16): Likewise. 8025 (__arm_vfmasq_n_f16): Likewise. 8026 (__arm_vfmsq_f16): Likewise. 8027 (__arm_vabsq_m_f16): Likewise. 8028 (__arm_vcvtmq_m_s16_f16): Likewise. 8029 (__arm_vcvtnq_m_s16_f16): Likewise. 8030 (__arm_vcvtpq_m_s16_f16): Likewise. 8031 (__arm_vcvtq_m_s16_f16): Likewise. 8032 (__arm_vdupq_m_n_f16): Likewise. 8033 (__arm_vmaxnmaq_m_f16): Likewise. 8034 (__arm_vmaxnmavq_p_f16): Likewise. 8035 (__arm_vmaxnmvq_p_f16): Likewise. 8036 (__arm_vminnmaq_m_f16): Likewise. 8037 (__arm_vminnmavq_p_f16): Likewise. 8038 (__arm_vminnmvq_p_f16): Likewise. 8039 (__arm_vnegq_m_f16): Likewise. 8040 (__arm_vpselq_f16): Likewise. 8041 (__arm_vrev64q_m_f16): Likewise. 8042 (__arm_vrndaq_m_f16): Likewise. 8043 (__arm_vrndmq_m_f16): Likewise. 8044 (__arm_vrndnq_m_f16): Likewise. 8045 (__arm_vrndpq_m_f16): Likewise. 8046 (__arm_vrndq_m_f16): Likewise. 8047 (__arm_vrndxq_m_f16): Likewise. 8048 (__arm_vcmpeqq_m_n_f16): Likewise. 8049 (__arm_vcmpgeq_m_f16): Likewise. 8050 (__arm_vcmpgeq_m_n_f16): Likewise. 8051 (__arm_vcmpgtq_m_f16): Likewise. 8052 (__arm_vcmpgtq_m_n_f16): Likewise. 8053 (__arm_vcmpleq_m_f16): Likewise. 8054 (__arm_vcmpleq_m_n_f16): Likewise. 8055 (__arm_vcmpltq_m_f16): Likewise. 8056 (__arm_vcmpltq_m_n_f16): Likewise. 8057 (__arm_vcmpneq_m_f16): Likewise. 8058 (__arm_vcmpneq_m_n_f16): Likewise. 8059 (__arm_vcvtmq_m_u16_f16): Likewise. 8060 (__arm_vcvtnq_m_u16_f16): Likewise. 8061 (__arm_vcvtpq_m_u16_f16): Likewise. 8062 (__arm_vcvtq_m_u16_f16): Likewise. 8063 (__arm_vcmlaq_f32): Likewise. 8064 (__arm_vcmlaq_rot180_f32): Likewise. 8065 (__arm_vcmlaq_rot270_f32): Likewise. 8066 (__arm_vcmlaq_rot90_f32): Likewise. 8067 (__arm_vfmaq_f32): Likewise. 8068 (__arm_vfmaq_n_f32): Likewise. 8069 (__arm_vfmasq_n_f32): Likewise. 8070 (__arm_vfmsq_f32): Likewise. 8071 (__arm_vabsq_m_f32): Likewise. 8072 (__arm_vcvtmq_m_s32_f32): Likewise. 8073 (__arm_vcvtnq_m_s32_f32): Likewise. 8074 (__arm_vcvtpq_m_s32_f32): Likewise. 8075 (__arm_vcvtq_m_s32_f32): Likewise. 8076 (__arm_vdupq_m_n_f32): Likewise. 8077 (__arm_vmaxnmaq_m_f32): Likewise. 8078 (__arm_vmaxnmavq_p_f32): Likewise. 8079 (__arm_vmaxnmvq_p_f32): Likewise. 8080 (__arm_vminnmaq_m_f32): Likewise. 8081 (__arm_vminnmavq_p_f32): Likewise. 8082 (__arm_vminnmvq_p_f32): Likewise. 8083 (__arm_vnegq_m_f32): Likewise. 8084 (__arm_vpselq_f32): Likewise. 8085 (__arm_vrev64q_m_f32): Likewise. 8086 (__arm_vrndaq_m_f32): Likewise. 8087 (__arm_vrndmq_m_f32): Likewise. 8088 (__arm_vrndnq_m_f32): Likewise. 8089 (__arm_vrndpq_m_f32): Likewise. 8090 (__arm_vrndq_m_f32): Likewise. 8091 (__arm_vrndxq_m_f32): Likewise. 8092 (__arm_vcmpeqq_m_n_f32): Likewise. 8093 (__arm_vcmpgeq_m_f32): Likewise. 8094 (__arm_vcmpgeq_m_n_f32): Likewise. 8095 (__arm_vcmpgtq_m_f32): Likewise. 8096 (__arm_vcmpgtq_m_n_f32): Likewise. 8097 (__arm_vcmpleq_m_f32): Likewise. 8098 (__arm_vcmpleq_m_n_f32): Likewise. 8099 (__arm_vcmpltq_m_f32): Likewise. 8100 (__arm_vcmpltq_m_n_f32): Likewise. 8101 (__arm_vcmpneq_m_f32): Likewise. 8102 (__arm_vcmpneq_m_n_f32): Likewise. 8103 (__arm_vcvtmq_m_u32_f32): Likewise. 8104 (__arm_vcvtnq_m_u32_f32): Likewise. 8105 (__arm_vcvtpq_m_u32_f32): Likewise. 8106 (__arm_vcvtq_m_u32_f32): Likewise. 8107 (vcvtq_m): Define polymorphic variant. 8108 (vabsq_m): Likewise. 8109 (vcmlaq): Likewise. 8110 (vcmlaq_rot180): Likewise. 8111 (vcmlaq_rot270): Likewise. 8112 (vcmlaq_rot90): Likewise. 8113 (vcmpeqq_m_n): Likewise. 8114 (vcmpgeq_m_n): Likewise. 8115 (vrndxq_m): Likewise. 8116 (vrndq_m): Likewise. 8117 (vrndpq_m): Likewise. 8118 (vcmpgtq_m_n): Likewise. 8119 (vcmpgtq_m): Likewise. 8120 (vcmpleq_m): Likewise. 8121 (vcmpleq_m_n): Likewise. 8122 (vcmpltq_m_n): Likewise. 8123 (vcmpltq_m): Likewise. 8124 (vcmpneq_m): Likewise. 8125 (vcmpneq_m_n): Likewise. 8126 (vcvtbq_m): Likewise. 8127 (vcvttq_m): Likewise. 8128 (vcvtmq_m): Likewise. 8129 (vcvtnq_m): Likewise. 8130 (vcvtpq_m): Likewise. 8131 (vdupq_m_n): Likewise. 8132 (vfmaq_n): Likewise. 8133 (vfmaq): Likewise. 8134 (vfmasq_n): Likewise. 8135 (vfmsq): Likewise. 8136 (vmaxnmaq_m): Likewise. 8137 (vmaxnmavq_m): Likewise. 8138 (vmaxnmvq_m): Likewise. 8139 (vmaxnmavq_p): Likewise. 8140 (vmaxnmvq_p): Likewise. 8141 (vminnmaq_m): Likewise. 8142 (vminnmavq_p): Likewise. 8143 (vminnmvq_p): Likewise. 8144 (vrndnq_m): Likewise. 8145 (vrndaq_m): Likewise. 8146 (vrndmq_m): Likewise. 8147 (vrev64q_m): Likewise. 8148 (vrev32q_m): Likewise. 8149 (vpselq): Likewise. 8150 (vnegq_m): Likewise. 8151 (vcmpgeq_m): Likewise. 8152 (vshrntq_n): Likewise. 8153 (vrshrntq_n): Likewise. 8154 (vmovlbq_m): Likewise. 8155 (vmovnbq_m): Likewise. 8156 (vmovntq_m): Likewise. 8157 (vmvnq_m_n): Likewise. 8158 (vmvnq_m): Likewise. 8159 (vshrnbq_n): Likewise. 8160 (vrshrnbq_n): Likewise. 8161 (vqshruntq_n): Likewise. 8162 (vrev16q_m): Likewise. 8163 (vqshrunbq_n): Likewise. 8164 (vqshrntq_n): Likewise. 8165 (vqrshruntq_n): Likewise. 8166 (vqrshrntq_n): Likewise. 8167 (vqshrnbq_n): Likewise. 8168 (vqmovuntq_m): Likewise. 8169 (vqmovntq_m): Likewise. 8170 (vqmovnbq_m): Likewise. 8171 (vorrq_m_n): Likewise. 8172 (vmovltq_m): Likewise. 8173 (vqmovunbq_m): Likewise. 8174 (vaddlvaq_p): Likewise. 8175 (vmlaldavaq): Likewise. 8176 (vmlaldavaxq): Likewise. 8177 (vmlaldavq_p): Likewise. 8178 (vmlaldavxq_p): Likewise. 8179 (vmlsldavaq): Likewise. 8180 (vmlsldavaxq): Likewise. 8181 (vmlsldavq_p): Likewise. 8182 (vmlsldavxq_p): Likewise. 8183 (vrmlaldavhaxq): Likewise. 8184 (vrmlaldavhq_p): Likewise. 8185 (vrmlaldavhxq_p): Likewise. 8186 (vrmlsldavhaq): Likewise. 8187 (vrmlsldavhaxq): Likewise. 8188 (vrmlsldavhq_p): Likewise. 8189 (vrmlsldavhxq_p): Likewise. 8190 * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_IMM_UNONE): Use 8191 builtin qualifier. 8192 (TERNOP_NONE_NONE_NONE_IMM): Likewise. 8193 (TERNOP_NONE_NONE_NONE_NONE): Likewise. 8194 (TERNOP_NONE_NONE_NONE_UNONE): Likewise. 8195 (TERNOP_UNONE_NONE_NONE_UNONE): Likewise. 8196 (TERNOP_UNONE_UNONE_IMM_UNONE): Likewise. 8197 (TERNOP_UNONE_UNONE_NONE_IMM): Likewise. 8198 (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise. 8199 (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise. 8200 (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise. 8201 * config/arm/mve.md (MVE_constraint3): Define mode attribute iterator. 8202 (MVE_pred3): Likewise. 8203 (MVE_constraint1): Likewise. 8204 (MVE_pred1): Likewise. 8205 (VMLALDAVQ_P): Define iterator. 8206 (VQMOVNBQ_M): Likewise. 8207 (VMOVLTQ_M): Likewise. 8208 (VMOVNBQ_M): Likewise. 8209 (VRSHRNTQ_N): Likewise. 8210 (VORRQ_M_N): Likewise. 8211 (VREV32Q_M): Likewise. 8212 (VREV16Q_M): Likewise. 8213 (VQRSHRNTQ_N): Likewise. 8214 (VMOVNTQ_M): Likewise. 8215 (VMOVLBQ_M): Likewise. 8216 (VMLALDAVAQ): Likewise. 8217 (VQSHRNBQ_N): Likewise. 8218 (VSHRNBQ_N): Likewise. 8219 (VRSHRNBQ_N): Likewise. 8220 (VMLALDAVXQ_P): Likewise. 8221 (VQMOVNTQ_M): Likewise. 8222 (VMVNQ_M_N): Likewise. 8223 (VQSHRNTQ_N): Likewise. 8224 (VMLALDAVAXQ): Likewise. 8225 (VSHRNTQ_N): Likewise. 8226 (VCVTMQ_M): Likewise. 8227 (VCVTNQ_M): Likewise. 8228 (VCVTPQ_M): Likewise. 8229 (VCVTQ_M_N_FROM_F): Likewise. 8230 (VCVTQ_M_FROM_F): Likewise. 8231 (VRMLALDAVHQ_P): Likewise. 8232 (VADDLVAQ_P): Likewise. 8233 (mve_vrndq_m_f<mode>): Define RTL pattern. 8234 (mve_vabsq_m_f<mode>): Likewise. 8235 (mve_vaddlvaq_p_<supf>v4si): Likewise. 8236 (mve_vcmlaq_f<mode>): Likewise. 8237 (mve_vcmlaq_rot180_f<mode>): Likewise. 8238 (mve_vcmlaq_rot270_f<mode>): Likewise. 8239 (mve_vcmlaq_rot90_f<mode>): Likewise. 8240 (mve_vcmpeqq_m_n_f<mode>): Likewise. 8241 (mve_vcmpgeq_m_f<mode>): Likewise. 8242 (mve_vcmpgeq_m_n_f<mode>): Likewise. 8243 (mve_vcmpgtq_m_f<mode>): Likewise. 8244 (mve_vcmpgtq_m_n_f<mode>): Likewise. 8245 (mve_vcmpleq_m_f<mode>): Likewise. 8246 (mve_vcmpleq_m_n_f<mode>): Likewise. 8247 (mve_vcmpltq_m_f<mode>): Likewise. 8248 (mve_vcmpltq_m_n_f<mode>): Likewise. 8249 (mve_vcmpneq_m_f<mode>): Likewise. 8250 (mve_vcmpneq_m_n_f<mode>): Likewise. 8251 (mve_vcvtbq_m_f16_f32v8hf): Likewise. 8252 (mve_vcvtbq_m_f32_f16v4sf): Likewise. 8253 (mve_vcvttq_m_f16_f32v8hf): Likewise. 8254 (mve_vcvttq_m_f32_f16v4sf): Likewise. 8255 (mve_vdupq_m_n_f<mode>): Likewise. 8256 (mve_vfmaq_f<mode>): Likewise. 8257 (mve_vfmaq_n_f<mode>): Likewise. 8258 (mve_vfmasq_n_f<mode>): Likewise. 8259 (mve_vfmsq_f<mode>): Likewise. 8260 (mve_vmaxnmaq_m_f<mode>): Likewise. 8261 (mve_vmaxnmavq_p_f<mode>): Likewise. 8262 (mve_vmaxnmvq_p_f<mode>): Likewise. 8263 (mve_vminnmaq_m_f<mode>): Likewise. 8264 (mve_vminnmavq_p_f<mode>): Likewise. 8265 (mve_vminnmvq_p_f<mode>): Likewise. 8266 (mve_vmlaldavaq_<supf><mode>): Likewise. 8267 (mve_vmlaldavaxq_<supf><mode>): Likewise. 8268 (mve_vmlaldavq_p_<supf><mode>): Likewise. 8269 (mve_vmlaldavxq_p_<supf><mode>): Likewise. 8270 (mve_vmlsldavaq_s<mode>): Likewise. 8271 (mve_vmlsldavaxq_s<mode>): Likewise. 8272 (mve_vmlsldavq_p_s<mode>): Likewise. 8273 (mve_vmlsldavxq_p_s<mode>): Likewise. 8274 (mve_vmovlbq_m_<supf><mode>): Likewise. 8275 (mve_vmovltq_m_<supf><mode>): Likewise. 8276 (mve_vmovnbq_m_<supf><mode>): Likewise. 8277 (mve_vmovntq_m_<supf><mode>): Likewise. 8278 (mve_vmvnq_m_n_<supf><mode>): Likewise. 8279 (mve_vnegq_m_f<mode>): Likewise. 8280 (mve_vorrq_m_n_<supf><mode>): Likewise. 8281 (mve_vpselq_f<mode>): Likewise. 8282 (mve_vqmovnbq_m_<supf><mode>): Likewise. 8283 (mve_vqmovntq_m_<supf><mode>): Likewise. 8284 (mve_vqmovunbq_m_s<mode>): Likewise. 8285 (mve_vqmovuntq_m_s<mode>): Likewise. 8286 (mve_vqrshrntq_n_<supf><mode>): Likewise. 8287 (mve_vqrshruntq_n_s<mode>): Likewise. 8288 (mve_vqshrnbq_n_<supf><mode>): Likewise. 8289 (mve_vqshrntq_n_<supf><mode>): Likewise. 8290 (mve_vqshrunbq_n_s<mode>): Likewise. 8291 (mve_vqshruntq_n_s<mode>): Likewise. 8292 (mve_vrev32q_m_fv8hf): Likewise. 8293 (mve_vrev32q_m_<supf><mode>): Likewise. 8294 (mve_vrev64q_m_f<mode>): Likewise. 8295 (mve_vrmlaldavhaxq_sv4si): Likewise. 8296 (mve_vrmlaldavhxq_p_sv4si): Likewise. 8297 (mve_vrmlsldavhaxq_sv4si): Likewise. 8298 (mve_vrmlsldavhq_p_sv4si): Likewise. 8299 (mve_vrmlsldavhxq_p_sv4si): Likewise. 8300 (mve_vrndaq_m_f<mode>): Likewise. 8301 (mve_vrndmq_m_f<mode>): Likewise. 8302 (mve_vrndnq_m_f<mode>): Likewise. 8303 (mve_vrndpq_m_f<mode>): Likewise. 8304 (mve_vrndxq_m_f<mode>): Likewise. 8305 (mve_vrshrnbq_n_<supf><mode>): Likewise. 8306 (mve_vrshrntq_n_<supf><mode>): Likewise. 8307 (mve_vshrnbq_n_<supf><mode>): Likewise. 8308 (mve_vshrntq_n_<supf><mode>): Likewise. 8309 (mve_vcvtmq_m_<supf><mode>): Likewise. 8310 (mve_vcvtpq_m_<supf><mode>): Likewise. 8311 (mve_vcvtnq_m_<supf><mode>): Likewise. 8312 (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise. 8313 (mve_vrev16q_m_<supf>v16qi): Likewise. 8314 (mve_vcvtq_m_from_f_<supf><mode>): Likewise. 8315 (mve_vrmlaldavhq_p_<supf>v4si): Likewise. 8316 (mve_vrmlsldavhaq_sv4si): Likewise. 8317 83182020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> 8319 Mihail Ionescu <mihail.ionescu@arm.com> 8320 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 8321 8322 * config/arm/arm_mve.h (vpselq_u8): Define macro. 8323 (vpselq_s8): Likewise. 8324 (vrev64q_m_u8): Likewise. 8325 (vqrdmlashq_n_u8): Likewise. 8326 (vqrdmlahq_n_u8): Likewise. 8327 (vqdmlahq_n_u8): Likewise. 8328 (vmvnq_m_u8): Likewise. 8329 (vmlasq_n_u8): Likewise. 8330 (vmlaq_n_u8): Likewise. 8331 (vmladavq_p_u8): Likewise. 8332 (vmladavaq_u8): Likewise. 8333 (vminvq_p_u8): Likewise. 8334 (vmaxvq_p_u8): Likewise. 8335 (vdupq_m_n_u8): Likewise. 8336 (vcmpneq_m_u8): Likewise. 8337 (vcmpneq_m_n_u8): Likewise. 8338 (vcmphiq_m_u8): Likewise. 8339 (vcmphiq_m_n_u8): Likewise. 8340 (vcmpeqq_m_u8): Likewise. 8341 (vcmpeqq_m_n_u8): Likewise. 8342 (vcmpcsq_m_u8): Likewise. 8343 (vcmpcsq_m_n_u8): Likewise. 8344 (vclzq_m_u8): Likewise. 8345 (vaddvaq_p_u8): Likewise. 8346 (vsriq_n_u8): Likewise. 8347 (vsliq_n_u8): Likewise. 8348 (vshlq_m_r_u8): Likewise. 8349 (vrshlq_m_n_u8): Likewise. 8350 (vqshlq_m_r_u8): Likewise. 8351 (vqrshlq_m_n_u8): Likewise. 8352 (vminavq_p_s8): Likewise. 8353 (vminaq_m_s8): Likewise. 8354 (vmaxavq_p_s8): Likewise. 8355 (vmaxaq_m_s8): Likewise. 8356 (vcmpneq_m_s8): Likewise. 8357 (vcmpneq_m_n_s8): Likewise. 8358 (vcmpltq_m_s8): Likewise. 8359 (vcmpltq_m_n_s8): Likewise. 8360 (vcmpleq_m_s8): Likewise. 8361 (vcmpleq_m_n_s8): Likewise. 8362 (vcmpgtq_m_s8): Likewise. 8363 (vcmpgtq_m_n_s8): Likewise. 8364 (vcmpgeq_m_s8): Likewise. 8365 (vcmpgeq_m_n_s8): Likewise. 8366 (vcmpeqq_m_s8): Likewise. 8367 (vcmpeqq_m_n_s8): Likewise. 8368 (vshlq_m_r_s8): Likewise. 8369 (vrshlq_m_n_s8): Likewise. 8370 (vrev64q_m_s8): Likewise. 8371 (vqshlq_m_r_s8): Likewise. 8372 (vqrshlq_m_n_s8): Likewise. 8373 (vqnegq_m_s8): Likewise. 8374 (vqabsq_m_s8): Likewise. 8375 (vnegq_m_s8): Likewise. 8376 (vmvnq_m_s8): Likewise. 8377 (vmlsdavxq_p_s8): Likewise. 8378 (vmlsdavq_p_s8): Likewise. 8379 (vmladavxq_p_s8): Likewise. 8380 (vmladavq_p_s8): Likewise. 8381 (vminvq_p_s8): Likewise. 8382 (vmaxvq_p_s8): Likewise. 8383 (vdupq_m_n_s8): Likewise. 8384 (vclzq_m_s8): Likewise. 8385 (vclsq_m_s8): Likewise. 8386 (vaddvaq_p_s8): Likewise. 8387 (vabsq_m_s8): Likewise. 8388 (vqrdmlsdhxq_s8): Likewise. 8389 (vqrdmlsdhq_s8): Likewise. 8390 (vqrdmlashq_n_s8): Likewise. 8391 (vqrdmlahq_n_s8): Likewise. 8392 (vqrdmladhxq_s8): Likewise. 8393 (vqrdmladhq_s8): Likewise. 8394 (vqdmlsdhxq_s8): Likewise. 8395 (vqdmlsdhq_s8): Likewise. 8396 (vqdmlahq_n_s8): Likewise. 8397 (vqdmladhxq_s8): Likewise. 8398 (vqdmladhq_s8): Likewise. 8399 (vmlsdavaxq_s8): Likewise. 8400 (vmlsdavaq_s8): Likewise. 8401 (vmlasq_n_s8): Likewise. 8402 (vmlaq_n_s8): Likewise. 8403 (vmladavaxq_s8): Likewise. 8404 (vmladavaq_s8): Likewise. 8405 (vsriq_n_s8): Likewise. 8406 (vsliq_n_s8): Likewise. 8407 (vpselq_u16): Likewise. 8408 (vpselq_s16): Likewise. 8409 (vrev64q_m_u16): Likewise. 8410 (vqrdmlashq_n_u16): Likewise. 8411 (vqrdmlahq_n_u16): Likewise. 8412 (vqdmlahq_n_u16): Likewise. 8413 (vmvnq_m_u16): Likewise. 8414 (vmlasq_n_u16): Likewise. 8415 (vmlaq_n_u16): Likewise. 8416 (vmladavq_p_u16): Likewise. 8417 (vmladavaq_u16): Likewise. 8418 (vminvq_p_u16): Likewise. 8419 (vmaxvq_p_u16): Likewise. 8420 (vdupq_m_n_u16): Likewise. 8421 (vcmpneq_m_u16): Likewise. 8422 (vcmpneq_m_n_u16): Likewise. 8423 (vcmphiq_m_u16): Likewise. 8424 (vcmphiq_m_n_u16): Likewise. 8425 (vcmpeqq_m_u16): Likewise. 8426 (vcmpeqq_m_n_u16): Likewise. 8427 (vcmpcsq_m_u16): Likewise. 8428 (vcmpcsq_m_n_u16): Likewise. 8429 (vclzq_m_u16): Likewise. 8430 (vaddvaq_p_u16): Likewise. 8431 (vsriq_n_u16): Likewise. 8432 (vsliq_n_u16): Likewise. 8433 (vshlq_m_r_u16): Likewise. 8434 (vrshlq_m_n_u16): Likewise. 8435 (vqshlq_m_r_u16): Likewise. 8436 (vqrshlq_m_n_u16): Likewise. 8437 (vminavq_p_s16): Likewise. 8438 (vminaq_m_s16): Likewise. 8439 (vmaxavq_p_s16): Likewise. 8440 (vmaxaq_m_s16): Likewise. 8441 (vcmpneq_m_s16): Likewise. 8442 (vcmpneq_m_n_s16): Likewise. 8443 (vcmpltq_m_s16): Likewise. 8444 (vcmpltq_m_n_s16): Likewise. 8445 (vcmpleq_m_s16): Likewise. 8446 (vcmpleq_m_n_s16): Likewise. 8447 (vcmpgtq_m_s16): Likewise. 8448 (vcmpgtq_m_n_s16): Likewise. 8449 (vcmpgeq_m_s16): Likewise. 8450 (vcmpgeq_m_n_s16): Likewise. 8451 (vcmpeqq_m_s16): Likewise. 8452 (vcmpeqq_m_n_s16): Likewise. 8453 (vshlq_m_r_s16): Likewise. 8454 (vrshlq_m_n_s16): Likewise. 8455 (vrev64q_m_s16): Likewise. 8456 (vqshlq_m_r_s16): Likewise. 8457 (vqrshlq_m_n_s16): Likewise. 8458 (vqnegq_m_s16): Likewise. 8459 (vqabsq_m_s16): Likewise. 8460 (vnegq_m_s16): Likewise. 8461 (vmvnq_m_s16): Likewise. 8462 (vmlsdavxq_p_s16): Likewise. 8463 (vmlsdavq_p_s16): Likewise. 8464 (vmladavxq_p_s16): Likewise. 8465 (vmladavq_p_s16): Likewise. 8466 (vminvq_p_s16): Likewise. 8467 (vmaxvq_p_s16): Likewise. 8468 (vdupq_m_n_s16): Likewise. 8469 (vclzq_m_s16): Likewise. 8470 (vclsq_m_s16): Likewise. 8471 (vaddvaq_p_s16): Likewise. 8472 (vabsq_m_s16): Likewise. 8473 (vqrdmlsdhxq_s16): Likewise. 8474 (vqrdmlsdhq_s16): Likewise. 8475 (vqrdmlashq_n_s16): Likewise. 8476 (vqrdmlahq_n_s16): Likewise. 8477 (vqrdmladhxq_s16): Likewise. 8478 (vqrdmladhq_s16): Likewise. 8479 (vqdmlsdhxq_s16): Likewise. 8480 (vqdmlsdhq_s16): Likewise. 8481 (vqdmlahq_n_s16): Likewise. 8482 (vqdmladhxq_s16): Likewise. 8483 (vqdmladhq_s16): Likewise. 8484 (vmlsdavaxq_s16): Likewise. 8485 (vmlsdavaq_s16): Likewise. 8486 (vmlasq_n_s16): Likewise. 8487 (vmlaq_n_s16): Likewise. 8488 (vmladavaxq_s16): Likewise. 8489 (vmladavaq_s16): Likewise. 8490 (vsriq_n_s16): Likewise. 8491 (vsliq_n_s16): Likewise. 8492 (vpselq_u32): Likewise. 8493 (vpselq_s32): Likewise. 8494 (vrev64q_m_u32): Likewise. 8495 (vqrdmlashq_n_u32): Likewise. 8496 (vqrdmlahq_n_u32): Likewise. 8497 (vqdmlahq_n_u32): Likewise. 8498 (vmvnq_m_u32): Likewise. 8499 (vmlasq_n_u32): Likewise. 8500 (vmlaq_n_u32): Likewise. 8501 (vmladavq_p_u32): Likewise. 8502 (vmladavaq_u32): Likewise. 8503 (vminvq_p_u32): Likewise. 8504 (vmaxvq_p_u32): Likewise. 8505 (vdupq_m_n_u32): Likewise. 8506 (vcmpneq_m_u32): Likewise. 8507 (vcmpneq_m_n_u32): Likewise. 8508 (vcmphiq_m_u32): Likewise. 8509 (vcmphiq_m_n_u32): Likewise. 8510 (vcmpeqq_m_u32): Likewise. 8511 (vcmpeqq_m_n_u32): Likewise. 8512 (vcmpcsq_m_u32): Likewise. 8513 (vcmpcsq_m_n_u32): Likewise. 8514 (vclzq_m_u32): Likewise. 8515 (vaddvaq_p_u32): Likewise. 8516 (vsriq_n_u32): Likewise. 8517 (vsliq_n_u32): Likewise. 8518 (vshlq_m_r_u32): Likewise. 8519 (vrshlq_m_n_u32): Likewise. 8520 (vqshlq_m_r_u32): Likewise. 8521 (vqrshlq_m_n_u32): Likewise. 8522 (vminavq_p_s32): Likewise. 8523 (vminaq_m_s32): Likewise. 8524 (vmaxavq_p_s32): Likewise. 8525 (vmaxaq_m_s32): Likewise. 8526 (vcmpneq_m_s32): Likewise. 8527 (vcmpneq_m_n_s32): Likewise. 8528 (vcmpltq_m_s32): Likewise. 8529 (vcmpltq_m_n_s32): Likewise. 8530 (vcmpleq_m_s32): Likewise. 8531 (vcmpleq_m_n_s32): Likewise. 8532 (vcmpgtq_m_s32): Likewise. 8533 (vcmpgtq_m_n_s32): Likewise. 8534 (vcmpgeq_m_s32): Likewise. 8535 (vcmpgeq_m_n_s32): Likewise. 8536 (vcmpeqq_m_s32): Likewise. 8537 (vcmpeqq_m_n_s32): Likewise. 8538 (vshlq_m_r_s32): Likewise. 8539 (vrshlq_m_n_s32): Likewise. 8540 (vrev64q_m_s32): Likewise. 8541 (vqshlq_m_r_s32): Likewise. 8542 (vqrshlq_m_n_s32): Likewise. 8543 (vqnegq_m_s32): Likewise. 8544 (vqabsq_m_s32): Likewise. 8545 (vnegq_m_s32): Likewise. 8546 (vmvnq_m_s32): Likewise. 8547 (vmlsdavxq_p_s32): Likewise. 8548 (vmlsdavq_p_s32): Likewise. 8549 (vmladavxq_p_s32): Likewise. 8550 (vmladavq_p_s32): Likewise. 8551 (vminvq_p_s32): Likewise. 8552 (vmaxvq_p_s32): Likewise. 8553 (vdupq_m_n_s32): Likewise. 8554 (vclzq_m_s32): Likewise. 8555 (vclsq_m_s32): Likewise. 8556 (vaddvaq_p_s32): Likewise. 8557 (vabsq_m_s32): Likewise. 8558 (vqrdmlsdhxq_s32): Likewise. 8559 (vqrdmlsdhq_s32): Likewise. 8560 (vqrdmlashq_n_s32): Likewise. 8561 (vqrdmlahq_n_s32): Likewise. 8562 (vqrdmladhxq_s32): Likewise. 8563 (vqrdmladhq_s32): Likewise. 8564 (vqdmlsdhxq_s32): Likewise. 8565 (vqdmlsdhq_s32): Likewise. 8566 (vqdmlahq_n_s32): Likewise. 8567 (vqdmladhxq_s32): Likewise. 8568 (vqdmladhq_s32): Likewise. 8569 (vmlsdavaxq_s32): Likewise. 8570 (vmlsdavaq_s32): Likewise. 8571 (vmlasq_n_s32): Likewise. 8572 (vmlaq_n_s32): Likewise. 8573 (vmladavaxq_s32): Likewise. 8574 (vmladavaq_s32): Likewise. 8575 (vsriq_n_s32): Likewise. 8576 (vsliq_n_s32): Likewise. 8577 (vpselq_u64): Likewise. 8578 (vpselq_s64): Likewise. 8579 (__arm_vpselq_u8): Define intrinsic. 8580 (__arm_vpselq_s8): Likewise. 8581 (__arm_vrev64q_m_u8): Likewise. 8582 (__arm_vqrdmlashq_n_u8): Likewise. 8583 (__arm_vqrdmlahq_n_u8): Likewise. 8584 (__arm_vqdmlahq_n_u8): Likewise. 8585 (__arm_vmvnq_m_u8): Likewise. 8586 (__arm_vmlasq_n_u8): Likewise. 8587 (__arm_vmlaq_n_u8): Likewise. 8588 (__arm_vmladavq_p_u8): Likewise. 8589 (__arm_vmladavaq_u8): Likewise. 8590 (__arm_vminvq_p_u8): Likewise. 8591 (__arm_vmaxvq_p_u8): Likewise. 8592 (__arm_vdupq_m_n_u8): Likewise. 8593 (__arm_vcmpneq_m_u8): Likewise. 8594 (__arm_vcmpneq_m_n_u8): Likewise. 8595 (__arm_vcmphiq_m_u8): Likewise. 8596 (__arm_vcmphiq_m_n_u8): Likewise. 8597 (__arm_vcmpeqq_m_u8): Likewise. 8598 (__arm_vcmpeqq_m_n_u8): Likewise. 8599 (__arm_vcmpcsq_m_u8): Likewise. 8600 (__arm_vcmpcsq_m_n_u8): Likewise. 8601 (__arm_vclzq_m_u8): Likewise. 8602 (__arm_vaddvaq_p_u8): Likewise. 8603 (__arm_vsriq_n_u8): Likewise. 8604 (__arm_vsliq_n_u8): Likewise. 8605 (__arm_vshlq_m_r_u8): Likewise. 8606 (__arm_vrshlq_m_n_u8): Likewise. 8607 (__arm_vqshlq_m_r_u8): Likewise. 8608 (__arm_vqrshlq_m_n_u8): Likewise. 8609 (__arm_vminavq_p_s8): Likewise. 8610 (__arm_vminaq_m_s8): Likewise. 8611 (__arm_vmaxavq_p_s8): Likewise. 8612 (__arm_vmaxaq_m_s8): Likewise. 8613 (__arm_vcmpneq_m_s8): Likewise. 8614 (__arm_vcmpneq_m_n_s8): Likewise. 8615 (__arm_vcmpltq_m_s8): Likewise. 8616 (__arm_vcmpltq_m_n_s8): Likewise. 8617 (__arm_vcmpleq_m_s8): Likewise. 8618 (__arm_vcmpleq_m_n_s8): Likewise. 8619 (__arm_vcmpgtq_m_s8): Likewise. 8620 (__arm_vcmpgtq_m_n_s8): Likewise. 8621 (__arm_vcmpgeq_m_s8): Likewise. 8622 (__arm_vcmpgeq_m_n_s8): Likewise. 8623 (__arm_vcmpeqq_m_s8): Likewise. 8624 (__arm_vcmpeqq_m_n_s8): Likewise. 8625 (__arm_vshlq_m_r_s8): Likewise. 8626 (__arm_vrshlq_m_n_s8): Likewise. 8627 (__arm_vrev64q_m_s8): Likewise. 8628 (__arm_vqshlq_m_r_s8): Likewise. 8629 (__arm_vqrshlq_m_n_s8): Likewise. 8630 (__arm_vqnegq_m_s8): Likewise. 8631 (__arm_vqabsq_m_s8): Likewise. 8632 (__arm_vnegq_m_s8): Likewise. 8633 (__arm_vmvnq_m_s8): Likewise. 8634 (__arm_vmlsdavxq_p_s8): Likewise. 8635 (__arm_vmlsdavq_p_s8): Likewise. 8636 (__arm_vmladavxq_p_s8): Likewise. 8637 (__arm_vmladavq_p_s8): Likewise. 8638 (__arm_vminvq_p_s8): Likewise. 8639 (__arm_vmaxvq_p_s8): Likewise. 8640 (__arm_vdupq_m_n_s8): Likewise. 8641 (__arm_vclzq_m_s8): Likewise. 8642 (__arm_vclsq_m_s8): Likewise. 8643 (__arm_vaddvaq_p_s8): Likewise. 8644 (__arm_vabsq_m_s8): Likewise. 8645 (__arm_vqrdmlsdhxq_s8): Likewise. 8646 (__arm_vqrdmlsdhq_s8): Likewise. 8647 (__arm_vqrdmlashq_n_s8): Likewise. 8648 (__arm_vqrdmlahq_n_s8): Likewise. 8649 (__arm_vqrdmladhxq_s8): Likewise. 8650 (__arm_vqrdmladhq_s8): Likewise. 8651 (__arm_vqdmlsdhxq_s8): Likewise. 8652 (__arm_vqdmlsdhq_s8): Likewise. 8653 (__arm_vqdmlahq_n_s8): Likewise. 8654 (__arm_vqdmladhxq_s8): Likewise. 8655 (__arm_vqdmladhq_s8): Likewise. 8656 (__arm_vmlsdavaxq_s8): Likewise. 8657 (__arm_vmlsdavaq_s8): Likewise. 8658 (__arm_vmlasq_n_s8): Likewise. 8659 (__arm_vmlaq_n_s8): Likewise. 8660 (__arm_vmladavaxq_s8): Likewise. 8661 (__arm_vmladavaq_s8): Likewise. 8662 (__arm_vsriq_n_s8): Likewise. 8663 (__arm_vsliq_n_s8): Likewise. 8664 (__arm_vpselq_u16): Likewise. 8665 (__arm_vpselq_s16): Likewise. 8666 (__arm_vrev64q_m_u16): Likewise. 8667 (__arm_vqrdmlashq_n_u16): Likewise. 8668 (__arm_vqrdmlahq_n_u16): Likewise. 8669 (__arm_vqdmlahq_n_u16): Likewise. 8670 (__arm_vmvnq_m_u16): Likewise. 8671 (__arm_vmlasq_n_u16): Likewise. 8672 (__arm_vmlaq_n_u16): Likewise. 8673 (__arm_vmladavq_p_u16): Likewise. 8674 (__arm_vmladavaq_u16): Likewise. 8675 (__arm_vminvq_p_u16): Likewise. 8676 (__arm_vmaxvq_p_u16): Likewise. 8677 (__arm_vdupq_m_n_u16): Likewise. 8678 (__arm_vcmpneq_m_u16): Likewise. 8679 (__arm_vcmpneq_m_n_u16): Likewise. 8680 (__arm_vcmphiq_m_u16): Likewise. 8681 (__arm_vcmphiq_m_n_u16): Likewise. 8682 (__arm_vcmpeqq_m_u16): Likewise. 8683 (__arm_vcmpeqq_m_n_u16): Likewise. 8684 (__arm_vcmpcsq_m_u16): Likewise. 8685 (__arm_vcmpcsq_m_n_u16): Likewise. 8686 (__arm_vclzq_m_u16): Likewise. 8687 (__arm_vaddvaq_p_u16): Likewise. 8688 (__arm_vsriq_n_u16): Likewise. 8689 (__arm_vsliq_n_u16): Likewise. 8690 (__arm_vshlq_m_r_u16): Likewise. 8691 (__arm_vrshlq_m_n_u16): Likewise. 8692 (__arm_vqshlq_m_r_u16): Likewise. 8693 (__arm_vqrshlq_m_n_u16): Likewise. 8694 (__arm_vminavq_p_s16): Likewise. 8695 (__arm_vminaq_m_s16): Likewise. 8696 (__arm_vmaxavq_p_s16): Likewise. 8697 (__arm_vmaxaq_m_s16): Likewise. 8698 (__arm_vcmpneq_m_s16): Likewise. 8699 (__arm_vcmpneq_m_n_s16): Likewise. 8700 (__arm_vcmpltq_m_s16): Likewise. 8701 (__arm_vcmpltq_m_n_s16): Likewise. 8702 (__arm_vcmpleq_m_s16): Likewise. 8703 (__arm_vcmpleq_m_n_s16): Likewise. 8704 (__arm_vcmpgtq_m_s16): Likewise. 8705 (__arm_vcmpgtq_m_n_s16): Likewise. 8706 (__arm_vcmpgeq_m_s16): Likewise. 8707 (__arm_vcmpgeq_m_n_s16): Likewise. 8708 (__arm_vcmpeqq_m_s16): Likewise. 8709 (__arm_vcmpeqq_m_n_s16): Likewise. 8710 (__arm_vshlq_m_r_s16): Likewise. 8711 (__arm_vrshlq_m_n_s16): Likewise. 8712 (__arm_vrev64q_m_s16): Likewise. 8713 (__arm_vqshlq_m_r_s16): Likewise. 8714 (__arm_vqrshlq_m_n_s16): Likewise. 8715 (__arm_vqnegq_m_s16): Likewise. 8716 (__arm_vqabsq_m_s16): Likewise. 8717 (__arm_vnegq_m_s16): Likewise. 8718 (__arm_vmvnq_m_s16): Likewise. 8719 (__arm_vmlsdavxq_p_s16): Likewise. 8720 (__arm_vmlsdavq_p_s16): Likewise. 8721 (__arm_vmladavxq_p_s16): Likewise. 8722 (__arm_vmladavq_p_s16): Likewise. 8723 (__arm_vminvq_p_s16): Likewise. 8724 (__arm_vmaxvq_p_s16): Likewise. 8725 (__arm_vdupq_m_n_s16): Likewise. 8726 (__arm_vclzq_m_s16): Likewise. 8727 (__arm_vclsq_m_s16): Likewise. 8728 (__arm_vaddvaq_p_s16): Likewise. 8729 (__arm_vabsq_m_s16): Likewise. 8730 (__arm_vqrdmlsdhxq_s16): Likewise. 8731 (__arm_vqrdmlsdhq_s16): Likewise. 8732 (__arm_vqrdmlashq_n_s16): Likewise. 8733 (__arm_vqrdmlahq_n_s16): Likewise. 8734 (__arm_vqrdmladhxq_s16): Likewise. 8735 (__arm_vqrdmladhq_s16): Likewise. 8736 (__arm_vqdmlsdhxq_s16): Likewise. 8737 (__arm_vqdmlsdhq_s16): Likewise. 8738 (__arm_vqdmlahq_n_s16): Likewise. 8739 (__arm_vqdmladhxq_s16): Likewise. 8740 (__arm_vqdmladhq_s16): Likewise. 8741 (__arm_vmlsdavaxq_s16): Likewise. 8742 (__arm_vmlsdavaq_s16): Likewise. 8743 (__arm_vmlasq_n_s16): Likewise. 8744 (__arm_vmlaq_n_s16): Likewise. 8745 (__arm_vmladavaxq_s16): Likewise. 8746 (__arm_vmladavaq_s16): Likewise. 8747 (__arm_vsriq_n_s16): Likewise. 8748 (__arm_vsliq_n_s16): Likewise. 8749 (__arm_vpselq_u32): Likewise. 8750 (__arm_vpselq_s32): Likewise. 8751 (__arm_vrev64q_m_u32): Likewise. 8752 (__arm_vqrdmlashq_n_u32): Likewise. 8753 (__arm_vqrdmlahq_n_u32): Likewise. 8754 (__arm_vqdmlahq_n_u32): Likewise. 8755 (__arm_vmvnq_m_u32): Likewise. 8756 (__arm_vmlasq_n_u32): Likewise. 8757 (__arm_vmlaq_n_u32): Likewise. 8758 (__arm_vmladavq_p_u32): Likewise. 8759 (__arm_vmladavaq_u32): Likewise. 8760 (__arm_vminvq_p_u32): Likewise. 8761 (__arm_vmaxvq_p_u32): Likewise. 8762 (__arm_vdupq_m_n_u32): Likewise. 8763 (__arm_vcmpneq_m_u32): Likewise. 8764 (__arm_vcmpneq_m_n_u32): Likewise. 8765 (__arm_vcmphiq_m_u32): Likewise. 8766 (__arm_vcmphiq_m_n_u32): Likewise. 8767 (__arm_vcmpeqq_m_u32): Likewise. 8768 (__arm_vcmpeqq_m_n_u32): Likewise. 8769 (__arm_vcmpcsq_m_u32): Likewise. 8770 (__arm_vcmpcsq_m_n_u32): Likewise. 8771 (__arm_vclzq_m_u32): Likewise. 8772 (__arm_vaddvaq_p_u32): Likewise. 8773 (__arm_vsriq_n_u32): Likewise. 8774 (__arm_vsliq_n_u32): Likewise. 8775 (__arm_vshlq_m_r_u32): Likewise. 8776 (__arm_vrshlq_m_n_u32): Likewise. 8777 (__arm_vqshlq_m_r_u32): Likewise. 8778 (__arm_vqrshlq_m_n_u32): Likewise. 8779 (__arm_vminavq_p_s32): Likewise. 8780 (__arm_vminaq_m_s32): Likewise. 8781 (__arm_vmaxavq_p_s32): Likewise. 8782 (__arm_vmaxaq_m_s32): Likewise. 8783 (__arm_vcmpneq_m_s32): Likewise. 8784 (__arm_vcmpneq_m_n_s32): Likewise. 8785 (__arm_vcmpltq_m_s32): Likewise. 8786 (__arm_vcmpltq_m_n_s32): Likewise. 8787 (__arm_vcmpleq_m_s32): Likewise. 8788 (__arm_vcmpleq_m_n_s32): Likewise. 8789 (__arm_vcmpgtq_m_s32): Likewise. 8790 (__arm_vcmpgtq_m_n_s32): Likewise. 8791 (__arm_vcmpgeq_m_s32): Likewise. 8792 (__arm_vcmpgeq_m_n_s32): Likewise. 8793 (__arm_vcmpeqq_m_s32): Likewise. 8794 (__arm_vcmpeqq_m_n_s32): Likewise. 8795 (__arm_vshlq_m_r_s32): Likewise. 8796 (__arm_vrshlq_m_n_s32): Likewise. 8797 (__arm_vrev64q_m_s32): Likewise. 8798 (__arm_vqshlq_m_r_s32): Likewise. 8799 (__arm_vqrshlq_m_n_s32): Likewise. 8800 (__arm_vqnegq_m_s32): Likewise. 8801 (__arm_vqabsq_m_s32): Likewise. 8802 (__arm_vnegq_m_s32): Likewise. 8803 (__arm_vmvnq_m_s32): Likewise. 8804 (__arm_vmlsdavxq_p_s32): Likewise. 8805 (__arm_vmlsdavq_p_s32): Likewise. 8806 (__arm_vmladavxq_p_s32): Likewise. 8807 (__arm_vmladavq_p_s32): Likewise. 8808 (__arm_vminvq_p_s32): Likewise. 8809 (__arm_vmaxvq_p_s32): Likewise. 8810 (__arm_vdupq_m_n_s32): Likewise. 8811 (__arm_vclzq_m_s32): Likewise. 8812 (__arm_vclsq_m_s32): Likewise. 8813 (__arm_vaddvaq_p_s32): Likewise. 8814 (__arm_vabsq_m_s32): Likewise. 8815 (__arm_vqrdmlsdhxq_s32): Likewise. 8816 (__arm_vqrdmlsdhq_s32): Likewise. 8817 (__arm_vqrdmlashq_n_s32): Likewise. 8818 (__arm_vqrdmlahq_n_s32): Likewise. 8819 (__arm_vqrdmladhxq_s32): Likewise. 8820 (__arm_vqrdmladhq_s32): Likewise. 8821 (__arm_vqdmlsdhxq_s32): Likewise. 8822 (__arm_vqdmlsdhq_s32): Likewise. 8823 (__arm_vqdmlahq_n_s32): Likewise. 8824 (__arm_vqdmladhxq_s32): Likewise. 8825 (__arm_vqdmladhq_s32): Likewise. 8826 (__arm_vmlsdavaxq_s32): Likewise. 8827 (__arm_vmlsdavaq_s32): Likewise. 8828 (__arm_vmlasq_n_s32): Likewise. 8829 (__arm_vmlaq_n_s32): Likewise. 8830 (__arm_vmladavaxq_s32): Likewise. 8831 (__arm_vmladavaq_s32): Likewise. 8832 (__arm_vsriq_n_s32): Likewise. 8833 (__arm_vsliq_n_s32): Likewise. 8834 (__arm_vpselq_u64): Likewise. 8835 (__arm_vpselq_s64): Likewise. 8836 (vcmpneq_m_n): Define polymorphic variant. 8837 (vcmpneq_m): Likewise. 8838 (vqrdmlsdhq): Likewise. 8839 (vqrdmlsdhxq): Likewise. 8840 (vqrshlq_m_n): Likewise. 8841 (vqshlq_m_r): Likewise. 8842 (vrev64q_m): Likewise. 8843 (vrshlq_m_n): Likewise. 8844 (vshlq_m_r): Likewise. 8845 (vsliq_n): Likewise. 8846 (vsriq_n): Likewise. 8847 (vqrdmlashq_n): Likewise. 8848 (vqrdmlahq): Likewise. 8849 (vqrdmladhxq): Likewise. 8850 (vqrdmladhq): Likewise. 8851 (vqnegq_m): Likewise. 8852 (vqdmlsdhxq): Likewise. 8853 (vabsq_m): Likewise. 8854 (vclsq_m): Likewise. 8855 (vclzq_m): Likewise. 8856 (vcmpgeq_m): Likewise. 8857 (vcmpgeq_m_n): Likewise. 8858 (vdupq_m_n): Likewise. 8859 (vmaxaq_m): Likewise. 8860 (vmlaq_n): Likewise. 8861 (vmlasq_n): Likewise. 8862 (vmvnq_m): Likewise. 8863 (vnegq_m): Likewise. 8864 (vpselq): Likewise. 8865 (vqdmlahq_n): Likewise. 8866 (vqrdmlahq_n): Likewise. 8867 (vqdmlsdhq): Likewise. 8868 (vqdmladhq): Likewise. 8869 (vqabsq_m): Likewise. 8870 (vminaq_m): Likewise. 8871 (vrmlaldavhaq): Likewise. 8872 (vmlsdavxq_p): Likewise. 8873 (vmlsdavq_p): Likewise. 8874 (vmlsdavaxq): Likewise. 8875 (vmlsdavaq): Likewise. 8876 (vaddvaq_p): Likewise. 8877 (vcmpcsq_m_n): Likewise. 8878 (vcmpcsq_m): Likewise. 8879 (vcmpeqq_m_n): Likewise. 8880 (vcmpeqq_m): Likewise. 8881 (vmladavxq_p): Likewise. 8882 (vmladavq_p): Likewise. 8883 (vmladavaxq): Likewise. 8884 (vmladavaq): Likewise. 8885 (vminvq_p): Likewise. 8886 (vminavq_p): Likewise. 8887 (vmaxvq_p): Likewise. 8888 (vmaxavq_p): Likewise. 8889 (vcmpltq_m_n): Likewise. 8890 (vcmpltq_m): Likewise. 8891 (vcmpleq_m): Likewise. 8892 (vcmpleq_m_n): Likewise. 8893 (vcmphiq_m_n): Likewise. 8894 (vcmphiq_m): Likewise. 8895 (vcmpgtq_m_n): Likewise. 8896 (vcmpgtq_m): Likewise. 8897 * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_NONE_IMM): Use 8898 builtin qualifier. 8899 (TERNOP_NONE_NONE_NONE_NONE): Likewise. 8900 (TERNOP_NONE_NONE_NONE_UNONE): Likewise. 8901 (TERNOP_UNONE_NONE_NONE_UNONE): Likewise. 8902 (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise. 8903 (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise. 8904 (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise. 8905 * config/arm/constraints.md (Rc): Define constraint to check constant is 8906 in the range of 0 to 15. 8907 (Re): Define constraint to check constant is in the range of 0 to 31. 8908 * config/arm/mve.md (VADDVAQ_P): Define iterator. 8909 (VCLZQ_M): Likewise. 8910 (VCMPEQQ_M_N): Likewise. 8911 (VCMPEQQ_M): Likewise. 8912 (VCMPNEQ_M_N): Likewise. 8913 (VCMPNEQ_M): Likewise. 8914 (VDUPQ_M_N): Likewise. 8915 (VMAXVQ_P): Likewise. 8916 (VMINVQ_P): Likewise. 8917 (VMLADAVAQ): Likewise. 8918 (VMLADAVQ_P): Likewise. 8919 (VMLAQ_N): Likewise. 8920 (VMLASQ_N): Likewise. 8921 (VMVNQ_M): Likewise. 8922 (VPSELQ): Likewise. 8923 (VQDMLAHQ_N): Likewise. 8924 (VQRDMLAHQ_N): Likewise. 8925 (VQRDMLASHQ_N): Likewise. 8926 (VQRSHLQ_M_N): Likewise. 8927 (VQSHLQ_M_R): Likewise. 8928 (VREV64Q_M): Likewise. 8929 (VRSHLQ_M_N): Likewise. 8930 (VSHLQ_M_R): Likewise. 8931 (VSLIQ_N): Likewise. 8932 (VSRIQ_N): Likewise. 8933 (mve_vabsq_m_s<mode>): Define RTL pattern. 8934 (mve_vaddvaq_p_<supf><mode>): Likewise. 8935 (mve_vclsq_m_s<mode>): Likewise. 8936 (mve_vclzq_m_<supf><mode>): Likewise. 8937 (mve_vcmpcsq_m_n_u<mode>): Likewise. 8938 (mve_vcmpcsq_m_u<mode>): Likewise. 8939 (mve_vcmpeqq_m_n_<supf><mode>): Likewise. 8940 (mve_vcmpeqq_m_<supf><mode>): Likewise. 8941 (mve_vcmpgeq_m_n_s<mode>): Likewise. 8942 (mve_vcmpgeq_m_s<mode>): Likewise. 8943 (mve_vcmpgtq_m_n_s<mode>): Likewise. 8944 (mve_vcmpgtq_m_s<mode>): Likewise. 8945 (mve_vcmphiq_m_n_u<mode>): Likewise. 8946 (mve_vcmphiq_m_u<mode>): Likewise. 8947 (mve_vcmpleq_m_n_s<mode>): Likewise. 8948 (mve_vcmpleq_m_s<mode>): Likewise. 8949 (mve_vcmpltq_m_n_s<mode>): Likewise. 8950 (mve_vcmpltq_m_s<mode>): Likewise. 8951 (mve_vcmpneq_m_n_<supf><mode>): Likewise. 8952 (mve_vcmpneq_m_<supf><mode>): Likewise. 8953 (mve_vdupq_m_n_<supf><mode>): Likewise. 8954 (mve_vmaxaq_m_s<mode>): Likewise. 8955 (mve_vmaxavq_p_s<mode>): Likewise. 8956 (mve_vmaxvq_p_<supf><mode>): Likewise. 8957 (mve_vminaq_m_s<mode>): Likewise. 8958 (mve_vminavq_p_s<mode>): Likewise. 8959 (mve_vminvq_p_<supf><mode>): Likewise. 8960 (mve_vmladavaq_<supf><mode>): Likewise. 8961 (mve_vmladavq_p_<supf><mode>): Likewise. 8962 (mve_vmladavxq_p_s<mode>): Likewise. 8963 (mve_vmlaq_n_<supf><mode>): Likewise. 8964 (mve_vmlasq_n_<supf><mode>): Likewise. 8965 (mve_vmlsdavq_p_s<mode>): Likewise. 8966 (mve_vmlsdavxq_p_s<mode>): Likewise. 8967 (mve_vmvnq_m_<supf><mode>): Likewise. 8968 (mve_vnegq_m_s<mode>): Likewise. 8969 (mve_vpselq_<supf><mode>): Likewise. 8970 (mve_vqabsq_m_s<mode>): Likewise. 8971 (mve_vqdmlahq_n_<supf><mode>): Likewise. 8972 (mve_vqnegq_m_s<mode>): Likewise. 8973 (mve_vqrdmladhq_s<mode>): Likewise. 8974 (mve_vqrdmladhxq_s<mode>): Likewise. 8975 (mve_vqrdmlahq_n_<supf><mode>): Likewise. 8976 (mve_vqrdmlashq_n_<supf><mode>): Likewise. 8977 (mve_vqrdmlsdhq_s<mode>): Likewise. 8978 (mve_vqrdmlsdhxq_s<mode>): Likewise. 8979 (mve_vqrshlq_m_n_<supf><mode>): Likewise. 8980 (mve_vqshlq_m_r_<supf><mode>): Likewise. 8981 (mve_vrev64q_m_<supf><mode>): Likewise. 8982 (mve_vrshlq_m_n_<supf><mode>): Likewise. 8983 (mve_vshlq_m_r_<supf><mode>): Likewise. 8984 (mve_vsliq_n_<supf><mode>): Likewise. 8985 (mve_vsriq_n_<supf><mode>): Likewise. 8986 (mve_vqdmlsdhxq_s<mode>): Likewise. 8987 (mve_vqdmlsdhq_s<mode>): Likewise. 8988 (mve_vqdmladhxq_s<mode>): Likewise. 8989 (mve_vqdmladhq_s<mode>): Likewise. 8990 (mve_vmlsdavaxq_s<mode>): Likewise. 8991 (mve_vmlsdavaq_s<mode>): Likewise. 8992 (mve_vmladavaxq_s<mode>): Likewise. 8993 * config/arm/predicates.md (mve_imm_15):Define predicate to check the 8994 matching constraint Rc. 8995 (mve_imm_31): Define predicate to check the matching constraint Re. 8996 89972020-03-18 Andrew Stubbs <ams@codesourcery.com> 8998 8999 * config/gcn/gcn-valu.md (vec_cmp<mode>di): Set operand 1 to DImode. 9000 (vec_cmp<mode>di_dup): Likewise. 9001 * config/gcn/gcn.h (STORE_FLAG_VALUE): Set to -1. 9002 90032020-03-18 Andrew Stubbs <ams@codesourcery.com> 9004 9005 * config/gcn/gcn-valu.md (COND_MODE): Delete. 9006 (COND_INT_MODE): Delete. 9007 (cond_op): Add "mult". 9008 (cond_<expander><mode>): Use VEC_ALLREG_MODE. 9009 (cond_<expander><mode>): Use VEC_ALLREG_INT_MODE. 9010 90112020-03-18 Richard Biener <rguenther@suse.de> 9012 9013 PR middle-end/94206 9014 * gimple-fold.c (gimple_fold_builtin_memset): Avoid using 9015 partial int modes or not mode-precision integer types for 9016 the store. 9017 90182020-03-18 Jakub Jelinek <jakub@redhat.com> 9019 9020 * asan.c (get_mem_refs_of_builtin_call): Fix up duplicated word issue 9021 in a comment. 9022 * config/arc/arc.c (frame_stack_add): Likewise. 9023 * gimple-loop-versioning.cc (loop_versioning::analyze_arbitrary_term): 9024 Likewise. 9025 * ipa-predicate.c (predicate::remap_after_inlining): Likewise. 9026 * tree-ssa-strlen.h (handle_printf_call): Likewise. 9027 * tree-ssa-strlen.c (is_strlen_related_p): Likewise. 9028 * optinfo-emit-json.cc (optrecord_json_writer::add_record): Likewise. 9029 90302020-03-18 Duan bo <duanbo3@huawei.com> 9031 9032 PR target/94201 9033 * config/aarch64/aarch64.md (ldr_got_tiny): Delete. 9034 (@ldr_got_tiny_<mode>): New pattern. 9035 (ldr_got_tiny_sidi): Likewise. 9036 * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Use 9037 them to handle SYMBOL_TINY_GOT for ILP32. 9038 90392020-03-18 Richard Sandiford <richard.sandiford@arm.com> 9040 9041 * config/aarch64/aarch64.c (aarch64_sve_abi): Treat p12-p15 as 9042 call-preserved for SVE PCS functions. 9043 (aarch64_layout_frame): Cope with up to 12 predicate save slots. 9044 Optimize the case in which there are no following vector save slots. 9045 90462020-03-18 Richard Biener <rguenther@suse.de> 9047 9048 PR middle-end/94188 9049 * fold-const.c (build_fold_addr_expr): Convert address to 9050 correct type. 9051 * asan.c (maybe_create_ssa_name): Strip useless type conversions. 9052 * gimple-fold.c (gimple_fold_stmt_to_constant_1): Use build1 9053 to build the ADDR_EXPR which we don't really want to simplify. 9054 * tree-ssa-dom.c (record_equivalences_from_stmt): Likewise. 9055 * tree-ssa-loop-im.c (gather_mem_refs_stmt): Likewise. 9056 * tree-ssa-forwprop.c (forward_propagate_addr_expr_1): Likewise. 9057 (simplify_builtin_call): Strip useless type conversions. 9058 * tree-ssa-strlen.c (new_strinfo): Likewise. 9059 90602020-03-17 Alexey Neyman <stilor@att.net> 9061 9062 PR debug/93751 9063 * dwarf2out.c (gen_decl_die): Proceed to generating the DIE if 9064 the debug level is terse and the declaration is public. Do not 9065 generate type info. 9066 (dwarf2out_decl): Same. 9067 (add_type_attribute): Return immediately if debug level is 9068 terse. 9069 90702020-03-17 Richard Sandiford <richard.sandiford@arm.com> 9071 9072 * config/aarch64/iterators.md (Vmtype): Handle V4BF and V8BF. 9073 90742020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com> 9075 Mihail Ionescu <mihail.ionescu@arm.com> 9076 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 9077 9078 * config/arm/arm-builtins.c (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS): 9079 Define qualifier for ternary operands. 9080 (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise. 9081 (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise. 9082 (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise. 9083 (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise. 9084 (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise. 9085 (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. 9086 (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. 9087 (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise. 9088 (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. 9089 (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. 9090 (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise. 9091 (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. 9092 (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise. 9093 * config/arm/arm_mve.h (vabavq_s8): Define macro. 9094 (vabavq_s16): Likewise. 9095 (vabavq_s32): Likewise. 9096 (vbicq_m_n_s16): Likewise. 9097 (vbicq_m_n_s32): Likewise. 9098 (vbicq_m_n_u16): Likewise. 9099 (vbicq_m_n_u32): Likewise. 9100 (vcmpeqq_m_f16): Likewise. 9101 (vcmpeqq_m_f32): Likewise. 9102 (vcvtaq_m_s16_f16): Likewise. 9103 (vcvtaq_m_u16_f16): Likewise. 9104 (vcvtaq_m_s32_f32): Likewise. 9105 (vcvtaq_m_u32_f32): Likewise. 9106 (vcvtq_m_f16_s16): Likewise. 9107 (vcvtq_m_f16_u16): Likewise. 9108 (vcvtq_m_f32_s32): Likewise. 9109 (vcvtq_m_f32_u32): Likewise. 9110 (vqrshrnbq_n_s16): Likewise. 9111 (vqrshrnbq_n_u16): Likewise. 9112 (vqrshrnbq_n_s32): Likewise. 9113 (vqrshrnbq_n_u32): Likewise. 9114 (vqrshrunbq_n_s16): Likewise. 9115 (vqrshrunbq_n_s32): Likewise. 9116 (vrmlaldavhaq_s32): Likewise. 9117 (vrmlaldavhaq_u32): Likewise. 9118 (vshlcq_s8): Likewise. 9119 (vshlcq_u8): Likewise. 9120 (vshlcq_s16): Likewise. 9121 (vshlcq_u16): Likewise. 9122 (vshlcq_s32): Likewise. 9123 (vshlcq_u32): Likewise. 9124 (vabavq_u8): Likewise. 9125 (vabavq_u16): Likewise. 9126 (vabavq_u32): Likewise. 9127 (__arm_vabavq_s8): Define intrinsic. 9128 (__arm_vabavq_s16): Likewise. 9129 (__arm_vabavq_s32): Likewise. 9130 (__arm_vabavq_u8): Likewise. 9131 (__arm_vabavq_u16): Likewise. 9132 (__arm_vabavq_u32): Likewise. 9133 (__arm_vbicq_m_n_s16): Likewise. 9134 (__arm_vbicq_m_n_s32): Likewise. 9135 (__arm_vbicq_m_n_u16): Likewise. 9136 (__arm_vbicq_m_n_u32): Likewise. 9137 (__arm_vqrshrnbq_n_s16): Likewise. 9138 (__arm_vqrshrnbq_n_u16): Likewise. 9139 (__arm_vqrshrnbq_n_s32): Likewise. 9140 (__arm_vqrshrnbq_n_u32): Likewise. 9141 (__arm_vqrshrunbq_n_s16): Likewise. 9142 (__arm_vqrshrunbq_n_s32): Likewise. 9143 (__arm_vrmlaldavhaq_s32): Likewise. 9144 (__arm_vrmlaldavhaq_u32): Likewise. 9145 (__arm_vshlcq_s8): Likewise. 9146 (__arm_vshlcq_u8): Likewise. 9147 (__arm_vshlcq_s16): Likewise. 9148 (__arm_vshlcq_u16): Likewise. 9149 (__arm_vshlcq_s32): Likewise. 9150 (__arm_vshlcq_u32): Likewise. 9151 (__arm_vcmpeqq_m_f16): Likewise. 9152 (__arm_vcmpeqq_m_f32): Likewise. 9153 (__arm_vcvtaq_m_s16_f16): Likewise. 9154 (__arm_vcvtaq_m_u16_f16): Likewise. 9155 (__arm_vcvtaq_m_s32_f32): Likewise. 9156 (__arm_vcvtaq_m_u32_f32): Likewise. 9157 (__arm_vcvtq_m_f16_s16): Likewise. 9158 (__arm_vcvtq_m_f16_u16): Likewise. 9159 (__arm_vcvtq_m_f32_s32): Likewise. 9160 (__arm_vcvtq_m_f32_u32): Likewise. 9161 (vcvtaq_m): Define polymorphic variant. 9162 (vcvtq_m): Likewise. 9163 (vabavq): Likewise. 9164 (vshlcq): Likewise. 9165 (vbicq_m_n): Likewise. 9166 (vqrshrnbq_n): Likewise. 9167 (vqrshrunbq_n): Likewise. 9168 * config/arm/arm_mve_builtins.def 9169 (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS): Use the builtin qualifer. 9170 (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise. 9171 (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise. 9172 (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise. 9173 (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise. 9174 (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise. 9175 (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. 9176 (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. 9177 (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise. 9178 (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. 9179 (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. 9180 (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise. 9181 (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. 9182 (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise. 9183 * config/arm/mve.md (VBICQ_M_N): Define iterator. 9184 (VCVTAQ_M): Likewise. 9185 (VCVTQ_M_TO_F): Likewise. 9186 (VQRSHRNBQ_N): Likewise. 9187 (VABAVQ): Likewise. 9188 (VSHLCQ): Likewise. 9189 (VRMLALDAVHAQ): Likewise. 9190 (mve_vbicq_m_n_<supf><mode>): Define RTL pattern. 9191 (mve_vcmpeqq_m_f<mode>): Likewise. 9192 (mve_vcvtaq_m_<supf><mode>): Likewise. 9193 (mve_vcvtq_m_to_f_<supf><mode>): Likewise. 9194 (mve_vqrshrnbq_n_<supf><mode>): Likewise. 9195 (mve_vqrshrunbq_n_s<mode>): Likewise. 9196 (mve_vrmlaldavhaq_<supf>v4si): Likewise. 9197 (mve_vabavq_<supf><mode>): Likewise. 9198 (mve_vshlcq_<supf><mode>): Likewise. 9199 (mve_vshlcq_<supf><mode>): Likewise. 9200 (mve_vshlcq_vec_<supf><mode>): Define RTL expand. 9201 (mve_vshlcq_carry_<supf><mode>): Likewise. 9202 92032020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com> 9204 Mihail Ionescu <mihail.ionescu@arm.com> 9205 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 9206 9207 * config/arm/arm_mve.h (vqmovntq_u16): Define macro. 9208 (vqmovnbq_u16): Likewise. 9209 (vmulltq_poly_p8): Likewise. 9210 (vmullbq_poly_p8): Likewise. 9211 (vmovntq_u16): Likewise. 9212 (vmovnbq_u16): Likewise. 9213 (vmlaldavxq_u16): Likewise. 9214 (vmlaldavq_u16): Likewise. 9215 (vqmovuntq_s16): Likewise. 9216 (vqmovunbq_s16): Likewise. 9217 (vshlltq_n_u8): Likewise. 9218 (vshllbq_n_u8): Likewise. 9219 (vorrq_n_u16): Likewise. 9220 (vbicq_n_u16): Likewise. 9221 (vcmpneq_n_f16): Likewise. 9222 (vcmpneq_f16): Likewise. 9223 (vcmpltq_n_f16): Likewise. 9224 (vcmpltq_f16): Likewise. 9225 (vcmpleq_n_f16): Likewise. 9226 (vcmpleq_f16): Likewise. 9227 (vcmpgtq_n_f16): Likewise. 9228 (vcmpgtq_f16): Likewise. 9229 (vcmpgeq_n_f16): Likewise. 9230 (vcmpgeq_f16): Likewise. 9231 (vcmpeqq_n_f16): Likewise. 9232 (vcmpeqq_f16): Likewise. 9233 (vsubq_f16): Likewise. 9234 (vqmovntq_s16): Likewise. 9235 (vqmovnbq_s16): Likewise. 9236 (vqdmulltq_s16): Likewise. 9237 (vqdmulltq_n_s16): Likewise. 9238 (vqdmullbq_s16): Likewise. 9239 (vqdmullbq_n_s16): Likewise. 9240 (vorrq_f16): Likewise. 9241 (vornq_f16): Likewise. 9242 (vmulq_n_f16): Likewise. 9243 (vmulq_f16): Likewise. 9244 (vmovntq_s16): Likewise. 9245 (vmovnbq_s16): Likewise. 9246 (vmlsldavxq_s16): Likewise. 9247 (vmlsldavq_s16): Likewise. 9248 (vmlaldavxq_s16): Likewise. 9249 (vmlaldavq_s16): Likewise. 9250 (vminnmvq_f16): Likewise. 9251 (vminnmq_f16): Likewise. 9252 (vminnmavq_f16): Likewise. 9253 (vminnmaq_f16): Likewise. 9254 (vmaxnmvq_f16): Likewise. 9255 (vmaxnmq_f16): Likewise. 9256 (vmaxnmavq_f16): Likewise. 9257 (vmaxnmaq_f16): Likewise. 9258 (veorq_f16): Likewise. 9259 (vcmulq_rot90_f16): Likewise. 9260 (vcmulq_rot270_f16): Likewise. 9261 (vcmulq_rot180_f16): Likewise. 9262 (vcmulq_f16): Likewise. 9263 (vcaddq_rot90_f16): Likewise. 9264 (vcaddq_rot270_f16): Likewise. 9265 (vbicq_f16): Likewise. 9266 (vandq_f16): Likewise. 9267 (vaddq_n_f16): Likewise. 9268 (vabdq_f16): Likewise. 9269 (vshlltq_n_s8): Likewise. 9270 (vshllbq_n_s8): Likewise. 9271 (vorrq_n_s16): Likewise. 9272 (vbicq_n_s16): Likewise. 9273 (vqmovntq_u32): Likewise. 9274 (vqmovnbq_u32): Likewise. 9275 (vmulltq_poly_p16): Likewise. 9276 (vmullbq_poly_p16): Likewise. 9277 (vmovntq_u32): Likewise. 9278 (vmovnbq_u32): Likewise. 9279 (vmlaldavxq_u32): Likewise. 9280 (vmlaldavq_u32): Likewise. 9281 (vqmovuntq_s32): Likewise. 9282 (vqmovunbq_s32): Likewise. 9283 (vshlltq_n_u16): Likewise. 9284 (vshllbq_n_u16): Likewise. 9285 (vorrq_n_u32): Likewise. 9286 (vbicq_n_u32): Likewise. 9287 (vcmpneq_n_f32): Likewise. 9288 (vcmpneq_f32): Likewise. 9289 (vcmpltq_n_f32): Likewise. 9290 (vcmpltq_f32): Likewise. 9291 (vcmpleq_n_f32): Likewise. 9292 (vcmpleq_f32): Likewise. 9293 (vcmpgtq_n_f32): Likewise. 9294 (vcmpgtq_f32): Likewise. 9295 (vcmpgeq_n_f32): Likewise. 9296 (vcmpgeq_f32): Likewise. 9297 (vcmpeqq_n_f32): Likewise. 9298 (vcmpeqq_f32): Likewise. 9299 (vsubq_f32): Likewise. 9300 (vqmovntq_s32): Likewise. 9301 (vqmovnbq_s32): Likewise. 9302 (vqdmulltq_s32): Likewise. 9303 (vqdmulltq_n_s32): Likewise. 9304 (vqdmullbq_s32): Likewise. 9305 (vqdmullbq_n_s32): Likewise. 9306 (vorrq_f32): Likewise. 9307 (vornq_f32): Likewise. 9308 (vmulq_n_f32): Likewise. 9309 (vmulq_f32): Likewise. 9310 (vmovntq_s32): Likewise. 9311 (vmovnbq_s32): Likewise. 9312 (vmlsldavxq_s32): Likewise. 9313 (vmlsldavq_s32): Likewise. 9314 (vmlaldavxq_s32): Likewise. 9315 (vmlaldavq_s32): Likewise. 9316 (vminnmvq_f32): Likewise. 9317 (vminnmq_f32): Likewise. 9318 (vminnmavq_f32): Likewise. 9319 (vminnmaq_f32): Likewise. 9320 (vmaxnmvq_f32): Likewise. 9321 (vmaxnmq_f32): Likewise. 9322 (vmaxnmavq_f32): Likewise. 9323 (vmaxnmaq_f32): Likewise. 9324 (veorq_f32): Likewise. 9325 (vcmulq_rot90_f32): Likewise. 9326 (vcmulq_rot270_f32): Likewise. 9327 (vcmulq_rot180_f32): Likewise. 9328 (vcmulq_f32): Likewise. 9329 (vcaddq_rot90_f32): Likewise. 9330 (vcaddq_rot270_f32): Likewise. 9331 (vbicq_f32): Likewise. 9332 (vandq_f32): Likewise. 9333 (vaddq_n_f32): Likewise. 9334 (vabdq_f32): Likewise. 9335 (vshlltq_n_s16): Likewise. 9336 (vshllbq_n_s16): Likewise. 9337 (vorrq_n_s32): Likewise. 9338 (vbicq_n_s32): Likewise. 9339 (vrmlaldavhq_u32): Likewise. 9340 (vctp8q_m): Likewise. 9341 (vctp64q_m): Likewise. 9342 (vctp32q_m): Likewise. 9343 (vctp16q_m): Likewise. 9344 (vaddlvaq_u32): Likewise. 9345 (vrmlsldavhxq_s32): Likewise. 9346 (vrmlsldavhq_s32): Likewise. 9347 (vrmlaldavhxq_s32): Likewise. 9348 (vrmlaldavhq_s32): Likewise. 9349 (vcvttq_f16_f32): Likewise. 9350 (vcvtbq_f16_f32): Likewise. 9351 (vaddlvaq_s32): Likewise. 9352 (__arm_vqmovntq_u16): Define intrinsic. 9353 (__arm_vqmovnbq_u16): Likewise. 9354 (__arm_vmulltq_poly_p8): Likewise. 9355 (__arm_vmullbq_poly_p8): Likewise. 9356 (__arm_vmovntq_u16): Likewise. 9357 (__arm_vmovnbq_u16): Likewise. 9358 (__arm_vmlaldavxq_u16): Likewise. 9359 (__arm_vmlaldavq_u16): Likewise. 9360 (__arm_vqmovuntq_s16): Likewise. 9361 (__arm_vqmovunbq_s16): Likewise. 9362 (__arm_vshlltq_n_u8): Likewise. 9363 (__arm_vshllbq_n_u8): Likewise. 9364 (__arm_vorrq_n_u16): Likewise. 9365 (__arm_vbicq_n_u16): Likewise. 9366 (__arm_vcmpneq_n_f16): Likewise. 9367 (__arm_vcmpneq_f16): Likewise. 9368 (__arm_vcmpltq_n_f16): Likewise. 9369 (__arm_vcmpltq_f16): Likewise. 9370 (__arm_vcmpleq_n_f16): Likewise. 9371 (__arm_vcmpleq_f16): Likewise. 9372 (__arm_vcmpgtq_n_f16): Likewise. 9373 (__arm_vcmpgtq_f16): Likewise. 9374 (__arm_vcmpgeq_n_f16): Likewise. 9375 (__arm_vcmpgeq_f16): Likewise. 9376 (__arm_vcmpeqq_n_f16): Likewise. 9377 (__arm_vcmpeqq_f16): Likewise. 9378 (__arm_vsubq_f16): Likewise. 9379 (__arm_vqmovntq_s16): Likewise. 9380 (__arm_vqmovnbq_s16): Likewise. 9381 (__arm_vqdmulltq_s16): Likewise. 9382 (__arm_vqdmulltq_n_s16): Likewise. 9383 (__arm_vqdmullbq_s16): Likewise. 9384 (__arm_vqdmullbq_n_s16): Likewise. 9385 (__arm_vorrq_f16): Likewise. 9386 (__arm_vornq_f16): Likewise. 9387 (__arm_vmulq_n_f16): Likewise. 9388 (__arm_vmulq_f16): Likewise. 9389 (__arm_vmovntq_s16): Likewise. 9390 (__arm_vmovnbq_s16): Likewise. 9391 (__arm_vmlsldavxq_s16): Likewise. 9392 (__arm_vmlsldavq_s16): Likewise. 9393 (__arm_vmlaldavxq_s16): Likewise. 9394 (__arm_vmlaldavq_s16): Likewise. 9395 (__arm_vminnmvq_f16): Likewise. 9396 (__arm_vminnmq_f16): Likewise. 9397 (__arm_vminnmavq_f16): Likewise. 9398 (__arm_vminnmaq_f16): Likewise. 9399 (__arm_vmaxnmvq_f16): Likewise. 9400 (__arm_vmaxnmq_f16): Likewise. 9401 (__arm_vmaxnmavq_f16): Likewise. 9402 (__arm_vmaxnmaq_f16): Likewise. 9403 (__arm_veorq_f16): Likewise. 9404 (__arm_vcmulq_rot90_f16): Likewise. 9405 (__arm_vcmulq_rot270_f16): Likewise. 9406 (__arm_vcmulq_rot180_f16): Likewise. 9407 (__arm_vcmulq_f16): Likewise. 9408 (__arm_vcaddq_rot90_f16): Likewise. 9409 (__arm_vcaddq_rot270_f16): Likewise. 9410 (__arm_vbicq_f16): Likewise. 9411 (__arm_vandq_f16): Likewise. 9412 (__arm_vaddq_n_f16): Likewise. 9413 (__arm_vabdq_f16): Likewise. 9414 (__arm_vshlltq_n_s8): Likewise. 9415 (__arm_vshllbq_n_s8): Likewise. 9416 (__arm_vorrq_n_s16): Likewise. 9417 (__arm_vbicq_n_s16): Likewise. 9418 (__arm_vqmovntq_u32): Likewise. 9419 (__arm_vqmovnbq_u32): Likewise. 9420 (__arm_vmulltq_poly_p16): Likewise. 9421 (__arm_vmullbq_poly_p16): Likewise. 9422 (__arm_vmovntq_u32): Likewise. 9423 (__arm_vmovnbq_u32): Likewise. 9424 (__arm_vmlaldavxq_u32): Likewise. 9425 (__arm_vmlaldavq_u32): Likewise. 9426 (__arm_vqmovuntq_s32): Likewise. 9427 (__arm_vqmovunbq_s32): Likewise. 9428 (__arm_vshlltq_n_u16): Likewise. 9429 (__arm_vshllbq_n_u16): Likewise. 9430 (__arm_vorrq_n_u32): Likewise. 9431 (__arm_vbicq_n_u32): Likewise. 9432 (__arm_vcmpneq_n_f32): Likewise. 9433 (__arm_vcmpneq_f32): Likewise. 9434 (__arm_vcmpltq_n_f32): Likewise. 9435 (__arm_vcmpltq_f32): Likewise. 9436 (__arm_vcmpleq_n_f32): Likewise. 9437 (__arm_vcmpleq_f32): Likewise. 9438 (__arm_vcmpgtq_n_f32): Likewise. 9439 (__arm_vcmpgtq_f32): Likewise. 9440 (__arm_vcmpgeq_n_f32): Likewise. 9441 (__arm_vcmpgeq_f32): Likewise. 9442 (__arm_vcmpeqq_n_f32): Likewise. 9443 (__arm_vcmpeqq_f32): Likewise. 9444 (__arm_vsubq_f32): Likewise. 9445 (__arm_vqmovntq_s32): Likewise. 9446 (__arm_vqmovnbq_s32): Likewise. 9447 (__arm_vqdmulltq_s32): Likewise. 9448 (__arm_vqdmulltq_n_s32): Likewise. 9449 (__arm_vqdmullbq_s32): Likewise. 9450 (__arm_vqdmullbq_n_s32): Likewise. 9451 (__arm_vorrq_f32): Likewise. 9452 (__arm_vornq_f32): Likewise. 9453 (__arm_vmulq_n_f32): Likewise. 9454 (__arm_vmulq_f32): Likewise. 9455 (__arm_vmovntq_s32): Likewise. 9456 (__arm_vmovnbq_s32): Likewise. 9457 (__arm_vmlsldavxq_s32): Likewise. 9458 (__arm_vmlsldavq_s32): Likewise. 9459 (__arm_vmlaldavxq_s32): Likewise. 9460 (__arm_vmlaldavq_s32): Likewise. 9461 (__arm_vminnmvq_f32): Likewise. 9462 (__arm_vminnmq_f32): Likewise. 9463 (__arm_vminnmavq_f32): Likewise. 9464 (__arm_vminnmaq_f32): Likewise. 9465 (__arm_vmaxnmvq_f32): Likewise. 9466 (__arm_vmaxnmq_f32): Likewise. 9467 (__arm_vmaxnmavq_f32): Likewise. 9468 (__arm_vmaxnmaq_f32): Likewise. 9469 (__arm_veorq_f32): Likewise. 9470 (__arm_vcmulq_rot90_f32): Likewise. 9471 (__arm_vcmulq_rot270_f32): Likewise. 9472 (__arm_vcmulq_rot180_f32): Likewise. 9473 (__arm_vcmulq_f32): Likewise. 9474 (__arm_vcaddq_rot90_f32): Likewise. 9475 (__arm_vcaddq_rot270_f32): Likewise. 9476 (__arm_vbicq_f32): Likewise. 9477 (__arm_vandq_f32): Likewise. 9478 (__arm_vaddq_n_f32): Likewise. 9479 (__arm_vabdq_f32): Likewise. 9480 (__arm_vshlltq_n_s16): Likewise. 9481 (__arm_vshllbq_n_s16): Likewise. 9482 (__arm_vorrq_n_s32): Likewise. 9483 (__arm_vbicq_n_s32): Likewise. 9484 (__arm_vrmlaldavhq_u32): Likewise. 9485 (__arm_vctp8q_m): Likewise. 9486 (__arm_vctp64q_m): Likewise. 9487 (__arm_vctp32q_m): Likewise. 9488 (__arm_vctp16q_m): Likewise. 9489 (__arm_vaddlvaq_u32): Likewise. 9490 (__arm_vrmlsldavhxq_s32): Likewise. 9491 (__arm_vrmlsldavhq_s32): Likewise. 9492 (__arm_vrmlaldavhxq_s32): Likewise. 9493 (__arm_vrmlaldavhq_s32): Likewise. 9494 (__arm_vcvttq_f16_f32): Likewise. 9495 (__arm_vcvtbq_f16_f32): Likewise. 9496 (__arm_vaddlvaq_s32): Likewise. 9497 (vst4q): Define polymorphic variant. 9498 (vrndxq): Likewise. 9499 (vrndq): Likewise. 9500 (vrndpq): Likewise. 9501 (vrndnq): Likewise. 9502 (vrndmq): Likewise. 9503 (vrndaq): Likewise. 9504 (vrev64q): Likewise. 9505 (vnegq): Likewise. 9506 (vdupq_n): Likewise. 9507 (vabsq): Likewise. 9508 (vrev32q): Likewise. 9509 (vcvtbq_f32): Likewise. 9510 (vcvttq_f32): Likewise. 9511 (vcvtq): Likewise. 9512 (vsubq_n): Likewise. 9513 (vbrsrq_n): Likewise. 9514 (vcvtq_n): Likewise. 9515 (vsubq): Likewise. 9516 (vorrq): Likewise. 9517 (vabdq): Likewise. 9518 (vaddq_n): Likewise. 9519 (vandq): Likewise. 9520 (vbicq): Likewise. 9521 (vornq): Likewise. 9522 (vmulq_n): Likewise. 9523 (vmulq): Likewise. 9524 (vcaddq_rot270): Likewise. 9525 (vcmpeqq_n): Likewise. 9526 (vcmpeqq): Likewise. 9527 (vcaddq_rot90): Likewise. 9528 (vcmpgeq_n): Likewise. 9529 (vcmpgeq): Likewise. 9530 (vcmpgtq_n): Likewise. 9531 (vcmpgtq): Likewise. 9532 (vcmpgtq): Likewise. 9533 (vcmpleq_n): Likewise. 9534 (vcmpleq_n): Likewise. 9535 (vcmpleq): Likewise. 9536 (vcmpleq): Likewise. 9537 (vcmpltq_n): Likewise. 9538 (vcmpltq_n): Likewise. 9539 (vcmpltq): Likewise. 9540 (vcmpltq): Likewise. 9541 (vcmpneq_n): Likewise. 9542 (vcmpneq_n): Likewise. 9543 (vcmpneq): Likewise. 9544 (vcmpneq): Likewise. 9545 (vcmulq): Likewise. 9546 (vcmulq): Likewise. 9547 (vcmulq_rot180): Likewise. 9548 (vcmulq_rot180): Likewise. 9549 (vcmulq_rot270): Likewise. 9550 (vcmulq_rot270): Likewise. 9551 (vcmulq_rot90): Likewise. 9552 (vcmulq_rot90): Likewise. 9553 (veorq): Likewise. 9554 (veorq): Likewise. 9555 (vmaxnmaq): Likewise. 9556 (vmaxnmaq): Likewise. 9557 (vmaxnmavq): Likewise. 9558 (vmaxnmavq): Likewise. 9559 (vmaxnmq): Likewise. 9560 (vmaxnmq): Likewise. 9561 (vmaxnmvq): Likewise. 9562 (vmaxnmvq): Likewise. 9563 (vminnmaq): Likewise. 9564 (vminnmaq): Likewise. 9565 (vminnmavq): Likewise. 9566 (vminnmavq): Likewise. 9567 (vminnmq): Likewise. 9568 (vminnmq): Likewise. 9569 (vminnmvq): Likewise. 9570 (vminnmvq): Likewise. 9571 (vbicq_n): Likewise. 9572 (vqmovntq): Likewise. 9573 (vqmovntq): Likewise. 9574 (vqmovnbq): Likewise. 9575 (vqmovnbq): Likewise. 9576 (vmulltq_poly): Likewise. 9577 (vmulltq_poly): Likewise. 9578 (vmullbq_poly): Likewise. 9579 (vmullbq_poly): Likewise. 9580 (vmovntq): Likewise. 9581 (vmovntq): Likewise. 9582 (vmovnbq): Likewise. 9583 (vmovnbq): Likewise. 9584 (vmlaldavxq): Likewise. 9585 (vmlaldavxq): Likewise. 9586 (vqmovuntq): Likewise. 9587 (vqmovuntq): Likewise. 9588 (vshlltq_n): Likewise. 9589 (vshlltq_n): Likewise. 9590 (vshllbq_n): Likewise. 9591 (vshllbq_n): Likewise. 9592 (vorrq_n): Likewise. 9593 (vorrq_n): Likewise. 9594 (vmlaldavq): Likewise. 9595 (vmlaldavq): Likewise. 9596 (vqmovunbq): Likewise. 9597 (vqmovunbq): Likewise. 9598 (vqdmulltq_n): Likewise. 9599 (vqdmulltq_n): Likewise. 9600 (vqdmulltq): Likewise. 9601 (vqdmulltq): Likewise. 9602 (vqdmullbq_n): Likewise. 9603 (vqdmullbq_n): Likewise. 9604 (vqdmullbq): Likewise. 9605 (vqdmullbq): Likewise. 9606 (vaddlvaq): Likewise. 9607 (vaddlvaq): Likewise. 9608 (vrmlaldavhq): Likewise. 9609 (vrmlaldavhq): Likewise. 9610 (vrmlaldavhxq): Likewise. 9611 (vrmlaldavhxq): Likewise. 9612 (vrmlsldavhq): Likewise. 9613 (vrmlsldavhq): Likewise. 9614 (vrmlsldavhxq): Likewise. 9615 (vrmlsldavhxq): Likewise. 9616 (vmlsldavxq): Likewise. 9617 (vmlsldavxq): Likewise. 9618 (vmlsldavq): Likewise. 9619 (vmlsldavq): Likewise. 9620 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it. 9621 (BINOP_NONE_NONE_NONE): Likewise. 9622 (BINOP_UNONE_NONE_NONE): Likewise. 9623 (BINOP_UNONE_UNONE_IMM): Likewise. 9624 (BINOP_UNONE_UNONE_NONE): Likewise. 9625 (BINOP_UNONE_UNONE_UNONE): Likewise. 9626 * config/arm/mve.md (mve_vabdq_f<mode>): Define RTL pattern. 9627 (mve_vaddlvaq_<supf>v4si): Likewise. 9628 (mve_vaddq_n_f<mode>): Likewise. 9629 (mve_vandq_f<mode>): Likewise. 9630 (mve_vbicq_f<mode>): Likewise. 9631 (mve_vbicq_n_<supf><mode>): Likewise. 9632 (mve_vcaddq_rot270_f<mode>): Likewise. 9633 (mve_vcaddq_rot90_f<mode>): Likewise. 9634 (mve_vcmpeqq_f<mode>): Likewise. 9635 (mve_vcmpeqq_n_f<mode>): Likewise. 9636 (mve_vcmpgeq_f<mode>): Likewise. 9637 (mve_vcmpgeq_n_f<mode>): Likewise. 9638 (mve_vcmpgtq_f<mode>): Likewise. 9639 (mve_vcmpgtq_n_f<mode>): Likewise. 9640 (mve_vcmpleq_f<mode>): Likewise. 9641 (mve_vcmpleq_n_f<mode>): Likewise. 9642 (mve_vcmpltq_f<mode>): Likewise. 9643 (mve_vcmpltq_n_f<mode>): Likewise. 9644 (mve_vcmpneq_f<mode>): Likewise. 9645 (mve_vcmpneq_n_f<mode>): Likewise. 9646 (mve_vcmulq_f<mode>): Likewise. 9647 (mve_vcmulq_rot180_f<mode>): Likewise. 9648 (mve_vcmulq_rot270_f<mode>): Likewise. 9649 (mve_vcmulq_rot90_f<mode>): Likewise. 9650 (mve_vctp<mode1>q_mhi): Likewise. 9651 (mve_vcvtbq_f16_f32v8hf): Likewise. 9652 (mve_vcvttq_f16_f32v8hf): Likewise. 9653 (mve_veorq_f<mode>): Likewise. 9654 (mve_vmaxnmaq_f<mode>): Likewise. 9655 (mve_vmaxnmavq_f<mode>): Likewise. 9656 (mve_vmaxnmq_f<mode>): Likewise. 9657 (mve_vmaxnmvq_f<mode>): Likewise. 9658 (mve_vminnmaq_f<mode>): Likewise. 9659 (mve_vminnmavq_f<mode>): Likewise. 9660 (mve_vminnmq_f<mode>): Likewise. 9661 (mve_vminnmvq_f<mode>): Likewise. 9662 (mve_vmlaldavq_<supf><mode>): Likewise. 9663 (mve_vmlaldavxq_<supf><mode>): Likewise. 9664 (mve_vmlsldavq_s<mode>): Likewise. 9665 (mve_vmlsldavxq_s<mode>): Likewise. 9666 (mve_vmovnbq_<supf><mode>): Likewise. 9667 (mve_vmovntq_<supf><mode>): Likewise. 9668 (mve_vmulq_f<mode>): Likewise. 9669 (mve_vmulq_n_f<mode>): Likewise. 9670 (mve_vornq_f<mode>): Likewise. 9671 (mve_vorrq_f<mode>): Likewise. 9672 (mve_vorrq_n_<supf><mode>): Likewise. 9673 (mve_vqdmullbq_n_s<mode>): Likewise. 9674 (mve_vqdmullbq_s<mode>): Likewise. 9675 (mve_vqdmulltq_n_s<mode>): Likewise. 9676 (mve_vqdmulltq_s<mode>): Likewise. 9677 (mve_vqmovnbq_<supf><mode>): Likewise. 9678 (mve_vqmovntq_<supf><mode>): Likewise. 9679 (mve_vqmovunbq_s<mode>): Likewise. 9680 (mve_vqmovuntq_s<mode>): Likewise. 9681 (mve_vrmlaldavhxq_sv4si): Likewise. 9682 (mve_vrmlsldavhq_sv4si): Likewise. 9683 (mve_vrmlsldavhxq_sv4si): Likewise. 9684 (mve_vshllbq_n_<supf><mode>): Likewise. 9685 (mve_vshlltq_n_<supf><mode>): Likewise. 9686 (mve_vsubq_f<mode>): Likewise. 9687 (mve_vmulltq_poly_p<mode>): Likewise. 9688 (mve_vmullbq_poly_p<mode>): Likewise. 9689 (mve_vrmlaldavhq_<supf>v4si): Likewise. 9690 96912020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com> 9692 Mihail Ionescu <mihail.ionescu@arm.com> 9693 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 9694 9695 * config/arm/arm_mve.h (vsubq_u8): Define macro. 9696 (vsubq_n_u8): Likewise. 9697 (vrmulhq_u8): Likewise. 9698 (vrhaddq_u8): Likewise. 9699 (vqsubq_u8): Likewise. 9700 (vqsubq_n_u8): Likewise. 9701 (vqaddq_u8): Likewise. 9702 (vqaddq_n_u8): Likewise. 9703 (vorrq_u8): Likewise. 9704 (vornq_u8): Likewise. 9705 (vmulq_u8): Likewise. 9706 (vmulq_n_u8): Likewise. 9707 (vmulltq_int_u8): Likewise. 9708 (vmullbq_int_u8): Likewise. 9709 (vmulhq_u8): Likewise. 9710 (vmladavq_u8): Likewise. 9711 (vminvq_u8): Likewise. 9712 (vminq_u8): Likewise. 9713 (vmaxvq_u8): Likewise. 9714 (vmaxq_u8): Likewise. 9715 (vhsubq_u8): Likewise. 9716 (vhsubq_n_u8): Likewise. 9717 (vhaddq_u8): Likewise. 9718 (vhaddq_n_u8): Likewise. 9719 (veorq_u8): Likewise. 9720 (vcmpneq_n_u8): Likewise. 9721 (vcmphiq_u8): Likewise. 9722 (vcmphiq_n_u8): Likewise. 9723 (vcmpeqq_u8): Likewise. 9724 (vcmpeqq_n_u8): Likewise. 9725 (vcmpcsq_u8): Likewise. 9726 (vcmpcsq_n_u8): Likewise. 9727 (vcaddq_rot90_u8): Likewise. 9728 (vcaddq_rot270_u8): Likewise. 9729 (vbicq_u8): Likewise. 9730 (vandq_u8): Likewise. 9731 (vaddvq_p_u8): Likewise. 9732 (vaddvaq_u8): Likewise. 9733 (vaddq_n_u8): Likewise. 9734 (vabdq_u8): Likewise. 9735 (vshlq_r_u8): Likewise. 9736 (vrshlq_u8): Likewise. 9737 (vrshlq_n_u8): Likewise. 9738 (vqshlq_u8): Likewise. 9739 (vqshlq_r_u8): Likewise. 9740 (vqrshlq_u8): Likewise. 9741 (vqrshlq_n_u8): Likewise. 9742 (vminavq_s8): Likewise. 9743 (vminaq_s8): Likewise. 9744 (vmaxavq_s8): Likewise. 9745 (vmaxaq_s8): Likewise. 9746 (vbrsrq_n_u8): Likewise. 9747 (vshlq_n_u8): Likewise. 9748 (vrshrq_n_u8): Likewise. 9749 (vqshlq_n_u8): Likewise. 9750 (vcmpneq_n_s8): Likewise. 9751 (vcmpltq_s8): Likewise. 9752 (vcmpltq_n_s8): Likewise. 9753 (vcmpleq_s8): Likewise. 9754 (vcmpleq_n_s8): Likewise. 9755 (vcmpgtq_s8): Likewise. 9756 (vcmpgtq_n_s8): Likewise. 9757 (vcmpgeq_s8): Likewise. 9758 (vcmpgeq_n_s8): Likewise. 9759 (vcmpeqq_s8): Likewise. 9760 (vcmpeqq_n_s8): Likewise. 9761 (vqshluq_n_s8): Likewise. 9762 (vaddvq_p_s8): Likewise. 9763 (vsubq_s8): Likewise. 9764 (vsubq_n_s8): Likewise. 9765 (vshlq_r_s8): Likewise. 9766 (vrshlq_s8): Likewise. 9767 (vrshlq_n_s8): Likewise. 9768 (vrmulhq_s8): Likewise. 9769 (vrhaddq_s8): Likewise. 9770 (vqsubq_s8): Likewise. 9771 (vqsubq_n_s8): Likewise. 9772 (vqshlq_s8): Likewise. 9773 (vqshlq_r_s8): Likewise. 9774 (vqrshlq_s8): Likewise. 9775 (vqrshlq_n_s8): Likewise. 9776 (vqrdmulhq_s8): Likewise. 9777 (vqrdmulhq_n_s8): Likewise. 9778 (vqdmulhq_s8): Likewise. 9779 (vqdmulhq_n_s8): Likewise. 9780 (vqaddq_s8): Likewise. 9781 (vqaddq_n_s8): Likewise. 9782 (vorrq_s8): Likewise. 9783 (vornq_s8): Likewise. 9784 (vmulq_s8): Likewise. 9785 (vmulq_n_s8): Likewise. 9786 (vmulltq_int_s8): Likewise. 9787 (vmullbq_int_s8): Likewise. 9788 (vmulhq_s8): Likewise. 9789 (vmlsdavxq_s8): Likewise. 9790 (vmlsdavq_s8): Likewise. 9791 (vmladavxq_s8): Likewise. 9792 (vmladavq_s8): Likewise. 9793 (vminvq_s8): Likewise. 9794 (vminq_s8): Likewise. 9795 (vmaxvq_s8): Likewise. 9796 (vmaxq_s8): Likewise. 9797 (vhsubq_s8): Likewise. 9798 (vhsubq_n_s8): Likewise. 9799 (vhcaddq_rot90_s8): Likewise. 9800 (vhcaddq_rot270_s8): Likewise. 9801 (vhaddq_s8): Likewise. 9802 (vhaddq_n_s8): Likewise. 9803 (veorq_s8): Likewise. 9804 (vcaddq_rot90_s8): Likewise. 9805 (vcaddq_rot270_s8): Likewise. 9806 (vbrsrq_n_s8): Likewise. 9807 (vbicq_s8): Likewise. 9808 (vandq_s8): Likewise. 9809 (vaddvaq_s8): Likewise. 9810 (vaddq_n_s8): Likewise. 9811 (vabdq_s8): Likewise. 9812 (vshlq_n_s8): Likewise. 9813 (vrshrq_n_s8): Likewise. 9814 (vqshlq_n_s8): Likewise. 9815 (vsubq_u16): Likewise. 9816 (vsubq_n_u16): Likewise. 9817 (vrmulhq_u16): Likewise. 9818 (vrhaddq_u16): Likewise. 9819 (vqsubq_u16): Likewise. 9820 (vqsubq_n_u16): Likewise. 9821 (vqaddq_u16): Likewise. 9822 (vqaddq_n_u16): Likewise. 9823 (vorrq_u16): Likewise. 9824 (vornq_u16): Likewise. 9825 (vmulq_u16): Likewise. 9826 (vmulq_n_u16): Likewise. 9827 (vmulltq_int_u16): Likewise. 9828 (vmullbq_int_u16): Likewise. 9829 (vmulhq_u16): Likewise. 9830 (vmladavq_u16): Likewise. 9831 (vminvq_u16): Likewise. 9832 (vminq_u16): Likewise. 9833 (vmaxvq_u16): Likewise. 9834 (vmaxq_u16): Likewise. 9835 (vhsubq_u16): Likewise. 9836 (vhsubq_n_u16): Likewise. 9837 (vhaddq_u16): Likewise. 9838 (vhaddq_n_u16): Likewise. 9839 (veorq_u16): Likewise. 9840 (vcmpneq_n_u16): Likewise. 9841 (vcmphiq_u16): Likewise. 9842 (vcmphiq_n_u16): Likewise. 9843 (vcmpeqq_u16): Likewise. 9844 (vcmpeqq_n_u16): Likewise. 9845 (vcmpcsq_u16): Likewise. 9846 (vcmpcsq_n_u16): Likewise. 9847 (vcaddq_rot90_u16): Likewise. 9848 (vcaddq_rot270_u16): Likewise. 9849 (vbicq_u16): Likewise. 9850 (vandq_u16): Likewise. 9851 (vaddvq_p_u16): Likewise. 9852 (vaddvaq_u16): Likewise. 9853 (vaddq_n_u16): Likewise. 9854 (vabdq_u16): Likewise. 9855 (vshlq_r_u16): Likewise. 9856 (vrshlq_u16): Likewise. 9857 (vrshlq_n_u16): Likewise. 9858 (vqshlq_u16): Likewise. 9859 (vqshlq_r_u16): Likewise. 9860 (vqrshlq_u16): Likewise. 9861 (vqrshlq_n_u16): Likewise. 9862 (vminavq_s16): Likewise. 9863 (vminaq_s16): Likewise. 9864 (vmaxavq_s16): Likewise. 9865 (vmaxaq_s16): Likewise. 9866 (vbrsrq_n_u16): Likewise. 9867 (vshlq_n_u16): Likewise. 9868 (vrshrq_n_u16): Likewise. 9869 (vqshlq_n_u16): Likewise. 9870 (vcmpneq_n_s16): Likewise. 9871 (vcmpltq_s16): Likewise. 9872 (vcmpltq_n_s16): Likewise. 9873 (vcmpleq_s16): Likewise. 9874 (vcmpleq_n_s16): Likewise. 9875 (vcmpgtq_s16): Likewise. 9876 (vcmpgtq_n_s16): Likewise. 9877 (vcmpgeq_s16): Likewise. 9878 (vcmpgeq_n_s16): Likewise. 9879 (vcmpeqq_s16): Likewise. 9880 (vcmpeqq_n_s16): Likewise. 9881 (vqshluq_n_s16): Likewise. 9882 (vaddvq_p_s16): Likewise. 9883 (vsubq_s16): Likewise. 9884 (vsubq_n_s16): Likewise. 9885 (vshlq_r_s16): Likewise. 9886 (vrshlq_s16): Likewise. 9887 (vrshlq_n_s16): Likewise. 9888 (vrmulhq_s16): Likewise. 9889 (vrhaddq_s16): Likewise. 9890 (vqsubq_s16): Likewise. 9891 (vqsubq_n_s16): Likewise. 9892 (vqshlq_s16): Likewise. 9893 (vqshlq_r_s16): Likewise. 9894 (vqrshlq_s16): Likewise. 9895 (vqrshlq_n_s16): Likewise. 9896 (vqrdmulhq_s16): Likewise. 9897 (vqrdmulhq_n_s16): Likewise. 9898 (vqdmulhq_s16): Likewise. 9899 (vqdmulhq_n_s16): Likewise. 9900 (vqaddq_s16): Likewise. 9901 (vqaddq_n_s16): Likewise. 9902 (vorrq_s16): Likewise. 9903 (vornq_s16): Likewise. 9904 (vmulq_s16): Likewise. 9905 (vmulq_n_s16): Likewise. 9906 (vmulltq_int_s16): Likewise. 9907 (vmullbq_int_s16): Likewise. 9908 (vmulhq_s16): Likewise. 9909 (vmlsdavxq_s16): Likewise. 9910 (vmlsdavq_s16): Likewise. 9911 (vmladavxq_s16): Likewise. 9912 (vmladavq_s16): Likewise. 9913 (vminvq_s16): Likewise. 9914 (vminq_s16): Likewise. 9915 (vmaxvq_s16): Likewise. 9916 (vmaxq_s16): Likewise. 9917 (vhsubq_s16): Likewise. 9918 (vhsubq_n_s16): Likewise. 9919 (vhcaddq_rot90_s16): Likewise. 9920 (vhcaddq_rot270_s16): Likewise. 9921 (vhaddq_s16): Likewise. 9922 (vhaddq_n_s16): Likewise. 9923 (veorq_s16): Likewise. 9924 (vcaddq_rot90_s16): Likewise. 9925 (vcaddq_rot270_s16): Likewise. 9926 (vbrsrq_n_s16): Likewise. 9927 (vbicq_s16): Likewise. 9928 (vandq_s16): Likewise. 9929 (vaddvaq_s16): Likewise. 9930 (vaddq_n_s16): Likewise. 9931 (vabdq_s16): Likewise. 9932 (vshlq_n_s16): Likewise. 9933 (vrshrq_n_s16): Likewise. 9934 (vqshlq_n_s16): Likewise. 9935 (vsubq_u32): Likewise. 9936 (vsubq_n_u32): Likewise. 9937 (vrmulhq_u32): Likewise. 9938 (vrhaddq_u32): Likewise. 9939 (vqsubq_u32): Likewise. 9940 (vqsubq_n_u32): Likewise. 9941 (vqaddq_u32): Likewise. 9942 (vqaddq_n_u32): Likewise. 9943 (vorrq_u32): Likewise. 9944 (vornq_u32): Likewise. 9945 (vmulq_u32): Likewise. 9946 (vmulq_n_u32): Likewise. 9947 (vmulltq_int_u32): Likewise. 9948 (vmullbq_int_u32): Likewise. 9949 (vmulhq_u32): Likewise. 9950 (vmladavq_u32): Likewise. 9951 (vminvq_u32): Likewise. 9952 (vminq_u32): Likewise. 9953 (vmaxvq_u32): Likewise. 9954 (vmaxq_u32): Likewise. 9955 (vhsubq_u32): Likewise. 9956 (vhsubq_n_u32): Likewise. 9957 (vhaddq_u32): Likewise. 9958 (vhaddq_n_u32): Likewise. 9959 (veorq_u32): Likewise. 9960 (vcmpneq_n_u32): Likewise. 9961 (vcmphiq_u32): Likewise. 9962 (vcmphiq_n_u32): Likewise. 9963 (vcmpeqq_u32): Likewise. 9964 (vcmpeqq_n_u32): Likewise. 9965 (vcmpcsq_u32): Likewise. 9966 (vcmpcsq_n_u32): Likewise. 9967 (vcaddq_rot90_u32): Likewise. 9968 (vcaddq_rot270_u32): Likewise. 9969 (vbicq_u32): Likewise. 9970 (vandq_u32): Likewise. 9971 (vaddvq_p_u32): Likewise. 9972 (vaddvaq_u32): Likewise. 9973 (vaddq_n_u32): Likewise. 9974 (vabdq_u32): Likewise. 9975 (vshlq_r_u32): Likewise. 9976 (vrshlq_u32): Likewise. 9977 (vrshlq_n_u32): Likewise. 9978 (vqshlq_u32): Likewise. 9979 (vqshlq_r_u32): Likewise. 9980 (vqrshlq_u32): Likewise. 9981 (vqrshlq_n_u32): Likewise. 9982 (vminavq_s32): Likewise. 9983 (vminaq_s32): Likewise. 9984 (vmaxavq_s32): Likewise. 9985 (vmaxaq_s32): Likewise. 9986 (vbrsrq_n_u32): Likewise. 9987 (vshlq_n_u32): Likewise. 9988 (vrshrq_n_u32): Likewise. 9989 (vqshlq_n_u32): Likewise. 9990 (vcmpneq_n_s32): Likewise. 9991 (vcmpltq_s32): Likewise. 9992 (vcmpltq_n_s32): Likewise. 9993 (vcmpleq_s32): Likewise. 9994 (vcmpleq_n_s32): Likewise. 9995 (vcmpgtq_s32): Likewise. 9996 (vcmpgtq_n_s32): Likewise. 9997 (vcmpgeq_s32): Likewise. 9998 (vcmpgeq_n_s32): Likewise. 9999 (vcmpeqq_s32): Likewise. 10000 (vcmpeqq_n_s32): Likewise. 10001 (vqshluq_n_s32): Likewise. 10002 (vaddvq_p_s32): Likewise. 10003 (vsubq_s32): Likewise. 10004 (vsubq_n_s32): Likewise. 10005 (vshlq_r_s32): Likewise. 10006 (vrshlq_s32): Likewise. 10007 (vrshlq_n_s32): Likewise. 10008 (vrmulhq_s32): Likewise. 10009 (vrhaddq_s32): Likewise. 10010 (vqsubq_s32): Likewise. 10011 (vqsubq_n_s32): Likewise. 10012 (vqshlq_s32): Likewise. 10013 (vqshlq_r_s32): Likewise. 10014 (vqrshlq_s32): Likewise. 10015 (vqrshlq_n_s32): Likewise. 10016 (vqrdmulhq_s32): Likewise. 10017 (vqrdmulhq_n_s32): Likewise. 10018 (vqdmulhq_s32): Likewise. 10019 (vqdmulhq_n_s32): Likewise. 10020 (vqaddq_s32): Likewise. 10021 (vqaddq_n_s32): Likewise. 10022 (vorrq_s32): Likewise. 10023 (vornq_s32): Likewise. 10024 (vmulq_s32): Likewise. 10025 (vmulq_n_s32): Likewise. 10026 (vmulltq_int_s32): Likewise. 10027 (vmullbq_int_s32): Likewise. 10028 (vmulhq_s32): Likewise. 10029 (vmlsdavxq_s32): Likewise. 10030 (vmlsdavq_s32): Likewise. 10031 (vmladavxq_s32): Likewise. 10032 (vmladavq_s32): Likewise. 10033 (vminvq_s32): Likewise. 10034 (vminq_s32): Likewise. 10035 (vmaxvq_s32): Likewise. 10036 (vmaxq_s32): Likewise. 10037 (vhsubq_s32): Likewise. 10038 (vhsubq_n_s32): Likewise. 10039 (vhcaddq_rot90_s32): Likewise. 10040 (vhcaddq_rot270_s32): Likewise. 10041 (vhaddq_s32): Likewise. 10042 (vhaddq_n_s32): Likewise. 10043 (veorq_s32): Likewise. 10044 (vcaddq_rot90_s32): Likewise. 10045 (vcaddq_rot270_s32): Likewise. 10046 (vbrsrq_n_s32): Likewise. 10047 (vbicq_s32): Likewise. 10048 (vandq_s32): Likewise. 10049 (vaddvaq_s32): Likewise. 10050 (vaddq_n_s32): Likewise. 10051 (vabdq_s32): Likewise. 10052 (vshlq_n_s32): Likewise. 10053 (vrshrq_n_s32): Likewise. 10054 (vqshlq_n_s32): Likewise. 10055 (__arm_vsubq_u8): Define intrinsic. 10056 (__arm_vsubq_n_u8): Likewise. 10057 (__arm_vrmulhq_u8): Likewise. 10058 (__arm_vrhaddq_u8): Likewise. 10059 (__arm_vqsubq_u8): Likewise. 10060 (__arm_vqsubq_n_u8): Likewise. 10061 (__arm_vqaddq_u8): Likewise. 10062 (__arm_vqaddq_n_u8): Likewise. 10063 (__arm_vorrq_u8): Likewise. 10064 (__arm_vornq_u8): Likewise. 10065 (__arm_vmulq_u8): Likewise. 10066 (__arm_vmulq_n_u8): Likewise. 10067 (__arm_vmulltq_int_u8): Likewise. 10068 (__arm_vmullbq_int_u8): Likewise. 10069 (__arm_vmulhq_u8): Likewise. 10070 (__arm_vmladavq_u8): Likewise. 10071 (__arm_vminvq_u8): Likewise. 10072 (__arm_vminq_u8): Likewise. 10073 (__arm_vmaxvq_u8): Likewise. 10074 (__arm_vmaxq_u8): Likewise. 10075 (__arm_vhsubq_u8): Likewise. 10076 (__arm_vhsubq_n_u8): Likewise. 10077 (__arm_vhaddq_u8): Likewise. 10078 (__arm_vhaddq_n_u8): Likewise. 10079 (__arm_veorq_u8): Likewise. 10080 (__arm_vcmpneq_n_u8): Likewise. 10081 (__arm_vcmphiq_u8): Likewise. 10082 (__arm_vcmphiq_n_u8): Likewise. 10083 (__arm_vcmpeqq_u8): Likewise. 10084 (__arm_vcmpeqq_n_u8): Likewise. 10085 (__arm_vcmpcsq_u8): Likewise. 10086 (__arm_vcmpcsq_n_u8): Likewise. 10087 (__arm_vcaddq_rot90_u8): Likewise. 10088 (__arm_vcaddq_rot270_u8): Likewise. 10089 (__arm_vbicq_u8): Likewise. 10090 (__arm_vandq_u8): Likewise. 10091 (__arm_vaddvq_p_u8): Likewise. 10092 (__arm_vaddvaq_u8): Likewise. 10093 (__arm_vaddq_n_u8): Likewise. 10094 (__arm_vabdq_u8): Likewise. 10095 (__arm_vshlq_r_u8): Likewise. 10096 (__arm_vrshlq_u8): Likewise. 10097 (__arm_vrshlq_n_u8): Likewise. 10098 (__arm_vqshlq_u8): Likewise. 10099 (__arm_vqshlq_r_u8): Likewise. 10100 (__arm_vqrshlq_u8): Likewise. 10101 (__arm_vqrshlq_n_u8): Likewise. 10102 (__arm_vminavq_s8): Likewise. 10103 (__arm_vminaq_s8): Likewise. 10104 (__arm_vmaxavq_s8): Likewise. 10105 (__arm_vmaxaq_s8): Likewise. 10106 (__arm_vbrsrq_n_u8): Likewise. 10107 (__arm_vshlq_n_u8): Likewise. 10108 (__arm_vrshrq_n_u8): Likewise. 10109 (__arm_vqshlq_n_u8): Likewise. 10110 (__arm_vcmpneq_n_s8): Likewise. 10111 (__arm_vcmpltq_s8): Likewise. 10112 (__arm_vcmpltq_n_s8): Likewise. 10113 (__arm_vcmpleq_s8): Likewise. 10114 (__arm_vcmpleq_n_s8): Likewise. 10115 (__arm_vcmpgtq_s8): Likewise. 10116 (__arm_vcmpgtq_n_s8): Likewise. 10117 (__arm_vcmpgeq_s8): Likewise. 10118 (__arm_vcmpgeq_n_s8): Likewise. 10119 (__arm_vcmpeqq_s8): Likewise. 10120 (__arm_vcmpeqq_n_s8): Likewise. 10121 (__arm_vqshluq_n_s8): Likewise. 10122 (__arm_vaddvq_p_s8): Likewise. 10123 (__arm_vsubq_s8): Likewise. 10124 (__arm_vsubq_n_s8): Likewise. 10125 (__arm_vshlq_r_s8): Likewise. 10126 (__arm_vrshlq_s8): Likewise. 10127 (__arm_vrshlq_n_s8): Likewise. 10128 (__arm_vrmulhq_s8): Likewise. 10129 (__arm_vrhaddq_s8): Likewise. 10130 (__arm_vqsubq_s8): Likewise. 10131 (__arm_vqsubq_n_s8): Likewise. 10132 (__arm_vqshlq_s8): Likewise. 10133 (__arm_vqshlq_r_s8): Likewise. 10134 (__arm_vqrshlq_s8): Likewise. 10135 (__arm_vqrshlq_n_s8): Likewise. 10136 (__arm_vqrdmulhq_s8): Likewise. 10137 (__arm_vqrdmulhq_n_s8): Likewise. 10138 (__arm_vqdmulhq_s8): Likewise. 10139 (__arm_vqdmulhq_n_s8): Likewise. 10140 (__arm_vqaddq_s8): Likewise. 10141 (__arm_vqaddq_n_s8): Likewise. 10142 (__arm_vorrq_s8): Likewise. 10143 (__arm_vornq_s8): Likewise. 10144 (__arm_vmulq_s8): Likewise. 10145 (__arm_vmulq_n_s8): Likewise. 10146 (__arm_vmulltq_int_s8): Likewise. 10147 (__arm_vmullbq_int_s8): Likewise. 10148 (__arm_vmulhq_s8): Likewise. 10149 (__arm_vmlsdavxq_s8): Likewise. 10150 (__arm_vmlsdavq_s8): Likewise. 10151 (__arm_vmladavxq_s8): Likewise. 10152 (__arm_vmladavq_s8): Likewise. 10153 (__arm_vminvq_s8): Likewise. 10154 (__arm_vminq_s8): Likewise. 10155 (__arm_vmaxvq_s8): Likewise. 10156 (__arm_vmaxq_s8): Likewise. 10157 (__arm_vhsubq_s8): Likewise. 10158 (__arm_vhsubq_n_s8): Likewise. 10159 (__arm_vhcaddq_rot90_s8): Likewise. 10160 (__arm_vhcaddq_rot270_s8): Likewise. 10161 (__arm_vhaddq_s8): Likewise. 10162 (__arm_vhaddq_n_s8): Likewise. 10163 (__arm_veorq_s8): Likewise. 10164 (__arm_vcaddq_rot90_s8): Likewise. 10165 (__arm_vcaddq_rot270_s8): Likewise. 10166 (__arm_vbrsrq_n_s8): Likewise. 10167 (__arm_vbicq_s8): Likewise. 10168 (__arm_vandq_s8): Likewise. 10169 (__arm_vaddvaq_s8): Likewise. 10170 (__arm_vaddq_n_s8): Likewise. 10171 (__arm_vabdq_s8): Likewise. 10172 (__arm_vshlq_n_s8): Likewise. 10173 (__arm_vrshrq_n_s8): Likewise. 10174 (__arm_vqshlq_n_s8): Likewise. 10175 (__arm_vsubq_u16): Likewise. 10176 (__arm_vsubq_n_u16): Likewise. 10177 (__arm_vrmulhq_u16): Likewise. 10178 (__arm_vrhaddq_u16): Likewise. 10179 (__arm_vqsubq_u16): Likewise. 10180 (__arm_vqsubq_n_u16): Likewise. 10181 (__arm_vqaddq_u16): Likewise. 10182 (__arm_vqaddq_n_u16): Likewise. 10183 (__arm_vorrq_u16): Likewise. 10184 (__arm_vornq_u16): Likewise. 10185 (__arm_vmulq_u16): Likewise. 10186 (__arm_vmulq_n_u16): Likewise. 10187 (__arm_vmulltq_int_u16): Likewise. 10188 (__arm_vmullbq_int_u16): Likewise. 10189 (__arm_vmulhq_u16): Likewise. 10190 (__arm_vmladavq_u16): Likewise. 10191 (__arm_vminvq_u16): Likewise. 10192 (__arm_vminq_u16): Likewise. 10193 (__arm_vmaxvq_u16): Likewise. 10194 (__arm_vmaxq_u16): Likewise. 10195 (__arm_vhsubq_u16): Likewise. 10196 (__arm_vhsubq_n_u16): Likewise. 10197 (__arm_vhaddq_u16): Likewise. 10198 (__arm_vhaddq_n_u16): Likewise. 10199 (__arm_veorq_u16): Likewise. 10200 (__arm_vcmpneq_n_u16): Likewise. 10201 (__arm_vcmphiq_u16): Likewise. 10202 (__arm_vcmphiq_n_u16): Likewise. 10203 (__arm_vcmpeqq_u16): Likewise. 10204 (__arm_vcmpeqq_n_u16): Likewise. 10205 (__arm_vcmpcsq_u16): Likewise. 10206 (__arm_vcmpcsq_n_u16): Likewise. 10207 (__arm_vcaddq_rot90_u16): Likewise. 10208 (__arm_vcaddq_rot270_u16): Likewise. 10209 (__arm_vbicq_u16): Likewise. 10210 (__arm_vandq_u16): Likewise. 10211 (__arm_vaddvq_p_u16): Likewise. 10212 (__arm_vaddvaq_u16): Likewise. 10213 (__arm_vaddq_n_u16): Likewise. 10214 (__arm_vabdq_u16): Likewise. 10215 (__arm_vshlq_r_u16): Likewise. 10216 (__arm_vrshlq_u16): Likewise. 10217 (__arm_vrshlq_n_u16): Likewise. 10218 (__arm_vqshlq_u16): Likewise. 10219 (__arm_vqshlq_r_u16): Likewise. 10220 (__arm_vqrshlq_u16): Likewise. 10221 (__arm_vqrshlq_n_u16): Likewise. 10222 (__arm_vminavq_s16): Likewise. 10223 (__arm_vminaq_s16): Likewise. 10224 (__arm_vmaxavq_s16): Likewise. 10225 (__arm_vmaxaq_s16): Likewise. 10226 (__arm_vbrsrq_n_u16): Likewise. 10227 (__arm_vshlq_n_u16): Likewise. 10228 (__arm_vrshrq_n_u16): Likewise. 10229 (__arm_vqshlq_n_u16): Likewise. 10230 (__arm_vcmpneq_n_s16): Likewise. 10231 (__arm_vcmpltq_s16): Likewise. 10232 (__arm_vcmpltq_n_s16): Likewise. 10233 (__arm_vcmpleq_s16): Likewise. 10234 (__arm_vcmpleq_n_s16): Likewise. 10235 (__arm_vcmpgtq_s16): Likewise. 10236 (__arm_vcmpgtq_n_s16): Likewise. 10237 (__arm_vcmpgeq_s16): Likewise. 10238 (__arm_vcmpgeq_n_s16): Likewise. 10239 (__arm_vcmpeqq_s16): Likewise. 10240 (__arm_vcmpeqq_n_s16): Likewise. 10241 (__arm_vqshluq_n_s16): Likewise. 10242 (__arm_vaddvq_p_s16): Likewise. 10243 (__arm_vsubq_s16): Likewise. 10244 (__arm_vsubq_n_s16): Likewise. 10245 (__arm_vshlq_r_s16): Likewise. 10246 (__arm_vrshlq_s16): Likewise. 10247 (__arm_vrshlq_n_s16): Likewise. 10248 (__arm_vrmulhq_s16): Likewise. 10249 (__arm_vrhaddq_s16): Likewise. 10250 (__arm_vqsubq_s16): Likewise. 10251 (__arm_vqsubq_n_s16): Likewise. 10252 (__arm_vqshlq_s16): Likewise. 10253 (__arm_vqshlq_r_s16): Likewise. 10254 (__arm_vqrshlq_s16): Likewise. 10255 (__arm_vqrshlq_n_s16): Likewise. 10256 (__arm_vqrdmulhq_s16): Likewise. 10257 (__arm_vqrdmulhq_n_s16): Likewise. 10258 (__arm_vqdmulhq_s16): Likewise. 10259 (__arm_vqdmulhq_n_s16): Likewise. 10260 (__arm_vqaddq_s16): Likewise. 10261 (__arm_vqaddq_n_s16): Likewise. 10262 (__arm_vorrq_s16): Likewise. 10263 (__arm_vornq_s16): Likewise. 10264 (__arm_vmulq_s16): Likewise. 10265 (__arm_vmulq_n_s16): Likewise. 10266 (__arm_vmulltq_int_s16): Likewise. 10267 (__arm_vmullbq_int_s16): Likewise. 10268 (__arm_vmulhq_s16): Likewise. 10269 (__arm_vmlsdavxq_s16): Likewise. 10270 (__arm_vmlsdavq_s16): Likewise. 10271 (__arm_vmladavxq_s16): Likewise. 10272 (__arm_vmladavq_s16): Likewise. 10273 (__arm_vminvq_s16): Likewise. 10274 (__arm_vminq_s16): Likewise. 10275 (__arm_vmaxvq_s16): Likewise. 10276 (__arm_vmaxq_s16): Likewise. 10277 (__arm_vhsubq_s16): Likewise. 10278 (__arm_vhsubq_n_s16): Likewise. 10279 (__arm_vhcaddq_rot90_s16): Likewise. 10280 (__arm_vhcaddq_rot270_s16): Likewise. 10281 (__arm_vhaddq_s16): Likewise. 10282 (__arm_vhaddq_n_s16): Likewise. 10283 (__arm_veorq_s16): Likewise. 10284 (__arm_vcaddq_rot90_s16): Likewise. 10285 (__arm_vcaddq_rot270_s16): Likewise. 10286 (__arm_vbrsrq_n_s16): Likewise. 10287 (__arm_vbicq_s16): Likewise. 10288 (__arm_vandq_s16): Likewise. 10289 (__arm_vaddvaq_s16): Likewise. 10290 (__arm_vaddq_n_s16): Likewise. 10291 (__arm_vabdq_s16): Likewise. 10292 (__arm_vshlq_n_s16): Likewise. 10293 (__arm_vrshrq_n_s16): Likewise. 10294 (__arm_vqshlq_n_s16): Likewise. 10295 (__arm_vsubq_u32): Likewise. 10296 (__arm_vsubq_n_u32): Likewise. 10297 (__arm_vrmulhq_u32): Likewise. 10298 (__arm_vrhaddq_u32): Likewise. 10299 (__arm_vqsubq_u32): Likewise. 10300 (__arm_vqsubq_n_u32): Likewise. 10301 (__arm_vqaddq_u32): Likewise. 10302 (__arm_vqaddq_n_u32): Likewise. 10303 (__arm_vorrq_u32): Likewise. 10304 (__arm_vornq_u32): Likewise. 10305 (__arm_vmulq_u32): Likewise. 10306 (__arm_vmulq_n_u32): Likewise. 10307 (__arm_vmulltq_int_u32): Likewise. 10308 (__arm_vmullbq_int_u32): Likewise. 10309 (__arm_vmulhq_u32): Likewise. 10310 (__arm_vmladavq_u32): Likewise. 10311 (__arm_vminvq_u32): Likewise. 10312 (__arm_vminq_u32): Likewise. 10313 (__arm_vmaxvq_u32): Likewise. 10314 (__arm_vmaxq_u32): Likewise. 10315 (__arm_vhsubq_u32): Likewise. 10316 (__arm_vhsubq_n_u32): Likewise. 10317 (__arm_vhaddq_u32): Likewise. 10318 (__arm_vhaddq_n_u32): Likewise. 10319 (__arm_veorq_u32): Likewise. 10320 (__arm_vcmpneq_n_u32): Likewise. 10321 (__arm_vcmphiq_u32): Likewise. 10322 (__arm_vcmphiq_n_u32): Likewise. 10323 (__arm_vcmpeqq_u32): Likewise. 10324 (__arm_vcmpeqq_n_u32): Likewise. 10325 (__arm_vcmpcsq_u32): Likewise. 10326 (__arm_vcmpcsq_n_u32): Likewise. 10327 (__arm_vcaddq_rot90_u32): Likewise. 10328 (__arm_vcaddq_rot270_u32): Likewise. 10329 (__arm_vbicq_u32): Likewise. 10330 (__arm_vandq_u32): Likewise. 10331 (__arm_vaddvq_p_u32): Likewise. 10332 (__arm_vaddvaq_u32): Likewise. 10333 (__arm_vaddq_n_u32): Likewise. 10334 (__arm_vabdq_u32): Likewise. 10335 (__arm_vshlq_r_u32): Likewise. 10336 (__arm_vrshlq_u32): Likewise. 10337 (__arm_vrshlq_n_u32): Likewise. 10338 (__arm_vqshlq_u32): Likewise. 10339 (__arm_vqshlq_r_u32): Likewise. 10340 (__arm_vqrshlq_u32): Likewise. 10341 (__arm_vqrshlq_n_u32): Likewise. 10342 (__arm_vminavq_s32): Likewise. 10343 (__arm_vminaq_s32): Likewise. 10344 (__arm_vmaxavq_s32): Likewise. 10345 (__arm_vmaxaq_s32): Likewise. 10346 (__arm_vbrsrq_n_u32): Likewise. 10347 (__arm_vshlq_n_u32): Likewise. 10348 (__arm_vrshrq_n_u32): Likewise. 10349 (__arm_vqshlq_n_u32): Likewise. 10350 (__arm_vcmpneq_n_s32): Likewise. 10351 (__arm_vcmpltq_s32): Likewise. 10352 (__arm_vcmpltq_n_s32): Likewise. 10353 (__arm_vcmpleq_s32): Likewise. 10354 (__arm_vcmpleq_n_s32): Likewise. 10355 (__arm_vcmpgtq_s32): Likewise. 10356 (__arm_vcmpgtq_n_s32): Likewise. 10357 (__arm_vcmpgeq_s32): Likewise. 10358 (__arm_vcmpgeq_n_s32): Likewise. 10359 (__arm_vcmpeqq_s32): Likewise. 10360 (__arm_vcmpeqq_n_s32): Likewise. 10361 (__arm_vqshluq_n_s32): Likewise. 10362 (__arm_vaddvq_p_s32): Likewise. 10363 (__arm_vsubq_s32): Likewise. 10364 (__arm_vsubq_n_s32): Likewise. 10365 (__arm_vshlq_r_s32): Likewise. 10366 (__arm_vrshlq_s32): Likewise. 10367 (__arm_vrshlq_n_s32): Likewise. 10368 (__arm_vrmulhq_s32): Likewise. 10369 (__arm_vrhaddq_s32): Likewise. 10370 (__arm_vqsubq_s32): Likewise. 10371 (__arm_vqsubq_n_s32): Likewise. 10372 (__arm_vqshlq_s32): Likewise. 10373 (__arm_vqshlq_r_s32): Likewise. 10374 (__arm_vqrshlq_s32): Likewise. 10375 (__arm_vqrshlq_n_s32): Likewise. 10376 (__arm_vqrdmulhq_s32): Likewise. 10377 (__arm_vqrdmulhq_n_s32): Likewise. 10378 (__arm_vqdmulhq_s32): Likewise. 10379 (__arm_vqdmulhq_n_s32): Likewise. 10380 (__arm_vqaddq_s32): Likewise. 10381 (__arm_vqaddq_n_s32): Likewise. 10382 (__arm_vorrq_s32): Likewise. 10383 (__arm_vornq_s32): Likewise. 10384 (__arm_vmulq_s32): Likewise. 10385 (__arm_vmulq_n_s32): Likewise. 10386 (__arm_vmulltq_int_s32): Likewise. 10387 (__arm_vmullbq_int_s32): Likewise. 10388 (__arm_vmulhq_s32): Likewise. 10389 (__arm_vmlsdavxq_s32): Likewise. 10390 (__arm_vmlsdavq_s32): Likewise. 10391 (__arm_vmladavxq_s32): Likewise. 10392 (__arm_vmladavq_s32): Likewise. 10393 (__arm_vminvq_s32): Likewise. 10394 (__arm_vminq_s32): Likewise. 10395 (__arm_vmaxvq_s32): Likewise. 10396 (__arm_vmaxq_s32): Likewise. 10397 (__arm_vhsubq_s32): Likewise. 10398 (__arm_vhsubq_n_s32): Likewise. 10399 (__arm_vhcaddq_rot90_s32): Likewise. 10400 (__arm_vhcaddq_rot270_s32): Likewise. 10401 (__arm_vhaddq_s32): Likewise. 10402 (__arm_vhaddq_n_s32): Likewise. 10403 (__arm_veorq_s32): Likewise. 10404 (__arm_vcaddq_rot90_s32): Likewise. 10405 (__arm_vcaddq_rot270_s32): Likewise. 10406 (__arm_vbrsrq_n_s32): Likewise. 10407 (__arm_vbicq_s32): Likewise. 10408 (__arm_vandq_s32): Likewise. 10409 (__arm_vaddvaq_s32): Likewise. 10410 (__arm_vaddq_n_s32): Likewise. 10411 (__arm_vabdq_s32): Likewise. 10412 (__arm_vshlq_n_s32): Likewise. 10413 (__arm_vrshrq_n_s32): Likewise. 10414 (__arm_vqshlq_n_s32): Likewise. 10415 (vsubq): Define polymorphic variant. 10416 (vsubq_n): Likewise. 10417 (vshlq_r): Likewise. 10418 (vrshlq_n): Likewise. 10419 (vrshlq): Likewise. 10420 (vrmulhq): Likewise. 10421 (vrhaddq): Likewise. 10422 (vqsubq_n): Likewise. 10423 (vqsubq): Likewise. 10424 (vqshlq): Likewise. 10425 (vqshlq_r): Likewise. 10426 (vqshluq): Likewise. 10427 (vrshrq_n): Likewise. 10428 (vshlq_n): Likewise. 10429 (vqshluq_n): Likewise. 10430 (vqshlq_n): Likewise. 10431 (vqrshlq_n): Likewise. 10432 (vqrshlq): Likewise. 10433 (vqrdmulhq_n): Likewise. 10434 (vqrdmulhq): Likewise. 10435 (vqdmulhq_n): Likewise. 10436 (vqdmulhq): Likewise. 10437 (vqaddq_n): Likewise. 10438 (vqaddq): Likewise. 10439 (vorrq_n): Likewise. 10440 (vorrq): Likewise. 10441 (vornq): Likewise. 10442 (vmulq_n): Likewise. 10443 (vmulq): Likewise. 10444 (vmulltq_int): Likewise. 10445 (vmullbq_int): Likewise. 10446 (vmulhq): Likewise. 10447 (vminq): Likewise. 10448 (vminaq): Likewise. 10449 (vmaxq): Likewise. 10450 (vmaxaq): Likewise. 10451 (vhsubq_n): Likewise. 10452 (vhsubq): Likewise. 10453 (vhcaddq_rot90): Likewise. 10454 (vhcaddq_rot270): Likewise. 10455 (vhaddq_n): Likewise. 10456 (vhaddq): Likewise. 10457 (veorq): Likewise. 10458 (vcaddq_rot90): Likewise. 10459 (vcaddq_rot270): Likewise. 10460 (vbrsrq_n): Likewise. 10461 (vbicq_n): Likewise. 10462 (vbicq): Likewise. 10463 (vaddq): Likewise. 10464 (vaddq_n): Likewise. 10465 (vandq): Likewise. 10466 (vabdq): Likewise. 10467 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it. 10468 (BINOP_NONE_NONE_NONE): Likewise. 10469 (BINOP_NONE_NONE_UNONE): Likewise. 10470 (BINOP_UNONE_NONE_IMM): Likewise. 10471 (BINOP_UNONE_NONE_NONE): Likewise. 10472 (BINOP_UNONE_UNONE_IMM): Likewise. 10473 (BINOP_UNONE_UNONE_NONE): Likewise. 10474 (BINOP_UNONE_UNONE_UNONE): Likewise. 10475 * config/arm/constraints.md (Ra): Define constraint to check constant is 10476 in the range of 0 to 7. 10477 (Rg): Define constriant to check the constant is one among 1, 2, 4 10478 and 8. 10479 * config/arm/mve.md (mve_vabdq_<supf>): Define RTL pattern. 10480 (mve_vaddq_n_<supf>): Likewise. 10481 (mve_vaddvaq_<supf>): Likewise. 10482 (mve_vaddvq_p_<supf>): Likewise. 10483 (mve_vandq_<supf>): Likewise. 10484 (mve_vbicq_<supf>): Likewise. 10485 (mve_vbrsrq_n_<supf>): Likewise. 10486 (mve_vcaddq_rot270_<supf>): Likewise. 10487 (mve_vcaddq_rot90_<supf>): Likewise. 10488 (mve_vcmpcsq_n_u): Likewise. 10489 (mve_vcmpcsq_u): Likewise. 10490 (mve_vcmpeqq_n_<supf>): Likewise. 10491 (mve_vcmpeqq_<supf>): Likewise. 10492 (mve_vcmpgeq_n_s): Likewise. 10493 (mve_vcmpgeq_s): Likewise. 10494 (mve_vcmpgtq_n_s): Likewise. 10495 (mve_vcmpgtq_s): Likewise. 10496 (mve_vcmphiq_n_u): Likewise. 10497 (mve_vcmphiq_u): Likewise. 10498 (mve_vcmpleq_n_s): Likewise. 10499 (mve_vcmpleq_s): Likewise. 10500 (mve_vcmpltq_n_s): Likewise. 10501 (mve_vcmpltq_s): Likewise. 10502 (mve_vcmpneq_n_<supf>): Likewise. 10503 (mve_vddupq_n_u): Likewise. 10504 (mve_veorq_<supf>): Likewise. 10505 (mve_vhaddq_n_<supf>): Likewise. 10506 (mve_vhaddq_<supf>): Likewise. 10507 (mve_vhcaddq_rot270_s): Likewise. 10508 (mve_vhcaddq_rot90_s): Likewise. 10509 (mve_vhsubq_n_<supf>): Likewise. 10510 (mve_vhsubq_<supf>): Likewise. 10511 (mve_vidupq_n_u): Likewise. 10512 (mve_vmaxaq_s): Likewise. 10513 (mve_vmaxavq_s): Likewise. 10514 (mve_vmaxq_<supf>): Likewise. 10515 (mve_vmaxvq_<supf>): Likewise. 10516 (mve_vminaq_s): Likewise. 10517 (mve_vminavq_s): Likewise. 10518 (mve_vminq_<supf>): Likewise. 10519 (mve_vminvq_<supf>): Likewise. 10520 (mve_vmladavq_<supf>): Likewise. 10521 (mve_vmladavxq_s): Likewise. 10522 (mve_vmlsdavq_s): Likewise. 10523 (mve_vmlsdavxq_s): Likewise. 10524 (mve_vmulhq_<supf>): Likewise. 10525 (mve_vmullbq_int_<supf>): Likewise. 10526 (mve_vmulltq_int_<supf>): Likewise. 10527 (mve_vmulq_n_<supf>): Likewise. 10528 (mve_vmulq_<supf>): Likewise. 10529 (mve_vornq_<supf>): Likewise. 10530 (mve_vorrq_<supf>): Likewise. 10531 (mve_vqaddq_n_<supf>): Likewise. 10532 (mve_vqaddq_<supf>): Likewise. 10533 (mve_vqdmulhq_n_s): Likewise. 10534 (mve_vqdmulhq_s): Likewise. 10535 (mve_vqrdmulhq_n_s): Likewise. 10536 (mve_vqrdmulhq_s): Likewise. 10537 (mve_vqrshlq_n_<supf>): Likewise. 10538 (mve_vqrshlq_<supf>): Likewise. 10539 (mve_vqshlq_n_<supf>): Likewise. 10540 (mve_vqshlq_r_<supf>): Likewise. 10541 (mve_vqshlq_<supf>): Likewise. 10542 (mve_vqshluq_n_s): Likewise. 10543 (mve_vqsubq_n_<supf>): Likewise. 10544 (mve_vqsubq_<supf>): Likewise. 10545 (mve_vrhaddq_<supf>): Likewise. 10546 (mve_vrmulhq_<supf>): Likewise. 10547 (mve_vrshlq_n_<supf>): Likewise. 10548 (mve_vrshlq_<supf>): Likewise. 10549 (mve_vrshrq_n_<supf>): Likewise. 10550 (mve_vshlq_n_<supf>): Likewise. 10551 (mve_vshlq_r_<supf>): Likewise. 10552 (mve_vsubq_n_<supf>): Likewise. 10553 (mve_vsubq_<supf>): Likewise. 10554 * config/arm/predicates.md (mve_imm_7): Define predicate to check 10555 the matching constraint Ra. 10556 (mve_imm_selective_upto_8): Define predicate to check the matching 10557 constraint Rg. 10558 105592020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com> 10560 Mihail Ionescu <mihail.ionescu@arm.com> 10561 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 10562 10563 * config/arm/arm-builtins.c (BINOP_NONE_NONE_UNONE_QUALIFIERS): Define 10564 qualifier for binary operands. 10565 (BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise. 10566 (BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise. 10567 * config/arm/arm_mve.h (vaddlvq_p_s32): Define macro. 10568 (vaddlvq_p_u32): Likewise. 10569 (vcmpneq_s8): Likewise. 10570 (vcmpneq_s16): Likewise. 10571 (vcmpneq_s32): Likewise. 10572 (vcmpneq_u8): Likewise. 10573 (vcmpneq_u16): Likewise. 10574 (vcmpneq_u32): Likewise. 10575 (vshlq_s8): Likewise. 10576 (vshlq_s16): Likewise. 10577 (vshlq_s32): Likewise. 10578 (vshlq_u8): Likewise. 10579 (vshlq_u16): Likewise. 10580 (vshlq_u32): Likewise. 10581 (__arm_vaddlvq_p_s32): Define intrinsic. 10582 (__arm_vaddlvq_p_u32): Likewise. 10583 (__arm_vcmpneq_s8): Likewise. 10584 (__arm_vcmpneq_s16): Likewise. 10585 (__arm_vcmpneq_s32): Likewise. 10586 (__arm_vcmpneq_u8): Likewise. 10587 (__arm_vcmpneq_u16): Likewise. 10588 (__arm_vcmpneq_u32): Likewise. 10589 (__arm_vshlq_s8): Likewise. 10590 (__arm_vshlq_s16): Likewise. 10591 (__arm_vshlq_s32): Likewise. 10592 (__arm_vshlq_u8): Likewise. 10593 (__arm_vshlq_u16): Likewise. 10594 (__arm_vshlq_u32): Likewise. 10595 (vaddlvq_p): Define polymorphic variant. 10596 (vcmpneq): Likewise. 10597 (vshlq): Likewise. 10598 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_UNONE_QUALIFIERS): 10599 Use it. 10600 (BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise. 10601 (BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise. 10602 * config/arm/mve.md (mve_vaddlvq_p_<supf>v4si): Define RTL pattern. 10603 (mve_vcmpneq_<supf><mode>): Likewise. 10604 (mve_vshlq_<supf><mode>): Likewise. 10605 106062020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com> 10607 Mihail Ionescu <mihail.ionescu@arm.com> 10608 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 10609 10610 * config/arm/arm-builtins.c (BINOP_UNONE_UNONE_IMM_QUALIFIERS): Define 10611 qualifier for binary operands. 10612 (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. 10613 (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise. 10614 * config/arm/arm_mve.h (vcvtq_n_s16_f16): Define macro. 10615 (vcvtq_n_s32_f32): Likewise. 10616 (vcvtq_n_u16_f16): Likewise. 10617 (vcvtq_n_u32_f32): Likewise. 10618 (vcreateq_u8): Likewise. 10619 (vcreateq_u16): Likewise. 10620 (vcreateq_u32): Likewise. 10621 (vcreateq_u64): Likewise. 10622 (vcreateq_s8): Likewise. 10623 (vcreateq_s16): Likewise. 10624 (vcreateq_s32): Likewise. 10625 (vcreateq_s64): Likewise. 10626 (vshrq_n_s8): Likewise. 10627 (vshrq_n_s16): Likewise. 10628 (vshrq_n_s32): Likewise. 10629 (vshrq_n_u8): Likewise. 10630 (vshrq_n_u16): Likewise. 10631 (vshrq_n_u32): Likewise. 10632 (__arm_vcreateq_u8): Define intrinsic. 10633 (__arm_vcreateq_u16): Likewise. 10634 (__arm_vcreateq_u32): Likewise. 10635 (__arm_vcreateq_u64): Likewise. 10636 (__arm_vcreateq_s8): Likewise. 10637 (__arm_vcreateq_s16): Likewise. 10638 (__arm_vcreateq_s32): Likewise. 10639 (__arm_vcreateq_s64): Likewise. 10640 (__arm_vshrq_n_s8): Likewise. 10641 (__arm_vshrq_n_s16): Likewise. 10642 (__arm_vshrq_n_s32): Likewise. 10643 (__arm_vshrq_n_u8): Likewise. 10644 (__arm_vshrq_n_u16): Likewise. 10645 (__arm_vshrq_n_u32): Likewise. 10646 (__arm_vcvtq_n_s16_f16): Likewise. 10647 (__arm_vcvtq_n_s32_f32): Likewise. 10648 (__arm_vcvtq_n_u16_f16): Likewise. 10649 (__arm_vcvtq_n_u32_f32): Likewise. 10650 (vshrq_n): Define polymorphic variant. 10651 * config/arm/arm_mve_builtins.def (BINOP_UNONE_UNONE_IMM_QUALIFIERS): 10652 Use it. 10653 (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. 10654 (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise. 10655 * config/arm/constraints.md (Rb): Define constraint to check constant is 10656 in the range of 1 to 8. 10657 (Rf): Define constraint to check constant is in the range of 1 to 32. 10658 * config/arm/mve.md (mve_vcreateq_<supf><mode>): Define RTL pattern. 10659 (mve_vshrq_n_<supf><mode>): Likewise. 10660 (mve_vcvtq_n_from_f_<supf><mode>): Likewise. 10661 * config/arm/predicates.md (mve_imm_8): Define predicate to check 10662 the matching constraint Rb. 10663 (mve_imm_32): Define predicate to check the matching constraint Rf. 10664 106652020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com> 10666 Mihail Ionescu <mihail.ionescu@arm.com> 10667 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 10668 10669 * config/arm/arm-builtins.c (BINOP_NONE_NONE_NONE_QUALIFIERS): Define 10670 qualifier for binary operands. 10671 (BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise. 10672 (BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise. 10673 (BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise. 10674 * config/arm/arm_mve.h (vsubq_n_f16): Define macro. 10675 (vsubq_n_f32): Likewise. 10676 (vbrsrq_n_f16): Likewise. 10677 (vbrsrq_n_f32): Likewise. 10678 (vcvtq_n_f16_s16): Likewise. 10679 (vcvtq_n_f32_s32): Likewise. 10680 (vcvtq_n_f16_u16): Likewise. 10681 (vcvtq_n_f32_u32): Likewise. 10682 (vcreateq_f16): Likewise. 10683 (vcreateq_f32): Likewise. 10684 (__arm_vsubq_n_f16): Define intrinsic. 10685 (__arm_vsubq_n_f32): Likewise. 10686 (__arm_vbrsrq_n_f16): Likewise. 10687 (__arm_vbrsrq_n_f32): Likewise. 10688 (__arm_vcvtq_n_f16_s16): Likewise. 10689 (__arm_vcvtq_n_f32_s32): Likewise. 10690 (__arm_vcvtq_n_f16_u16): Likewise. 10691 (__arm_vcvtq_n_f32_u32): Likewise. 10692 (__arm_vcreateq_f16): Likewise. 10693 (__arm_vcreateq_f32): Likewise. 10694 (vsubq): Define polymorphic variant. 10695 (vbrsrq): Likewise. 10696 (vcvtq_n): Likewise. 10697 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_NONE_QUALIFIERS): Use 10698 it. 10699 (BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise. 10700 (BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise. 10701 (BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise. 10702 * config/arm/constraints.md (Rd): Define constraint to check constant is 10703 in the range of 1 to 16. 10704 * config/arm/mve.md (mve_vsubq_n_f<mode>): Define RTL pattern. 10705 mve_vbrsrq_n_f<mode>: Likewise. 10706 mve_vcvtq_n_to_f_<supf><mode>: Likewise. 10707 mve_vcreateq_f<mode>: Likewise. 10708 * config/arm/predicates.md (mve_imm_16): Define predicate to check 10709 the matching constraint Rd. 10710 107112020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com> 10712 Mihail Ionescu <mihail.ionescu@arm.com> 10713 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 10714 10715 * config/arm/arm-builtins.c (hi_UP): Define mode. 10716 * config/arm/arm.h (IS_VPR_REGNUM): Move. 10717 * config/arm/arm.md (VPR_REGNUM): Define before APSRQ_REGNUM. 10718 (APSRQ_REGNUM): Modify. 10719 (APSRGE_REGNUM): Modify. 10720 * config/arm/arm_mve.h (vctp16q): Define macro. 10721 (vctp32q): Likewise. 10722 (vctp64q): Likewise. 10723 (vctp8q): Likewise. 10724 (vpnot): Likewise. 10725 (__arm_vctp16q): Define intrinsic. 10726 (__arm_vctp32q): Likewise. 10727 (__arm_vctp64q): Likewise. 10728 (__arm_vctp8q): Likewise. 10729 (__arm_vpnot): Likewise. 10730 * config/arm/arm_mve_builtins.def (UNOP_UNONE_UNONE): Use builtin 10731 qualifier. 10732 * config/arm/mve.md (mve_vctp<mode1>qhi): Define RTL pattern. 10733 (mve_vpnothi): Likewise. 10734 107352020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com> 10736 Mihail Ionescu <mihail.ionescu@arm.com> 10737 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 10738 10739 * config/arm/arm.h (enum reg_class): Define new class EVEN_REGS. 10740 * config/arm/arm_mve.h (vdupq_n_s8): Define macro. 10741 (vdupq_n_s16): Likewise. 10742 (vdupq_n_s32): Likewise. 10743 (vabsq_s8): Likewise. 10744 (vabsq_s16): Likewise. 10745 (vabsq_s32): Likewise. 10746 (vclsq_s8): Likewise. 10747 (vclsq_s16): Likewise. 10748 (vclsq_s32): Likewise. 10749 (vclzq_s8): Likewise. 10750 (vclzq_s16): Likewise. 10751 (vclzq_s32): Likewise. 10752 (vnegq_s8): Likewise. 10753 (vnegq_s16): Likewise. 10754 (vnegq_s32): Likewise. 10755 (vaddlvq_s32): Likewise. 10756 (vaddvq_s8): Likewise. 10757 (vaddvq_s16): Likewise. 10758 (vaddvq_s32): Likewise. 10759 (vmovlbq_s8): Likewise. 10760 (vmovlbq_s16): Likewise. 10761 (vmovltq_s8): Likewise. 10762 (vmovltq_s16): Likewise. 10763 (vmvnq_s8): Likewise. 10764 (vmvnq_s16): Likewise. 10765 (vmvnq_s32): Likewise. 10766 (vrev16q_s8): Likewise. 10767 (vrev32q_s8): Likewise. 10768 (vrev32q_s16): Likewise. 10769 (vqabsq_s8): Likewise. 10770 (vqabsq_s16): Likewise. 10771 (vqabsq_s32): Likewise. 10772 (vqnegq_s8): Likewise. 10773 (vqnegq_s16): Likewise. 10774 (vqnegq_s32): Likewise. 10775 (vcvtaq_s16_f16): Likewise. 10776 (vcvtaq_s32_f32): Likewise. 10777 (vcvtnq_s16_f16): Likewise. 10778 (vcvtnq_s32_f32): Likewise. 10779 (vcvtpq_s16_f16): Likewise. 10780 (vcvtpq_s32_f32): Likewise. 10781 (vcvtmq_s16_f16): Likewise. 10782 (vcvtmq_s32_f32): Likewise. 10783 (vmvnq_u8): Likewise. 10784 (vmvnq_u16): Likewise. 10785 (vmvnq_u32): Likewise. 10786 (vdupq_n_u8): Likewise. 10787 (vdupq_n_u16): Likewise. 10788 (vdupq_n_u32): Likewise. 10789 (vclzq_u8): Likewise. 10790 (vclzq_u16): Likewise. 10791 (vclzq_u32): Likewise. 10792 (vaddvq_u8): Likewise. 10793 (vaddvq_u16): Likewise. 10794 (vaddvq_u32): Likewise. 10795 (vrev32q_u8): Likewise. 10796 (vrev32q_u16): Likewise. 10797 (vmovltq_u8): Likewise. 10798 (vmovltq_u16): Likewise. 10799 (vmovlbq_u8): Likewise. 10800 (vmovlbq_u16): Likewise. 10801 (vrev16q_u8): Likewise. 10802 (vaddlvq_u32): Likewise. 10803 (vcvtpq_u16_f16): Likewise. 10804 (vcvtpq_u32_f32): Likewise. 10805 (vcvtnq_u16_f16): Likewise. 10806 (vcvtmq_u16_f16): Likewise. 10807 (vcvtmq_u32_f32): Likewise. 10808 (vcvtaq_u16_f16): Likewise. 10809 (vcvtaq_u32_f32): Likewise. 10810 (__arm_vdupq_n_s8): Define intrinsic. 10811 (__arm_vdupq_n_s16): Likewise. 10812 (__arm_vdupq_n_s32): Likewise. 10813 (__arm_vabsq_s8): Likewise. 10814 (__arm_vabsq_s16): Likewise. 10815 (__arm_vabsq_s32): Likewise. 10816 (__arm_vclsq_s8): Likewise. 10817 (__arm_vclsq_s16): Likewise. 10818 (__arm_vclsq_s32): Likewise. 10819 (__arm_vclzq_s8): Likewise. 10820 (__arm_vclzq_s16): Likewise. 10821 (__arm_vclzq_s32): Likewise. 10822 (__arm_vnegq_s8): Likewise. 10823 (__arm_vnegq_s16): Likewise. 10824 (__arm_vnegq_s32): Likewise. 10825 (__arm_vaddlvq_s32): Likewise. 10826 (__arm_vaddvq_s8): Likewise. 10827 (__arm_vaddvq_s16): Likewise. 10828 (__arm_vaddvq_s32): Likewise. 10829 (__arm_vmovlbq_s8): Likewise. 10830 (__arm_vmovlbq_s16): Likewise. 10831 (__arm_vmovltq_s8): Likewise. 10832 (__arm_vmovltq_s16): Likewise. 10833 (__arm_vmvnq_s8): Likewise. 10834 (__arm_vmvnq_s16): Likewise. 10835 (__arm_vmvnq_s32): Likewise. 10836 (__arm_vrev16q_s8): Likewise. 10837 (__arm_vrev32q_s8): Likewise. 10838 (__arm_vrev32q_s16): Likewise. 10839 (__arm_vqabsq_s8): Likewise. 10840 (__arm_vqabsq_s16): Likewise. 10841 (__arm_vqabsq_s32): Likewise. 10842 (__arm_vqnegq_s8): Likewise. 10843 (__arm_vqnegq_s16): Likewise. 10844 (__arm_vqnegq_s32): Likewise. 10845 (__arm_vmvnq_u8): Likewise. 10846 (__arm_vmvnq_u16): Likewise. 10847 (__arm_vmvnq_u32): Likewise. 10848 (__arm_vdupq_n_u8): Likewise. 10849 (__arm_vdupq_n_u16): Likewise. 10850 (__arm_vdupq_n_u32): Likewise. 10851 (__arm_vclzq_u8): Likewise. 10852 (__arm_vclzq_u16): Likewise. 10853 (__arm_vclzq_u32): Likewise. 10854 (__arm_vaddvq_u8): Likewise. 10855 (__arm_vaddvq_u16): Likewise. 10856 (__arm_vaddvq_u32): Likewise. 10857 (__arm_vrev32q_u8): Likewise. 10858 (__arm_vrev32q_u16): Likewise. 10859 (__arm_vmovltq_u8): Likewise. 10860 (__arm_vmovltq_u16): Likewise. 10861 (__arm_vmovlbq_u8): Likewise. 10862 (__arm_vmovlbq_u16): Likewise. 10863 (__arm_vrev16q_u8): Likewise. 10864 (__arm_vaddlvq_u32): Likewise. 10865 (__arm_vcvtpq_u16_f16): Likewise. 10866 (__arm_vcvtpq_u32_f32): Likewise. 10867 (__arm_vcvtnq_u16_f16): Likewise. 10868 (__arm_vcvtmq_u16_f16): Likewise. 10869 (__arm_vcvtmq_u32_f32): Likewise. 10870 (__arm_vcvtaq_u16_f16): Likewise. 10871 (__arm_vcvtaq_u32_f32): Likewise. 10872 (__arm_vcvtaq_s16_f16): Likewise. 10873 (__arm_vcvtaq_s32_f32): Likewise. 10874 (__arm_vcvtnq_s16_f16): Likewise. 10875 (__arm_vcvtnq_s32_f32): Likewise. 10876 (__arm_vcvtpq_s16_f16): Likewise. 10877 (__arm_vcvtpq_s32_f32): Likewise. 10878 (__arm_vcvtmq_s16_f16): Likewise. 10879 (__arm_vcvtmq_s32_f32): Likewise. 10880 (vdupq_n): Define polymorphic variant. 10881 (vabsq): Likewise. 10882 (vclsq): Likewise. 10883 (vclzq): Likewise. 10884 (vnegq): Likewise. 10885 (vaddlvq): Likewise. 10886 (vaddvq): Likewise. 10887 (vmovlbq): Likewise. 10888 (vmovltq): Likewise. 10889 (vmvnq): Likewise. 10890 (vrev16q): Likewise. 10891 (vrev32q): Likewise. 10892 (vqabsq): Likewise. 10893 (vqnegq): Likewise. 10894 * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it. 10895 (UNOP_SNONE_NONE): Likewise. 10896 (UNOP_UNONE_UNONE): Likewise. 10897 (UNOP_UNONE_NONE): Likewise. 10898 * config/arm/constraints.md (e): Define new constriant to allow only 10899 even registers. 10900 * config/arm/mve.md (mve_vqabsq_s<mode>): Define RTL pattern. 10901 (mve_vnegq_s<mode>): Likewise. 10902 (mve_vmvnq_<supf><mode>): Likewise. 10903 (mve_vdupq_n_<supf><mode>): Likewise. 10904 (mve_vclzq_<supf><mode>): Likewise. 10905 (mve_vclsq_s<mode>): Likewise. 10906 (mve_vaddvq_<supf><mode>): Likewise. 10907 (mve_vabsq_s<mode>): Likewise. 10908 (mve_vrev32q_<supf><mode>): Likewise. 10909 (mve_vmovltq_<supf><mode>): Likewise. 10910 (mve_vmovlbq_<supf><mode>): Likewise. 10911 (mve_vcvtpq_<supf><mode>): Likewise. 10912 (mve_vcvtnq_<supf><mode>): Likewise. 10913 (mve_vcvtmq_<supf><mode>): Likewise. 10914 (mve_vcvtaq_<supf><mode>): Likewise. 10915 (mve_vrev16q_<supf>v16qi): Likewise. 10916 (mve_vaddlvq_<supf>v4si): Likewise. 10917 109182020-03-17 Jakub Jelinek <jakub@redhat.com> 10919 10920 * lra-spills.c (remove_pseudos): Fix up duplicated word issue in 10921 a dump message. 10922 * tree-sra.c (create_access_replacement): Fix up duplicated word issue 10923 in a comment. 10924 * read-rtl-function.c (find_param_by_name, 10925 function_reader::parse_enum_value, function_reader::get_insn_by_uid): 10926 Likewise. 10927 * spellcheck.c (get_edit_distance_cutoff): Likewise. 10928 * tree-data-ref.c (create_ifn_alias_checks): Likewise. 10929 * tree.def (SWITCH_EXPR): Likewise. 10930 * selftest.c (assert_str_contains): Likewise. 10931 * ipa-param-manipulation.h (class ipa_param_body_adjustments): 10932 Likewise. 10933 * tree-ssa-math-opts.c (convert_expand_mult_copysign): Likewise. 10934 * tree-ssa-loop-split.c (find_vdef_in_loop): Likewise. 10935 * langhooks.h (struct lang_hooks_for_decls): Likewise. 10936 * ipa-prop.h (struct ipa_param_descriptor): Likewise. 10937 * tree-ssa-strlen.c (handle_builtin_string_cmp, handle_store): 10938 Likewise. 10939 * tree-ssa-dom.c (simplify_stmt_for_jump_threading): Likewise. 10940 * tree-ssa-reassoc.c (reassociate_bb): Likewise. 10941 * tree.c (component_ref_size): Likewise. 10942 * hsa-common.c (hsa_init_compilation_unit_data): Likewise. 10943 * gimple-ssa-sprintf.c (get_string_length, format_string, 10944 format_directive): Likewise. 10945 * omp-grid.c (grid_process_kernel_body_copy): Likewise. 10946 * input.c (string_concat_db::get_string_concatenation, 10947 test_lexer_string_locations_ucn4): Likewise. 10948 * cfgexpand.c (pass_expand::execute): Likewise. 10949 * gimple-ssa-warn-restrict.c (builtin_memref::offset_out_of_bounds, 10950 maybe_diag_overlap): Likewise. 10951 * rtl.c (RTX_CODE_HWINT_P_1): Likewise. 10952 * shrink-wrap.c (spread_components): Likewise. 10953 * tree-ssa-dse.c (initialize_ao_ref_for_dse, valid_ao_ref_for_dse): 10954 Likewise. 10955 * tree-call-cdce.c (shrink_wrap_one_built_in_call_with_conds): 10956 Likewise. 10957 * dwarf2out.c (dwarf2out_early_finish): Likewise. 10958 * gimple-ssa-store-merging.c: Likewise. 10959 * ira-costs.c (record_operand_costs): Likewise. 10960 * tree-vect-loop.c (vectorizable_reduction): Likewise. 10961 * target.def (dispatch): Likewise. 10962 (validate_dims, gen_ccmp_first): Fix up duplicated word issue 10963 in documentation text. 10964 * doc/tm.texi: Regenerated. 10965 * config/i386/x86-tune.def (X86_TUNE_PARTIAL_FLAG_REG_STALL): Fix up 10966 duplicated word issue in a comment. 10967 * config/i386/i386.c (ix86_test_loading_unspec): Likewise. 10968 * config/i386/i386-features.c (remove_partial_avx_dependency): 10969 Likewise. 10970 * config/msp430/msp430.c (msp430_select_section): Likewise. 10971 * config/gcn/gcn-run.c (load_image): Likewise. 10972 * config/aarch64/aarch64-sve.md (sve_ld1r<mode>): Likewise. 10973 * config/aarch64/aarch64.c (aarch64_gen_adjusted_ldpstp): Likewise. 10974 * config/aarch64/falkor-tag-collision-avoidance.c 10975 (single_dest_per_chain): Likewise. 10976 * config/nvptx/nvptx.c (nvptx_record_fndecl): Likewise. 10977 * config/fr30/fr30.c (fr30_arg_partial_bytes): Likewise. 10978 * config/rs6000/rs6000-string.c (expand_cmp_vec_sequence): Likewise. 10979 * config/rs6000/rs6000-p8swap.c (replace_swapped_load_constant): 10980 Likewise. 10981 * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Likewise. 10982 * config/rs6000/rs6000.c (rs6000_option_override_internal): Likewise. 10983 * config/rs6000/rs6000-logue.c 10984 (rs6000_emit_probe_stack_range_stack_clash): Likewise. 10985 * config/nds32/nds32-md-auxiliary.c (nds32_split_ashiftdi3): Likewise. 10986 Fix various other issues in the comment. 10987 109882020-03-17 Mihail Ionescu <mihail.ionescu@arm.com> 10989 10990 * config/arm/t-rmprofile: create new multilib for 10991 armv8.1-m.main+mve hard float and reuse v8-m.main ones for 10992 v8.1-m.main+mve. 10993 109942020-03-17 Jakub Jelinek <jakub@redhat.com> 10995 10996 PR tree-optimization/94015 10997 * tree-ssa-strlen.c (count_nonzero_bytes): Split portions of the 10998 function where EXP is address of the bytes being stored rather than 10999 the bytes themselves into count_nonzero_bytes_addr. Punt on zero 11000 sized MEM_REF. Use VAR_P macro and handle CONST_DECL like VAR_DECLs. 11001 Use ctor_for_folding instead of looking at DECL_INITIAL. Punt before 11002 calling native_encode_expr if host or target doesn't have 8-bit 11003 chars. Formatting fixes. 11004 (count_nonzero_bytes_addr): New function. 11005 110062020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com> 11007 Mihail Ionescu <mihail.ionescu@arm.com> 11008 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 11009 11010 * config/arm/arm-builtins.c (UNOP_SNONE_SNONE_QUALIFIERS): Define. 11011 (UNOP_SNONE_NONE_QUALIFIERS): Likewise. 11012 (UNOP_SNONE_IMM_QUALIFIERS): Likewise. 11013 (UNOP_UNONE_NONE_QUALIFIERS): Likewise. 11014 (UNOP_UNONE_UNONE_QUALIFIERS): Likewise. 11015 (UNOP_UNONE_IMM_QUALIFIERS): Likewise. 11016 * config/arm/arm_mve.h (vmvnq_n_s16): Define macro. 11017 (vmvnq_n_s32): Likewise. 11018 (vrev64q_s8): Likewise. 11019 (vrev64q_s16): Likewise. 11020 (vrev64q_s32): Likewise. 11021 (vcvtq_s16_f16): Likewise. 11022 (vcvtq_s32_f32): Likewise. 11023 (vrev64q_u8): Likewise. 11024 (vrev64q_u16): Likewise. 11025 (vrev64q_u32): Likewise. 11026 (vmvnq_n_u16): Likewise. 11027 (vmvnq_n_u32): Likewise. 11028 (vcvtq_u16_f16): Likewise. 11029 (vcvtq_u32_f32): Likewise. 11030 (__arm_vmvnq_n_s16): Define intrinsic. 11031 (__arm_vmvnq_n_s32): Likewise. 11032 (__arm_vrev64q_s8): Likewise. 11033 (__arm_vrev64q_s16): Likewise. 11034 (__arm_vrev64q_s32): Likewise. 11035 (__arm_vrev64q_u8): Likewise. 11036 (__arm_vrev64q_u16): Likewise. 11037 (__arm_vrev64q_u32): Likewise. 11038 (__arm_vmvnq_n_u16): Likewise. 11039 (__arm_vmvnq_n_u32): Likewise. 11040 (__arm_vcvtq_s16_f16): Likewise. 11041 (__arm_vcvtq_s32_f32): Likewise. 11042 (__arm_vcvtq_u16_f16): Likewise. 11043 (__arm_vcvtq_u32_f32): Likewise. 11044 (vrev64q): Define polymorphic variant. 11045 * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it. 11046 (UNOP_SNONE_NONE): Likewise. 11047 (UNOP_SNONE_IMM): Likewise. 11048 (UNOP_UNONE_UNONE): Likewise. 11049 (UNOP_UNONE_NONE): Likewise. 11050 (UNOP_UNONE_IMM): Likewise. 11051 * config/arm/mve.md (mve_vrev64q_<supf><mode>): Define RTL pattern. 11052 (mve_vcvtq_from_f_<supf><mode>): Likewise. 11053 (mve_vmvnq_n_<supf><mode>): Likewise. 11054 110552020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com> 11056 Mihail Ionescu <mihail.ionescu@arm.com> 11057 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 11058 11059 * config/arm/arm-builtins.c (UNOP_NONE_NONE_QUALIFIERS): Define macro. 11060 (UNOP_NONE_SNONE_QUALIFIERS): Likewise. 11061 (UNOP_NONE_UNONE_QUALIFIERS): Likewise. 11062 * config/arm/arm_mve.h (vrndxq_f16): Define macro. 11063 (vrndxq_f32): Likewise. 11064 (vrndq_f16) Likewise. 11065 (vrndq_f32): Likewise. 11066 (vrndpq_f16): Likewise. 11067 (vrndpq_f32): Likewise. 11068 (vrndnq_f16): Likewise. 11069 (vrndnq_f32): Likewise. 11070 (vrndmq_f16): Likewise. 11071 (vrndmq_f32): Likewise. 11072 (vrndaq_f16): Likewise. 11073 (vrndaq_f32): Likewise. 11074 (vrev64q_f16): Likewise. 11075 (vrev64q_f32): Likewise. 11076 (vnegq_f16): Likewise. 11077 (vnegq_f32): Likewise. 11078 (vdupq_n_f16): Likewise. 11079 (vdupq_n_f32): Likewise. 11080 (vabsq_f16): Likewise. 11081 (vabsq_f32): Likewise. 11082 (vrev32q_f16): Likewise. 11083 (vcvttq_f32_f16): Likewise. 11084 (vcvtbq_f32_f16): Likewise. 11085 (vcvtq_f16_s16): Likewise. 11086 (vcvtq_f32_s32): Likewise. 11087 (vcvtq_f16_u16): Likewise. 11088 (vcvtq_f32_u32): Likewise. 11089 (__arm_vrndxq_f16): Define intrinsic. 11090 (__arm_vrndxq_f32): Likewise. 11091 (__arm_vrndq_f16): Likewise. 11092 (__arm_vrndq_f32): Likewise. 11093 (__arm_vrndpq_f16): Likewise. 11094 (__arm_vrndpq_f32): Likewise. 11095 (__arm_vrndnq_f16): Likewise. 11096 (__arm_vrndnq_f32): Likewise. 11097 (__arm_vrndmq_f16): Likewise. 11098 (__arm_vrndmq_f32): Likewise. 11099 (__arm_vrndaq_f16): Likewise. 11100 (__arm_vrndaq_f32): Likewise. 11101 (__arm_vrev64q_f16): Likewise. 11102 (__arm_vrev64q_f32): Likewise. 11103 (__arm_vnegq_f16): Likewise. 11104 (__arm_vnegq_f32): Likewise. 11105 (__arm_vdupq_n_f16): Likewise. 11106 (__arm_vdupq_n_f32): Likewise. 11107 (__arm_vabsq_f16): Likewise. 11108 (__arm_vabsq_f32): Likewise. 11109 (__arm_vrev32q_f16): Likewise. 11110 (__arm_vcvttq_f32_f16): Likewise. 11111 (__arm_vcvtbq_f32_f16): Likewise. 11112 (__arm_vcvtq_f16_s16): Likewise. 11113 (__arm_vcvtq_f32_s32): Likewise. 11114 (__arm_vcvtq_f16_u16): Likewise. 11115 (__arm_vcvtq_f32_u32): Likewise. 11116 (vrndxq): Define polymorphic variants. 11117 (vrndq): Likewise. 11118 (vrndpq): Likewise. 11119 (vrndnq): Likewise. 11120 (vrndmq): Likewise. 11121 (vrndaq): Likewise. 11122 (vrev64q): Likewise. 11123 (vnegq): Likewise. 11124 (vabsq): Likewise. 11125 (vrev32q): Likewise. 11126 (vcvtbq_f32): Likewise. 11127 (vcvttq_f32): Likewise. 11128 (vcvtq): Likewise. 11129 * config/arm/arm_mve_builtins.def (VAR2): Define. 11130 (VAR1): Define. 11131 * config/arm/mve.md (mve_vrndxq_f<mode>): Add RTL pattern. 11132 (mve_vrndq_f<mode>): Likewise. 11133 (mve_vrndpq_f<mode>): Likewise. 11134 (mve_vrndnq_f<mode>): Likewise. 11135 (mve_vrndmq_f<mode>): Likewise. 11136 (mve_vrndaq_f<mode>): Likewise. 11137 (mve_vrev64q_f<mode>): Likewise. 11138 (mve_vnegq_f<mode>): Likewise. 11139 (mve_vdupq_n_f<mode>): Likewise. 11140 (mve_vabsq_f<mode>): Likewise. 11141 (mve_vrev32q_fv8hf): Likewise. 11142 (mve_vcvttq_f32_f16v4sf): Likewise. 11143 (mve_vcvtbq_f32_f16v4sf): Likewise. 11144 (mve_vcvtq_to_f_<supf><mode>): Likewise. 11145 111462020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com> 11147 Mihail Ionescu <mihail.ionescu@arm.com> 11148 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 11149 11150 * config/arm/arm-builtins.c (CF): Define mve_builtin_data. 11151 (VAR1): Define. 11152 (ARM_BUILTIN_MVE_PATTERN_START): Define. 11153 (arm_init_mve_builtins): Define function. 11154 (arm_init_builtins): Add TARGET_HAVE_MVE check. 11155 (arm_expand_builtin_1): Check the range of fcode. 11156 (arm_expand_mve_builtin): Define function to expand MVE builtins. 11157 (arm_expand_builtin): Check the range of fcode. 11158 * config/arm/arm_mve.h (__ARM_FEATURE_MVE): Define MVE floating point 11159 types. 11160 (__ARM_MVE_PRESERVE_USER_NAMESPACE): Define to protect user namespace. 11161 (vst4q_s8): Define macro. 11162 (vst4q_s16): Likewise. 11163 (vst4q_s32): Likewise. 11164 (vst4q_u8): Likewise. 11165 (vst4q_u16): Likewise. 11166 (vst4q_u32): Likewise. 11167 (vst4q_f16): Likewise. 11168 (vst4q_f32): Likewise. 11169 (__arm_vst4q_s8): Define inline builtin. 11170 (__arm_vst4q_s16): Likewise. 11171 (__arm_vst4q_s32): Likewise. 11172 (__arm_vst4q_u8): Likewise. 11173 (__arm_vst4q_u16): Likewise. 11174 (__arm_vst4q_u32): Likewise. 11175 (__arm_vst4q_f16): Likewise. 11176 (__arm_vst4q_f32): Likewise. 11177 (__ARM_mve_typeid): Define macro with MVE types. 11178 (__ARM_mve_coerce): Define macro with _Generic feature. 11179 (vst4q): Define polymorphic variant for different vst4q builtins. 11180 * config/arm/arm_mve_builtins.def: New file. 11181 * config/arm/iterators.md (VSTRUCT): Modify to allow XI and OI 11182 modes in MVE. 11183 * config/arm/mve.md (MVE_VLD_ST): Define iterator. 11184 (unspec): Define unspec. 11185 (mve_vst4q<mode>): Define RTL pattern. 11186 * config/arm/neon.md (mov<mode>): Modify expand to allow XI and OI 11187 modes in MVE. 11188 (neon_mov<mode>): Modify RTL define_insn to allow XI and OI modes 11189 in MVE. 11190 (define_split): Allow OI mode split for MVE after reload. 11191 (define_split): Allow XI mode split for MVE after reload. 11192 * config/arm/t-arm (arm.o): Add entry for arm_mve_builtins.def. 11193 (arm-builtins.o): Likewise. 11194 111952020-03-17 Christophe Lyon <christophe.lyon@linaro.org> 11196 11197 * c-typeck.c (process_init_element): Handle constructor_type with 11198 type size represented by POLY_INT_CST. 11199 112002020-03-17 Jakub Jelinek <jakub@redhat.com> 11201 11202 PR tree-optimization/94187 11203 * tree-ssa-strlen.c (count_nonzero_bytes): Punt if 11204 nchars - offset < nbytes. 11205 11206 PR middle-end/94189 11207 * builtins.c (expand_builtin_strnlen): Do return NULL_RTX if we would 11208 emit a warning if it was enabled and don't depend on TREE_NO_WARNING 11209 for code-generation. 11210 112112020-03-16 Vladimir Makarov <vmakarov@redhat.com> 11212 11213 PR target/94185 11214 * lra-spills.c (remove_pseudos): Do not reuse insn alternative 11215 after changing memory subreg. 11216 112172020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com> 11218 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 11219 11220 * config/arm/arm.c (arm_libcall_uses_aapcs_base): Modify function to add 11221 emulator calls for dobule precision arithmetic operations for MVE. 11222 112232020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com> 11224 Mihail Ionescu <mihail.ionescu@arm.com> 11225 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 11226 11227 * common/config/arm/arm-common.c (arm_asm_auto_mfpu): When vfp_base 11228 feature bit is on and -mfpu=auto is passed as compiler option, do not 11229 generate error on not finding any matching fpu. Because in this case 11230 fpu is not required. 11231 * config/arm/arm-cpus.in (vfp_base): Define feature bit, this bit is 11232 enabled for MVE and also for all VFP extensions. 11233 (VFPv2): Modify fgroup to enable vfp_base feature bit when ever VFPv2 11234 is enabled. 11235 (MVE): Define fgroup to enable feature bits mve, vfp_base and armv7em. 11236 (MVE_FP): Define fgroup to enable feature bits is fgroup MVE and FPv5 11237 along with feature bits mve_float. 11238 (mve): Modify add options in armv8.1-m.main arch for MVE. 11239 (mve.fp): Modify add options in armv8.1-m.main arch for MVE with 11240 floating point. 11241 * config/arm/arm.c (use_return_insn): Replace the 11242 check with TARGET_VFP_BASE. 11243 (thumb2_legitimate_index_p): Replace TARGET_HARD_FLOAT with 11244 TARGET_VFP_BASE. 11245 (arm_rtx_costs_internal): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE" 11246 with TARGET_VFP_BASE, to allow cost calculations for copies in MVE as 11247 well. 11248 (arm_get_vfp_saved_size): Replace TARGET_HARD_FLOAT with 11249 TARGET_VFP_BASE, to allow space calculation for VFP registers in MVE 11250 as well. 11251 (arm_compute_frame_layout): Likewise. 11252 (arm_save_coproc_regs): Likewise. 11253 (arm_fixed_condition_code_regs): Modify to enable using VFPCC_REGNUM 11254 in MVE as well. 11255 (arm_hard_regno_mode_ok): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE" 11256 with equivalent macro TARGET_VFP_BASE. 11257 (arm_expand_epilogue_apcs_frame): Likewise. 11258 (arm_expand_epilogue): Likewise. 11259 (arm_conditional_register_usage): Likewise. 11260 (arm_declare_function_name): Add check to skip printing .fpu directive 11261 in assembly file when TARGET_VFP_BASE is enabled and fpu_to_print is 11262 "softvfp". 11263 * config/arm/arm.h (TARGET_VFP_BASE): Define. 11264 * config/arm/arm.md (arch): Add "mve" to arch. 11265 (eq_attr "arch" "mve"): Enable on TARGET_HAVE_MVE is true. 11266 (vfp_pop_multiple_with_writeback): Replace "TARGET_HARD_FLOAT 11267 || TARGET_HAVE_MVE" with equivalent macro TARGET_VFP_BASE. 11268 * config/arm/constraints.md (Uf): Define to allow modification to FPCCR 11269 in MVE. 11270 * config/arm/thumb2.md (thumb2_movsfcc_soft_insn): Modify target guard 11271 to not allow for MVE. 11272 * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Move to volatile unspecs 11273 enum. 11274 (VUNSPEC_GET_FPSCR): Define. 11275 * config/arm/vfp.md (thumb2_movhi_vfp): Add support for VMSR and VMRS 11276 instructions which move to general-purpose Register from Floating-point 11277 Special register and vice-versa. 11278 (thumb2_movhi_fp16): Likewise. 11279 (thumb2_movsi_vfp): Add support for VMSR and VMRS instructions along 11280 with MCR and MRC instructions which set and get Floating-point Status 11281 and Control Register (FPSCR). 11282 (movdi_vfp): Modify pattern to enable Single-precision scalar float move 11283 in MVE. 11284 (thumb2_movdf_vfp): Modify pattern to enable Double-precision scalar 11285 float move patterns in MVE. 11286 (thumb2_movsfcc_vfp): Modify pattern to enable single float conditional 11287 code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check. 11288 (thumb2_movdfcc_vfp): Modify pattern to enable double float conditional 11289 code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check. 11290 (push_multi_vfp): Add support to use VFP VPUSH pattern for MVE by adding 11291 TARGET_VFP_BASE check. 11292 (set_fpscr): Add support to set FPSCR register for MVE. Modify pattern 11293 using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR 11294 register. 11295 (get_fpscr): Add support to get FPSCR register for MVE. Modify pattern 11296 using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR 11297 register. 11298 11299 113002020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com> 11301 Mihail Ionescu <mihail.ionescu@arm.com> 11302 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 11303 11304 * config.gcc (arm_mve.h): Include mve intrinsics header file. 11305 * config/arm/aout.h (p0): Add new register name for MVE predicated 11306 cases. 11307 * config/arm-builtins.c (ARM_BUILTIN_SIMD_LANE_CHECK): Define macro 11308 common to Neon and MVE. 11309 (ARM_BUILTIN_NEON_LANE_CHECK): Renamed to ARM_BUILTIN_SIMD_LANE_CHECK. 11310 (arm_init_simd_builtin_types): Disable poly types for MVE. 11311 (arm_init_neon_builtins): Move a check to arm_init_builtins function. 11312 (arm_init_builtins): Use ARM_BUILTIN_SIMD_LANE_CHECK instead of 11313 ARM_BUILTIN_NEON_LANE_CHECK. 11314 (mve_dereference_pointer): Add function. 11315 (arm_expand_builtin_args): Call to mve_dereference_pointer when MVE is 11316 enabled. 11317 (arm_expand_neon_builtin): Moved to arm_expand_builtin function. 11318 (arm_expand_builtin): Moved from arm_expand_neon_builtin function. 11319 * config/arm/arm-c.c (__ARM_FEATURE_MVE): Define macro for MVE and MVE 11320 with floating point enabled. 11321 * config/arm/arm-protos.h (neon_immediate_valid_for_move): Renamed to 11322 simd_immediate_valid_for_move. 11323 (simd_immediate_valid_for_move): Renamed from 11324 neon_immediate_valid_for_move function. 11325 * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Generate 11326 error if vfpv2 feature bit is disabled and mve feature bit is also 11327 disabled for HARD_FLOAT_ABI. 11328 (use_return_insn): Check to not push VFP regs for MVE. 11329 (aapcs_vfp_allocate): Add MVE check to have same Procedure Call Standard 11330 as Neon. 11331 (aapcs_vfp_allocate_return_reg): Likewise. 11332 (thumb2_legitimate_address_p): Check to return 0 on valid Thumb-2 11333 address operand for MVE. 11334 (arm_rtx_costs_internal): MVE check to determine cost of rtx. 11335 (neon_valid_immediate): Rename to simd_valid_immediate. 11336 (simd_valid_immediate): Rename from neon_valid_immediate. 11337 (simd_valid_immediate): MVE check on size of vector is 128 bits. 11338 (neon_immediate_valid_for_move): Rename to 11339 simd_immediate_valid_for_move. 11340 (simd_immediate_valid_for_move): Rename from 11341 neon_immediate_valid_for_move. 11342 (neon_immediate_valid_for_logic): Modify call to neon_valid_immediate 11343 function. 11344 (neon_make_constant): Modify call to neon_valid_immediate function. 11345 (neon_vector_mem_operand): Return VFP register for POST_INC or PRE_DEC 11346 for MVE. 11347 (output_move_neon): Add MVE check to generate vldm/vstm instrcutions. 11348 (arm_compute_frame_layout): Calculate space for saved VFP registers for 11349 MVE. 11350 (arm_save_coproc_regs): Save coproc registers for MVE. 11351 (arm_print_operand): Add case 'E' to print memory operands for MVE. 11352 (arm_print_operand_address): Check to print register number for MVE. 11353 (arm_hard_regno_mode_ok): Check for arm hard regno mode ok for MVE. 11354 (arm_modes_tieable_p): Check to allow structure mode for MVE. 11355 (arm_regno_class): Add VPR_REGNUM check. 11356 (arm_expand_epilogue_apcs_frame): MVE check to calculate epilogue code 11357 for APCS frame. 11358 (arm_expand_epilogue): MVE check for enabling pop instructions in 11359 epilogue. 11360 (arm_print_asm_arch_directives): Modify function to disable print of 11361 .arch_extension "mve" and "fp" for cases where MVE is enabled with 11362 "SOFT FLOAT ABI". 11363 (arm_vector_mode_supported_p): Check for modes available in MVE interger 11364 and MVE floating point. 11365 (arm_array_mode_supported_p): Add TARGET_HAVE_MVE check for array mode 11366 pointer support. 11367 (arm_conditional_register_usage): Enable usage of conditional regsiter 11368 for MVE. 11369 (fixed_regs[VPR_REGNUM]): Enable VPR_REG for MVE. 11370 (arm_declare_function_name): Modify function to disable print of 11371 .arch_extension "mve" and "fp" for cases where MVE is enabled with 11372 "SOFT FLOAT ABI". 11373 * config/arm/arm.h (TARGET_HAVE_MVE): Disable for soft float abi and 11374 when target general registers are required. 11375 (TARGET_HAVE_MVE_FLOAT): Likewise. 11376 (FIXED_REGISTERS): Add bit for VFP_REG class which is enabled in arm.c 11377 for MVE. 11378 (CALL_USED_REGISTERS): Set bit for VFP_REG class in CALL_USED_REGISTERS 11379 which indicate this is not available for across function calls. 11380 (FIRST_PSEUDO_REGISTER): Modify. 11381 (VALID_MVE_MODE): Define valid MVE mode. 11382 (VALID_MVE_SI_MODE): Define valid MVE SI mode. 11383 (VALID_MVE_SF_MODE): Define valid MVE SF mode. 11384 (VALID_MVE_STRUCT_MODE): Define valid MVE struct mode. 11385 (VPR_REGNUM): Add Vector Predication Register in arm_regs_in_sequence 11386 for MVE. 11387 (IS_VPR_REGNUM): Macro to check for VPR_REG register. 11388 (REG_ALLOC_ORDER): Add VPR_REGNUM entry. 11389 (enum reg_class): Add VPR_REG entry. 11390 (REG_CLASS_NAMES): Add VPR_REG entry. 11391 * config/arm/arm.md (VPR_REGNUM): Define. 11392 (conds): Check is_mve_type attrbiute to differentiate "conditional" and 11393 "unconditional" instructions. 11394 (arm_movsf_soft_insn): Modify RTL to not allow for MVE. 11395 (movdf_soft_insn): Modify RTL to not allow for MVE. 11396 (vfp_pop_multiple_with_writeback): Enable for MVE. 11397 (include "mve.md"): Include mve.md file. 11398 * config/arm/arm_mve.h: Add MVE intrinsics head file. 11399 * config/arm/constraints.md (Up): Constraint to enable "p0" register in MVE 11400 for vector predicated operands. 11401 * config/arm/iterators.md (VNIM1): Define. 11402 (VNINOTM1): Define. 11403 (VHFBF_split): Define 11404 * config/arm/mve.md: New file. 11405 (mve_mov<mode>): Define RTL for move, store and load in MVE. 11406 (mve_mov<mode>): Define move RTL pattern with vec_duplicate operator for 11407 second operand. 11408 * config/arm/neon.md (neon_immediate_valid_for_move): Rename with 11409 simd_immediate_valid_for_move. 11410 (neon_mov<mode>): Split pattern and move expand pattern "movv8hf" which 11411 is common to MVE and NEON to vec-common.md file. 11412 (vec_init<mode><V_elem_l>): Add TARGET_HAVE_MVE check. 11413 * config/arm/predicates.md (vpr_register_operand): Define. 11414 * config/arm/t-arm: Add mve.md file. 11415 * config/arm/types.md (mve_move): Add MVE instructions mve_move to 11416 attribute "type". 11417 (mve_store): Add MVE instructions mve_store to attribute "type". 11418 (mve_load): Add MVE instructions mve_load to attribute "type". 11419 (is_mve_type): Define attribute. 11420 * config/arm/vec-common.md (mov<mode>): Modify RTL expand to support 11421 standard move patterns in MVE along with NEON and IWMMXT with mode 11422 iterator VNIM1. 11423 (mov<mode>): Modify RTL expand to support standard move patterns in NEON 11424 and IWMMXT with mode iterator V8HF. 11425 (movv8hf): Define RTL expand to support standard "movv8hf" pattern in 11426 NEON and MVE. 11427 * config/arm/vfp.md (neon_immediate_valid_for_move): Rename to 11428 simd_immediate_valid_for_move. 11429 11430 114312020-03-16 H.J. Lu <hongjiu.lu@intel.com> 11432 11433 PR target/89229 11434 * config/i386/i386.md (*movsi_internal): Call ix86_output_ssemov 11435 for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL 11436 check. 11437 * config/i386/predicates.md (ext_sse_reg_operand): Removed. 11438 114392020-03-16 Jakub Jelinek <jakub@redhat.com> 11440 11441 PR debug/94167 11442 * tree-inline.c (insert_init_stmt): Don't gimple_regimplify_operands 11443 DEBUG_STMTs. 11444 11445 PR tree-optimization/94166 11446 * tree-ssa-reassoc.c (sort_by_mach_mode): Use SSA_NAME_VERSION 11447 as secondary comparison key. 11448 114492020-03-16 Bin Cheng <bin.cheng@linux.alibaba.com> 11450 11451 PR tree-optimization/94125 11452 * tree-loop-distribution.c 11453 (loop_distribution::break_alias_scc_partitions): Update post order 11454 number for merged scc. 11455 114562020-03-15 H.J. Lu <hongjiu.lu@intel.com> 11457 11458 PR target/89229 11459 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_SI and 11460 MODE_SF. 11461 * config/i386/i386.md (*movsf_internal): Call ix86_output_ssemov 11462 for TYPE_SSEMOV. Remove TARGET_PREFER_AVX256, TARGET_AVX512VL 11463 and ext_sse_reg_operand check. 11464 114652020-03-15 Lewis Hyatt <lhyatt@gmail.com> 11466 11467 * common.opt: Avoid redundancy in the help text. 11468 * config/arc/arc.opt: Likewise. 11469 * config/cr16/cr16.opt: Likewise. 11470 114712020-03-14 Jakub Jelinek <jakub@redhat.com> 11472 11473 PR middle-end/93566 11474 * tree-nested.c (convert_nonlocal_omp_clauses, 11475 convert_local_omp_clauses): Handle {,in_,task_}reduction clauses 11476 with C/C++ array sections. 11477 114782020-03-14 H.J. Lu <hongjiu.lu@intel.com> 11479 11480 PR target/89229 11481 * config/i386/i386.md (*movdi_internal): Call ix86_output_ssemov 11482 for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL 11483 check. 11484 114852020-03-14 Jakub Jelinek <jakub@redhat.com> 11486 11487 * gimple-fold.c (gimple_fold_builtin_strncpy): Change 11488 "a an" to "an" in a comment. 11489 * hsa-common.h (is_a_helper): Likewise. 11490 * tree-ssa-strlen.c (maybe_diag_stxncpy_trunc): Likewise. 11491 * config/arc/arc.c (arc600_corereg_hazard): Likewise. 11492 * config/s390/s390.c (s390_indirect_branch_via_thunk): Likewise. 11493 114942020-03-13 Aaron Sawdey <acsawdey@linux.ibm.com> 11495 11496 PR target/92379 11497 * config/rs6000/rs6000.c (num_insns_constant_multi): Don't shift a 11498 64-bit value by 64 bits (UB). 11499 115002020-03-13 Vladimir Makarov <vmakarov@redhat.com> 11501 11502 PR rtl-optimization/92303 11503 * lra-spills.c (remove_pseudos): Try to simplify memory subreg. 11504 115052020-03-13 Segher Boessenkool <segher@kernel.crashing.org> 11506 11507 PR rtl-optimization/94148 11508 PR rtl-optimization/94042 11509 * df-core.c (BB_LAST_CHANGE_AGE): Delete. 11510 (df_worklist_propagate_forward): New parameter last_change_age, use 11511 that instead of bb->aux. 11512 (df_worklist_propagate_backward): Ditto. 11513 (df_worklist_dataflow_doublequeue): Use a local array last_change_age. 11514 115152020-03-13 Richard Biener <rguenther@suse.de> 11516 11517 PR tree-optimization/94163 11518 * tree-ssa-pre.c (create_expression_by_pieces): Check 11519 whether alignment would be zero. 11520 115212020-03-13 Martin Liska <mliska@suse.cz> 11522 11523 PR lto/94157 11524 * lto-wrapper.c (run_gcc): Use concat for appending 11525 to collect_gcc_options. 11526 115272020-03-13 Jakub Jelinek <jakub@redhat.com> 11528 11529 PR target/94121 11530 * config/aarch64/aarch64.c (aarch64_add_offset_1): Use gen_int_mode 11531 instead of GEN_INT. 11532 115332020-03-13 H.J. Lu <hongjiu.lu@intel.com> 11534 11535 PR target/89229 11536 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_DF. 11537 * config/i386/i386.md (*movdf_internal): Call ix86_output_ssemov 11538 for TYPE_SSEMOV. Remove TARGET_AVX512F, TARGET_PREFER_AVX256, 11539 TARGET_AVX512VL and ext_sse_reg_operand check. 11540 115412020-03-13 Bu Le <bule1@huawei.com> 11542 11543 PR target/94154 11544 * config/aarch64/aarch64.opt (-param=aarch64-float-recp-precision=) 11545 (-param=aarch64-double-recp-precision=): New options. 11546 * doc/invoke.texi: Document them. 11547 * config/aarch64/aarch64.c (aarch64_emit_approx_div): Use them 11548 instead of hard-coding the choice of 1 for float and 2 for double. 11549 115502020-03-13 Eric Botcazou <ebotcazou@adacore.com> 11551 11552 PR rtl-optimization/94119 11553 * resource.h (clear_hashed_info_until_next_barrier): Declare. 11554 * resource.c (clear_hashed_info_until_next_barrier): New function. 11555 * reorg.c (add_to_delay_list): Fix formatting. 11556 (relax_delay_slots): Call clear_hashed_info_until_next_barrier on 11557 the next instruction after removing a BARRIER. 11558 115592020-03-13 Eric Botcazou <ebotcazou@adacore.com> 11560 11561 PR middle-end/92071 11562 * expmed.c (store_integral_bit_field): For fields larger than a word, 11563 call extract_bit_field on the value if the mode is BLKmode. Remove 11564 specific path for big-endian targets and tidy things up a little bit. 11565 115662020-03-12 Richard Sandiford <richard.sandiford@arm.com> 11567 11568 PR rtl-optimization/90275 11569 * cse.c (cse_insn): Delete no-op register moves too. 11570 115712020-03-12 Darius Galis <darius.galis@cyberthorstudios.com> 11572 11573 * config/rx/rx.md (CTRLREG_CPEN): Remove. 11574 * config/rx/rx.c (rx_print_operand): Remove CTRLREG_CPEN support. 11575 115762020-03-12 Richard Biener <rguenther@suse.de> 11577 11578 PR tree-optimization/94103 11579 * tree-ssa-sccvn.c (visit_reference_op_load): Avoid type 11580 punning when the mode precision is not sufficient. 11581 115822020-03-12 H.J. Lu <hongjiu.lu@intel.com> 11583 11584 PR target/89229 11585 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_DI, 11586 MODE_V1DF and MODE_V2SF. 11587 * config/i386/mmx.md (MMXMODE:*mov<mode>_internal): Call 11588 ix86_output_ssemov for TYPE_SSEMOV. Remove ext_sse_reg_operand 11589 check. 11590 115912020-03-12 Jakub Jelinek <jakub@redhat.com> 11592 11593 * doc/tm.texi.in (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Change 11594 ASM_OUTPUT_ALIGNED_DECL in description to ASM_OUTPUT_ALIGNED_LOCAL 11595 and ASM_OUTPUT_DECL to ASM_OUTPUT_LOCAL. 11596 * doc/tm.texi: Regenerated. 11597 11598 PR tree-optimization/94130 11599 * tree-ssa-dse.c: Include gimplify.h. 11600 (increment_start_addr): If stmt has lhs, drop the lhs from call and 11601 set it after the call to the original value of the first argument. 11602 Formatting fixes. 11603 (decrement_count): Formatting fix. 11604 116052020-03-11 Delia Burduv <delia.burduv@arm.com> 11606 11607 * config/arm/arm-builtins.c 11608 (arm_init_simd_builtin_scalar_types): New. 11609 * config/arm/arm_neon.h (vld2_bf16): Used new builtin type. 11610 (vld2q_bf16): Used new builtin type. 11611 (vld3_bf16): Used new builtin type. 11612 (vld3q_bf16): Used new builtin type. 11613 (vld4_bf16): Used new builtin type. 11614 (vld4q_bf16): Used new builtin type. 11615 (vld2_dup_bf16): Used new builtin type. 11616 (vld2q_dup_bf16): Used new builtin type. 11617 (vld3_dup_bf16): Used new builtin type. 11618 (vld3q_dup_bf16): Used new builtin type. 11619 (vld4_dup_bf16): Used new builtin type. 11620 (vld4q_dup_bf16): Used new builtin type. 11621 116222020-03-11 Jakub Jelinek <jakub@redhat.com> 11623 11624 PR target/94134 11625 * config/pdp11/pdp11.c (pdp11_asm_output_var): Call switch_to_section 11626 at the start to switch to data section. Don't print extra newline if 11627 .globl directive has not been emitted. 11628 116292020-03-11 Richard Biener <rguenther@suse.de> 11630 11631 * match.pd ((T *)(ptr - ptr-cst) -> &MEM[ptr + -ptr-cst]): 11632 New pattern. 11633 116342020-03-11 Eric Botcazou <ebotcazou@adacore.com> 11635 11636 PR middle-end/93961 11637 * tree.c (variably_modified_type_p) <RECORD_TYPE>: Recurse into fields 11638 whose type is a qualified union. 11639 116402020-03-11 Jakub Jelinek <jakub@redhat.com> 11641 11642 PR target/94121 11643 * config/aarch64/aarch64.c (aarch64_add_offset_1): Use absu_hwi 11644 instead of abs_hwi, change moffset type to unsigned HOST_WIDE_INT. 11645 11646 PR bootstrap/93962 11647 * value-prof.c (dump_histogram_value): Use abs_hwi instead of 11648 std::abs. 11649 (get_nth_most_common_value): Use abs_hwi instead of abs. 11650 11651 PR middle-end/94111 11652 * dfp.c (decimal_to_binary): Only use decimal128ToString if from->cl 11653 is rvc_normal, otherwise use real_to_decimal to print the number to 11654 string. 11655 11656 PR tree-optimization/94114 11657 * tree-loop-distribution.c (generate_memset_builtin): Call 11658 rewrite_to_non_trapping_overflow even on mem. 11659 (generate_memcpy_builtin): Call rewrite_to_non_trapping_overflow even 11660 on dest and src. 11661 116622020-03-10 Jeff Law <law@redhat.com> 11663 11664 * config/bfin/bfin.md (movsi_insv): Add length attribute. 11665 116662020-03-10 Jiufu Guo <guojiufu@linux.ibm.com> 11667 11668 PR target/93709 11669 * gcc/config/rs6000/rs6000.c (rs6000_emit_p9_fp_minmax): Check 11670 NAN and SIGNED_ZEROR for smax/smin. 11671 116722020-03-10 Will Schmidt <will_schmidt@vnet.ibm.com> 11673 11674 PR target/90763 11675 * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Add 11676 clause to handle P9V_BUILTIN_VEC_LXVL with const arguments. 11677 116782020-03-10 Roman Zhuykov <zhroma@ispras.ru> 11679 11680 * loop-iv.c (find_simple_exit): Make it static. 11681 * cfgloop.h: Remove the corresponding prototype. 11682 116832020-03-10 Roman Zhuykov <zhroma@ispras.ru> 11684 11685 * ddg.c (create_ddg): Fix intendation. 11686 (set_recurrence_length): Likewise. 11687 (create_ddg_all_sccs): Likewise. 11688 116892020-03-10 Jakub Jelinek <jakub@redhat.com> 11690 11691 PR target/94088 11692 * config/i386/i386.md (*testqi_ext_3): Call ix86_match_ccmode with 11693 CCZmode instead of CCNOmode if operands[2] has DImode and pos + len 11694 is 32. 11695 116962020-03-09 Jason Merrill <jason@redhat.com> 11697 11698 * gdbinit.in (pgs): Fix typo in documentation. 11699 117002020-03-09 Vladimir Makarov <vmakarov@redhat.com> 11701 11702 Revert: 11703 11704 2020-02-28 Vladimir Makarov <vmakarov@redhat.com> 11705 11706 PR rtl-optimization/93564 11707 * ira-color.c (assign_hard_reg): Prefer smaller hard regno when we 11708 do not honor reg alloc order. 11709 117102020-03-09 Andrew Pinski <apinski@marvell.com> 11711 11712 PR inline-asm/94095 11713 * doc/extend.texi (x86 Operand Modifiers): Fix column 11714 for 'A' modifier. 11715 117162020-03-09 Martin Liska <mliska@suse.cz> 11717 11718 PR target/93800 11719 * config/rs6000/rs6000.c (rs6000_option_override_internal): 11720 Remove set of str_align_loops and str_align_jumps as these 11721 should be set in previous 2 conditions in the function. 11722 117232020-03-09 Jakub Jelinek <jakub@redhat.com> 11724 11725 PR rtl-optimization/94045 11726 * params.opt (-param=max-find-base-term-values=): New option. 11727 * alias.c (find_base_term): Add cut-off for number of visited VALUEs 11728 in a single toplevel find_base_term call. 11729 117302020-03-06 Wilco Dijkstra <wdijkstr@arm.com> 11731 11732 PR target/91598 11733 * config/aarch64/aarch64-builtins.c (TYPES_TERNOPU_LANE): Add define. 11734 * config/aarch64/aarch64-simd.md 11735 (aarch64_vec_<su>mult_lane<Qlane>): Add new insn for widening lane mul. 11736 (aarch64_vec_<su>mlal_lane<Qlane>): Likewise. 11737 * config/aarch64/aarch64-simd-builtins.def: Add intrinsics. 11738 * config/aarch64/arm_neon.h: 11739 (vmlal_lane_s16): Expand using intrinsics rather than inline asm. 11740 (vmlal_lane_u16): Likewise. 11741 (vmlal_lane_s32): Likewise. 11742 (vmlal_lane_u32): Likewise. 11743 (vmlal_laneq_s16): Likewise. 11744 (vmlal_laneq_u16): Likewise. 11745 (vmlal_laneq_s32): Likewise. 11746 (vmlal_laneq_u32): Likewise. 11747 (vmull_lane_s16): Likewise. 11748 (vmull_lane_u16): Likewise. 11749 (vmull_lane_s32): Likewise. 11750 (vmull_lane_u32): Likewise. 11751 (vmull_laneq_s16): Likewise. 11752 (vmull_laneq_u16): Likewise. 11753 (vmull_laneq_s32): Likewise. 11754 (vmull_laneq_u32): Likewise. 11755 * config/aarch64/iterators.md (Vcondtype): New iterator for lane mul. 11756 (Qlane): Likewise. 11757 117582020-03-06 Wilco Dijkstra <wdijkstr@arm.com> 11759 11760 * aarch64/aarch64-simd.md (aarch64_mla_elt<mode>): Correct lane syntax. 11761 (aarch64_mla_elt_<vswap_width_name><mode>): Likewise. 11762 (aarch64_mls_elt<mode>): Likewise. 11763 (aarch64_mls_elt_<vswap_width_name><mode>): Likewise. 11764 (aarch64_fma4_elt<mode>): Likewise. 11765 (aarch64_fma4_elt_<vswap_width_name><mode>): Likewise. 11766 (aarch64_fma4_elt_to_64v2df): Likewise. 11767 (aarch64_fnma4_elt<mode>): Likewise. 11768 (aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise. 11769 (aarch64_fnma4_elt_to_64v2df): Likewise. 11770 117712020-03-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 11772 11773 * config/aarch64/aarch64-sve2.md (@aarch64_sve_<sve_int_op><mode>: 11774 Specify movprfx attribute. 11775 (@aarch64_sve_<sve_int_op>_lane_<mode>): Likewise. 11776 117772020-03-06 David Edelsohn <dje.gcc@gmail.com> 11778 11779 PR target/94065 11780 * config/rs6000/aix61.h (TARGET_NO_SUM_IN_TOC): Set to 1 for 11781 cmodel=large. 11782 (TARGET_NO_FP_IN_TOC): Same. 11783 * config/rs6000/aix71.h: Same. 11784 * config/rs6000/aix72.h: Same. 11785 117862020-03-06 Andrew Pinski <apinski@marvell.com> 11787 Jeff Law <law@redhat.com> 11788 11789 PR rtl-optimization/93996 11790 * haifa-sched.c (remove_notes): Be more careful when adding 11791 REG_SAVE_NOTE. 11792 117932020-03-06 Delia Burduv <delia.burduv@arm.com> 11794 11795 * config/arm/arm_neon.h (vld2_bf16): New. 11796 (vld2q_bf16): New. 11797 (vld3_bf16): New. 11798 (vld3q_bf16): New. 11799 (vld4_bf16): New. 11800 (vld4q_bf16): New. 11801 (vld2_dup_bf16): New. 11802 (vld2q_dup_bf16): New. 11803 (vld3_dup_bf16): New. 11804 (vld3q_dup_bf16): New. 11805 (vld4_dup_bf16): New. 11806 (vld4q_dup_bf16): New. 11807 * config/arm/arm_neon_builtins.def 11808 (vld2): Changed to VAR13 and added v4bf, v8bf 11809 (vld2_dup): Changed to VAR8 and added v4bf, v8bf 11810 (vld3): Changed to VAR13 and added v4bf, v8bf 11811 (vld3_dup): Changed to VAR8 and added v4bf, v8bf 11812 (vld4): Changed to VAR13 and added v4bf, v8bf 11813 (vld4_dup): Changed to VAR8 and added v4bf, v8bf 11814 * config/arm/iterators.md (VDXBF2): New iterator. 11815 *config/arm/neon.md (neon_vld2): Use new iterators. 11816 (neon_vld2_dup<mode): Use new iterators. 11817 (neon_vld3<mode>): Likewise. 11818 (neon_vld3qa<mode>): Likewise. 11819 (neon_vld3qb<mode>): Likewise. 11820 (neon_vld3_dup<mode>): Likewise. 11821 (neon_vld4<mode>): Likewise. 11822 (neon_vld4qa<mode>): Likewise. 11823 (neon_vld4qb<mode>): Likewise. 11824 (neon_vld4_dup<mode>): Likewise. 11825 (neon_vld2_dupv8bf): New. 11826 (neon_vld3_dupv8bf): Likewise. 11827 (neon_vld4_dupv8bf): Likewise. 11828 118292020-03-06 Delia Burduv <delia.burduv@arm.com> 11830 11831 * config/arm/arm_neon.h (bfloat16x4x2_t): New typedef. 11832 (bfloat16x8x2_t): New typedef. 11833 (bfloat16x4x3_t): New typedef. 11834 (bfloat16x8x3_t): New typedef. 11835 (bfloat16x4x4_t): New typedef. 11836 (bfloat16x8x4_t): New typedef. 11837 (vst2_bf16): New. 11838 (vst2q_bf16): New. 11839 (vst3_bf16): New. 11840 (vst3q_bf16): New. 11841 (vst4_bf16): New. 11842 (vst4q_bf16): New. 11843 * config/arm/arm-builtins.c (v2bf_UP): Define. 11844 (VAR13): New. 11845 (arm_init_simd_builtin_types): Init Bfloat16x2_t eltype. 11846 * config/arm/arm-modes.def (V2BF): New mode. 11847 * config/arm/arm-simd-builtin-types.def 11848 (Bfloat16x2_t): New entry. 11849 * config/arm/arm_neon_builtins.def 11850 (vst2): Changed to VAR13 and added v4bf, v8bf 11851 (vst3): Changed to VAR13 and added v4bf, v8bf 11852 (vst4): Changed to VAR13 and added v4bf, v8bf 11853 * config/arm/iterators.md (VDXBF): New iterator. 11854 (VQ2BF): New iterator. 11855 *config/arm/neon.md (neon_vst2<mode>): Used new iterators. 11856 (neon_vst2<mode>): Used new iterators. 11857 (neon_vst3<mode>): Used new iterators. 11858 (neon_vst3<mode>): Used new iterators. 11859 (neon_vst3qa<mode>): Used new iterators. 11860 (neon_vst3qb<mode>): Used new iterators. 11861 (neon_vst4<mode>): Used new iterators. 11862 (neon_vst4<mode>): Used new iterators. 11863 (neon_vst4qa<mode>): Used new iterators. 11864 (neon_vst4qb<mode>): Used new iterators. 11865 118662020-03-06 Delia Burduv <delia.burduv@arm.com> 11867 11868 * config/aarch64/aarch64-simd-builtins.def 11869 (bfcvtn): New built-in function. 11870 (bfcvtn_q): New built-in function. 11871 (bfcvtn2): New built-in function. 11872 (bfcvt): New built-in function. 11873 * config/aarch64/aarch64-simd.md 11874 (aarch64_bfcvtn<q><mode>): New pattern. 11875 (aarch64_bfcvtn2v8bf): New pattern. 11876 (aarch64_bfcvtbf): New pattern. 11877 * config/aarch64/arm_bf16.h (float32_t): New typedef. 11878 (vcvth_bf16_f32): New intrinsic. 11879 * config/aarch64/arm_bf16.h (vcvt_bf16_f32): New intrinsic. 11880 (vcvtq_low_bf16_f32): New intrinsic. 11881 (vcvtq_high_bf16_f32): New intrinsic. 11882 * config/aarch64/iterators.md (V4SF_TO_BF): New mode iterator. 11883 (UNSPEC_BFCVTN): New UNSPEC. 11884 (UNSPEC_BFCVTN2): New UNSPEC. 11885 (UNSPEC_BFCVT): New UNSPEC. 11886 * config/arm/types.md (bf_cvt): New type. 11887 118882020-03-06 Andreas Krebbel <krebbel@linux.ibm.com> 11889 11890 * config/s390/s390.md ("tabort"): Get rid of two consecutive 11891 blanks in format string. 11892 118932020-03-05 H.J. Lu <hongjiu.lu@intel.com> 11894 11895 PR target/89229 11896 PR target/89346 11897 * config/i386/i386-protos.h (ix86_output_ssemov): New prototype. 11898 * config/i386/i386.c (ix86_get_ssemov): New function. 11899 (ix86_output_ssemov): Likewise. 11900 * config/i386/sse.md (VMOVE:mov<mode>_internal): Call 11901 ix86_output_ssemov for TYPE_SSEMOV. Remove TARGET_AVX512VL 11902 check. 11903 (*movxi_internal_avx512f): Call ix86_output_ssemov for TYPE_SSEMOV. 11904 (*movoi_internal_avx): Call ix86_output_ssemov for TYPE_SSEMOV. 11905 Remove ext_sse_reg_operand and TARGET_AVX512VL check. 11906 (*movti_internal): Likewise. 11907 (*movtf_internal): Call ix86_output_ssemov for TYPE_SSEMOV. 11908 119092020-03-05 Jeff Law <law@redhat.com> 11910 11911 PR tree-optimization/91890 11912 * gimple-ssa-warn-restrict.c (maybe_diag_overlap): Remove LOC argument. 11913 Use gimple_or_expr_nonartificial_location. 11914 (check_bounds_overlap): Drop LOC argument to maybe_diag_access_bounds. 11915 Use gimple_or_expr_nonartificial_location. 11916 * gimple.c (gimple_or_expr_nonartificial_location): New function. 11917 * gimple.h (gimple_or_expr_nonartificial_location): Declare it. 11918 * tree-ssa-strlen.c (maybe_warn_overflow): Use 11919 gimple_or_expr_nonartificial_location. 11920 (maybe_diag_stxncpy_trunc, handle_builtin_stxncpy_strncat): Likewise. 11921 (maybe_warn_pointless_strcmp): Likewise. 11922 119232020-03-05 Jakub Jelinek <jakub@redhat.com> 11924 11925 PR target/94046 11926 * config/i386/avx2intrin.h (_mm_mask_i32gather_ps): Fix first cast of 11927 SRC and MASK arguments to __m128 from __m128d. 11928 (_mm256_mask_i32gather_ps): Fix first cast of MASK argument to __m256 11929 from __m256d. 11930 (_mm_mask_i64gather_ps): Fix first cast of MASK argument to __m128 11931 from __m128d. 11932 * config/i386/xopintrin.h (_mm_permute2_pd): Fix first cast of C 11933 argument to __m128i from __m128d. 11934 (_mm256_permute2_pd): Fix first cast of C argument to __m256i from 11935 __m256d. 11936 (_mm_permute2_ps): Fix first cast of C argument to __m128i from __m128. 11937 (_mm256_permute2_ps): Fix first cast of C argument to __m256i from 11938 __m256. 11939 119402020-03-05 Delia Burduv <delia.burduv@arm.com> 11941 11942 * config/arm/arm_neon.h (vbfmmlaq_f32): New. 11943 (vbfmlalbq_f32): New. 11944 (vbfmlaltq_f32): New. 11945 (vbfmlalbq_lane_f32): New. 11946 (vbfmlaltq_lane_f32): New. 11947 (vbfmlalbq_laneq_f32): New. 11948 (vbfmlaltq_laneq_f32): New. 11949 * config/arm/arm_neon_builtins.def (vmmla): New. 11950 (vfmab): New. 11951 (vfmat): New. 11952 (vfmab_lane): New. 11953 (vfmat_lane): New. 11954 (vfmab_laneq): New. 11955 (vfmat_laneq): New. 11956 * config/arm/iterators.md (BF_MA): New int iterator. 11957 (bt): New int attribute. 11958 (VQXBF): Copy of VQX with V8BF. 11959 * config/arm/neon.md (neon_vmmlav8bf): New insn. 11960 (neon_vfma<bt>v8bf): New insn. 11961 (neon_vfma<bt>_lanev8bf): New insn. 11962 (neon_vfma<bt>_laneqv8bf): New expand. 11963 (neon_vget_high<mode>): Changed iterator to VQXBF. 11964 * config/arm/unspecs.md (UNSPEC_BFMMLA): New UNSPEC. 11965 (UNSPEC_BFMAB): New UNSPEC. 11966 (UNSPEC_BFMAT): New UNSPEC. 11967 119682020-03-05 Jakub Jelinek <jakub@redhat.com> 11969 11970 PR middle-end/93399 11971 * tree-pretty-print.h (pretty_print_string): Declare. 11972 * tree-pretty-print.c (pretty_print_string): Remove forward 11973 declaration, no longer static. Change nbytes parameter type 11974 from unsigned to size_t. 11975 * print-rtl.c (print_value) <case CONST_STRING>: Use 11976 pretty_print_string and for shrink way too long strings. 11977 119782020-03-05 Richard Biener <rguenther@suse.de> 11979 Jakub Jelinek <jakub@redhat.com> 11980 11981 PR tree-optimization/93582 11982 * tree-ssa-sccvn.c (vn_reference_lookup_3): Treat POINTER_PLUS_EXPR 11983 last operand as signed when looking for memset offset. Formatting 11984 fix. 11985 119862020-03-04 Andrew Pinski <apinski@marvell.com> 11987 11988 PR bootstrap/93962 11989 * value-prof.c (dump_histogram_value): Use std::abs. 11990 119912020-03-04 Martin Sebor <msebor@redhat.com> 11992 11993 PR tree-optimization/93986 11994 * tree-ssa-strlen.c (maybe_warn_overflow): Convert all wide_int 11995 operands to the same precision widest_int to avoid ICEs. 11996 119972020-03-04 Bill Schmidt <wschmidt@linux.ibm.com> 11998 11999 PR target/87560 12000 * rs6000-cpus.def (OTHER_ALTIVEC_MASKS): New #define. 12001 * rs6000.c (rs6000_disable_incompatible_switches): Add table entry 12002 for OPTION_MASK_ALTIVEC. 12003 120042020-03-04 Andreas Krebbel <krebbel@linux.ibm.com> 12005 12006 * config.gcc: Include the glibc-stdint.h header for zTPF. 12007 120082020-03-04 Andreas Krebbel <krebbel@linux.ibm.com> 12009 12010 * config/s390/s390.c (s390_secondary_memory_needed): Disallow 12011 direct FPR-GPR copies. 12012 (s390_register_info_gprtofpr): Disallow GPR content to be saved in 12013 FPRs. 12014 120152020-03-04 Andreas Krebbel <krebbel@linux.ibm.com> 12016 12017 * config/s390/s390.c (s390_emit_prologue): Specify the 2 new 12018 operands to the prologue_tpf expander. 12019 (s390_emit_epilogue): Likewise. 12020 (s390_option_override_internal): Do error checking and setup for 12021 the new options. 12022 * config/s390/tpf.h (TPF_TRACE_PROLOGUE_CHECK) 12023 (TPF_TRACE_EPILOGUE_CHECK, TPF_TRACE_PROLOGUE_TARGET) 12024 (TPF_TRACE_EPILOGUE_TARGET, TPF_TRACE_PROLOGUE_SKIP_TARGET) 12025 (TPF_TRACE_EPILOGUE_SKIP_TARGET): New macro definitions. 12026 * config/s390/tpf.md ("prologue_tpf", "epilogue_tpf"): Add two new 12027 operands for the check flag and the branch target. 12028 * config/s390/tpf.opt ("mtpf-trace-hook-prologue-check") 12029 ("mtpf-trace-hook-prologue-target") 12030 ("mtpf-trace-hook-epilogue-check") 12031 ("mtpf-trace-hook-epilogue-target", "mtpf-trace-skip"): New 12032 options. 12033 * doc/invoke.texi: Document -mtpf-trace-skip option. The other 12034 options are for debugging purposes and will not be documented 12035 here. 12036 120372020-03-04 Jakub Jelinek <jakub@redhat.com> 12038 12039 PR debug/93888 12040 * tree-inline.c (copy_decl_to_var): Copy DECL_BY_REFERENCE flag. 12041 12042 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Add offseti 12043 argument. Change pd argument so that it can be modified. Turn 12044 constant non-CONSTRUCTOR store into non-constant if it is too large. 12045 Adjust offset and size of CONSTRUCTOR or non-constant store to avoid 12046 overflows. 12047 (vn_walk_cb_data::vn_walk_cb_data, vn_reference_lookup_3): Adjust 12048 callers. 12049 120502020-02-04 Richard Biener <rguenther@suse.de> 12051 12052 PR tree-optimization/93964 12053 * graphite-isl-ast-to-gimple.c 12054 (gcc_expression_from_isl_ast_expr_id): Add intermediate 12055 conversion for pointer to integer converts. 12056 * graphite-scop-detection.c (assign_parameter_index_in_region): 12057 Relax assert. 12058 120592020-03-04 Martin Liska <mliska@suse.cz> 12060 12061 PR c/93886 12062 PR c/93887 12063 * doc/invoke.texi: Clarify --help=language and --help=common 12064 interaction. 12065 120662020-03-04 Jakub Jelinek <jakub@redhat.com> 12067 12068 PR tree-optimization/94001 12069 * tree-tailcall.c (process_assignment): Before comparing op1 to 12070 *ass_var, verify *ass_var is non-NULL. 12071 120722020-03-04 Kito Cheng <kito.cheng@sifive.com> 12073 12074 PR target/93995 12075 * config/riscv/riscv.c (riscv_emit_float_compare): Using NE to compare 12076 the result of IOR. 12077 120782020-03-03 Dennis Zhang <dennis.zhang@arm.com> 12079 12080 * config/arm/arm_bf16.h (vcvtah_f32_bf16, vcvth_bf16_f32): New. 12081 * config/arm/arm_neon.h (vcvt_f32_bf16, vcvtq_low_f32_bf16): New. 12082 (vcvtq_high_f32_bf16, vcvt_bf16_f32): New. 12083 (vcvtq_low_bf16_f32, vcvtq_high_bf16_f32): New. 12084 * config/arm/arm_neon_builtins.def (vbfcvt, vbfcvt_high): New entries. 12085 (vbfcvtv4sf, vbfcvtv4sf_high): Likewise. 12086 * config/arm/iterators.md (VBFCVT, VBFCVTM): New mode iterators. 12087 (V_bf_low, V_bf_cvt_m): New mode attributes. 12088 * config/arm/neon.md (neon_vbfcvtv4sf<VBFCVT:mode>): New. 12089 (neon_vbfcvtv4sf_highv8bf, neon_vbfcvtsf): New. 12090 (neon_vbfcvt<VBFCVT:mode>, neon_vbfcvt_highv8bf): New. 12091 (neon_vbfcvtbf_cvtmode<mode>, neon_vbfcvtbf): New 12092 * config/arm/unspecs.md (UNSPEC_BFCVT, UNSPEC_BFCVT_HIG): New. 12093 120942020-03-03 Jakub Jelinek <jakub@redhat.com> 12095 12096 PR tree-optimization/93582 12097 * tree-ssa-sccvn.h (vn_reference_lookup): Add mask argument. 12098 * tree-ssa-sccvn.c (struct vn_walk_cb_data): Add mask and masked_result 12099 members, initialize them in the constructor and if mask is non-NULL, 12100 artificially push_partial_def {} for the portions of the mask that 12101 contain zeros. 12102 (vn_walk_cb_data::finish): If mask is non-NULL, set masked_result to 12103 val and return (void *)-1. Formatting fix. 12104 (vn_reference_lookup_pieces): Adjust vn_walk_cb_data initialization. 12105 Formatting fix. 12106 (vn_reference_lookup): Add mask argument. If non-NULL, don't call 12107 fully_constant_vn_reference_p nor vn_reference_lookup_1 and return 12108 data.mask_result. 12109 (visit_nary_op): Handle BIT_AND_EXPR of a memory load and INTEGER_CST 12110 mask. 12111 (visit_stmt): Formatting fix. 12112 121132020-03-03 Richard Biener <rguenther@suse.de> 12114 12115 PR tree-optimization/93946 12116 * alias.h (refs_same_for_tbaa_p): Declare. 12117 * alias.c (refs_same_for_tbaa_p): New function. 12118 * tree-ssa-alias.c (ao_ref_alias_set): For a NULL ref return 12119 zero. 12120 * tree-ssa-scopedtables.h 12121 (avail_exprs_stack::lookup_avail_expr): Add output argument 12122 giving access to the hashtable entry. 12123 * tree-ssa-scopedtables.c (avail_exprs_stack::lookup_avail_expr): 12124 Likewise. 12125 * tree-ssa-dom.c: Include alias.h. 12126 (dom_opt_dom_walker::optimize_stmt): Validate TBAA state before 12127 removing redundant store. 12128 * tree-ssa-sccvn.h (vn_reference_s::base_set): New member. 12129 (ao_ref_init_from_vn_reference): Adjust prototype. 12130 (vn_reference_lookup_pieces): Likewise. 12131 (vn_reference_insert_pieces): Likewise. 12132 * tree-ssa-sccvn.c: Track base alias set in addition to alias 12133 set everywhere. 12134 (eliminate_dom_walker::eliminate_stmt): Also check base alias 12135 set when removing redundant stores. 12136 (visit_reference_op_store): Likewise. 12137 * dse.c (record_store): Adjust valdity check for redundant 12138 store removal. 12139 121402020-03-03 Jakub Jelinek <jakub@redhat.com> 12141 12142 PR target/26877 12143 * config/s390/s390.h (OPTION_DEFAULT_SPECS): Reorder. 12144 12145 PR rtl-optimization/94002 12146 * explow.c (plus_constant): Punt if cst has VOIDmode and 12147 get_pool_mode is different from mode. 12148 121492020-03-03 Claudiu Zissulescu <claziss@synopsys.com> 12150 12151 * config/arc/arc.c (leigitimate_small_data_address_p): Check if an 12152 address has an offset which fits the scalling constraint for a 12153 load/store operation. 12154 (legitimate_scaled_address_p): Update use 12155 leigitimate_small_data_address_p. 12156 (arc_print_operand): Likewise. 12157 (arc_legitimate_address_p): Likewise. 12158 (legitimate_small_data_address_p): Likewise. 12159 121602020-03-03 Claudiu Zissulescu <claziss@synopsys.com> 12161 12162 * config/arc/arc.md (fmasf4_fpu): Use accl_operand predicate. 12163 (fnmasf4_fpu): Likewise. 12164 121652020-03-03 Claudiu Zissulescu <claziss@synopsys.com> 12166 12167 * config/arc/arc.md (adddi3): Early expand the 64bit operation into 12168 32bit ops. 12169 (subdi3): Likewise. 12170 (adddi3_i): Remove pattern. 12171 (subdi3_i): Likewise. 12172 121732020-03-03 Claudiu Zissulescu <claziss@synopsys.com> 12174 12175 * config/arc/arc.md (eh_return): Add length info. 12176 121772020-03-02 David Malcolm <dmalcolm@redhat.com> 12178 12179 * doc/invoke.texi (-fanalyzer-show-duplicate-count): New. 12180 121812020-03-02 David Malcolm <dmalcolm@redhat.com> 12182 12183 * doc/invoke.texi (Static Analyzer Options): Add 12184 -Wanalyzer-stale-setjmp-buffer to the list of options enabled 12185 by -fanalyzer. 12186 121872020-03-02 Uroš Bizjak <ubizjak@gmail.com> 12188 12189 PR target/93997 12190 * config/i386/i386.md (movstrict<mode>): Allow only 12191 registers with VALID_INT_MODE_P modes. 12192 121932020-03-02 Andrew Stubbs <ams@codesourcery.com> 12194 12195 * config/gcn/gcn-valu.md (dpp_move<mode>): New. 12196 (reduc_insn): Use 'U' and 'B' operand codes. 12197 (reduc_<reduc_op>_scal_<mode>): Allow all types. 12198 (reduc_<reduc_op>_scal_v64di): Delete. 12199 (*<reduc_op>_dpp_shr_<mode>): Allow all 1reg types. 12200 (*plus_carry_dpp_shr_v64si): Change to ... 12201 (*plus_carry_dpp_shr_<mode>): ... this and allow all 1reg int types. 12202 (mov_from_lane63_v64di): Change to ... 12203 (mov_from_lane63_<mode>): ... this, and allow all 64-bit modes. 12204 * config/gcn/gcn.c (gcn_expand_dpp_shr_insn): Increase buffer size. 12205 Support UNSPEC_MOV_DPP_SHR output formats. 12206 (gcn_expand_reduc_scalar): Add "use_moves" reductions. 12207 Add "use_extends" reductions. 12208 (print_operand_address): Add 'I' and 'U' codes. 12209 * config/gcn/gcn.md (unspec): Add UNSPEC_MOV_DPP_SHR. 12210 122112020-03-02 Martin Liska <mliska@suse.cz> 12212 12213 * lto-wrapper.c: Fix typo in comment about 12214 C++ standard version. 12215 122162020-03-01 Martin Sebor <msebor@redhat.com> 12217 12218 PR c++/92721 12219 * calls.c (init_attr_rdwr_indices): Correctly handle attribute. 12220 122212020-03-01 Martin Sebor <msebor@redhat.com> 12222 12223 PR middle-end/93829 12224 * tree-ssa-strlen.c (count_nonzero_bytes): Set the size to that 12225 of a pointer in the outermost ADDR_EXPRs. 12226 122272020-02-28 Jeff Law <law@redhat.com> 12228 12229 * config/v850/v850.h (STATIC_CHAIN_REGNUM): Change to r19. 12230 * config/v850/v850.c (v850_asm_trampoline_template): Update 12231 accordingly. 12232 122332020-02-28 Michael Meissner <meissner@linux.ibm.com> 12234 12235 PR target/93937 12236 * config/rs6000/vsx.md (vsx_extract_<mode>_<VS_scalar>mode_var): 12237 Delete insn. 12238 122392020-02-28 Martin Liska <mliska@suse.cz> 12240 12241 PR other/93965 12242 * configure.ac: Improve detection of ld_date by requiring 12243 either two dashes or none. 12244 * configure: Regenerate. 12245 122462020-02-28 Vladimir Makarov <vmakarov@redhat.com> 12247 12248 PR rtl-optimization/93564 12249 * ira-color.c (assign_hard_reg): Prefer smaller hard regno when we 12250 do not honor reg alloc order. 12251 122522020-02-27 Joel Hutton <Joel.Hutton@arm.com> 12253 12254 PR target/87612 12255 * config/aarch64/aarch64.c (aarch64_override_options): Fix 12256 misleading warning string. 12257 122582020-02-27 Martin Sebor <msebor@redhat.com> 12259 12260 * doc/invoke.texi (-Wbuiltin-declaration-mismatch): Fix a typo. 12261 122622020-02-27 Michael Meissner <meissner@linux.ibm.com> 12263 12264 PR target/93932 12265 * config/rs6000/vsx.md (vsx_extract_<mode>_var, VSX_D iterator): 12266 Split the insn into two parts. This insn only does variable 12267 extract from a register. 12268 (vsx_extract_<mode>_var_load, VSX_D iterator): New insn, do 12269 variable extract from memory. 12270 (vsx_extract_v4sf_var): Split the insn into two parts. This insn 12271 only does variable extract from a register. 12272 (vsx_extract_v4sf_var_load): New insn, do variable extract from 12273 memory. 12274 (vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): Split the insn 12275 into two parts. This insn only does variable extract from a 12276 register. 12277 (vsx_extract_<mode>_var_load, VSX_EXTRACT_I iterator): New insn, 12278 do variable extract from memory. 12279 122802020-02-27 Martin Jambor <mjambor@suse.cz> 12281 Feng Xue <fxue@os.amperecomputing.com> 12282 12283 PR ipa/93707 12284 * ipa-cp.c (same_node_or_its_all_contexts_clone_p): Replaced with 12285 new function calls_same_node_or_its_all_contexts_clone_p. 12286 (cgraph_edge_brings_value_p): Use it. 12287 (cgraph_edge_brings_value_p): Likewise. 12288 (self_recursive_pass_through_p): Return false if caller is a clone. 12289 (self_recursive_agg_pass_through_p): Likewise. 12290 122912020-02-27 Jan Hubicka <hubicka@ucw.cz> 12292 12293 PR middle-end/92152 12294 * alias.c (ends_tbaa_access_path_p): Break out from ... 12295 (component_uses_parent_alias_set_from): ... here. 12296 * alias.h (ends_tbaa_access_path_p): Declare. 12297 * tree-ssa-alias.c (access_path_may_continue_p): Break out from ...; 12298 handle trailing arrays past end of tbaa access path. 12299 (aliasing_component_refs_p): ... here; likewise. 12300 (nonoverlapping_refs_since_match_p): Track TBAA segment of the access 12301 path; disambiguate also past end of it. 12302 (nonoverlapping_component_refs_p): Use only TBAA segment of the access 12303 path. 12304 123052020-02-27 Mihail Ionescu <mihail.ionescu@arm.com> 12306 12307 * (__ARM_NUM_LANES, __arm_lane, __arm_lane_q): Move to the 12308 beginning of the file. 12309 (vcreate_bf16, vcombine_bf16): New. 12310 (vdup_n_bf16, vdupq_n_bf16): New. 12311 (vdup_lane_bf16, vdup_laneq_bf16): New. 12312 (vdupq_lane_bf16, vdupq_laneq_bf16): New. 12313 (vduph_lane_bf16, vduph_laneq_bf16): New. 12314 (vset_lane_bf16, vsetq_lane_bf16): New. 12315 (vget_lane_bf16, vgetq_lane_bf16): New. 12316 (vget_high_bf16, vget_low_bf16): New. 12317 (vreinterpret_bf16_u8, vreinterpretq_bf16_u8): New. 12318 (vreinterpret_bf16_u16, vreinterpretq_bf16_u16): New. 12319 (vreinterpret_bf16_u32, vreinterpretq_bf16_u32): New. 12320 (vreinterpret_bf16_u64, vreinterpretq_bf16_u64): New. 12321 (vreinterpret_bf16_s8, vreinterpretq_bf16_s8): New. 12322 (vreinterpret_bf16_s16, vreinterpretq_bf16_s16): New. 12323 (vreinterpret_bf16_s32, vreinterpretq_bf16_s32): New. 12324 (vreinterpret_bf16_s64, vreinterpretq_bf16_s64): New. 12325 (vreinterpret_bf16_p8, vreinterpretq_bf16_p8): New. 12326 (vreinterpret_bf16_p16, vreinterpretq_bf16_p16): New. 12327 (vreinterpret_bf16_p64, vreinterpretq_bf16_p64): New. 12328 (vreinterpret_bf16_f32, vreinterpretq_bf16_f32): New. 12329 (vreinterpret_bf16_f64, vreinterpretq_bf16_f64): New. 12330 (vreinterpretq_bf16_p128): New. 12331 (vreinterpret_s8_bf16, vreinterpretq_s8_bf16): New. 12332 (vreinterpret_s16_bf16, vreinterpretq_s16_bf16): New. 12333 (vreinterpret_s32_bf16, vreinterpretq_s32_bf16): New. 12334 (vreinterpret_s64_bf16, vreinterpretq_s64_bf16): New. 12335 (vreinterpret_u8_bf16, vreinterpretq_u8_bf16): New. 12336 (vreinterpret_u16_bf16, vreinterpretq_u16_bf16): New. 12337 (vreinterpret_u32_bf16, vreinterpretq_u32_bf16): New. 12338 (vreinterpret_u64_bf16, vreinterpretq_u64_bf16): New. 12339 (vreinterpret_p8_bf16, vreinterpretq_p8_bf16): New. 12340 (vreinterpret_p16_bf16, vreinterpretq_p16_bf16): New. 12341 (vreinterpret_p64_bf16, vreinterpretq_p64_bf16): New. 12342 (vreinterpret_f32_bf16, vreinterpretq_f32_bf16): New. 12343 (vreinterpretq_p128_bf16): New. 12344 * config/arm/arm_neon_builtins.def (VDX): Add V4BF. 12345 (V_elem): Likewise. 12346 (V_elem_l): Likewise. 12347 (VD_LANE): Likewise. 12348 (VQX) Add V8BF. 12349 (V_DOUBLE): Likewise. 12350 (VDQX): Add V4BF and V8BF. 12351 (V_two_elem, V_three_elem, V_four_elem): Likewise. 12352 (V_reg): Likewise. 12353 (V_HALF): Likewise. 12354 (V_double_vector_mode): Likewise. 12355 (V_cmp_result): Likewise. 12356 (V_uf_sclr): Likewise. 12357 (V_sz_elem): Likewise. 12358 (Is_d_reg): Likewise. 12359 (V_mode_nunits): Likewise. 12360 * config/arm/neon.md (neon_vdup_lane): Enable for BFloat16. 12361 123622020-02-27 Andrew Stubbs <ams@codesourcery.com> 12363 12364 * config/gcn/gcn-valu.md (VEC_SUBDWORD_MODE): New mode iterator. 12365 (<expander><mode>2<exec>): Change modes to VEC_ALL1REG_INT_MODE. 12366 (<expander><mode>3<exec>): Likewise. 12367 (<expander><mode>3): New. 12368 (v<expander><mode>3): New. 12369 (<expander><mode>3): New. 12370 (<expander><mode>3<exec>): Rename to ... 12371 (<expander>v64si3<exec>): ... this, and change modes to V64SI. 12372 * config/gcn/gcn.md (mnemonic): Use '%B' for not. 12373 123742020-02-27 Alexandre Oliva <oliva@adacore.com> 12375 12376 * config/vx-common.h (NO_DOLLAR_IN_LABEL, NO_DOT_IN_LABEL): Leave 12377 them alone on vx7. 12378 123792020-02-27 Richard Biener <rguenther@suse.de> 12380 12381 PR tree-optimization/93508 12382 * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle _CHK like 12383 non-_CHK variants. Valueize their length arguments. 12384 123852020-02-27 Richard Biener <rguenther@suse.de> 12386 12387 PR tree-optimization/93953 12388 * tree-vect-slp.c (slp_copy_subtree): Avoid keeping a reference 12389 to the hash-map entry. 12390 123912020-02-27 Andrew Stubbs <ams@codesourcery.com> 12392 12393 * config/gcn/gcn.md (mov<mode>): Add transformations for BI subregs. 12394 123952020-02-27 Mark Williams <mwilliams@fb.com> 12396 12397 * dwarf2out.c (file_name_acquire): Call remap_debug_filename. 12398 * lto-opts.c (lto_write_options): Drop -fdebug-prefix-map, 12399 -ffile-prefix-map and -fmacro-prefix-map. 12400 * lto-streamer-out.c: Include file-prefix-map.h. 12401 (lto_output_location): Remap the file part of locations. 12402 124032020-02-27 Jakub Jelinek <jakub@redhat.com> 12404 12405 PR c/93949 12406 * gimplify.c (gimplify_init_constructor): Don't promote readonly 12407 DECL_REGISTER variables to TREE_STATIC. 12408 12409 PR tree-optimization/93582 12410 PR tree-optimization/93945 12411 * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle memset with 12412 non-zero INTEGER_CST second argument and ref->offset or ref->size 12413 not a multiple of BITS_PER_UNIT. 12414 124152020-02-27 Jonathan Wakely <jwakely@redhat.com> 12416 12417 * doc/install.texi (Binaries): Update description of BullFreeware. 12418 124192020-02-26 Sandra Loosemore <sandra@codesourcery.com> 12420 12421 PR c++/90467 12422 12423 * doc/invoke.texi (Option Summary): Re-alphabetize warnings in 12424 C++ Language Options, Warning Options, and Static Analyzer 12425 Options lists. Document negative form of options enabled by 12426 default. Move some things around to more accurately sort 12427 warnings by category. 12428 (C++ Dialect Options, Warning Options, Static Analyzer 12429 Options): Document negative form of options when enabled by 12430 default. Move some things around to more accurately sort 12431 warnings by category. Add some missing index entries. 12432 Light copy-editing. 12433 124342020-02-26 Carl Love <cel@us.ibm.com> 12435 12436 PR target/91276 12437 * doc/extend.texi (PowerPC AltiVec Built-in Functions available on 12438 ISA 2.07): The builtin-function name __builtin_crypto_vpmsumb is only 12439 for the vector unsigned short arguments. It is also listed as the 12440 name of the built-in for arguments vector unsigned short, 12441 vector unsigned int and vector unsigned long long built-ins. The 12442 name of the builtins for these arguments should be: 12443 __builtin_crypto_vpmsumh, __builtin_crypto_vpmsumw and 12444 __builtin_crypto_vpmsumd respectively. 12445 124462020-02-26 Richard Biener <rguenther@suse.de> 12447 12448 * tree-vect-slp.c (vect_print_slp_tree): Also dump ref count 12449 and load permutation. 12450 124512020-02-26 Richard Sandiford <richard.sandiford@arm.com> 12452 12453 PR middle-end/93843 12454 * optabs-tree.c (supportable_convert_operation): Reject types with 12455 scalar modes. 12456 124572020-02-26 David Malcolm <dmalcolm@redhat.com> 12458 12459 * Makefile.in (ANALYZER_OBJS): Add analyzer/bar-chart.o. 12460 124612020-02-26 Jakub Jelinek <jakub@redhat.com> 12462 12463 PR tree-optimization/93820 12464 * gimple-ssa-store-merging.c (check_no_overlap): Change RHS_CODE 12465 argument to ALL_INTEGER_CST_P boolean. 12466 (imm_store_chain_info::try_coalesce_bswap): Adjust caller. 12467 (imm_store_chain_info::coalesce_immediate_stores): Likewise. Handle 12468 adjacent INTEGER_CST store into merged_store->only_constants like 12469 overlapping one. 12470 124712020-02-25 Jakub Jelinek <jakub@redhat.com> 12472 12473 PR other/93912 12474 * config/sh/sh.c (expand_cbranchdi4): Fix comment typo, probablity 12475 -> probability. 12476 * cfghooks.c (verify_flow_info): Likewise. 12477 * predict.c (combine_predictions_for_bb): Likewise. 12478 * bb-reorder.c (connect_better_edge_p): Likewise. Fix comment typo, 12479 sucessor -> successor. 12480 (find_traces_1_round): Fix comment typo, destinarion -> destination. 12481 * omp-expand.c (expand_oacc_for): Fix comment typo, sucessors -> 12482 successors. 12483 * tree-ssa-loop-ch.c (should_duplicate_loop_header_p): Fix dump 12484 message typo, sucessors -> successors. 12485 124862020-02-25 Martin Sebor <msebor@redhat.com> 12487 12488 * doc/extend.texi (attribute access): Correct an example. 12489 124902020-02-25 Mihail Ionescu <mihail.ionescu@arm.com> 12491 12492 * config/aarch64/aarch64-builtins.c (aarch64_scalar_builtin_types): 12493 Add simd_bf. 12494 (aarch64_init_simd_builtin_scalar_types): Register simd_bf. 12495 (VAR15, VAR16): New. 12496 * config/aarch64/iterators.md (VALLDIF): Enable for V4BF and V8BF. 12497 (VD): Enable for V4BF. 12498 (VDC): Likewise. 12499 (VQ): Enable for V8BF. 12500 (VQ2): Likewise. 12501 (VQ_NO2E): Likewise. 12502 (VDBL, Vdbl): Add V4BF. 12503 (V_INT_EQUIV, v_int_equiv): Add V4BF and V8BF. 12504 * config/aarch64/arm_neon.h (bfloat16x4x2_t): New typedef. 12505 (bfloat16x8x2_t): Likewise. 12506 (bfloat16x4x3_t): Likewise. 12507 (bfloat16x8x3_t): Likewise. 12508 (bfloat16x4x4_t): Likewise. 12509 (bfloat16x8x4_t): Likewise. 12510 (vcombine_bf16): New. 12511 (vld1_bf16, vld1_bf16_x2): New. 12512 (vld1_bf16_x3, vld1_bf16_x4): New. 12513 (vld1q_bf16, vld1q_bf16_x2): New. 12514 (vld1q_bf16_x3, vld1q_bf16_x4): New. 12515 (vld1_lane_bf16): New. 12516 (vld1q_lane_bf16): New. 12517 (vld1_dup_bf16): New. 12518 (vld1q_dup_bf16): New. 12519 (vld2_bf16): New. 12520 (vld2q_bf16): New. 12521 (vld2_dup_bf16): New. 12522 (vld2q_dup_bf16): New. 12523 (vld3_bf16): New. 12524 (vld3q_bf16): New. 12525 (vld3_dup_bf16): New. 12526 (vld3q_dup_bf16): New. 12527 (vld4_bf16): New. 12528 (vld4q_bf16): New. 12529 (vld4_dup_bf16): New. 12530 (vld4q_dup_bf16): New. 12531 (vst1_bf16, vst1_bf16_x2): New. 12532 (vst1_bf16_x3, vst1_bf16_x4): New. 12533 (vst1q_bf16, vst1q_bf16_x2): New. 12534 (vst1q_bf16_x3, vst1q_bf16_x4): New. 12535 (vst1_lane_bf16): New. 12536 (vst1q_lane_bf16): New. 12537 (vst2_bf16): New. 12538 (vst2q_bf16): New. 12539 (vst3_bf16): New. 12540 (vst3q_bf16): New. 12541 (vst4_bf16): New. 12542 (vst4q_bf16): New. 12543 125442020-02-25 Mihail Ionescu <mihail.ionescu@arm.com> 12545 12546 * config/aarch64/iterators.md (VDQF_F16) Add V4BF and V8BF. 12547 (VALL_F16): Likewise. 12548 (VALLDI_F16): Likewise. 12549 (Vtype): Likewise. 12550 (Vetype): Likewise. 12551 (vswap_width_name): Likewise. 12552 (VSWAP_WIDTH): Likewise. 12553 (Vel): Likewise. 12554 (VEL): Likewise. 12555 (q): Likewise. 12556 * config/aarch64/arm_neon.h (vset_lane_bf16, vsetq_lane_bf16): New. 12557 (vget_lane_bf16, vgetq_lane_bf16): New. 12558 (vcreate_bf16): New. 12559 (vdup_n_bf16, vdupq_n_bf16): New. 12560 (vdup_lane_bf16, vdup_laneq_bf16): New. 12561 (vdupq_lane_bf16, vdupq_laneq_bf16): New. 12562 (vduph_lane_bf16, vduph_laneq_bf16): New. 12563 (vreinterpret_bf16_u8, vreinterpretq_bf16_u8): New. 12564 (vreinterpret_bf16_u16, vreinterpretq_bf16_u16): New. 12565 (vreinterpret_bf16_u32, vreinterpretq_bf16_u32): New. 12566 (vreinterpret_bf16_u64, vreinterpretq_bf16_u64): New. 12567 (vreinterpret_bf16_s8, vreinterpretq_bf16_s8): New. 12568 (vreinterpret_bf16_s16, vreinterpretq_bf16_s16): New. 12569 (vreinterpret_bf16_s32, vreinterpretq_bf16_s32): New. 12570 (vreinterpret_bf16_s64, vreinterpretq_bf16_s64): New. 12571 (vreinterpret_bf16_p8, vreinterpretq_bf16_p8): New. 12572 (vreinterpret_bf16_p16, vreinterpretq_bf16_p16): New. 12573 (vreinterpret_bf16_p64, vreinterpretq_bf16_p64): New 12574 (vreinterpret_bf16_f16, vreinterpretq_bf16_f16): New 12575 (vreinterpret_bf16_f32, vreinterpretq_bf16_f32): New. 12576 (vreinterpret_bf16_f64, vreinterpretq_bf16_f64): New. 12577 (vreinterpretq_bf16_p128): New. 12578 (vreinterpret_s8_bf16, vreinterpretq_s8_bf16): New. 12579 (vreinterpret_s16_bf16, vreinterpretq_s16_bf16): New. 12580 (vreinterpret_s32_bf16, vreinterpretq_s32_bf16): New. 12581 (vreinterpret_s64_bf16, vreinterpretq_s64_bf16): New. 12582 (vreinterpret_u8_bf16, vreinterpretq_u8_bf16): New. 12583 (vreinterpret_u16_bf16, vreinterpretq_u16_bf16): New. 12584 (vreinterpret_u32_bf16, vreinterpretq_u32_bf16): New. 12585 (vreinterpret_u64_bf16, vreinterpretq_u64_bf16): New. 12586 (vreinterpret_p8_bf16, vreinterpretq_p8_bf16): New. 12587 (vreinterpret_p16_bf16, vreinterpretq_p16_bf16): New. 12588 (vreinterpret_p64_bf16, vreinterpretq_p64_bf16): New. 12589 (vreinterpret_f32_bf16, vreinterpretq_f32_bf16): New. 12590 (vreinterpret_f64_bf16,vreinterpretq_f64_bf16): New. 12591 (vreinterpret_f16_bf16,vreinterpretq_f16_bf16): New. 12592 (vreinterpretq_p128_bf16): New. 12593 125942020-02-25 Dennis Zhang <dennis.zhang@arm.com> 12595 12596 * config/arm/arm_neon.h (vbfdot_f32, vbfdotq_f32): New 12597 (vbfdot_lane_f32, vbfdotq_laneq_f32): New. 12598 (vbfdot_laneq_f32, vbfdotq_lane_f32): New. 12599 * config/arm/arm_neon_builtins.def (vbfdot): New entry. 12600 (vbfdot_lanev4bf, vbfdot_lanev8bf): Likewise. 12601 * config/arm/iterators.md (VSF2BF): New attribute. 12602 * config/arm/neon.md (neon_vbfdot<VCVTF:mode>): New entry. 12603 (neon_vbfdot_lanev4bf<VCVTF:mode>): Likewise. 12604 (neon_vbfdot_lanev8bf<VCVTF:mode>): Likewise. 12605 126062020-02-25 Christophe Lyon <christophe.lyon@linaro.org> 12607 12608 * config/arm/arm.md (required_for_purecode): New attribute. 12609 (enabled): Handle required_for_purecode. 12610 * config/arm/thumb1.md (thumb1_movsi_insn): Add alternative to 12611 work with -mpure-code. 12612 126132020-02-25 Jakub Jelinek <jakub@redhat.com> 12614 12615 PR rtl-optimization/93908 12616 * combine.c (find_split_point): For store into ZERO_EXTRACT, and src 12617 with mask. 12618 126192019-02-25 Eric Botcazou <ebotcazou@adacore.com> 12620 12621 * dwarf2out.c (dwarf2out_size_function): Run in early-DWARF mode. 12622 126232020-02-25 Roman Zhuykov <zhroma@ispras.ru> 12624 12625 * doc/install.texi (--enable-checking): Adjust wording. 12626 126272020-02-25 Richard Biener <rguenther@suse.de> 12628 12629 PR tree-optimization/93868 12630 * tree-vect-slp.c (slp_copy_subtree): New function. 12631 (vect_attempt_slp_rearrange_stmts): Copy the SLP tree before 12632 re-arranging stmts in it. 12633 126342020-02-25 Jakub Jelinek <jakub@redhat.com> 12635 12636 PR middle-end/93874 12637 * passes.c (pass_manager::dump_passes): Create a cgraph node for the 12638 dummy function and remove it at the end. 12639 12640 PR translation/93864 12641 * config/lm32/lm32.c (lm32_setup_incoming_varargs): Fix comment typo 12642 paramter -> parameter. 12643 * config/aarch64/aarch64.c (aarch64_is_extend_from_extract): Likewise. 12644 * ipa-prop.h (struct ipa_agg_replacement_value): Likewise. 12645 126462020-02-24 Roman Zhuykov <zhroma@ispras.ru> 12647 12648 * doc/install.texi (--enable-checking): Properly document current 12649 behavior. 12650 (--enable-stage1-checking): Minor clarification about bootstrap. 12651 126522020-02-24 David Malcolm <dmalcolm@redhat.com> 12653 12654 PR analyzer/93032 12655 * doc/invoke.texi (-Wnanalyzer-tainted-array-index): Note that 12656 -fanalyzer-checker=taint is also required. 12657 (-fanalyzer-checker=): Note that providing this option enables the 12658 given checker, and doing so may be required for checkers that are 12659 disabled by default. 12660 126612020-02-24 David Malcolm <dmalcolm@redhat.com> 12662 12663 * doc/invoke.texi (-fanalyzer-verbosity=): "2" only shows 12664 significant control flow events; add a "3" which shows all 12665 control flow events; the old "3" becomes "4". 12666 126672020-02-24 Jakub Jelinek <jakub@redhat.com> 12668 12669 PR tree-optimization/93582 12670 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Consider 12671 pd.offset and pd.size to be counted in bits rather than bytes, add 12672 support for maxsizei that is not a multiple of BITS_PER_UNIT and 12673 handle bitfield stores and loads. 12674 (vn_reference_lookup_3): Don't call ranges_known_overlap_p with 12675 uncomparable quantities - bytes vs. bits. Allow push_partial_def 12676 on offsets/sizes that aren't multiple of BITS_PER_UNIT and adjust 12677 pd.offset/pd.size to be counted in bits rather than bytes. 12678 Formatting fix. Rename shadowed len variable to buflen. 12679 126802020-02-24 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> 12681 Kugan Vivekandarajah <kugan.vivekanandarajah@linaro.org> 12682 12683 PR driver/47785 12684 * gcc.c (putenv_COLLECT_AS_OPTIONS): New function. 12685 (driver::main): Call putenv_COLLECT_AS_OPTIONS. 12686 * opts-common.c (parse_options_from_collect_gcc_options): New function. 12687 (prepend_xassembler_to_collect_as_options): Likewise. 12688 * opts.h (parse_options_from_collect_gcc_options): Declare prototype. 12689 (prepend_xassembler_to_collect_as_options): Likewise. 12690 * lto-opts.c (lto_write_options): Stream assembler options 12691 in COLLECT_AS_OPTIONS. 12692 * lto-wrapper.c (xassembler_options_error): New static variable. 12693 (get_options_from_collect_gcc_options): Move parsing options code to 12694 parse_options_from_collect_gcc_options and call it. 12695 (merge_and_complain): Validate -Xassembler options. 12696 (append_compiler_options): Handle OPT_Xassembler. 12697 (run_gcc): Append command line -Xassembler options to 12698 collect_gcc_options. 12699 * doc/invoke.texi: Add documentation about using Xassembler 12700 options with LTO. 12701 127022020-02-24 Kito Cheng <kito.cheng@sifive.com> 12703 12704 * config/riscv/riscv.c (riscv_emit_float_compare): Change the code gen 12705 for LTGT. 12706 (riscv_rtx_costs): Update cost model for LTGT. 12707 127082020-02-23 Vladimir Makarov <vmakarov@redhat.com> 12709 12710 PR rtl-optimization/93564 12711 * ira-color.c (struct update_cost_queue_elem): New member start. 12712 (queue_update_cost, get_next_update_cost): Add new arg start. 12713 (allocnos_conflict_p): New function. 12714 (update_costs_from_allocno): Add new arg conflict_cost_update_p. 12715 Add checking conflicts with allocnos_conflict_p. 12716 (update_costs_from_prefs, restore_costs_from_copies): Adjust 12717 update_costs_from_allocno calls. 12718 (update_conflict_hard_regno_costs): Add checking conflicts with 12719 allocnos_conflict_p. Adjust calls of queue_update_cost and 12720 get_next_update_cost. 12721 (assign_hard_reg): Adjust calls of queue_update_cost. Add 12722 debugging print. 12723 (bucket_allocno_compare_func): Restore previous version. 12724 127252020-02-21 John David Anglin <danglin@gcc.gnu.org> 12726 12727 * gcc/config/pa/pa.c (pa_function_value): Fix check for word and 12728 double-word size when handling aggregate return values. 12729 * gcc/config/pa/som.h (ASM_DECLARE_FUNCTION_NAME): Fix to indicate 12730 that homogeneous SFmode and DFmode aggregates are passed and returned 12731 in general registers. 12732 127332020-02-21 Jakub Jelinek <jakub@redhat.com> 12734 12735 PR translation/93759 12736 * opts.c (print_filtered_help): Translate help before appending 12737 messages to it rather than after that. 12738 127392020-02-19 Richard Sandiford <richard.sandiford@arm.com> 12740 12741 PR rtl-optimization/PR92989 12742 * lra-lives.c (process_bb_lives): Restore the original order 12743 of the bb liveness update. Call make_hard_regno_dead for each 12744 register clobbered at the start of an EH receiver. 12745 127462020-02-18 Feng Xue <fxue@os.amperecomputing.com> 12747 12748 PR ipa/93763 12749 * ipa-cp.c (self_recursively_generated_p): Mark self-dependent value as 12750 self-recursively generated. 12751 127522020-02-21 Iain Sandoe <iain@sandoe.co.uk> 12753 12754 PR target/93860 12755 * config/darwin-c.c (pop_field_alignment): Adjust quoting of 12756 error string. 12757 127582020-02-21 Mihail Ionescu <mihail.ionescu@arm.com> 12759 12760 * doc/sourcebuild.texi (arm_v8_1m_mve_ok): 12761 Document new target supports option. 12762 127632020-02-21 Dennis Zhang <dennis.zhang@arm.com> 12764 12765 * config/arm/arm_neon.h (vmmlaq_s32, vmmlaq_u32, vusmmlaq_s32): New. 12766 * config/arm/arm_neon_builtins.def (smmla, ummla, usmmla): New. 12767 * config/arm/iterators.md (MATMUL): New iterator. 12768 (sup): Add UNSPEC_MATMUL_S, UNSPEC_MATMUL_U, and UNSPEC_MATMUL_US. 12769 (mmla_sfx): New attribute. 12770 * config/arm/neon.md (neon_<sup>mmlav16qi): New. 12771 * config/arm/unspecs.md (UNSPEC_MATMUL_S, UNSPEC_MATMUL_U): New. 12772 (UNSPEC_MATMUL_US): New. 12773 127742020-02-21 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 12775 12776 * config/arm/arm.md: Prevent scalar shifts from being used when big 12777 endian is enabled. 12778 127792020-02-21 Jan Hubicka <hubicka@ucw.cz> 12780 Richard Biener <rguenther@suse.de> 12781 12782 PR tree-optimization/93586 12783 * tree-ssa-alias.c (nonoverlapping_array_refs_p): Finish array walk 12784 after mismatched array refs; do not sure type size information to 12785 recover from unmatched referneces with !flag_strict_aliasing_p. 12786 127872020-02-21 Andrew Stubbs <ams@codesourcery.com> 12788 12789 * config/gcn/gcn-valu.md (gather_load<mode>): Rename to ... 12790 (gather_load<mode>v64si): ... this and set operand 2 to V64SI. 12791 (scatter_store<mode>): Rename to ... 12792 (scatter_store<mode>v64si): ... this and set operand 1 to V64SI. 12793 (scatter<mode>_exec): Delete. Move contents ... 12794 (mask_scatter_store<mode>): ... here, and rename that to ... 12795 (mask_gather_load<mode>v64si): ... this. Set operand 2 to V64SI. 12796 Remove mode conversion. 12797 (mask_gather_load<mode>): Rename to ... 12798 (mask_scatter_store<mode>v64si): ... this. Set operand 1 to V64SI. 12799 Remove mode conversion. 12800 * config/gcn/gcn.c (gcn_expand_scaled_offsets): Remove mode conversion. 12801 128022020-02-21 Martin Jambor <mjambor@suse.cz> 12803 12804 PR tree-optimization/93845 12805 * tree-sra.c (verify_sra_access_forest): Only test access size of 12806 scalar types. 12807 128082020-02-21 Andrew Stubbs <ams@codesourcery.com> 12809 12810 * config/gcn/gcn.c (gcn_hard_regno_mode_ok): Align VGPR pairs. 12811 * config/gcn/gcn-valu.md (addv64di3): Remove early-clobber. 12812 (addv64di3_exec): Likewise. 12813 (subv64di3): Likewise. 12814 (subv64di3_exec): Likewise. 12815 (addv64di3_zext): Likewise. 12816 (addv64di3_zext_exec): Likewise. 12817 (addv64di3_zext_dup): Likewise. 12818 (addv64di3_zext_dup_exec): Likewise. 12819 (addv64di3_zext_dup2): Likewise. 12820 (addv64di3_zext_dup2_exec): Likewise. 12821 (addv64di3_sext_dup2): Likewise. 12822 (addv64di3_sext_dup2_exec): Likewise. 12823 (<expander>v64di3): Likewise. 12824 (<expander>v64di3_exec): Likewise. 12825 (*<reduc_op>_dpp_shr_v64di): Likewise. 12826 (*plus_carry_dpp_shr_v64di): Likewise. 12827 * config/gcn/gcn.md (adddi3): Likewise. 12828 (addptrdi3): Likewise. 12829 (<expander>di3): Likewise. 12830 128312020-02-21 Andrew Stubbs <ams@codesourcery.com> 12832 12833 * config/gcn/gcn-valu.md (vec_seriesv64di): Use gen_vec_duplicatev64di. 12834 128352020-02-21 Richard Sandiford <richard.sandiford@arm.com> 12836 12837 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Add SVE 12838 support. Use aarch64_emit_mult instead of emitting multiplication 12839 instructions directly. 12840 * config/aarch64/aarch64-sve.md (sqrt<mode>2, rsqrt<mode>2) 12841 (@aarch64_rsqrte<mode>, @aarch64_rsqrts<mode>): New expanders. 12842 128432020-02-21 Richard Sandiford <richard.sandiford@arm.com> 12844 12845 * config/aarch64/aarch64.c (aarch64_emit_mult): New function. 12846 (aarch64_emit_approx_div): Add SVE support. Use aarch64_emit_mult 12847 instead of emitting multiplication instructions directly. 12848 * config/aarch64/iterators.md (SVE_COND_FP_BINARY_OPTAB): New iterator. 12849 * config/aarch64/aarch64-sve.md (div<mode>3, @aarch64_frecpe<mode>) 12850 (@aarch64_frecps<mode>): New expanders. 12851 128522020-02-21 Richard Sandiford <richard.sandiford@arm.com> 12853 12854 * config/aarch64/aarch64-protos.h (AARCH64_APPROX_MODE): Operate 12855 on and produce uint64_ts rather than ints. 12856 (AARCH64_APPROX_NONE, AARCH64_APPROX_ALL): Change to uint64_ts. 12857 (cpu_approx_modes): Change the fields from unsigned int to uint64_t. 12858 128592020-02-21 Richard Sandiford <richard.sandiford@arm.com> 12860 12861 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Don't create 12862 an unused xmsk register when handling approximate rsqrt. 12863 128642020-02-21 Richard Sandiford <richard.sandiford@arm.com> 12865 12866 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Fix inverted 12867 flag_finite_math_only condition. 12868 128692020-02-20 Uroš Bizjak <ubizjak@gmail.com> 12870 12871 PR target/93828 12872 * config/i386/mmx.md (*vec_extractv2sf_1): Match source operand 12873 to destination operand for shufps alternative. 12874 (*vec_extractv2si_1): Ditto. 12875 128762020-02-20 Peter Bergner <bergner@linux.ibm.com> 12877 12878 PR target/93658 12879 * config/rs6000/rs6000.c (rs6000_legitimate_address_p): Handle VSX 12880 vector modes. 12881 128822020-02-20 Martin Liska <mliska@suse.cz> 12883 12884 PR translation/93831 12885 * config/darwin.c (darwin_override_options): Change 64b to 64-bit mode. 12886 128872020-02-20 Martin Liska <mliska@suse.cz> 12888 12889 PR translation/93830 12890 * common/config/avr/avr-common.c: Remote trailing "|". 12891 128922020-02-19 Bernd Edlinger <bernd.edlinger@hotmail.de> 12893 12894 * collect2.c (maybe_run_lto_and_relink): Fix typo in 12895 comment. 12896 128972020-02-19 Richard Sandiford <richard.sandiford@arm.com> 12898 12899 PR tree-optimization/93767 12900 * tree-vect-data-refs.c (vect_compile_time_alias): Remove the 12901 access-size bias from the offset calculations for negative strides. 12902 129032020-02-19 Bernd Edlinger <bernd.edlinger@hotmail.de> 12904 12905 * collect2.c (c_file, o_file): Make const again. 12906 (ldout,lderrout, dump_ld_file): Remove. 12907 (tool_cleanup): Avoid calling not signal-safe functions. 12908 (maybe_run_lto_and_relink): Avoid possible signal handler 12909 access to unintialzed memory (lto_o_files). 12910 (main): Avoid leaking temp files in $TMPDIR. 12911 Initialize c_file/o_file with concat, which avoids exposing 12912 uninitialized memory to signal handler, which calls unlink(!). 12913 Avoid calling maybe_unlink when the main function returns, 12914 since the atexit handler is already doing this. 12915 * collect2.h (dump_ld_file, ldout, lderrout): Remove. 12916 129172020-02-19 Martin Jambor <mjambor@suse.cz> 12918 12919 PR tree-optimization/93776 12920 * tree-sra.c (create_access): Do not create zero size accesses. 12921 (get_access_for_expr): Do not search for zero sized accesses. 12922 129232020-02-19 Martin Jambor <mjambor@suse.cz> 12924 12925 PR tree-optimization/93667 12926 * tree-sra.c (scalarizable_type_p): Return false if record fields 12927 do not follow wach other. 12928 129292020-01-21 Kito Cheng <kito.cheng@sifive.com> 12930 12931 * config/riscv/riscv.c (riscv_output_move) Using fmv.x.w/fmv.w.x 12932 rather than fmv.x.s/fmv.s.x. 12933 129342020-02-18 James Greenhalgh <james.greenhalgh@arm.com> 12935 12936 * config/aarch64/aarch64-simd-builtins.def 12937 (intrinsic_vec_smult_lo_): New. 12938 (intrinsic_vec_umult_lo_): Likewise. 12939 (vec_widen_smult_hi_): Likewise. 12940 (vec_widen_umult_hi_): Likewise. 12941 * config/aarch64/aarch64-simd.md 12942 (aarch64_intrinsic_vec_<su>mult_lo_<mode>): New. 12943 * config/aarch64/arm_neon.h (vmull_high_s8): Use intrinsics. 12944 (vmull_high_s16): Likewise. 12945 (vmull_high_s32): Likewise. 12946 (vmull_high_u8): Likewise. 12947 (vmull_high_u16): Likewise. 12948 (vmull_high_u32): Likewise. 12949 (vmull_s8): Likewise. 12950 (vmull_s16): Likewise. 12951 (vmull_s32): Likewise. 12952 (vmull_u8): Likewise. 12953 (vmull_u16): Likewise. 12954 (vmull_u32): Likewise. 12955 129562020-02-18 Martin Liska <mliska@suse.cz> 12957 12958 * value-prof.c (stream_out_histogram_value): Restore LTO PGO 12959 bootstrap by missing removal of invalid sanity check. 12960 129612020-02-18 Martin Liska <mliska@suse.cz> 12962 12963 PR ipa/92518 12964 * ipa-icf-gimple.c (func_checker::compare_gimple_assign): 12965 Always compare LHS of gimple_assign. 12966 129672020-02-18 Martin Liska <mliska@suse.cz> 12968 12969 PR ipa/93583 12970 * cgraph.c (cgraph_node::verify_node): Verify MALLOC attribute 12971 and return type of functions. 12972 * ipa-param-manipulation.c (ipa_param_adjustments::adjust_decl): 12973 Drop MALLOC attribute for void functions. 12974 * ipa-pure-const.c (funct_state_summary_t::duplicate): Drop 12975 malloc_state for a new VOID clone. 12976 129772020-02-18 Martin Liska <mliska@suse.cz> 12978 12979 PR ipa/92924 12980 * common.opt: Add -fprofile-reproducibility. 12981 * doc/invoke.texi: Document it. 12982 * value-prof.c (dump_histogram_value): 12983 Document and support behavior for counters[0] 12984 being a negative value. 12985 (get_nth_most_common_value): Handle negative 12986 counters[0] in respect to flag_profile_reproducible. 12987 129882020-02-18 Jakub Jelinek <jakub@redhat.com> 12989 12990 PR ipa/93797 12991 * cgraph.c (verify_speculative_call): Use speculative_id instead of 12992 speculative_uid in messages. Remove trailing whitespace from error 12993 message. Use num_speculative_call_targets instead of 12994 num_speculative_targets in a message. 12995 (cgraph_node::verify_node): Use call_stmt instead of cal_stmt in 12996 edge messages and stmt instead of cal_stmt in reference message. 12997 12998 PR tree-optimization/93780 12999 * tree-ssa.c (non_rewritable_lvalue_p): Check valid_vector_subparts_p 13000 before calling build_vector_type. 13001 (execute_update_addresses_taken): Likewise. 13002 13003 PR driver/93796 13004 * params.opt (-param=ipa-max-switch-predicate-bounds=): Fix help 13005 typo, functoin -> function. 13006 * tree.c (free_lang_data_in_decl): Fix comment typo, 13007 functoin -> function. 13008 * ipa-visibility.c (cgraph_externally_visible_p): Likewise. 13009 130102020-02-17 David Malcolm <dmalcolm@redhat.com> 13011 13012 * diagnostic.c (print_any_cwe): Don't call get_cwe_url if URLs 13013 won't be printed. 13014 (print_option_information): Don't call get_option_url if URLs 13015 won't be printed. 13016 130172020-02-17 Alexandre Oliva <oliva@adacore.com> 13018 13019 * tree-emutls.c (new_emutls_decl, emutls_common_1): Complete 13020 handling of register_common-less targets. 13021 130222020-02-17 Martin Liska <mliska@suse.cz> 13023 13024 PR ipa/93760 13025 * ipa-devirt.c (odr_types_equivalent_p): Fix grammar. 13026 130272020-02-17 Martin Liska <mliska@suse.cz> 13028 13029 PR translation/93755 13030 * config/rs6000/rs6000.c (rs6000_option_override_internal): 13031 Fix double quotes. 13032 130332020-02-17 Martin Liska <mliska@suse.cz> 13034 13035 PR other/93756 13036 * config/rx/elf.opt: Fix typo. 13037 130382020-02-17 Richard Biener <rguenther@suse.de> 13039 13040 PR c/86134 13041 * opts-global.c (print_ignored_options): Use inform and 13042 amend message. 13043 130442020-02-17 Jiufu Guo <guojiufu@linux.ibm.com> 13045 13046 PR target/93047 13047 * config/rs6000/rs6000.md (untyped_call): Add emit_clobber. 13048 130492020-02-16 Uroš Bizjak <ubizjak@gmail.com> 13050 13051 PR target/93743 13052 * config/i386/i386.md (atan2xf3): Swap operands 1 and 2. 13053 (atan2<mode>3): Update operand order in the call to gen_atan2xf3. 13054 130552020-02-15 Jason Merrill <jason@redhat.com> 13056 13057 * doc/invoke.texi (C Dialect Options): Add -std=c++20. 13058 130592020-02-15 Jakub Jelinek <jakub@redhat.com> 13060 13061 PR tree-optimization/93744 13062 * match.pd (((m1 >/</>=/<= m2) * d -> (m1 >/</>=/<= m2) ? d : 0, 13063 A - ((A - B) & -(C cmp D)) -> (C cmp D) ? B : A, 13064 A + ((B - A) & -(C cmp D)) -> (C cmp D) ? B : A): For GENERIC, make 13065 sure @2 in the first and @1 in the other patterns has no side-effects. 13066 130672020-02-15 David Malcolm <dmalcolm@redhat.com> 13068 Bernd Edlinger <bernd.edlinger@hotmail.de> 13069 13070 PR 87488 13071 PR other/93168 13072 * config.in (DIAGNOSTICS_URLS_DEFAULT): New define. 13073 * configure.ac (--with-diagnostics-urls): New configuration 13074 option, based on --with-diagnostics-color. 13075 (DIAGNOSTICS_URLS_DEFAULT): New define. 13076 * config.h: Regenerate. 13077 * configure: Regenerate. 13078 * diagnostic.c (diagnostic_urls_init): Handle -1 for 13079 DIAGNOSTICS_URLS_DEFAULT from configure-time 13080 --with-diagnostics-urls=auto-if-env by querying for a GCC_URLS 13081 and TERM_URLS environment variable. 13082 * diagnostic-url.h (diagnostic_url_format): New enum type. 13083 (diagnostic_urls_enabled_p): rename to... 13084 (determine_url_format): ... this, and change return type. 13085 * diagnostic-color.c (parse_env_vars_for_urls): New helper function. 13086 (auto_enable_urls): Disable URLs on xfce4-terminal, gnome-terminal, 13087 the linux console, and mingw. 13088 (diagnostic_urls_enabled_p): rename to... 13089 (determine_url_format): ... this, and adjust. 13090 * pretty-print.h (pretty_printer::show_urls): rename to... 13091 (pretty_printer::url_format): ... this, and change to enum. 13092 * pretty-print.c (pretty_printer::pretty_printer, 13093 pp_begin_url, pp_end_url, test_urls): Adjust. 13094 * doc/install.texi (--with-diagnostics-urls): Document the new 13095 configuration option. 13096 (--with-diagnostics-color): Document the existing interaction 13097 with GCC_COLORS better. 13098 * doc/invoke.texi (-fdiagnostics-urls): Add GCC_URLS and TERM_URLS 13099 vindex reference. Update description of defaults based on the above. 13100 (-fdiagnostics-color): Update description of how -fdiagnostics-color 13101 interacts with GCC_COLORS. 13102 131032020-02-14 Eric Botcazou <ebotcazou@adacore.com> 13104 13105 PR target/93704 13106 * config/sparc/sparc.c (eligible_for_call_delay): Test HAVE_GNU_LD in 13107 conjunction with TARGET_GNU_TLS in early return. 13108 131092020-02-14 Alexander Monakov <amonakov@ispras.ru> 13110 13111 * rtlanal.c (rtx_cost): Handle a SET up front. Avoid division if 13112 the mode is not wider than UNITS_PER_WORD. 13113 131142020-02-14 Martin Jambor <mjambor@suse.cz> 13115 13116 PR tree-optimization/93516 13117 * tree-sra.c (propagate_subaccesses_from_rhs): Do not create 13118 access of the same type as the parent. 13119 (propagate_subaccesses_from_lhs): Likewise. 13120 131212020-02-14 Hongtao Liu <hongtao.liu@intel.com> 13122 13123 PR target/93724 13124 * config/i386/avx512vbmi2intrin.h 13125 (_mm512_shrdi_epi16, _mm512_mask_shrdi_epi16, 13126 _mm512_maskz_shrdi_epi16, _mm512_shrdi_epi32, 13127 _mm512_mask_shrdi_epi32, _mm512_maskz_shrdi_epi32, 13128 _m512_shrdi_epi64, _m512_mask_shrdi_epi64, 13129 _m512_maskz_shrdi_epi64, _mm512_shldi_epi16, 13130 _mm512_mask_shldi_epi16, _mm512_maskz_shldi_epi16, 13131 _mm512_shldi_epi32, _mm512_mask_shldi_epi32, 13132 _mm512_maskz_shldi_epi32, _mm512_shldi_epi64, 13133 _mm512_mask_shldi_epi64, _mm512_maskz_shldi_epi64): Fix typo 13134 of lacking a closing parenthesis. 13135 * config/i386/avx512vbmi2vlintrin.h 13136 (_mm256_shrdi_epi16, _mm256_mask_shrdi_epi16, 13137 _mm256_maskz_shrdi_epi16, _mm256_shrdi_epi32, 13138 _mm256_mask_shrdi_epi32, _mm256_maskz_shrdi_epi32, 13139 _m256_shrdi_epi64, _m256_mask_shrdi_epi64, 13140 _m256_maskz_shrdi_epi64, _mm256_shldi_epi16, 13141 _mm256_mask_shldi_epi16, _mm256_maskz_shldi_epi16, 13142 _mm256_shldi_epi32, _mm256_mask_shldi_epi32, 13143 _mm256_maskz_shldi_epi32, _mm256_shldi_epi64, 13144 _mm256_mask_shldi_epi64, _mm256_maskz_shldi_epi64, 13145 _mm_shrdi_epi16, _mm_mask_shrdi_epi16, 13146 _mm_maskz_shrdi_epi16, _mm_shrdi_epi32, 13147 _mm_mask_shrdi_epi32, _mm_maskz_shrdi_epi32, 13148 _mm_shrdi_epi64, _mm_mask_shrdi_epi64, 13149 _m_maskz_shrdi_epi64, _mm_shldi_epi16, 13150 _mm_mask_shldi_epi16, _mm_maskz_shldi_epi16, 13151 _mm_shldi_epi32, _mm_mask_shldi_epi32, 13152 _mm_maskz_shldi_epi32, _mm_shldi_epi64, 13153 _mm_mask_shldi_epi64, _mm_maskz_shldi_epi64): Ditto. 13154 131552020-02-13 H.J. Lu <hongjiu.lu@intel.com> 13156 13157 PR target/93656 13158 * config/i386/i386.c (ix86_trampoline_init): Skip ENDBR32 at 13159 the target function entry. 13160 131612020-02-13 Claudiu Zissulescu <claziss@synopsys.com> 13162 13163 * common/config/arc/arc-common.c (arc_option_optimization_table): 13164 Disable if-conversion step when optimized for size. 13165 131662020-02-13 Claudiu Zissulescu <claziss@synopsys.com> 13167 13168 * config/arc/arc.c (arc_conditional_register_usage): R0-R3 and 13169 R12-R15 are always in ARCOMPACT16_REGS register class. 13170 * config/arc/arc.opt (mq-class): Deprecate. 13171 * config/arc/constraint.md ("q"): Remove dependency on mq-class 13172 option. 13173 * doc/invoke.texi (mq-class): Update text. 13174 * common/config/arc/arc-common.c (arc_option_optimization_table): 13175 Update list. 13176 131772020-02-13 Claudiu Zissulescu <claziss@synopsys.com> 13178 13179 * config/arc/arc.c (arc_insn_cost): New function. 13180 (TARGET_INSN_COST): Define. 13181 * config/arc/arc.md (cost): New attribute. 13182 (add_n): Use arc_nonmemory_operand. 13183 (ashlsi3_insn): Likewise, also update constraints. 13184 (ashrsi3_insn): Likewise. 13185 (rotrsi3): Likewise. 13186 (add_shift): Likewise. 13187 * config/arc/predicates.md (arc_nonmemory_operand): New predicate. 13188 131892020-02-13 Claudiu Zissulescu <claziss@synopsys.com> 13190 13191 * config/arc/arc.md (mulsidi_600): Correctly select mlo/mhi 13192 registers. 13193 (umulsidi_600): Likewise. 13194 131952020-02-13 Jakub Jelinek <jakub@redhat.com> 13196 13197 PR target/93696 13198 * config/i386/avx512bitalgintrin.h (_mm512_mask_popcnt_epi8, 13199 _mm512_mask_popcnt_epi16, _mm256_mask_popcnt_epi8, 13200 _mm256_mask_popcnt_epi16, _mm_mask_popcnt_epi8, 13201 _mm_mask_popcnt_epi16): Rename __B argument to __A and __A to __W, 13202 pass __A to the builtin followed by __W instead of __A followed by 13203 __B. 13204 * config/i386/avx512vpopcntdqintrin.h (_mm512_mask_popcnt_epi32, 13205 _mm512_mask_popcnt_epi64): Likewise. 13206 * config/i386/avx512vpopcntdqvlintrin.h (_mm_mask_popcnt_epi32, 13207 _mm256_mask_popcnt_epi32, _mm_mask_popcnt_epi64, 13208 _mm256_mask_popcnt_epi64): Likewise. 13209 13210 PR tree-optimization/93582 13211 * fold-const.h (shift_bytes_in_array_left, 13212 shift_bytes_in_array_right): Declare. 13213 * fold-const.c (shift_bytes_in_array_left, 13214 shift_bytes_in_array_right): New function, moved from 13215 gimple-ssa-store-merging.c, no longer static. 13216 * gimple-ssa-store-merging.c (shift_bytes_in_array): Move 13217 to gimple-ssa-store-merging.c and rename to shift_bytes_in_array_left. 13218 (shift_bytes_in_array_right): Move to gimple-ssa-store-merging.c. 13219 (encode_tree_to_bitpos): Use shift_bytes_in_array_left instead of 13220 shift_bytes_in_array. 13221 (verify_shift_bytes_in_array): Rename to ... 13222 (verify_shift_bytes_in_array_left): ... this. Use 13223 shift_bytes_in_array_left instead of shift_bytes_in_array. 13224 (store_merging_c_tests): Call verify_shift_bytes_in_array_left 13225 instead of verify_shift_bytes_in_array. 13226 * tree-ssa-sccvn.c (vn_reference_lookup_3): For native_encode_expr 13227 / native_interpret_expr where the store covers all needed bits, 13228 punt on PDP-endian, otherwise allow all involved offsets and sizes 13229 not to be byte-aligned. 13230 13231 PR target/93673 13232 * config/i386/sse.md (k<code><mode>): Drop mode from last operand and 13233 use const_0_to_255_operand predicate instead of immediate_operand. 13234 (avx512dq_fpclass<mode><mask_scalar_merge_name>, 13235 avx512dq_vmfpclass<mode><mask_scalar_merge_name>, 13236 vgf2p8affineinvqb_<mode><mask_name>, 13237 vgf2p8affineqb_<mode><mask_name>): Drop mode from 13238 const_0_to_255_operand predicated operands. 13239 132402020-02-12 Jeff Law <law@redhat.com> 13241 13242 * config/h8300/h8300.md (comparison shortening peepholes): Use 13243 a mode iterator to merge the HImode and SImode peepholes. 13244 132452020-02-12 Jakub Jelinek <jakub@redhat.com> 13246 13247 PR middle-end/93663 13248 * real.c (is_even): Make static. Function comment fix. 13249 (is_halfway_below): Make static, don't assert R is not inf/nan, 13250 instead return false for those. Small formatting fixes. 13251 132522020-02-12 Martin Sebor <msebor@redhat.com> 13253 13254 PR middle-end/93646 13255 * tree-ssa-strlen.c (handle_builtin_stxncpy): Rename... 13256 (handle_builtin_stxncpy_strncat): ...to this. Change first argument. 13257 Issue only -Wstringop-overflow strncat, never -Wstringop-truncation. 13258 (strlen_check_and_optimize_call): Adjust callee name. 13259 132602020-02-12 Jeff Law <law@redhat.com> 13261 13262 * config/h8300/h8300.md (comparison shortening peepholes): Drop 13263 (and (xor)) variant. Combine other two into single peephole. 13264 132652020-02-12 Wilco Dijkstra <wdijkstr@arm.com> 13266 13267 PR rtl-optimization/93565 13268 * config/aarch64/aarch64.c (aarch64_rtx_costs): Add CTZ costs. 13269 132702020-02-12 Wilco Dijkstra <wdijkstr@arm.com> 13271 13272 * config/aarch64/aarch64-simd.md 13273 (aarch64_zero_extend<GPI:mode>_reduc_plus_<VDQV_E:mode>): New pattern. 13274 * config/aarch64/aarch64.md (popcount<mode>2): Use it instead of 13275 generating separate ADDV and zero_extend patterns. 13276 * config/aarch64/iterators.md (VDQV_E): New iterator. 13277 132782020-02-12 Jeff Law <law@redhat.com> 13279 13280 * config/h8300/h8300.md (cpymemsi, movmd): Remove dead patterns, 13281 expanders, splits, etc. 13282 (movmd_internal_<mode>, movmd splitter, movstr, movsd): Likewise. 13283 (stpcpy_internal_<mode>, stpcpy splitter): Likewise. 13284 (peepholes to convert QI/HI mode pushes to SI mode pushes): Likewise. 13285 * config/h8300/h8300.c (h8300_swap_into_er6): Remove unused function. 13286 (h8300_swap_out_of_er6, h8sx_emit_movmd): Likewise 13287 * config/h8300/h8300-protos.h (h8300_swap_into_er6): Remove unused 13288 function prototype. 13289 (h8300_swap_out_of_er6, h8sx_emit_movmd): Likewise. 13290 132912020-02-12 Jakub Jelinek <jakub@redhat.com> 13292 13293 PR target/93670 13294 * config/i386/sse.md (VI48F_256_DQ): New mode iterator. 13295 (avx512vl_vextractf128<mode>): Use it instead of VI48F_256. Remove 13296 TARGET_AVX512DQ from condition. 13297 (vec_extract_lo_<mode><mask_name>): Use <mask_avx512dq_condition> 13298 instead of <mask_mode512bit_condition> in condition. If 13299 TARGET_AVX512DQ is false, emit vextract*64x4 instead of 13300 vextract*32x8. 13301 (vec_extract_lo_<mode><mask_name>): Drop <mask_avx512dq_condition> 13302 from condition. 13303 133042020-02-12 Kewen Lin <linkw@gcc.gnu.org> 13305 13306 PR target/91052 13307 * ira.c (combine_and_move_insns): Skip multiple_sets def_insn. 13308 133092020-02-12 Segher Boessenkool <segher@kernel.crashing.org> 13310 13311 * config/rs6000/rs6000.c (rs6000_debug_print_mode): Don't use sizeof 13312 where strlen is more legible. 13313 (rs6000_builtin_vectorized_libmass): Ditto. 13314 (rs6000_print_options_internal): Ditto. 13315 133162020-02-11 Martin Sebor <msebor@redhat.com> 13317 13318 PR tree-optimization/93683 13319 * tree-ssa-alias.c (stmt_kills_ref_p): Avoid using LHS when not set. 13320 133212020-02-11 Michael Meissner <meissner@linux.ibm.com> 13322 13323 * config/rs6000/predicates.md (cint34_operand): Rename the 13324 -mprefixed-addr option to be -mprefixed. 13325 * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Rename 13326 the -mprefixed-addr option to be -mprefixed. 13327 (OTHER_FUTURE_MASKS): Likewise. 13328 (POWERPC_MASKS): Likewise. 13329 * config/rs6000/rs6000.c (rs6000_option_override_internal): Rename 13330 the -mprefixed-addr option to be -mprefixed. Change error 13331 messages to refer to -mprefixed. 13332 (num_insns_constant_gpr): Rename the -mprefixed-addr option to be 13333 -mprefixed. 13334 (rs6000_legitimate_offset_address_p): Likewise. 13335 (rs6000_mode_dependent_address): Likewise. 13336 (rs6000_opt_masks): Change the spelling of "-mprefixed-addr" to be 13337 "-mprefixed" for target attributes and pragmas. 13338 (address_to_insn_form): Rename the -mprefixed-addr option to be 13339 -mprefixed. 13340 (rs6000_adjust_insn_length): Likewise. 13341 * config/rs6000/rs6000.h (FINAL_PRESCAN_INSN): Rename the 13342 -mprefixed-addr option to be -mprefixed. 13343 (ASM_OUTPUT_OPCODE): Likewise. 13344 * config/rs6000/rs6000.md (prefixed insn attribute): Rename the 13345 -mprefixed-addr option to be -mprefixed. 13346 * config/rs6000/rs6000.opt (-mprefixed): Rename the 13347 -mprefixed-addr option to be prefixed. Change the option from 13348 being undocumented to being documented. 13349 * doc/invoke.texi (RS/6000 and PowerPC Options): Document the 13350 -mprefixed option. Update the -mpcrel documentation to mention 13351 -mprefixed. 13352 133532020-02-11 Hans-Peter Nilsson <hp@axis.com> 13354 13355 * ira-conflicts.c (print_hard_reg_set): Correct output for sets 13356 including FIRST_PSEUDO_REGISTER - 1. 13357 * ira-color.c (print_hard_reg_set): Ditto. 13358 133592020-02-11 Stam Markianos-Wright <stam.markianos-wright@arm.com> 13360 13361 * config/arm/arm-builtins.c (enum arm_type_qualifiers): 13362 (USTERNOP_QUALIFIERS): New define. 13363 (USMAC_LANE_QUADTUP_QUALIFIERS): New define. 13364 (SUMAC_LANE_QUADTUP_QUALIFIERS): New define. 13365 (arm_expand_builtin_args): Add case ARG_BUILTIN_LANE_QUADTUP_INDEX. 13366 (arm_expand_builtin_1): Add qualifier_lane_quadtup_index. 13367 * config/arm/arm_neon.h (vusdot_s32): New. 13368 (vusdot_lane_s32): New. 13369 (vusdotq_lane_s32): New. 13370 (vsudot_lane_s32): New. 13371 (vsudotq_lane_s32): New. 13372 * config/arm/arm_neon_builtins.def (usdot, usdot_lane,sudot_lane): New. 13373 * config/arm/iterators.md (DOTPROD_I8MM): New. 13374 (sup, opsuffix): Add <us/su>. 13375 * config/arm/neon.md (neon_usdot, <us/su>dot_lane: New. 13376 * config/arm/unspecs.md (UNSPEC_DOT_US, UNSPEC_DOT_SU): New. 13377 133782020-02-11 Richard Biener <rguenther@suse.de> 13379 13380 PR tree-optimization/93661 13381 PR tree-optimization/93662 13382 * tree-ssa-sccvn.c (vn_reference_lookup_3): Properly guard 13383 tree_to_poly_int64. 13384 * tree-sra.c (get_access_for_expr): Likewise. 13385 133862020-02-10 Jakub Jelinek <jakub@redhat.com> 13387 13388 PR target/93637 13389 * config/i386/sse.md (VI_256_AVX2): New mode iterator. 13390 (vcond_mask_<mode><sseintvecmodelower>): Use it instead of VI_256. 13391 Change condition from TARGET_AVX2 to TARGET_AVX. 13392 133932020-02-10 Iain Sandoe <iain@sandoe.co.uk> 13394 13395 PR other/93641 13396 * config/darwin-c.c (darwin_cfstring_ref_p): Fix up last 13397 argument of strncmp. 13398 133992020-02-10 Hans-Peter Nilsson <hp@axis.com> 13400 13401 Try to generate zero-based comparisons. 13402 * config/cris/cris.c (cris_reduce_compare): New function. 13403 * config/cris/cris-protos.h (cris_reduce_compare): Add prototype. 13404 * config/cris/cris.md ("cbranch<mode>4", "cbranchdi4", "cstoredi4") 13405 (cstore<mode>4"): Apply cris_reduce_compare in expanders. 13406 134072020-02-10 Richard Earnshaw <rearnsha@arm.com> 13408 13409 PR target/91913 13410 * config/arm/arm.md (movsi_compare0): Allow SP as a source register 13411 in Thumb state and also as a destination in Arm state. Add T16 13412 variants. 13413 134142020-02-10 Hans-Peter Nilsson <hp@axis.com> 13415 13416 * md.texi (Define Subst): Match closing paren in example. 13417 134182020-02-10 Jakub Jelinek <jakub@redhat.com> 13419 13420 PR target/58218 13421 PR other/93641 13422 * config/i386/i386.c (x86_64_elf_section_type_flags): Fix up last 13423 arguments of strncmp. 13424 134252020-02-10 Feng Xue <fxue@os.amperecomputing.com> 13426 13427 PR ipa/93203 13428 * ipa-cp.c (ipcp_lattice::add_value): Add source with same call edge 13429 but different source value. 13430 (adjust_callers_for_value_intersection): New function. 13431 (gather_edges_for_value): Adjust order of callers to let a 13432 non-self-recursive caller be the first element. 13433 (self_recursive_pass_through_p): Add a new parameter "simple", and 13434 check generalized self-recursive pass-through jump function. 13435 (self_recursive_agg_pass_through_p): Likewise. 13436 (find_more_scalar_values_for_callers_subset): Compute value from 13437 pass-through jump function for self-recursive. 13438 (intersect_with_plats): Cleanup previous implementation code for value 13439 itersection with self-recursive call edge. 13440 (intersect_with_agg_replacements): Likewise. 13441 (intersect_aggregates_with_edge): Deduce value from pass-through jump 13442 function for self-recursive call edge. Cleanup previous implementation 13443 code for value intersection with self-recursive call edge. 13444 (decide_whether_version_node): Remove dead callers and adjust order 13445 to let a non-self-recursive caller be the first element. 13446 134472020-02-09 Uroš Bizjak <ubizjak@gmail.com> 13448 13449 * recog.c: Move pass_split_before_sched2 code in front of 13450 pass_split_before_regstack. 13451 (pass_data_split_before_sched2): Rename pass to split3 from split4. 13452 (pass_data_split_before_regstack): Rename pass to split4 from split3. 13453 (rest_of_handle_split_before_sched2): Remove. 13454 (pass_split_before_sched2::execute): Unconditionally call 13455 split_all_insns. 13456 (enable_split_before_sched2): New function. 13457 (pass_split_before_sched2::gate): Use enable_split_before_sched2. 13458 (pass_split_before_regstack::gate): Ditto. 13459 * config/nds32/nds32.c (nds32_split_double_word_load_store_p): 13460 Update name check for renamed split4 pass. 13461 * config/sh/sh.c (register_sh_passes): Update pass insertion 13462 point for renamed split4 pass. 13463 134642020-02-09 Jakub Jelinek <jakub@redhat.com> 13465 13466 * gimplify.c (gimplify_adjust_omp_clauses_1): Promote 13467 DECL_IN_CONSTANT_POOL variables into "omp declare target" to avoid 13468 copying them around between host and target. 13469 134702020-02-08 Andrew Pinski <apinski@marvell.com> 13471 13472 PR target/91927 13473 * config/aarch64/aarch64-simd.md (movmisalign<mode>): Check 13474 STRICT_ALIGNMENT also. 13475 134762020-02-08 Jim Wilson <jimw@sifive.com> 13477 13478 PR target/93532 13479 * config/riscv/riscv.h (HARD_REGNO_CALLER_SAVE_MODE): Define. 13480 134812020-02-08 Uroš Bizjak <ubizjak@gmail.com> 13482 Jakub Jelinek <jakub@redhat.com> 13483 13484 PR target/65782 13485 * config/i386/i386.h (CALL_USED_REGISTERS): Make 13486 xmm16-xmm31 call-used even in 64-bit ms-abi. 13487 134882020-02-07 Dennis Zhang <dennis.zhang@arm.com> 13489 13490 * config/aarch64/aarch64-simd-builtins.def (simd_smmla): New entry. 13491 (simd_ummla, simd_usmmla): Likewise. 13492 * config/aarch64/aarch64-simd.md (aarch64_simd_<sur>mmlav16qi): New. 13493 * config/aarch64/arm_neon.h (vmmlaq_s32, vmmlaq_u32): New. 13494 (vusmmlaq_s32): New. 13495 134962020-02-07 Richard Biener <rguenther@suse.de> 13497 13498 PR middle-end/93519 13499 * tree-inline.c (fold_marked_statements): Do a PRE walk, 13500 skipping unreachable regions. 13501 (optimize_inline_calls): Skip folding stmts when we didn't 13502 inline. 13503 135042020-02-07 H.J. Lu <hongjiu.lu@intel.com> 13505 13506 PR target/85667 13507 * config/i386/i386.c (function_arg_ms_64): Add a type argument. 13508 Don't return aggregates with only SFmode and DFmode in SSE 13509 register. 13510 (ix86_function_arg): Pass arg.type to function_arg_ms_64. 13511 135122020-02-07 Jakub Jelinek <jakub@redhat.com> 13513 13514 PR target/93122 13515 * config/rs6000/rs6000-logue.c 13516 (rs6000_emit_probe_stack_range_stack_clash): Always use gen_add3_insn, 13517 if it fails, move rs into end_addr and retry. Add 13518 REG_FRAME_RELATED_EXPR note whenever it returns more than one insn or 13519 the insn pattern doesn't describe well what exactly happens to 13520 dwarf2cfi.c. 13521 13522 PR target/93594 13523 * config/i386/predicates.md (avx_identity_operand): Remove. 13524 * config/i386/sse.md (*avx_vec_concat<mode>_1): Remove. 13525 (avx_<castmode><avxsizesuffix>_<castmode>, 13526 avx512f_<castmode><avxsizesuffix>_256<castmode>): Change patterns to 13527 a VEC_CONCAT of the operand and UNSPEC_CAST. 13528 (avx512f_<castmode><avxsizesuffix>_<castmode>): Change pattern to 13529 a VEC_CONCAT of VEC_CONCAT of the operand and UNSPEC_CAST with 13530 UNSPEC_CAST. 13531 13532 PR target/93611 13533 * config/i386/i386.c (ix86_lea_outperforms): Make sure to clear 13534 recog_data.insn if distance_non_agu_define changed it. 13535 135362020-02-06 Michael Meissner <meissner@linux.ibm.com> 13537 13538 PR target/93569 13539 * config/rs6000/rs6000.c (reg_to_non_prefixed): Before ISA 3.0 13540 we only had X-FORM (reg+reg) addressing for vectors. Also before 13541 ISA 3.0, we only had X-FORM addressing for scalars in the 13542 traditional Altivec registers. 13543 135442020-02-06 <zhongyunde@huawei.com> 13545 Vladimir Makarov <vmakarov@redhat.com> 13546 13547 PR rtl-optimization/93561 13548 * lra-assigns.c (spill_for): Check that tested hard regno is not out of 13549 hard register range. 13550 135512020-02-06 Richard Sandiford <richard.sandiford@arm.com> 13552 13553 * config/aarch64/aarch64.md (aarch64_movk<mode>): Add a type 13554 attribute. 13555 135562020-02-06 Segher Boessenkool <segher@kernel.crashing.org> 13557 13558 * config/rs6000/rs6000.c (rs6000_emit_set_long_const): Handle the case 13559 where the low and the high 32 bits are equal to each other specially, 13560 with an rldimi instruction. 13561 135622020-02-06 Mihail Ionescu <mihail.ionescu@arm.com> 13563 13564 * config/arm/arm-cpus.in: Set profile M for armv8.1-m.main. 13565 135662020-02-06 Mihail Ionescu <mihail.ionescu@arm.com> 13567 13568 * config/arm/arm-tables.opt: Regenerate. 13569 135702020-02-06 Richard Sandiford <richard.sandiford@arm.com> 13571 13572 PR target/87763 13573 * config/aarch64/aarch64-protos.h (aarch64_movk_shift): Declare. 13574 * config/aarch64/aarch64.c (aarch64_movk_shift): New function. 13575 * config/aarch64/aarch64.md (aarch64_movk<mode>): New pattern. 13576 135772020-02-06 Richard Sandiford <richard.sandiford@arm.com> 13578 13579 PR rtl-optimization/87763 13580 * config/aarch64/aarch64.md (*ashiftsi_extvdi_bfiz): New pattern. 13581 135822020-02-06 Delia Burduv <delia.burduv@arm.com> 13583 13584 * config/aarch64/aarch64-simd-builtins.def 13585 (bfmlaq): New built-in function. 13586 (bfmlalb): New built-in function. 13587 (bfmlalt): New built-in function. 13588 (bfmlalb_lane): New built-in function. 13589 (bfmlalt_lane): New built-in function. 13590 * config/aarch64/aarch64-simd.md 13591 (aarch64_bfmmlaqv4sf): New pattern. 13592 (aarch64_bfmlal<bt>v4sf): New pattern. 13593 (aarch64_bfmlal<bt>_lane<q>v4sf): New pattern. 13594 * config/aarch64/arm_neon.h (vbfmmlaq_f32): New intrinsic. 13595 (vbfmlalbq_f32): New intrinsic. 13596 (vbfmlaltq_f32): New intrinsic. 13597 (vbfmlalbq_lane_f32): New intrinsic. 13598 (vbfmlaltq_lane_f32): New intrinsic. 13599 (vbfmlalbq_laneq_f32): New intrinsic. 13600 (vbfmlaltq_laneq_f32): New intrinsic. 13601 * config/aarch64/iterators.md (BF_MLA): New int iterator. 13602 (bt): New int attribute. 13603 136042020-02-06 Uroš Bizjak <ubizjak@gmail.com> 13605 13606 * config/i386/i386.md (*pushtf): Emit "#" instead of 13607 calling gcc_unreachable in insn output. 13608 (*pushxf): Ditto. 13609 (*pushdf): Ditto. 13610 (*pushsf_rex64): Ditto for alternatives other than 1. 13611 (*pushsf): Ditto for alternatives other than 1. 13612 136132020-02-06 Martin Liska <mliska@suse.cz> 13614 13615 PR gcov-profile/91971 13616 PR gcov-profile/93466 13617 * coverage.c (coverage_init): Revert mangling of 13618 path into filename. It can lead to huge filename length. 13619 Creation of subfolders seem more natural. 13620 136212020-02-06 Stam Markianos-Wright <stam.markianos-wright@arm.com> 13622 13623 PR target/93300 13624 * config/arm/arm.c (arm_block_arith_comp_libfuncs_for_mode): New. 13625 (arm_init_libfuncs): Add BFmode support to block spurious BF libfuncs. 13626 Use arm_block_arith_comp_libfuncs_for_mode for HFmode. 13627 136282020-02-06 Jakub Jelinek <jakub@redhat.com> 13629 13630 PR target/93594 13631 * config/i386/predicates.md (avx_identity_operand): New predicate. 13632 * config/i386/sse.md (*avx_vec_concat<mode>_1): New 13633 define_insn_and_split. 13634 13635 PR libgomp/93515 13636 * omp-low.c (use_pointer_for_field): For nested constructs, also 13637 look for map clauses on target construct. 13638 (scan_omp_1_stmt) <case GIMPLE_OMP_TARGET>: Bump temporarily 13639 taskreg_nesting_level. 13640 13641 PR libgomp/93515 13642 * gimplify.c (gimplify_scan_omp_clauses) <do_notice>: If adding 13643 shared clause, call omp_notice_variable on outer context if any. 13644 136452020-02-05 Jason Merrill <jason@redhat.com> 13646 13647 PR c++/92003 13648 * symtab.c (symtab_node::nonzero_address): A DECL_COMDAT decl has 13649 non-zero address even if weak and not yet defined. 13650 136512020-02-05 Martin Sebor <msebor@redhat.com> 13652 13653 PR tree-optimization/92765 13654 * gimple-fold.c (get_range_strlen_tree): Handle MEM_REF and PARM_DECL. 13655 * tree-ssa-strlen.c (compute_string_length): Remove. 13656 (determine_min_objsize): Remove. 13657 (get_len_or_size): Add an argument. Call get_range_strlen_dynamic. 13658 Avoid using type size as the upper bound on string length. 13659 (handle_builtin_string_cmp): Add an argument. Adjust. 13660 (strlen_check_and_optimize_call): Pass additional argument to 13661 handle_builtin_string_cmp. 13662 136632020-02-05 Uroš Bizjak <ubizjak@gmail.com> 13664 13665 * config/i386/i386.md (*pushdi2_rex64 peephole2): Remove. 13666 (*pushdi2_rex64 peephole2): Unconditionally split after 13667 epilogue_completed. 13668 (*ashl<mode>3_doubleword): Ditto. 13669 (*<shift_insn><mode>3_doubleword): Ditto. 13670 136712020-02-05 Michael Meissner <meissner@linux.ibm.com> 13672 13673 PR target/93568 13674 * config/rs6000/rs6000.c (get_vector_offset): Fix 13675 136762020-02-05 Andrew Stubbs <ams@codesourcery.com> 13677 13678 * config/gcn/t-gcn-hsa (MULTILIB_OPTIONS): Use / not space. 13679 136802020-02-05 David Malcolm <dmalcolm@redhat.com> 13681 13682 * doc/analyzer.texi 13683 (Special Functions for Debugging the Analyzer): Update description 13684 of __analyzer_dump_exploded_nodes. 13685 136862020-02-05 Jakub Jelinek <jakub@redhat.com> 13687 13688 PR target/92190 13689 * config/i386/i386-features.c (ix86_add_reg_usage_to_vzeroupper): Only 13690 include sets and not clobbers in the vzeroupper pattern. 13691 * config/i386/sse.md (*avx_vzeroupper): Require in insn condition that 13692 the parallel has 17 (64-bit) or 9 (32-bit) elts. 13693 (*avx_vzeroupper_1): New define_insn_and_split. 13694 13695 PR target/92190 13696 * recog.c (pass_split_after_reload::gate): For STACK_REGS targets, 13697 don't run when !optimize. 13698 (pass_split_before_regstack::gate): For STACK_REGS targets, run even 13699 when !optimize. 13700 137012020-02-05 Richard Biener <rguenther@suse.de> 13702 13703 PR middle-end/90648 13704 * genmatch.c (dt_node::gen_kids_1): Emit number of argument 13705 checks before matching calls. 13706 137072020-02-05 Jakub Jelinek <jakub@redhat.com> 13708 13709 * tree-ssa-alias.c (aliasing_matching_component_refs_p): Fix up 13710 function comment typo. 13711 13712 PR middle-end/93555 13713 * omp-simd-clone.c (expand_simd_clones): If simd_clone_mangle or 13714 simd_clone_create failed when i == 0, adjust clone->nargs by 13715 clone->inbranch. 13716 137172020-02-05 Martin Liska <mliska@suse.cz> 13718 13719 PR c++/92717 13720 * doc/invoke.texi: Document that one should 13721 not combine ASLR and -fpch. 13722 137232020-02-04 Richard Biener <rguenther@suse.de> 13724 13725 PR tree-optimization/93538 13726 * match.pd (addr EQ/NE ptr): Amend to handle &ptr->x EQ/NE ptr. 13727 137282020-02-04 Richard Biener <rguenther@suse.de> 13729 13730 PR tree-optimization/91123 13731 * tree-ssa-sccvn.c (vn_walk_cb_data::finish): New method. 13732 (vn_walk_cb_data::last_vuse): New member. 13733 (vn_walk_cb_data::saved_operands): Likewsie. 13734 (vn_walk_cb_data::~vn_walk_cb_data): Release saved_operands. 13735 (vn_walk_cb_data::push_partial_def): Use finish. 13736 (vn_reference_lookup_2): Update last_vuse and use finish if 13737 we've saved operands. 13738 (vn_reference_lookup_3): Use finish and update calls to 13739 push_partial_defs everywhere. When translating through 13740 memcpy or aggregate copies save off operands and alias-set. 13741 (eliminate_dom_walker::eliminate_stmt): Restore VN_WALKREWRITE 13742 operation for redundant store removal. 13743 137442020-02-04 Richard Biener <rguenther@suse.de> 13745 13746 PR tree-optimization/92819 13747 * tree-ssa-forwprop.c (simplify_vector_constructor): Avoid 13748 generating more stmts than before. 13749 137502020-02-04 Martin Liska <mliska@suse.cz> 13751 13752 * config/arm/arm.c (arm_gen_far_branch): Move the function 13753 outside of selftests. 13754 137552020-02-03 Michael Meissner <meissner@linux.ibm.com> 13756 13757 * config/rs6000/rs6000.c (adjust_vec_address_pcrel): New helper 13758 function to adjust PC-relative vector addresses. 13759 (rs6000_adjust_vec_address): Call adjust_vec_address_pcrel to 13760 handle vectors with PC-relative addresses. 13761 137622020-02-03 Michael Meissner <meissner@linux.ibm.com> 13763 13764 * config/rs6000/rs6000.c (reg_to_non_prefixed): Add forward 13765 reference. 13766 (hard_reg_and_mode_to_addr_mask): Delete. 13767 (rs6000_adjust_vec_address): If the original vector address 13768 was REG+REG or REG+OFFSET and the element is not zero, do the add 13769 of the elements in the original address before adding the offset 13770 for the vector element. Use address_to_insn_form to validate the 13771 address using the register being loaded, rather than guessing 13772 whether the address is a DS-FORM or DQ-FORM address. 13773 137742020-02-03 Michael Meissner <meissner@linux.ibm.com> 13775 13776 * config/rs6000/rs6000.c (get_vector_offset): New helper function 13777 to calculate the offset in memory from the start of a vector of a 13778 particular element. Add code to keep the element number in 13779 bounds if the element number is variable. 13780 (rs6000_adjust_vec_address): Move calculation of offset of the 13781 vector element to get_vector_offset. 13782 (rs6000_split_vec_extract_var): Do not do the initial AND of 13783 element here, move the code to get_vector_offset. 13784 137852020-02-03 Michael Meissner <meissner@linux.ibm.com> 13786 13787 * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add some 13788 gcc_asserts. 13789 137902020-02-03 Segher Boessenkool <segher@kernel.crashing.org> 13791 13792 * config/rs6000/constraints.md: Improve documentation. 13793 137942020-02-03 Richard Earnshaw <rearnsha@arm.com> 13795 13796 PR target/93548 13797 * config/arm/t-arm: ($(srcdir)/config/arm/arm-tune.md) 13798 ($(srcdir)/config/arm/arm-tables.opt): Use move-if-change. 13799 138002020-02-03 Andrew Stubbs <ams@codesourcery.com> 13801 13802 * config.gcc: Remove "carrizo" support. 13803 * config/gcn/gcn-opts.h (processor_type): Likewise. 13804 * config/gcn/gcn.c (gcn_omp_device_kind_arch_isa): Likewise. 13805 * config/gcn/gcn.opt (gpu_type): Likewise. 13806 * config/gcn/t-omp-device: Likewise. 13807 138082020-02-03 Stam Markianos-Wright <stam.markianos-wright@arm.com> 13809 13810 PR target/91816 13811 * config/arm/arm-protos.h: New function arm_gen_far_branch prototype. 13812 * config/arm/arm.c (arm_gen_far_branch): New function 13813 arm_gen_far_branch. 13814 * config/arm/arm.md: Update b<cond> for Thumb2 range checks. 13815 138162020-02-03 Julian Brown <julian@codesourcery.com> 13817 Tobias Burnus <tobias@codesourcery.com> 13818 13819 * doc/invoke.texi: Update mention of OpenACC version to 2.6. 13820 138212020-02-03 Jakub Jelinek <jakub@redhat.com> 13822 13823 PR target/93533 13824 * config/s390/s390.md (popcounthi2_z196): Fix up expander to emit 13825 valid RTL to sum up the lowest and second lowest bytes of the popcnt 13826 result. 13827 138282020-02-02 Vladimir Makarov <vmakarov@redhat.com> 13829 13830 PR rtl-optimization/91333 13831 * ira-color.c (struct allocno_color_data): Add member 13832 hard_reg_prefs. 13833 (init_allocno_threads): Set the member up. 13834 (bucket_allocno_compare_func): Add compare hard reg 13835 prefs. 13836 138372020-01-31 Sandra Loosemore <sandra@codesourcery.com> 13838 13839 nios2: Support for GOT-relative DW_EH_PE_datarel encoding. 13840 13841 * configure.ac [nios2-*-*]: Check HAVE_AS_NIOS2_GOTOFF_RELOCATION. 13842 * config.in: Regenerated. 13843 * configure: Regenerated. 13844 * config/nios2/nios2.h (ASM_PREFERRED_EH_DATA_FORMAT): Fix handling 13845 for PIC when HAVE_AS_NIOS2_GOTOFF_RELOCATION. 13846 (ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX): New. 13847 138482020-02-01 Andrew Burgess <andrew.burgess@embecosm.com> 13849 13850 * configure: Regenerate. 13851 138522020-01-31 Vladimir Makarov <vmakarov@redhat.com> 13853 13854 PR rtl-optimization/91333 13855 * ira-color.c (bucket_allocno_compare_func): Move conflict hard 13856 reg preferences comparison up. 13857 138582020-01-31 Richard Sandiford <richard.sandiford@arm.com> 13859 13860 * config/aarch64/aarch64.h (TARGET_SVE_BF16): New macro. 13861 * config/aarch64/aarch64-sve-builtins-sve2.h (svcvtnt): Move to 13862 aarch64-sve-builtins-base.h. 13863 * config/aarch64/aarch64-sve-builtins-sve2.cc (svcvtnt): Move to 13864 aarch64-sve-builtins-base.cc. 13865 * config/aarch64/aarch64-sve-builtins-base.h (svbfdot, svbfdot_lane) 13866 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla) 13867 (svcvtnt): Declare. 13868 * config/aarch64/aarch64-sve-builtins-base.cc (svbfdot, svbfdot_lane) 13869 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla) 13870 (svcvtnt): New functions. 13871 * config/aarch64/aarch64-sve-builtins-base.def (svbfdot, svbfdot_lane) 13872 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla) 13873 (svcvtnt): New functions. 13874 (svcvt): Add a form that converts f32 to bf16. 13875 * config/aarch64/aarch64-sve-builtins-shapes.h (ternary_bfloat) 13876 (ternary_bfloat_lane, ternary_bfloat_lanex2, ternary_bfloat_opt_n): 13877 Declare. 13878 * config/aarch64/aarch64-sve-builtins-shapes.cc (parse_element_type): 13879 Treat B as bfloat16_t. 13880 (ternary_bfloat_lane_base): New class. 13881 (ternary_bfloat_def): Likewise. 13882 (ternary_bfloat): New shape. 13883 (ternary_bfloat_lane_def): New class. 13884 (ternary_bfloat_lane): New shape. 13885 (ternary_bfloat_lanex2_def): New class. 13886 (ternary_bfloat_lanex2): New shape. 13887 (ternary_bfloat_opt_n_def): New class. 13888 (ternary_bfloat_opt_n): New shape. 13889 * config/aarch64/aarch64-sve-builtins.cc (TYPES_cvt_bfloat): New macro. 13890 * config/aarch64/aarch64-sve.md (@aarch64_sve_<sve_fp_op>vnx4sf) 13891 (@aarch64_sve_<sve_fp_op>_lanevnx4sf): New patterns. 13892 (@aarch64_sve_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>) 13893 (@cond_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>): Likewise. 13894 (*cond_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>): Likewise. 13895 (@aarch64_sve_cvtnt<VNx8BF_ONLY:mode>): Likewise. 13896 * config/aarch64/aarch64-sve2.md (@aarch64_sve2_cvtnt<mode>): Key 13897 the pattern off the narrow mode instead of the wider one. 13898 * config/aarch64/iterators.md (VNx8BF_ONLY): New mode iterator. 13899 (UNSPEC_BFMLALB, UNSPEC_BFMLALT, UNSPEC_BFMMLA): New unspecs. 13900 (sve_fp_op): Handle them. 13901 (SVE_BFLOAT_TERNARY_LONG): New int itertor. 13902 (SVE_BFLOAT_TERNARY_LONG_LANE): Likewise. 13903 139042020-01-31 Richard Sandiford <richard.sandiford@arm.com> 13905 13906 * config/aarch64/arm_sve.h: Include arm_bf16.h. 13907 * config/aarch64/aarch64-modes.def (BF): Move definition before 13908 VECTOR_MODES. Remove separate VECTOR_MODES for V4BF and V8BF. 13909 (SVE_MODES): Handle BF modes. 13910 * config/aarch64/aarch64.c (aarch64_classify_vector_mode): Handle 13911 BF modes. 13912 (aarch64_full_sve_mode): Likewise. 13913 * config/aarch64/iterators.md (SVE_STRUCT): Add VNx16BF, VNx24BF 13914 and VNx32BF. 13915 (SVE_FULL, SVE_FULL_HSD, SVE_ALL): Add VNx8BF. 13916 (Vetype, Vesize, Vctype, VEL, Vel, VEL_INT, V128, v128, vwcore) 13917 (V_INT_EQUIV, v_int_equiv, V_FP_EQUIV, v_fp_equiv, vector_count) 13918 (insn_length, VSINGLE, vsingle, VPRED, vpred, VDOUBLE): Handle the 13919 new SVE BF modes. 13920 * config/aarch64/aarch64-sve-builtins.h (TYPE_bfloat): New 13921 type_class_index. 13922 * config/aarch64/aarch64-sve-builtins.cc (TYPES_all_arith): New macro. 13923 (TYPES_all_data): Add bf16. 13924 (TYPES_reinterpret1, TYPES_reinterpret): Likewise. 13925 (register_tuple_type): Increase buffer size. 13926 * config/aarch64/aarch64-sve-builtins.def (svbfloat16_t): New type. 13927 (bf16): New type suffix. 13928 * config/aarch64/aarch64-sve-builtins-base.def (svabd, svadd, svaddv) 13929 (svcmpeq, svcmpge, svcmpgt, svcmple, svcmplt, svcmpne, svmad, svmax) 13930 (svmaxv, svmin, svminv, svmla, svmls, svmsb, svmul, svsub, svsubr): 13931 Change type from all_data to all_arith. 13932 * config/aarch64/aarch64-sve-builtins-sve2.def (svaddp, svmaxp) 13933 (svminp): Likewise. 13934 139352020-01-31 Dennis Zhang <dennis.zhang@arm.com> 13936 Matthew Malcomson <matthew.malcomson@arm.com> 13937 Richard Sandiford <richard.sandiford@arm.com> 13938 13939 * doc/invoke.texi (f32mm): Document new AArch64 -march= extension. 13940 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define 13941 __ARM_FEATURE_SVE_MATMUL_INT8, __ARM_FEATURE_SVE_MATMUL_FP32 and 13942 __ARM_FEATURE_SVE_MATMUL_FP64 as appropriate. Don't define 13943 __ARM_FEATURE_MATMUL_FP64. 13944 * config/aarch64/aarch64-option-extensions.def (fp, simd, fp16) 13945 (sve): Add AARCH64_FL_F32MM to the list of extensions that should 13946 be disabled at the same time. 13947 (f32mm): New extension. 13948 * config/aarch64/aarch64.h (AARCH64_FL_F32MM): New macro. 13949 (AARCH64_FL_F64MM): Bump to the next bit up. 13950 (AARCH64_ISA_F32MM, TARGET_SVE_I8MM, TARGET_F32MM, TARGET_SVE_F32MM) 13951 (TARGET_SVE_F64MM): New macros. 13952 * config/aarch64/iterators.md (SVE_MATMULF): New mode iterator. 13953 (UNSPEC_FMMLA, UNSPEC_SMATMUL, UNSPEC_UMATMUL, UNSPEC_USMATMUL) 13954 (UNSPEC_TRN1Q, UNSPEC_TRN2Q, UNSPEC_UZP1Q, UNSPEC_UZP2Q, UNSPEC_ZIP1Q) 13955 (UNSPEC_ZIP2Q): New unspeccs. 13956 (DOTPROD_US_ONLY, PERMUTEQ, MATMUL, FMMLA): New int iterators. 13957 (optab, sur, perm_insn): Handle the new unspecs. 13958 (sve_fp_op): Handle UNSPEC_FMMLA. Resort. 13959 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): Use 13960 TARGET_SVE_F64MM instead of separate tests. 13961 (@aarch64_<DOTPROD_US_ONLY:sur>dot_prod<vsi2qi>): New pattern. 13962 (@aarch64_<DOTPROD_US_ONLY:sur>dot_prod_lane<vsi2qi>): Likewise. 13963 (@aarch64_sve_add_<MATMUL:optab><vsi2qi>): Likewise. 13964 (@aarch64_sve_<FMMLA:sve_fp_op><mode>): Likewise. 13965 (@aarch64_sve_<PERMUTEQ:optab><mode>): Likewise. 13966 * config/aarch64/aarch64-sve-builtins.cc (TYPES_s_float): New macro. 13967 (TYPES_s_float_hsd_integer, TYPES_s_float_sd_integer): Use it. 13968 (TYPES_s_signed): New macro. 13969 (TYPES_s_integer): Use it. 13970 (TYPES_d_float): New macro. 13971 (TYPES_d_data): Use it. 13972 * config/aarch64/aarch64-sve-builtins-shapes.h (mmla): Declare. 13973 (ternary_intq_uintq_lane, ternary_intq_uintq_opt_n, ternary_uintq_intq) 13974 (ternary_uintq_intq_lane, ternary_uintq_intq_opt_n): Likewise. 13975 * config/aarch64/aarch64-sve-builtins-shapes.cc (mmla_def): New class. 13976 (svmmla): New shape. 13977 (ternary_resize2_opt_n_base): Add TYPE_CLASS2 and TYPE_CLASS3 13978 template parameters. 13979 (ternary_resize2_lane_base): Likewise. 13980 (ternary_resize2_base): New class. 13981 (ternary_qq_lane_base): Likewise. 13982 (ternary_intq_uintq_lane_def): Likewise. 13983 (ternary_intq_uintq_lane): New shape. 13984 (ternary_intq_uintq_opt_n_def): New class 13985 (ternary_intq_uintq_opt_n): New shape. 13986 (ternary_qq_lane_def): Inherit from ternary_qq_lane_base. 13987 (ternary_uintq_intq_def): New class. 13988 (ternary_uintq_intq): New shape. 13989 (ternary_uintq_intq_lane_def): New class. 13990 (ternary_uintq_intq_lane): New shape. 13991 (ternary_uintq_intq_opt_n_def): New class. 13992 (ternary_uintq_intq_opt_n): New shape. 13993 * config/aarch64/aarch64-sve-builtins-base.h (svmmla, svsudot) 13994 (svsudot_lane, svtrn1q, svtrn2q, svusdot, svusdot_lane, svusmmla) 13995 (svuzp1q, svuzp2q, svzip1q, svzip2q): Declare. 13996 * config/aarch64/aarch64-sve-builtins-base.cc (svdot_lane_impl): 13997 Generalize to... 13998 (svdotprod_lane_impl): ...this new class. 13999 (svmmla_impl, svusdot_impl): New classes. 14000 (svdot_lane): Update to use svdotprod_lane_impl. 14001 (svmmla, svsudot, svsudot_lane, svtrn1q, svtrn2q, svusdot) 14002 (svusdot_lane, svusmmla, svuzp1q, svuzp2q, svzip1q, svzip2q): New 14003 functions. 14004 * config/aarch64/aarch64-sve-builtins-base.def (svmmla): New base 14005 function, with no types defined. 14006 (svmmla, svusmmla, svsudot, svsudot_lane, svusdot, svusdot_lane): New 14007 AARCH64_FL_I8MM functions. 14008 (svmmla): New AARCH64_FL_F32MM function. 14009 (svld1ro): Depend only on AARCH64_FL_F64MM, not on AARCH64_FL_V8_6. 14010 (svmmla, svtrn1q, svtrn2q, svuz1q, svuz2q, svzip1q, svzip2q): New 14011 AARCH64_FL_F64MM function. 14012 (REQUIRED_EXTENSIONS): 14013 140142020-01-31 Andrew Stubbs <ams@codesourcery.com> 14015 14016 * config/gcn/gcn-valu.md (addv64di3_exec): Allow one '0' in each 14017 alternative only. 14018 140192020-01-31 Uroš Bizjak <ubizjak@gmail.com> 14020 14021 * config/i386/i386.md (*movoi_internal_avx): Do not check for 14022 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL. Remove MODE_V8SF handling. 14023 (*movti_internal): Do not check for 14024 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL. 14025 (*movtf_internal): Move check for TARGET_SSE2 and size optimization 14026 just after check for TARGET_AVX. 14027 (*movdf_internal): Ditto. 14028 * config/i386/mmx.md (*mov<mode>_internal): Do not check for 14029 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL. 14030 * config/i386/sse.md (mov<mode>_internal): Only check 14031 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL with V2DFmode. Move check 14032 for TARGET_SSE2 and size optimization just after check for TARGET_AVX. 14033 (<sse>_andnot<mode>3<mask_name>): Move check for 14034 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL after check for TARGET_AVX. 14035 (<code><mode>3<mask_name>): Ditto. 14036 (*andnot<mode>3): Ditto. 14037 (*andnottf3): Ditto. 14038 (*<code><mode>3): Ditto. 14039 (*<code>tf3): Ditto. 14040 (*andnot<VI:mode>3): Remove 14041 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL handling. 14042 (<mask_codefor><code><VI48_AVX_AVX512F:mode>3<mask_name>): Ditto. 14043 (*<code><VI12_AVX_AVX512F:mode>3): Ditto. 14044 (sse4_1_blendv<ssemodesuffix>): Ditto. 14045 * config/i386/x86-tune.def (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL): 14046 Explain that tune applies to 128bit instructions only. 14047 140482020-01-31 Kwok Cheung Yeung <kcy@codesourcery.com> 14049 14050 * config/gcn/mkoffload.c (process_asm): Add sgpr_count and vgpr_count 14051 to definition of hsa_kernel_description. Parse assembly to find SGPR 14052 and VGPR count of kernel and store in hsa_kernel_description. 14053 140542020-01-31 Tamar Christina <tamar.christina@arm.com> 14055 14056 PR rtl-optimization/91838 14057 * simplify-rtx.c (simplify_binary_operation_1): Update LSHIFTRT case 14058 to truncate if allowed or reject combination. 14059 140602020-01-31 Andrew Stubbs <ams@codesourcery.com> 14061 14062 * tree-ssa-loop-ivopts.c (get_iv): Use sizetype for zero-step. 14063 (find_inv_vars_cb): Likewise. 14064 140652020-01-31 David Malcolm <dmalcolm@redhat.com> 14066 14067 * calls.c (special_function_p): Split out the check for DECL_NAME 14068 being non-NULL and fndecl being extern at file scope into a 14069 new maybe_special_function_p and call it. Drop check for fndecl 14070 being non-NULL that was after a usage of DECL_NAME (fndecl). 14071 * tree.h (maybe_special_function_p): New inline function. 14072 140732020-01-30 Andrew Stubbs <ams@codesourcery.com> 14074 14075 * config/gcn/gcn-valu.md (gather<mode>_exec): Move contents ... 14076 (mask_gather_load<mode>): ... here, and zero-initialize the 14077 destination. 14078 (maskload<mode>di): Zero-initialize the destination. 14079 * config/gcn/gcn.c: 14080 140812020-01-30 David Malcolm <dmalcolm@redhat.com> 14082 14083 PR analyzer/93356 14084 * doc/analyzer.texi (Limitations): Note that constraints on 14085 floating-point values are currently ignored. 14086 140872020-01-30 Jakub Jelinek <jakub@redhat.com> 14088 14089 PR lto/93384 14090 * symtab.c (symtab_node::noninterposable_alias): If localalias 14091 already exists, but is not usable, append numbers after it until 14092 a unique name is found. Formatting fix. 14093 14094 PR middle-end/93505 14095 * combine.c (simplify_comparison) <case ROTATE>: Punt on out of range 14096 rotate counts. 14097 140982020-01-30 Andrew Stubbs <ams@codesourcery.com> 14099 14100 * config/gcn/gcn.c (print_operand): Handle LTGT. 14101 * config/gcn/predicates.md (gcn_fp_compare_operator): Allow ltgt. 14102 141032020-01-30 Richard Biener <rguenther@suse.de> 14104 14105 * tree-pretty-print.c (dump_generic_node): Wrap VECTOR_CST 14106 and CONSTRUCTOR in _Literal (type) with TDF_GIMPLE. 14107 141082020-01-30 John David Anglin <danglin@gcc.gnu.org> 14109 14110 * config/pa/pa.c (pa_elf_select_rtx_section): Place function pointers 14111 without a DECL in .data.rel.ro.local. 14112 141132020-01-30 Jakub Jelinek <jakub@redhat.com> 14114 14115 PR target/93494 14116 * config/arm/arm.md (uaddvdi4): Actually emit what gen_uaddvsi4 14117 returned. 14118 14119 PR target/91824 14120 * config/i386/sse.md 14121 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext): Renamed to ... 14122 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext): ... this. Use 14123 any_extend code iterator instead of always zero_extend. 14124 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext_lt): Renamed to ... 14125 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_lt): ... this. 14126 Use any_extend code iterator instead of always zero_extend. 14127 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext_shift): Renamed to ... 14128 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_shift): ... this. 14129 Use any_extend code iterator instead of always zero_extend. 14130 (*sse2_pmovmskb_ext): New define_insn. 14131 (*sse2_pmovmskb_ext_lt): New define_insn_and_split. 14132 14133 PR target/91824 14134 * config/i386/i386.md (*popcountsi2_zext): New define_insn_and_split. 14135 (*popcountsi2_zext_falsedep): New define_insn. 14136 141372020-01-30 Dragan Mladjenovic <dmladjenovic@wavecomp.com> 14138 14139 * config.in: Regenerated. 14140 * configure: Regenerated. 14141 141422020-01-29 Tobias Burnus <tobias@codesourcery.com> 14143 14144 PR bootstrap/93409 14145 * config/gcn/gcn-hsa.h (ASM_SPEC): Add -mattr=-code-object-v3 as 14146 LLVM's assembler changed the default in version 9. 14147 141482020-01-24 Jeff Law <law@redhat.com> 14149 14150 PR tree-optimization/89689 14151 * builtins.def (BUILT_IN_OBJECT_SIZE): Make it const rather than pure. 14152 141532020-01-29 Richard Sandiford <richard.sandiford@arm.com> 14154 14155 Revert: 14156 14157 2020-01-28 Richard Sandiford <richard.sandiford@arm.com> 14158 14159 PR rtl-optimization/87763 14160 * simplify-rtx.c (simplify_truncation): Extend sign/zero_extract 14161 simplification to handle subregs as well as bare regs. 14162 * config/i386/i386.md (*testqi_ext_3): Match QI extracts too. 14163 141642020-01-29 Joel Hutton <Joel.Hutton@arm.com> 14165 14166 PR target/93221 14167 * ira.c (ira): Revert use of simplified LRA algorithm. 14168 141692020-01-29 Martin Jambor <mjambor@suse.cz> 14170 14171 PR tree-optimization/92706 14172 * tree-sra.c (struct access): Fields first_link, last_link, 14173 next_queued and grp_queued renamed to first_rhs_link, last_rhs_link, 14174 next_rhs_queued and grp_rhs_queued respectively, new fields 14175 first_lhs_link, last_lhs_link, next_lhs_queued and grp_lhs_queued. 14176 (struct assign_link): Field next renamed to next_rhs, new field 14177 next_lhs. Updated comment. 14178 (work_queue_head): Renamed to rhs_work_queue_head. 14179 (lhs_work_queue_head): New variable. 14180 (add_link_to_lhs): New function. 14181 (relink_to_new_repr): Also relink LHS lists. 14182 (add_access_to_work_queue): Renamed to add_access_to_rhs_work_queue. 14183 (add_access_to_lhs_work_queue): New function. 14184 (pop_access_from_work_queue): Renamed to 14185 pop_access_from_rhs_work_queue. 14186 (pop_access_from_lhs_work_queue): New function. 14187 (build_accesses_from_assign): Also add links to LHS lists and to LHS 14188 work_queue. 14189 (child_would_conflict_in_lacc): Renamed to 14190 child_would_conflict_in_acc. Adjusted parameter names. 14191 (create_artificial_child_access): New parameter set_grp_read, use it. 14192 (subtree_mark_written_and_enqueue): Renamed to 14193 subtree_mark_written_and_rhs_enqueue. 14194 (propagate_subaccesses_across_link): Renamed to 14195 propagate_subaccesses_from_rhs. 14196 (propagate_subaccesses_from_lhs): New function. 14197 (propagate_all_subaccesses): Also propagate subaccesses from LHSs to 14198 RHSs. 14199 142002020-01-29 Martin Jambor <mjambor@suse.cz> 14201 14202 PR tree-optimization/92706 14203 * tree-sra.c (struct access): Adjust comment of 14204 grp_total_scalarization. 14205 (find_access_in_subtree): Look for single children spanning an entire 14206 access. 14207 (scalarizable_type_p): Allow register accesses, adjust callers. 14208 (completely_scalarize): Remove function. 14209 (scalarize_elem): Likewise. 14210 (create_total_scalarization_access): Likewise. 14211 (sort_and_splice_var_accesses): Do not track total scalarization 14212 flags. 14213 (analyze_access_subtree): New parameter totally, adjust to new meaning 14214 of grp_total_scalarization. 14215 (analyze_access_trees): Pass new parameter to analyze_access_subtree. 14216 (can_totally_scalarize_forest_p): New function. 14217 (create_total_scalarization_access): Likewise. 14218 (create_total_access_and_reshape): Likewise. 14219 (total_should_skip_creating_access): Likewise. 14220 (totally_scalarize_subtree): Likewise. 14221 (analyze_all_variable_accesses): Perform total scalarization after 14222 subaccess propagation using the new functions above. 14223 (initialize_constant_pool_replacements): Output initializers by 14224 traversing the access tree. 14225 142262020-01-29 Martin Jambor <mjambor@suse.cz> 14227 14228 * tree-sra.c (verify_sra_access_forest): New function. 14229 (verify_all_sra_access_forests): Likewise. 14230 (create_artificial_child_access): Set parent. 14231 (analyze_all_variable_accesses): Call the verifier. 14232 142332020-01-28 Jan Hubicka <hubicka@ucw.cz> 14234 14235 * cgraph.c (cgraph_edge::resolve_speculation): Only lookup direct edge 14236 if called on indirect edge. 14237 (cgraph_edge::redirect_call_stmt_to_callee): Lookup indirect edge of 14238 speculative call if needed. 14239 142402020-01-29 Richard Biener <rguenther@suse.de> 14241 14242 PR tree-optimization/93428 14243 * tree-vect-slp.c (vect_build_slp_tree_2): Compute the load 14244 permutation when the load node is created. 14245 (vect_analyze_slp_instance): Re-use it here. 14246 142472020-01-28 Jan Hubicka <hubicka@ucw.cz> 14248 14249 * ipa-prop.c (update_indirect_edges_after_inlining): Fix warning. 14250 142512020-01-28 Vladimir Makarov <vmakarov@redhat.com> 14252 14253 PR rtl-optimization/93272 14254 * ira-lives.c (process_out_of_region_eh_regs): New function. 14255 (process_bb_node_lives): Call it. 14256 142572020-01-28 Jan Hubicka <hubicka@ucw.cz> 14258 14259 * coverage.c (read_counts_file): Make error message lowercase. 14260 142612020-01-28 Jan Hubicka <hubicka@ucw.cz> 14262 14263 * profile-count.c (profile_quality_display_names): Fix ordering. 14264 142652020-01-28 Jan Hubicka <hubicka@ucw.cz> 14266 14267 PR lto/93318 14268 * cgraph.c (cgraph_add_edge_to_call_site_hash): Update call site 14269 hash only when edge is first within the sequence. 14270 (cgraph_edge::set_call_stmt): Update handling of speculative calls. 14271 (symbol_table::create_edge): Do not set target_prob. 14272 (cgraph_edge::remove_caller): Watch for speculative calls when updating 14273 the call site hash. 14274 (cgraph_edge::make_speculative): Drop target_prob parameter. 14275 (cgraph_edge::speculative_call_info): Remove. 14276 (cgraph_edge::first_speculative_call_target): New member function. 14277 (update_call_stmt_hash_for_removing_direct_edge): New function. 14278 (cgraph_edge::resolve_speculation): Rewrite to new API. 14279 (cgraph_edge::speculative_call_for_target): New member function. 14280 (cgraph_edge::make_direct): Rewrite to new API; fix handling of 14281 multiple speculation targets. 14282 (cgraph_edge::redirect_call_stmt_to_callee): Likewise; fix updating 14283 of profile. 14284 (verify_speculative_call): Verify that targets form an interval. 14285 * cgraph.h (cgraph_edge::speculative_call_info): Remove. 14286 (cgraph_edge::first_speculative_call_target): New member function. 14287 (cgraph_edge::next_speculative_call_target): New member function. 14288 (cgraph_edge::speculative_call_target_ref): New member function. 14289 (cgraph_edge;:speculative_call_indirect_edge): New member funtion. 14290 (cgraph_edge): Remove target_prob. 14291 * cgraphclones.c (cgraph_node::set_call_stmt_including_clones): 14292 Fix handling of speculative calls. 14293 * ipa-devirt.c (ipa_devirt): Fix handling of speculative cals. 14294 * ipa-fnsummary.c (analyze_function_body): Likewise. 14295 * ipa-inline.c (speculation_useful_p): Use new speculative call API. 14296 * ipa-profile.c (dump_histogram): Fix formating. 14297 (ipa_profile_generate_summary): Watch for overflows. 14298 (ipa_profile): Do not require probablity to be 1/2; update to new API. 14299 * ipa-prop.c (ipa_make_edge_direct_to_target): Update to new API. 14300 (update_indirect_edges_after_inlining): Update to new API. 14301 * ipa-utils.c (ipa_merge_profiles): Rewrite merging of speculative call 14302 profiles. 14303 * profile-count.h: (profile_probability::adjusted): New. 14304 * tree-inline.c (copy_bb): Update to new speculative call API; fix 14305 updating of profile. 14306 * value-prof.c (gimple_ic_transform): Rename to ... 14307 (dump_ic_profile): ... this one; update dumping. 14308 (stream_in_histogram_value): Fix formating. 14309 (gimple_value_profile_transformations): Update. 14310 143112020-01-28 H.J. Lu <hongjiu.lu@intel.com> 14312 14313 PR target/91461 14314 * config/i386/i386.md (*movoi_internal_avx): Remove 14315 TARGET_SSE_TYPELESS_STORES check. 14316 (*movti_internal): Prefer TARGET_AVX over 14317 TARGET_SSE_TYPELESS_STORES. 14318 (*movtf_internal): Likewise. 14319 * config/i386/sse.md (mov<mode>_internal): Prefer TARGET_AVX over 14320 TARGET_SSE_TYPELESS_STORES. Remove "<MODE_SIZE> == 16" check 14321 from TARGET_SSE_TYPELESS_STORES. 14322 143232020-01-28 David Malcolm <dmalcolm@redhat.com> 14324 14325 * diagnostic-core.h (warning_at): Rename overload to... 14326 (warning_meta): ...this. 14327 (emit_diagnostic_valist): Delete decl of overload taking 14328 diagnostic_metadata. 14329 * diagnostic.c (emit_diagnostic_valist): Likewise for defn. 14330 (warning_at): Rename overload taking diagnostic_metadata to... 14331 (warning_meta): ...this. 14332 143332020-01-28 Richard Biener <rguenther@suse.de> 14334 14335 PR tree-optimization/93439 14336 * tree-parloops.c (create_loop_fn): Move clique bookkeeping... 14337 * tree-cfg.c (move_sese_region_to_fn): ... here. 14338 (verify_types_in_gimple_reference): Verify used cliques are 14339 tracked. 14340 143412020-01-28 H.J. Lu <hongjiu.lu@intel.com> 14342 14343 PR target/91399 14344 * config/i386/i386-options.c (set_ix86_tune_features): Add an 14345 argument of a pointer to struct gcc_options and pass it to 14346 parse_mtune_ctrl_str. 14347 (ix86_function_specific_restore): Pass opts to 14348 set_ix86_tune_features. 14349 (ix86_option_override_internal): Likewise. 14350 (parse_mtune_ctrl_str): Add an argument of a pointer to struct 14351 gcc_options and use it for x_ix86_tune_ctrl_string. 14352 143532020-01-28 Richard Sandiford <richard.sandiford@arm.com> 14354 14355 PR rtl-optimization/87763 14356 * simplify-rtx.c (simplify_truncation): Extend sign/zero_extract 14357 simplification to handle subregs as well as bare regs. 14358 * config/i386/i386.md (*testqi_ext_3): Match QI extracts too. 14359 143602020-01-28 Richard Sandiford <richard.sandiford@arm.com> 14361 14362 * tree-vect-loop.c (vectorizable_reduction): Fail gracefully 14363 for reduction chains that (now) include a call. 14364 143652020-01-28 Richard Sandiford <richard.sandiford@arm.com> 14366 14367 PR tree-optimization/92822 14368 * tree-ssa-forwprop.c (simplify_vector_constructor): When filling 14369 out the don't-care elements of a vector whose significant elements 14370 are duplicates, make the don't-care elements duplicates too. 14371 143722020-01-28 Richard Sandiford <richard.sandiford@arm.com> 14373 14374 PR tree-optimization/93434 14375 * tree-predcom.c (split_data_refs_to_components): Record which 14376 components have had aliasing loads removed. Prevent store-store 14377 commoning for all such components. 14378 143792020-01-28 Jakub Jelinek <jakub@redhat.com> 14380 14381 PR target/93418 14382 * config/i386/i386.c (ix86_fold_builtin) <do_shift>: If mask is not 14383 -1 or is_vshift is true, use new_vector with number of elts npatterns 14384 rather than new_unary_operation. 14385 14386 PR tree-optimization/93454 14387 * gimple-fold.c (fold_array_ctor_reference): Perform 14388 elt_size.to_uhwi () just once, instead of calling it in every 14389 iteration. Punt if that value is above size of the temporary 14390 buffer. Decrease third native_encode_expr argument when 14391 bufoff + elt_sz is above size of buf. 14392 143932020-01-27 Joseph Myers <joseph@codesourcery.com> 14394 14395 * config/mips/mips.c (mips_declare_object_name) 14396 [USE_GNU_UNIQUE_OBJECT]: Support use of gnu_unique_object. 14397 143982020-01-27 Martin Liska <mliska@suse.cz> 14399 14400 PR gcov-profile/93403 14401 * tree-profile.c (gimple_init_gcov_profiler): Generate 14402 both __gcov_indirect_call_profiler_v4 and 14403 __gcov_indirect_call_profiler_v4_atomic. 14404 144052020-01-27 Richard Sandiford <richard.sandiford@arm.com> 14406 14407 PR target/92822 14408 * config/aarch64/aarch64-simd.md (aarch64_get_half<mode>): New 14409 expander. 14410 (@aarch64_split_simd_mov<mode>): Use it. 14411 (aarch64_simd_mov_from_<mode>low): Add a GPR alternative. 14412 Leave the vec_extract patterns to handle 2-element vectors. 14413 (aarch64_simd_mov_from_<mode>high): Likewise. 14414 (vec_extract<VQMOV_NO2E:mode><Vhalf>): New expander. 14415 (vec_extractv2dfv1df): Likewise. 14416 144172020-01-27 Richard Sandiford <richard.sandiford@arm.com> 14418 14419 * config/aarch64/aarch64.c (aarch64_if_then_else_costs): Match 14420 jump conditions for *compare_condjump<GPI:mode>. 14421 144222020-01-27 David Malcolm <dmalcolm@redhat.com> 14423 14424 PR analyzer/93276 14425 * digraph.cc (test_edge::test_edge): Specify template for base 14426 class initializer. 14427 144282020-01-27 Claudiu Zissulescu <claziss@synopsys.com> 14429 14430 * config/arc/arc.c (arc_rtx_costs): Update mul64 cost. 14431 144322020-01-27 Claudiu Zissulescu <claziss@synopsys.com> 14433 14434 * config/arc/arc-protos.h (gen_mlo): Remove. 14435 (gen_mhi): Likewise. 14436 * config/arc/arc.c (AUX_MULHI): Define. 14437 (arc_must_save_reister): Special handling for r58/59. 14438 (arc_compute_frame_size): Consider mlo/mhi registers. 14439 (arc_save_callee_saves): Emit fp/sp move only when emit_move 14440 paramter is true. 14441 (arc_conditional_register_usage): Remove TARGET_BIG_ENDIAN from 14442 mlo/mhi name selection. 14443 (arc_restore_callee_saves): Don't early restore blink when ISR. 14444 (arc_expand_prologue): Add mlo/mhi saving. 14445 (arc_expand_epilogue): Add mlo/mhi restoring. 14446 (gen_mlo): Remove. 14447 (gen_mhi): Remove. 14448 * config/arc/arc.h (DBX_REGISTER_NUMBER): Correct register 14449 numbering when MUL64 option is used. 14450 (DWARF2_FRAME_REG_OUT): Define. 14451 * config/arc/arc.md (arc600_stall): New pattern. 14452 (VUNSPEC_ARC_ARC600_STALL): Define. 14453 (mulsi64): Use correct mlo/mhi registers. 14454 (mulsi_600): Clean it up. 14455 * config/arc/predicates.md (mlo_operand): Remove any dependency on 14456 TARGET_BIG_ENDIAN. 14457 (mhi_operand): Likewise. 14458 144592020-01-27 Claudiu Zissulescu <claziss@synopsys.com> 14460 Petro Karashchenko <petro.karashchenko@ring.com> 14461 14462 * config/arc/arc.c (arc_is_uncached_mem_p): Check struct 14463 attributes if needed. 14464 (prepare_move_operands): Generate special unspec instruction for 14465 direct access. 14466 (arc_isuncached_mem_p): Propagate uncached attribute to each 14467 structure member. 14468 * config/arc/arc.md (VUNSPEC_ARC_LDDI): Define. 14469 (VUNSPEC_ARC_STDI): Likewise. 14470 (ALLI): New mode iterator. 14471 (mALLI): New mode attribute. 14472 (lddi): New instruction pattern. 14473 (stdi): Likewise. 14474 (stdidi_split): Split instruction for architectures which are not 14475 supporting ll64 option. 14476 (lddidi_split): Likewise. 14477 144782020-01-27 Richard Sandiford <richard.sandiford@arm.com> 14479 14480 PR rtl-optimization/92989 14481 * lra-lives.c (process_bb_lives): Update the live-in set before 14482 processing additional clobbers. 14483 144842020-01-27 Richard Sandiford <richard.sandiford@arm.com> 14485 14486 PR rtl-optimization/93170 14487 * cselib.c (cselib_invalidate_regno_val): New function, split out 14488 from... 14489 (cselib_invalidate_regno): ...here. 14490 (cselib_invalidated_by_call_p): New function. 14491 (cselib_process_insn): Iterate over all the hard-register entries in 14492 REG_VALUES and invalidate any that cross call-clobbered registers. 14493 144942020-01-27 Richard Sandiford <richard.sandiford@arm.com> 14495 14496 * dojump.c (split_comparison): Use HONOR_NANS rather than 14497 HONOR_SNANS when splitting LTGT. 14498 144992020-01-27 Martin Liska <mliska@suse.cz> 14500 14501 PR driver/91220 14502 * opts.c (print_filtered_help): Exclude language-specific 14503 options from --help=common unless enabled in all FEs. 14504 145052020-01-27 Martin Liska <mliska@suse.cz> 14506 14507 * opts.c (print_help): Exclude params from 14508 all except --help=param. 14509 145102020-01-27 Martin Liska <mliska@suse.cz> 14511 14512 PR target/93274 14513 * config/i386/i386-features.c (make_resolver_func): 14514 Align the code with ppc64 target implementation. 14515 Do not generate a unique name for resolver function. 14516 145172020-01-27 Richard Biener <rguenther@suse.de> 14518 14519 PR tree-optimization/93397 14520 * tree-vect-slp.c (vect_analyze_slp_instance): Delay 14521 converted reduction chain SLP graph adjustment. 14522 145232020-01-26 Marek Polacek <polacek@redhat.com> 14524 14525 PR sanitizer/93436 14526 * sanopt.c (sanitize_rewrite_addressable_params): Avoid crash on 14527 null DECL_NAME. 14528 145292020-01-26 Jason Merrill <jason@redhat.com> 14530 14531 PR c++/92601 14532 * tree.c (verify_type_variant): Only verify TYPE_NEEDS_CONSTRUCTING 14533 of complete types. 14534 145352020-01-26 Darius Galis <darius.galis@cyberthorstudios.com> 14536 14537 * config/rx/rx.md (setmemsi): Added rx_allow_string_insns constraint 14538 (rx_setmem): Likewise. 14539 145402020-01-26 Jakub Jelinek <jakub@redhat.com> 14541 14542 PR target/93412 14543 * config/i386/i386.md (*addv<dwi>4_doubleword, *subv<dwi>4_doubleword): 14544 Use nonimmediate_operand instead of x86_64_hilo_general_operand and 14545 drop <di> from constraint of last operand. 14546 14547 PR target/93430 14548 * config/i386/sse.md (*avx_vperm_broadcast_<mode>): Disallow for 14549 TARGET_AVX2 and V4DFmode not in the split condition, but in the 14550 pattern condition, though allow { 0, 0, 0, 0 } broadcast always. 14551 145522020-01-25 Feng Xue <fxue@os.amperecomputing.com> 14553 14554 PR ipa/93166 14555 * ipa-cp.c (get_info_about_necessary_edges): Remove value 14556 check assertion. 14557 145582020-01-24 Jeff Law <law@redhat.com> 14559 14560 PR tree-optimization/92788 14561 * tree-ssa-threadedge.c (thread_across_edge): Check EDGE_COMPLEX 14562 not EDGE_ABNORMAL. 14563 145642020-01-24 Jakub Jelinek <jakub@redhat.com> 14565 14566 PR target/93395 14567 * config/i386/sse.md (*avx_vperm_broadcast_v4sf, 14568 *avx_vperm_broadcast_<mode>, 14569 <sse2_avx_avx512f>_vpermil<mode><mask_name>, 14570 *<sse2_avx_avx512f>_vpermilp<mode><mask_name>): 14571 Move before avx2_perm<mode>/avx512f_perm<mode>. 14572 14573 PR target/93376 14574 * simplify-rtx.c (simplify_const_unary_operation, 14575 simplify_const_binary_operation): Punt for mode precision above 14576 MAX_BITSIZE_MODE_ANY_INT. 14577 145782020-01-24 Andrew Pinski <apinski@marvell.com> 14579 14580 * config/arm/aarch-cost-tables.h (cortexa57_extra_costs): Change 14581 alu.shift_reg to 0. 14582 145832020-01-24 Jeff Law <law@redhat.com> 14584 14585 PR target/13721 14586 * config/h8300/h8300.c (h8300_print_operand): Only call byte_reg 14587 for REGs. Call output_operand_lossage to get more reasonable 14588 diagnostics. 14589 145902020-01-24 Andrew Stubbs <ams@codesourcery.com> 14591 14592 * config/gcn/gcn-valu.md (vec_cmp<mode>di): Use 14593 gcn_fp_compare_operator. 14594 (vec_cmpu<mode>di): Use gcn_compare_operator. 14595 (vec_cmp<u>v64qidi): Use gcn_compare_operator. 14596 (vec_cmp<mode>di_exec): Use gcn_fp_compare_operator. 14597 (vec_cmpu<mode>di_exec): Use gcn_compare_operator. 14598 (vec_cmp<u>v64qidi_exec): Use gcn_compare_operator. 14599 (vec_cmp<mode>di_dup): Use gcn_fp_compare_operator. 14600 (vec_cmp<mode>di_dup_exec): Use gcn_fp_compare_operator. 14601 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>): Use 14602 gcn_fp_compare_operator. 14603 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>_exec): Use 14604 gcn_fp_compare_operator. 14605 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>): Use 14606 gcn_fp_compare_operator. 14607 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>_exec): Use 14608 gcn_fp_compare_operator. 14609 146102020-01-24 Maciej W. Rozycki <macro@wdc.com> 14611 14612 * doc/install.texi (Cross-Compiler-Specific Options): Document 14613 `--with-toolexeclibdir' option. 14614 146152020-01-24 Hans-Peter Nilsson <hp@axis.com> 14616 14617 * target.def (flags_regnum): Also mention effect on delay slot filling. 14618 * doc/tm.texi: Regenerate. 14619 146202020-01-23 Jeff Law <law@redhat.com> 14621 14622 PR translation/90162 14623 * config/h8300/h8300.c (h8300_option_override): Fix diagnostic text. 14624 146252020-01-23 Mikael Tillenius <mti-1@tillenius.com> 14626 14627 PR target/92269 14628 * config/h8300/h8300.h (FUNCTION_PROFILER): Fix emission of 14629 profiling label 14630 146312020-01-23 Jakub Jelinek <jakub@redhat.com> 14632 14633 PR rtl-optimization/93402 14634 * postreload.c (reload_combine_recognize_pattern): Don't try to adjust 14635 USE insns. 14636 146372020-01-23 Dragan Mladjenovic <dmladjenovic@wavecomp.com> 14638 14639 * config.in: Regenerated. 14640 * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to 1 14641 for TARGET_LIBC_GNUSTACK. 14642 * configure: Regenerated. 14643 * configure.ac: Define TARGET_LIBC_GNUSTACK if glibc version is 14644 found to be 2.31 or greater. 14645 146462020-01-23 Dragan Mladjenovic <dmladjenovic@wavecomp.com> 14647 14648 * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to 14649 TARGET_SOFT_FLOAT. 14650 * config/mips/mips.c (TARGET_ASM_FILE_END): Define to ... 14651 (mips_asm_file_end): New function. Delegate to 14652 file_end_indicate_exec_stack if NEED_INDICATE_EXEC_STACK is true. 14653 * config/mips/mips.h (NEED_INDICATE_EXEC_STACK): Define to 0. 14654 146552020-01-23 Jakub Jelinek <jakub@redhat.com> 14656 14657 PR target/93376 14658 * config/i386/i386-modes.def (POImode): New mode. 14659 (MAX_BITSIZE_MODE_ANY_INT): Change from 128 to 160. 14660 * config/i386/i386.md (DPWI): New mode attribute. 14661 (addv<mode>4, subv<mode>4): Use <DPWI> instead of <DWI>. 14662 (QWI): Rename to... 14663 (QPWI): ... this. Use POI instead of OI for TImode. 14664 (*addv<dwi>4_doubleword, *addv<dwi>4_doubleword_1, 14665 *subv<dwi>4_doubleword, *subv<dwi>4_doubleword_1): Use <QPWI> 14666 instead of <QWI>. 14667 146682020-01-23 Richard Sandiford <richard.sandiford@arm.com> 14669 14670 PR target/93341 14671 * config/aarch64/aarch64.md (UNSPEC_SPECULATION_TRACKER_REV): New 14672 unspec. 14673 (speculation_tracker_rev): New pattern. 14674 * config/aarch64/aarch64-speculation.cc (aarch64_do_track_speculation): 14675 Use speculation_tracker_rev to track the inverse condition. 14676 146772020-01-23 Richard Biener <rguenther@suse.de> 14678 14679 PR tree-optimization/93381 14680 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Take 14681 alias-set of the def as argument and record the first one. 14682 (vn_walk_cb_data::first_set): New member. 14683 (vn_reference_lookup_3): Pass the alias-set of the current def 14684 to push_partial_def. Fix alias-set used in the aggregate copy 14685 case. 14686 (vn_reference_lookup): Consistently set *last_vuse_ptr. 14687 * real.c (clear_significand_below): Fix out-of-bound access. 14688 146892020-01-23 Jakub Jelinek <jakub@redhat.com> 14690 14691 PR target/93346 14692 * config/i386/i386.md (*bmi2_bzhi_<mode>3_2, *bmi2_bzhi_<mode>3_3): 14693 New define_insn patterns. 14694 146952020-01-23 Richard Sandiford <richard.sandiford@arm.com> 14696 14697 * doc/sourcebuild.texi (check-function-bodies): Add an 14698 optional target/xfail selector. 14699 147002020-01-23 Richard Sandiford <richard.sandiford@arm.com> 14701 14702 PR rtl-optimization/93124 14703 * auto-inc-dec.c (merge_in_block): Don't add auto inc/decs to 14704 bare USE and CLOBBER insns. 14705 147062020-01-22 Andrew Pinski <apinski@marvell.com> 14707 14708 * config/arc/arc.c (output_short_suffix): Check insn for nullness. 14709 147102020-01-22 David Malcolm <dmalcolm@redhat.com> 14711 14712 PR analyzer/93307 14713 * gdbinit.in (break-on-saved-diagnostic): Update for move of 14714 diagnostic_manager into "ana" namespace. 14715 * selftest-run-tests.c (selftest::run_tests): Update for move of 14716 selftest::run_analyzer_selftests to 14717 ana::selftest::run_analyzer_selftests. 14718 147192020-01-22 Richard Sandiford <richard.sandiford@arm.com> 14720 14721 * cfgexpand.c (union_stack_vars): Update the size. 14722 147232020-01-22 Richard Biener <rguenther@suse.de> 14724 14725 PR tree-optimization/93381 14726 * tree-ssa-structalias.c (find_func_aliases): Assume offsetting 14727 throughout, handle all conversions the same. 14728 147292020-01-22 Jakub Jelinek <jakub@redhat.com> 14730 14731 PR target/93335 14732 * config/aarch64/aarch64.c (aarch64_expand_subvti): Only use 14733 gen_subdi3_compare1_imm if low_in2 satisfies aarch64_plus_immediate 14734 predicate, not whenever it is CONST_INT. Otherwise, force_reg it. 14735 Call force_reg on high_in2 unconditionally. 14736 147372020-01-22 Martin Liska <mliska@suse.cz> 14738 14739 PR tree-optimization/92924 14740 * profile.c (compute_value_histograms): Divide 14741 all counter values. 14742 147432020-01-22 Jakub Jelinek <jakub@redhat.com> 14744 14745 PR target/91298 14746 * output.h (assemble_name_resolve): Declare. 14747 * varasm.c (assemble_name_resolve): New function. 14748 (assemble_name): Use it. 14749 * config/i386/i386.h (ASM_OUTPUT_SYMBOL_REF): Define. 14750 147512020-01-22 Joseph Myers <joseph@codesourcery.com> 14752 14753 * doc/sourcebuild.texi (Texinfo Manuals, Front End): Refer to 14754 update_web_docs_git instead of update_web_docs_svn. 14755 147562020-01-21 Andrew Pinski <apinski@marvell.com> 14757 14758 PR target/9311 14759 * config/aarch64/aarch64.md (tlsgd_small_<mode>): Have operand 0 14760 as PTR mode. Have operand 1 as being modeless, it can be P mode. 14761 (*tlsgd_small_<mode>): Likewise. 14762 * config/aarch64/aarch64.c (aarch64_load_symref_appropriately) 14763 <case SYMBOL_SMALL_TLSGD>: Call gen_tlsgd_small_* with a ptr_mode 14764 register. Convert that register back to dest using convert_mode. 14765 147662020-01-21 Jim Wilson <jimw@sifive.com> 14767 14768 * config/riscv/riscv-sr.c (riscv_sr_match_prologue): Use INTVAL 14769 instead of XINT. 14770 147712020-01-21 H.J. Lu <hongjiu.lu@intel.com> 14772 Uros Bizjak <ubizjak@gmail.com> 14773 14774 PR target/93319 14775 * config/i386/i386.c (ix86_tls_module_base): Replace Pmode 14776 with ptr_mode. 14777 (legitimize_tls_address): Do GNU2 TLS address computation in 14778 ptr_mode and zero-extend result to Pmode. 14779 * config/i386/i386.md (@tls_dynamic_gnu2_64_<mode>): Replace 14780 :P with :PTR and Pmode with ptr_mode. 14781 (*tls_dynamic_gnu2_lea_64_<mode>): Likewise. 14782 (*tls_dynamic_gnu2_call_64_<mode>): Likewise. 14783 (*tls_dynamic_gnu2_combine_64_<mode>): Likewise. 14784 147852020-01-21 Jakub Jelinek <jakub@redhat.com> 14786 14787 PR target/93333 14788 * config/riscv/riscv.c (riscv_rtx_costs) <case ZERO_EXTRACT>: Verify 14789 the last two operands are CONST_INT_P before using them as such. 14790 147912020-01-21 Richard Sandiford <richard.sandiford@arm.com> 14792 14793 * config/aarch64/aarch64-sve-builtins.def: Use get_typenode_from_name 14794 to get the integer element types. 14795 147962020-01-21 Richard Sandiford <richard.sandiford@arm.com> 14797 14798 * config/aarch64/aarch64-sve-builtins.h 14799 (function_expander::convert_to_pmode): Declare. 14800 * config/aarch64/aarch64-sve-builtins.cc 14801 (function_expander::convert_to_pmode): New function. 14802 (function_expander::get_contiguous_base): Use it. 14803 (function_expander::prepare_gather_address_operands): Likewise. 14804 * config/aarch64/aarch64-sve-builtins-sve2.cc 14805 (svwhilerw_svwhilewr_impl::expand): Likewise. 14806 148072020-01-21 Szabolcs Nagy <szabolcs.nagy@arm.com> 14808 14809 PR target/92424 14810 * config/aarch64/aarch64.c (aarch64_declare_function_name): Set 14811 cfun->machine->label_is_assembled. 14812 (aarch64_print_patchable_function_entry): New. 14813 (TARGET_ASM_PRINT_PATCHABLE_FUNCTION_ENTRY): Define. 14814 * config/aarch64/aarch64.h (struct machine_function): New field, 14815 label_is_assembled. 14816 148172020-01-21 David Malcolm <dmalcolm@redhat.com> 14818 14819 PR ipa/93315 14820 * ipa-profile.c (ipa_profile): Delete call_sums and set it to 14821 NULL on exit. 14822 148232020-01-18 Jan Hubicka <hubicka@ucw.cz> 14824 14825 PR lto/93318 14826 * cgraph.c (cgraph_edge::resolve_speculation, 14827 cgraph_edge::redirect_call_stmt_to_callee): Fix update of 14828 call_stmt_site_hash. 14829 148302020-01-21 Martin Liska <mliska@suse.cz> 14831 14832 * config/rs6000/rs6000.c (common_mode_defined): Remove 14833 unused variable. 14834 148352020-01-21 Richard Biener <rguenther@suse.de> 14836 14837 PR tree-optimization/92328 14838 * tree-ssa-sccvn.c (vn_reference_lookup_3): Preserve 14839 type when value-numbering same-sized store by inserting a 14840 VIEW_CONVERT_EXPR. 14841 (eliminate_dom_walker::eliminate_stmt): When eliminating 14842 a redundant store handle bit-reinterpretation of the same value. 14843 148442020-01-21 Andrew Pinski <apinski@marvel.com> 14845 14846 PR tree-opt/93321 14847 * tree-into-ssa.c (prepare_block_for_update_1): Split out 14848 from ... 14849 (prepare_block_for_update): This. Use a worklist instead of 14850 recursing. 14851 148522020-01-21 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 14853 14854 * gcc/config/arm/arm.c (clear_operation_p): 14855 Initialise last_regno, skip first iteration 14856 based on the first_set value and use ints instead 14857 of the unnecessary HOST_WIDE_INTs. 14858 148592020-01-21 Jakub Jelinek <jakub@redhat.com> 14860 14861 PR target/93073 14862 * config/rs6000/rs6000.c (rs6000_emit_cmove): If using fsel, punt for 14863 compare_mode other than SFmode or DFmode. 14864 148652020-01-21 Kito Cheng <kito.cheng@sifive.com> 14866 14867 PR target/93304 14868 * config/riscv/riscv-protos.h (riscv_hard_regno_rename_ok): New. 14869 * config/riscv/riscv.c (riscv_hard_regno_rename_ok): New. 14870 * config/riscv/riscv.h (HARD_REGNO_RENAME_OK): Defined. 14871 148722020-01-20 Wilco Dijkstra <wdijkstr@arm.com> 14873 14874 * config/aarch64/aarch64.c (neoversen1_tunings): Set jump_align to 4. 14875 148762020-01-20 Andrew Pinski <apinski@marvell.com> 14877 14878 PR middle-end/93242 14879 * targhooks.c (default_print_patchable_function_entry): Use 14880 output_asm_insn to emit the nop instruction. 14881 148822020-01-20 Fangrui Song <maskray@google.com> 14883 14884 PR middle-end/93194 14885 * targhooks.c (default_print_patchable_function_entry): Align to 14886 POINTER_SIZE. 14887 148882020-01-20 H.J. Lu <hongjiu.lu@intel.com> 14889 14890 PR target/93319 14891 * config/i386/i386.c (legitimize_tls_address): Pass Pmode to 14892 gen_tls_dynamic_gnu2_64. Compute GNU2 TLS address in ptr_mode. 14893 * config/i386/i386.md (tls_dynamic_gnu2_64): Renamed to ... 14894 (@tls_dynamic_gnu2_64_<mode>): This. Replace DI with P. 14895 (*tls_dynamic_gnu2_lea_64): Renamed to ... 14896 (*tls_dynamic_gnu2_lea_64_<mode>): This. Replace DI with P. 14897 Remove the {q} suffix from lea. 14898 (*tls_dynamic_gnu2_call_64): Renamed to ... 14899 (*tls_dynamic_gnu2_call_64_<mode>): This. Replace DI with P. 14900 (*tls_dynamic_gnu2_combine_64): Renamed to ... 14901 (*tls_dynamic_gnu2_combine_64_<mode>): This. Replace DI with P. 14902 Pass Pmode to gen_tls_dynamic_gnu2_64. 14903 149042020-01-20 Wilco Dijkstra <wdijkstr@arm.com> 14905 14906 * config/aarch64/aarch64.h (SLOW_BYTE_ACCESS): Set to 1. 14907 149082020-01-20 Richard Sandiford <richard.sandiford@arm.com> 14909 14910 * config/aarch64/aarch64-sve-builtins-base.cc 14911 (svld1ro_impl::memory_vector_mode): Remove parameter name. 14912 149132020-01-20 Richard Biener <rguenther@suse.de> 14914 14915 PR debug/92763 14916 * dwarf2out.c (prune_unused_types): Unconditionally mark 14917 called function DIEs. 14918 149192020-01-20 Martin Liska <mliska@suse.cz> 14920 14921 PR tree-optimization/93199 14922 * tree-eh.c (struct leh_state): Add 14923 new field outer_non_cleanup. 14924 (cleanup_is_dead_in): Pass leh_state instead 14925 of eh_region. Add a checking that state->outer_non_cleanup 14926 points to outer non-clean up region. 14927 (lower_try_finally): Record outer_non_cleanup 14928 for this_state. 14929 (lower_catch): Likewise. 14930 (lower_eh_filter): Likewise. 14931 (lower_eh_must_not_throw): Likewise. 14932 (lower_cleanup): Likewise. 14933 149342020-01-20 Richard Biener <rguenther@suse.de> 14935 14936 PR tree-optimization/93094 14937 * tree-vectorizer.h (vect_loop_versioning): Adjust. 14938 (vect_transform_loop): Likewise. 14939 * tree-vectorizer.c (try_vectorize_loop_1): Pass down 14940 loop_vectorized_call to vect_transform_loop. 14941 * tree-vect-loop.c (vect_transform_loop): Pass down 14942 loop_vectorized_call to vect_loop_versioning. 14943 * tree-vect-loop-manip.c (vect_loop_versioning): Use 14944 the earlier discovered loop_vectorized_call. 14945 149462020-01-19 Eric S. Raymond <esr@thyrsus.com> 14947 14948 * doc/contribute.texi: Update for SVN -> Git transition. 14949 * doc/install.texi: Likewise. 14950 149512020-01-18 Jan Hubicka <hubicka@ucw.cz> 14952 14953 PR lto/93318 14954 * cgraph.c (cgraph_edge::make_speculative): Increase number of 14955 speculative targets. 14956 (verify_speculative_call): New function 14957 (cgraph_node::verify_node): Use it. 14958 * ipa-profile.c (ipa_profile): Fix formating; do not set number of 14959 speculations. 14960 149612020-01-18 Jan Hubicka <hubicka@ucw.cz> 14962 14963 PR lto/93318 14964 * cgraph.c (cgraph_edge::resolve_speculation): Fix foramting. 14965 (cgraph_edge::make_direct): Remove all indirect targets. 14966 (cgraph_edge::redirect_call_stmt_to_callee): Use make_direct.. 14967 (cgraph_node::verify_node): Verify that only one call_stmt or 14968 lto_stmt_uid is set. 14969 * cgraphclones.c (cgraph_edge::clone): Set only one call_stmt or 14970 lto_stmt_uid. 14971 * lto-cgraph.c (lto_output_edge): Simplify streaming of stmt. 14972 (lto_output_ref): Simplify streaming of stmt. 14973 * lto-streamer-in.c (fixup_call_stmt_edges_1): Clear lto_stmt_uid. 14974 149752020-01-18 Tamar Christina <tamar.christina@arm.com> 14976 14977 * config/aarch64/aarch64-sve-builtins-base.cc (memory_vector_mode): 14978 Mark parameter unused. 14979 149802020-01-18 Hans-Peter Nilsson <hp@axis.com> 14981 14982 * config.gcc <obsolete targets>: Add crisv32-*-* and cris-*-linux* 14983 149842019-01-18 Gerald Pfeifer <gerald@pfeifer.com> 14985 14986 * varpool.c (ctor_useable_for_folding_p): Fix grammar. 14987 149882020-01-18 Iain Sandoe <iain@sandoe.co.uk> 14989 14990 * Makefile.in: Add coroutine-passes.o. 14991 * builtin-types.def (BT_CONST_SIZE): New. 14992 (BT_FN_BOOL_PTR): New. 14993 (BT_FN_PTR_PTR_CONST_SIZE_BOOL): New. 14994 * builtins.def (DEF_COROUTINE_BUILTIN): New. 14995 * coroutine-builtins.def: New file. 14996 * coroutine-passes.cc: New file. 14997 * function.h (struct GTY function): Add a bit to indicate that the 14998 function is a coroutine component. 14999 * internal-fn.c (expand_CO_FRAME): New. 15000 (expand_CO_YIELD): New. 15001 (expand_CO_SUSPN): New. 15002 (expand_CO_ACTOR): New. 15003 * internal-fn.def (CO_ACTOR): New. 15004 (CO_YIELD): New. 15005 (CO_SUSPN): New. 15006 (CO_FRAME): New. 15007 * passes.def: Add pass_coroutine_lower_builtins, 15008 pass_coroutine_early_expand_ifns. 15009 * tree-pass.h (make_pass_coroutine_lower_builtins): New. 15010 (make_pass_coroutine_early_expand_ifns): New. 15011 * doc/invoke.texi: Document the fcoroutines command line 15012 switch. 15013 150142020-01-18 Jakub Jelinek <jakub@redhat.com> 15015 15016 * config/arm/vfp.md (*clear_vfp_multiple): Remove unused variable. 15017 15018 PR target/93312 15019 * config/arm/arm.c (clear_operation_p): Don't use REGNO until 15020 after checking the argument is a REG. Don't use REGNO (reg) 15021 again to set last_regno, reuse regno variable instead. 15022 150232020-01-17 David Malcolm <dmalcolm@redhat.com> 15024 15025 * doc/analyzer.texi (Limitations): Add note about NaN. 15026 150272020-01-17 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 15028 Sudakshina Das <sudi.das@arm.com> 15029 15030 * config/arm/arm.md (ashldi3): Generate thumb2_lsll for both reg 15031 and valid immediate. 15032 (ashrdi3): Generate thumb2_asrl for both reg and valid immediate. 15033 (lshrdi3): Generate thumb2_lsrl for valid immediates. 15034 * config/arm/constraints.md (Pg): New. 15035 * config/arm/predicates.md (long_shift_imm): New. 15036 (arm_reg_or_long_shift_imm): Likewise. 15037 * config/arm/thumb2.md (thumb2_asrl): New immediate alternative. 15038 (thumb2_lsll): Likewise. 15039 (thumb2_lsrl): New. 15040 150412020-01-17 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 15042 Sudakshina Das <sudi.das@arm.com> 15043 15044 * config/arm/arm.md (ashldi3): Generate thumb2_lsll for TARGET_HAVE_MVE. 15045 (ashrdi3): Generate thumb2_asrl for TARGET_HAVE_MVE. 15046 * config/arm/arm.c (arm_hard_regno_mode_ok): Allocate even odd 15047 register pairs for doubleword quantities for ARMv8.1M-Mainline. 15048 * config/arm/thumb2.md (thumb2_asrl): New. 15049 (thumb2_lsll): Likewise. 15050 150512020-01-17 Jakub Jelinek <jakub@redhat.com> 15052 15053 * config/arm/arm.c (cmse_nonsecure_call_inline_register_clear): Remove 15054 unused variable. 15055 150562020-01-17 Alexander Monakov <amonakov@ispras.ru> 15057 15058 * gdbinit.in (help-gcc-hooks): New command. 15059 (pp, pr, prl, pt, pct, pgg, pgq, pgs, pge, pmz, ptc, pdn, ptn, pdd, prc, 15060 pi, pbm, pel, trt): Take $arg0 instead of $ if supplied. Update 15061 documentation. 15062 150632020-01-17 Matthew Malcomson <matthew.malcomson@arm.com> 15064 15065 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): Use the 15066 correct target macro. 15067 150682020-01-17 Matthew Malcomson <matthew.malcomson@arm.com> 15069 15070 * config/aarch64/aarch64-protos.h 15071 (aarch64_sve_ld1ro_operand_p): New. 15072 * config/aarch64/aarch64-sve-builtins-base.cc 15073 (class load_replicate): New. 15074 (class svld1ro_impl): New. 15075 (class svld1rq_impl): Change to inherit from load_replicate. 15076 (svld1ro): New sve intrinsic function base. 15077 * config/aarch64/aarch64-sve-builtins-base.def (svld1ro): 15078 New DEF_SVE_FUNCTION. 15079 * config/aarch64/aarch64-sve-builtins-base.h 15080 (svld1ro): New decl. 15081 * config/aarch64/aarch64-sve-builtins.cc 15082 (function_expander::add_mem_operand): Modify assert to allow 15083 OImode. 15084 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): New 15085 pattern. 15086 * config/aarch64/aarch64.c 15087 (aarch64_sve_ld1rq_operand_p): Implement in terms of ... 15088 (aarch64_sve_ld1rq_ld1ro_operand_p): This. 15089 (aarch64_sve_ld1ro_operand_p): New. 15090 * config/aarch64/aarch64.md (UNSPEC_LD1RO): New unspec. 15091 * config/aarch64/constraints.md (UOb,UOh,UOw,UOd): New. 15092 * config/aarch64/predicates.md 15093 (aarch64_sve_ld1ro_operand_{b,h,w,d}): New. 15094 150952020-01-17 Matthew Malcomson <matthew.malcomson@arm.com> 15096 15097 * config/aarch64/aarch64-c.c (_ARM_FEATURE_MATMUL_FLOAT64): 15098 Introduce this ACLE specified predefined macro. 15099 * config/aarch64/aarch64-option-extensions.def (f64mm): New. 15100 (fp): Disabling this disables f64mm. 15101 (simd): Disabling this disables f64mm. 15102 (fp16): Disabling this disables f64mm. 15103 (sve): Disabling this disables f64mm. 15104 * config/aarch64/aarch64.h (AARCH64_FL_F64MM): New. 15105 (AARCH64_ISA_F64MM): New. 15106 (TARGET_F64MM): New. 15107 * doc/invoke.texi (f64mm): Document new option. 15108 151092020-01-17 Wilco Dijkstra <wdijkstr@arm.com> 15110 15111 * config/aarch64/aarch64.c (generic_tunings): Add branch fusion. 15112 (neoversen1_tunings): Likewise. 15113 151142020-01-17 Wilco Dijkstra <wdijkstr@arm.com> 15115 15116 PR target/92692 15117 * config/aarch64/aarch64.c (aarch64_split_compare_and_swap) 15118 Add assert to ensure prolog has been emitted. 15119 (aarch64_split_atomic_op): Likewise. 15120 * config/aarch64/atomics.md (aarch64_compare_and_swap<mode>) 15121 Use epilogue_completed rather than reload_completed. 15122 (aarch64_atomic_exchange<mode>): Likewise. 15123 (aarch64_atomic_<atomic_optab><mode>): Likewise. 15124 (atomic_nand<mode>): Likewise. 15125 (aarch64_atomic_fetch_<atomic_optab><mode>): Likewise. 15126 (atomic_fetch_nand<mode>): Likewise. 15127 (aarch64_atomic_<atomic_optab>_fetch<mode>): Likewise. 15128 (atomic_nand_fetch<mode>): Likewise. 15129 151302020-01-17 Richard Sandiford <richard.sandiford@arm.com> 15131 15132 PR target/93133 15133 * config/aarch64/aarch64.h (REVERSIBLE_CC_MODE): Return false 15134 for FP modes. 15135 (REVERSE_CONDITION): Delete. 15136 * config/aarch64/iterators.md (CC_ONLY): New mode iterator. 15137 (CCFP_CCFPE): Likewise. 15138 (e): New mode attribute. 15139 * config/aarch64/aarch64.md (ccmp<GPI:mode>): Rename to... 15140 (@ccmp<CC_ONLY:mode><GPI:mode>): ...this, using CC_ONLY instead of CC. 15141 (fccmp<GPF:mode>, fccmpe<GPF:mode>): Merge into... 15142 (@ccmp<CCFP_CCFPE:mode><GPF:mode>): ...this combined pattern. 15143 (@ccmp<CC_ONLY:mode><GPI:mode>_rev): New pattern. 15144 (@ccmp<CCFP_CCFPE:mode><GPF:mode>_rev): Likewise. 15145 * config/aarch64/aarch64.c (aarch64_gen_compare_reg): Update 15146 name of generator from gen_ccmpdi to gen_ccmpccdi. 15147 (aarch64_gen_ccmp_next): Use code_for_ccmp. If we want to reverse 15148 the previous comparison but aren't able to, use the new ccmp_rev 15149 patterns instead. 15150 151512020-01-17 Richard Sandiford <richard.sandiford@arm.com> 15152 15153 * gimplify.c (gimplify_return_expr): Use poly_int_tree_p rather 15154 than testing directly for INTEGER_CST. 15155 (gimplify_target_expr, gimplify_omp_depend): Likewise. 15156 151572020-01-17 Jakub Jelinek <jakub@redhat.com> 15158 15159 PR tree-optimization/93292 15160 * tree-vect-stmts.c (vectorizable_comparison): Punt also if 15161 get_vectype_for_scalar_type returns NULL. 15162 151632020-01-16 Jan Hubicka <hubicka@ucw.cz> 15164 15165 * params.opt (-param=max-predicted-iterations): Increase range from 0. 15166 * predict.c (estimate_loops): Add 1 to param_max_predicted_iterations. 15167 151682020-01-16 Jan Hubicka <hubicka@ucw.cz> 15169 15170 * ipa-fnsummary.c (estimate_calls_size_and_time): Fix formating of 15171 dump. 15172 * params.opt: (max-predicted-iterations): Set bounds. 15173 * predict.c (real_almost_one, real_br_prob_base, 15174 real_inv_br_prob_base, real_one_half, real_bb_freq_max): Remove. 15175 (propagate_freq): Add max_cyclic_prob parameter; cap cyclic 15176 probabilities; do not truncate to reg_br_prob_bases. 15177 (estimate_loops_at_level): Pass max_cyclic_prob. 15178 (estimate_loops): Compute max_cyclic_prob. 15179 (estimate_bb_frequencies): Do not initialize real_*; update calculation 15180 of back edge prob. 15181 * profile-count.c (profile_probability::to_sreal): New. 15182 * profile-count.h (class sreal): Move up in file. 15183 (profile_probability::to_sreal): Declare. 15184 151852020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com> 15186 15187 * config/arm/arm.c 15188 (arm_invalid_conversion): New function for target hook. 15189 (arm_invalid_unary_op): New function for target hook. 15190 (arm_invalid_binary_op): New function for target hook. 15191 151922020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com> 15193 15194 * config.gcc: Add arm_bf16.h. 15195 * config/arm/arm-builtins.c (arm_mangle_builtin_type): Fix comment. 15196 (arm_simd_builtin_std_type): Add BFmode. 15197 (arm_init_simd_builtin_types): Define element types for vector types. 15198 (arm_init_bf16_types): New function. 15199 (arm_init_builtins): Add arm_init_bf16_types function call. 15200 * config/arm/arm-modes.def: Add BFmode and V4BF, V8BF vector modes. 15201 * config/arm/arm-simd-builtin-types.def: Add V4BF, V8BF. 15202 * config/arm/arm.c (aapcs_vfp_sub_candidate): Add BFmode. 15203 (arm_hard_regno_mode_ok): Add BFmode and tidy up statements. 15204 (arm_vector_mode_supported_p): Add V4BF, V8BF. 15205 (arm_mangle_type): Add __bf16. 15206 * config/arm/arm.h: Add V4BF, V8BF to VALID_NEON_DREG_MODE, 15207 VALID_NEON_QREG_MODE respectively. Add export arm_bf16_type_node, 15208 arm_bf16_ptr_type_node. 15209 * config/arm/arm.md: Add BFmode to movhf expand, mov pattern and 15210 define_split between ARM registers. 15211 * config/arm/arm_bf16.h: New file. 15212 * config/arm/arm_neon.h: Add arm_bf16.h and Bfloat vector types. 15213 * config/arm/iterators.md: (ANY64_BF, VDXMOV, VHFBF, HFBF, fporbf): New. 15214 (VQXMOV): Add V8BF. 15215 * config/arm/neon.md: Add BF vector types to movhf NEON move patterns. 15216 * config/arm/vfp.md: Add BFmode to movhf patterns. 15217 152182020-01-16 Mihail Ionescu <mihail.ionescu@arm.com> 15219 Andre Vieira <andre.simoesdiasvieira@arm.com> 15220 15221 * config/arm/arm-cpus.in (mve, mve_float): New features. 15222 (dsp, mve, mve.fp): New options. 15223 * config/arm/arm.h (TARGET_HAVE_MVE, TARGET_HAVE_MVE_FLOAT): Define. 15224 * config/arm/t-rmprofile: Map v8.1-M multilibs to v8-M. 15225 * doc/invoke.texi: Document the armv8.1-m mve and dps options. 15226 152272020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 15228 Thomas Preud'homme <thomas.preudhomme@arm.com> 15229 15230 * config/arm/arm-cpus.in (ARMv8_1m_main): Redefine as an extension to 15231 Armv8-M Mainline. 15232 * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Remove 15233 error for using -mcmse when targeting Armv8.1-M Mainline. 15234 152352020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 15236 Thomas Preud'homme <thomas.preudhomme@arm.com> 15237 15238 * config/arm/arm.md (nonsecure_call_internal): Do not force memory 15239 address in r4 when targeting Armv8.1-M Mainline. 15240 (nonsecure_call_value_internal): Likewise. 15241 * config/arm/thumb2.md (nonsecure_call_reg_thumb2): Make memory address 15242 a register match_operand again. Emit BLXNS when targeting 15243 Armv8.1-M Mainline. 15244 (nonsecure_call_value_reg_thumb2): Likewise. 15245 152462020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 15247 Thomas Preud'homme <thomas.preudhomme@arm.com> 15248 15249 * config/arm/arm.c (arm_add_cfa_adjust_cfa_note): Declare early. 15250 (cmse_nonsecure_call_inline_register_clear): Define new lazy_fpclear 15251 variable as true when floating-point ABI is not hard. Replace 15252 check against TARGET_HARD_FLOAT_ABI by checks against lazy_fpclear. 15253 Generate VLSTM and VLLDM instruction respectively before and 15254 after a function call to cmse_nonsecure_call function. 15255 * config/arm/unspecs.md (VUNSPEC_VLSTM): Define unspec. 15256 (VUNSPEC_VLLDM): Likewise. 15257 * config/arm/vfp.md (lazy_store_multiple_insn): New define_insn. 15258 (lazy_load_multiple_insn): Likewise. 15259 152602020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 15261 Thomas Preud'homme <thomas.preudhomme@arm.com> 15262 15263 * config/arm/arm.c (vfp_emit_fstmd): Declare early. 15264 (arm_emit_vfp_multi_reg_pop): Likewise. 15265 (cmse_nonsecure_call_inline_register_clear): Abstract number of VFP 15266 registers to clear in max_fp_regno. Emit VPUSH and VPOP to save and 15267 restore callee-saved VFP registers. 15268 152692020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 15270 Thomas Preud'homme <thomas.preudhomme@arm.com> 15271 15272 * config/arm/arm.c (arm_emit_multi_reg_pop): Declare early. 15273 (cmse_nonsecure_call_clear_caller_saved): Rename into ... 15274 (cmse_nonsecure_call_inline_register_clear): This. Save and clear 15275 callee-saved GPRs as well as clear ip register before doing a nonsecure 15276 call then restore callee-saved GPRs after it when targeting 15277 Armv8.1-M Mainline. 15278 (arm_reorg): Adapt to function rename. 15279 152802020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 15281 Thomas Preud'homme <thomas.preudhomme@arm.com> 15282 15283 * config/arm/arm-protos.h (clear_operation_p): Adapt prototype. 15284 * config/arm/arm.c (clear_operation_p): Extend to be able to check a 15285 clear_vfp_multiple pattern based on a new vfp parameter. 15286 (cmse_clear_registers): Generate VSCCLRM to clear VFP registers when 15287 targeting Armv8.1-M Mainline. 15288 (cmse_nonsecure_entry_clear_before_return): Clear VFP registers 15289 unconditionally when targeting Armv8.1-M Mainline architecture. Check 15290 whether VFP registers are available before looking call_used_regs for a 15291 VFP register. 15292 * config/arm/predicates.md (clear_multiple_operation): Adapt to change 15293 of prototype of clear_operation_p. 15294 (clear_vfp_multiple_operation): New predicate. 15295 * config/arm/unspecs.md (VUNSPEC_VSCCLRM_VPR): New volatile unspec. 15296 * config/arm/vfp.md (clear_vfp_multiple): New define_insn. 15297 152982020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 15299 Thomas Preud'homme <thomas.preudhomme@arm.com> 15300 15301 * config/arm/arm-protos.h (clear_operation_p): Declare. 15302 * config/arm/arm.c (clear_operation_p): New function. 15303 (cmse_clear_registers): Generate clear_multiple instruction pattern if 15304 targeting Armv8.1-M Mainline or successor. 15305 (output_return_instruction): Only output APSR register clearing if 15306 Armv8.1-M Mainline instructions not available. 15307 (thumb_exit): Likewise. 15308 * config/arm/predicates.md (clear_multiple_operation): New predicate. 15309 * config/arm/thumb2.md (clear_apsr): New define_insn. 15310 (clear_multiple): Likewise. 15311 * config/arm/unspecs.md (VUNSPEC_CLRM_APSR): New volatile unspec. 15312 153132020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 15314 Thomas Preud'homme <thomas.preudhomme@arm.com> 15315 15316 * config/arm/arm.c (fp_sysreg_names): Declare and define. 15317 (use_return_insn): Also return false for Armv8.1-M Mainline. 15318 (output_return_instruction): Skip FPSCR clearing if Armv8.1-M 15319 Mainline instructions are available. 15320 (arm_compute_frame_layout): Allocate space in frame for FPCXTNS 15321 when targeting Armv8.1-M Mainline Security Extensions. 15322 (arm_expand_prologue): Save FPCXTNS if this is an Armv8.1-M 15323 Mainline entry function. 15324 (cmse_nonsecure_entry_clear_before_return): Clear IP and r4 if 15325 targeting Armv8.1-M Mainline or successor. 15326 (arm_expand_epilogue): Fix indentation of caller-saved register 15327 clearing. Restore FPCXTNS if this is an Armv8.1-M Mainline 15328 entry function. 15329 * config/arm/arm.h (TARGET_HAVE_FP_CMSE): New macro. 15330 (FP_SYSREGS): Likewise. 15331 (enum vfp_sysregs_encoding): Define enum. 15332 (fp_sysreg_names): Declare. 15333 * config/arm/unspecs.md (VUNSPEC_VSTR_VLDR): New volatile unspec. 15334 * config/arm/vfp.md (push_fpsysreg_insn): New define_insn. 15335 (pop_fpsysreg_insn): Likewise. 15336 153372020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 15338 Thomas Preud'homme <thomas.preudhomme@arm.com> 15339 15340 * config/arm/arm-cpus.in (armv8_1m_main): New feature. 15341 (ARMv4, ARMv4t, ARMv5t, ARMv5te, ARMv5tej, ARMv6, ARMv6j, ARMv6k, 15342 ARMv6z, ARMv6kz, ARMv6zk, ARMv6t2, ARMv6m, ARMv7, ARMv7a, ARMv7ve, 15343 ARMv7r, ARMv7m, ARMv7em, ARMv8a, ARMv8_1a, ARMv8_2a, ARMv8_3a, 15344 ARMv8_4a, ARMv8_5a, ARMv8m_base, ARMv8m_main, ARMv8r): Reindent. 15345 (ARMv8_1m_main): New feature group. 15346 (armv8.1-m.main): New architecture. 15347 * config/arm/arm-tables.opt: Regenerate. 15348 * config/arm/arm.c (arm_arch8_1m_main): Define and default initialize. 15349 (arm_option_reconfigure_globals): Initialize arm_arch8_1m_main. 15350 (arm_options_perform_arch_sanity_checks): Error out when targeting 15351 Armv8.1-M Mainline Security Extensions. 15352 * config/arm/arm.h (arm_arch8_1m_main): Declare. 15353 153542020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com> 15355 15356 * config/aarch64/aarch64-simd-builtins.def (aarch64_bfdot, 15357 aarch64_bfdot_lane, aarch64_bfdot_laneq): New. 15358 * config/aarch64/aarch64-simd.md (aarch64_bfdot, aarch64_bfdot_lane, 15359 aarch64_bfdot_laneq): New. 15360 * config/aarch64/arm_bf16.h (vbfdot_f32, vbfdotq_f32, 15361 vbfdot_lane_f32, vbfdotq_lane_f32, vbfdot_laneq_f32, 15362 vbfdotq_laneq_f32): New. 15363 * config/aarch64/iterators.md (UNSPEC_BFDOT, Vbfdottype, 15364 VBFMLA_W, VBF): New. 15365 (isquadop): Add V4BF, V8BF. 15366 153672020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com> 15368 15369 * config/aarch64/aarch64-builtins.c: (enum aarch64_type_qualifiers): 15370 New qualifier_lane_quadtup_index, TYPES_TERNOP_SSUS, 15371 TYPES_QUADOPSSUS_LANE_QUADTUP, TYPES_QUADOPSSSU_LANE_QUADTUP. 15372 (aarch64_simd_expand_args): Add case SIMD_ARG_LANE_QUADTUP_INDEX. 15373 (aarch64_simd_expand_builtin): Add qualifier_lane_quadtup_index. 15374 * config/aarch64/aarch64-simd-builtins.def (usdot, usdot_lane, 15375 usdot_laneq, sudot_lane,sudot_laneq): New. 15376 * config/aarch64/aarch64-simd.md (aarch64_usdot): New. 15377 (aarch64_<sur>dot_lane): New. 15378 * config/aarch64/arm_neon.h (vusdot_s32): New. 15379 (vusdotq_s32): New. 15380 (vusdot_lane_s32): New. 15381 (vsudot_lane_s32): New. 15382 * config/aarch64/iterators.md (DOTPROD_I8MM): New iterator. 15383 (UNSPEC_USDOT, UNSPEC_SUDOT): New unspecs. 15384 153852020-01-16 Martin Liska <mliska@suse.cz> 15386 15387 * value-prof.c (dump_histogram_value): Fix 15388 obvious spacing issue. 15389 153902020-01-16 Andrew Pinski <apinski@marvell.com> 15391 15392 * tree-ssa-sccvn.c(vn_reference_lookup_3): Check lhs for 15393 !storage_order_barrier_p. 15394 153952020-01-16 Andrew Pinski <apinski@marvell.com> 15396 15397 * sched-int.h (_dep): Add unused bit-field field for the padding. 15398 * sched-deps.c (init_dep_1): Init unused field. 15399 154002020-01-16 Andrew Pinski <apinski@marvell.com> 15401 15402 * optabs.h (create_expand_operand): Initialize target field also. 15403 154042020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> 15405 15406 PR tree-optimization/92429 15407 * tree-ssa-loop-niter.h (simplify_replace_tree): Add parameter. 15408 * tree-ssa-loop-niter.c (simplify_replace_tree): Add parameter to 15409 control folding. 15410 * tree-vect-loop.c (update_epilogue_vinfo): Do not fold when replacing 15411 tree. 15412 154132020-01-16 Richard Sandiford <richard.sandiford@arm.com> 15414 15415 * config/aarch64/aarch64.c (aarch64_split_sve_subreg_move): Apply 15416 aarch64_sve_int_mode to each mode. 15417 154182020-01-15 David Malcolm <dmalcolm@redhat.com> 15419 15420 * doc/analyzer.texi (Overview): Add note about 15421 -fdump-ipa-analyzer. 15422 154232020-01-15 Wilco Dijkstra <wdijkstr@arm.com> 15424 15425 PR tree-optimization/93231 15426 * tree-ssa-forwprop.c (optimize_count_trailing_zeroes): Check 15427 input_type is unsigned. Use tree_to_shwi for shift constant. 15428 Check CST_STRING element size is CHAR_TYPE_SIZE bits. 15429 (simplify_count_trailing_zeroes): Add test to handle known non-zero 15430 inputs more efficiently. 15431 154322020-01-15 Uroš Bizjak <ubizjak@gmail.com> 15433 15434 * config/i386/i386.md (*movsf_internal): Do not require 15435 SSE2 ISA for alternatives 14 and 15. 15436 154372020-01-15 Richard Biener <rguenther@suse.de> 15438 15439 PR middle-end/93273 15440 * tree-eh.c (sink_clobbers): If we already visited the destination 15441 block do not defer insertion. 15442 (pass_lower_eh_dispatch::execute): Maintain BB_VISITED for 15443 the purpose of defered insertion. 15444 154452020-01-15 Jakub Jelinek <jakub@redhat.com> 15446 15447 * BASE-VER: Bump to 10.0.1. 15448 154492020-01-15 Richard Sandiford <richard.sandiford@arm.com> 15450 15451 PR tree-optimization/93247 15452 * tree-vect-loop.c (update_epilogue_loop_vinfo): Check the access 15453 type of the stmt that we're going to vectorize. 15454 154552020-01-15 Richard Sandiford <richard.sandiford@arm.com> 15456 15457 * tree-vect-slp.c (vectorize_slp_instance_root_stmt): Use a 15458 VIEW_CONVERT_EXPR if the vectorized constructor has a diffeent 15459 type from the lhs. 15460 154612020-01-15 Martin Liska <mliska@suse.cz> 15462 15463 * ipa-profile.c (ipa_profile_read_edge_summary): Do not allow 15464 2 calls of streamer_read_hwi in a function call. 15465 154662020-01-15 Richard Biener <rguenther@suse.de> 15467 15468 * alias.c (record_alias_subset): Avoid redundant work when 15469 subset is already recorded. 15470 154712020-01-14 David Malcolm <dmalcolm@redhat.com> 15472 15473 * doc/invoke.texi (-fdiagnostics-show-cwe): Add note that some of 15474 the analyzer options provide CWE identifiers. 15475 154762020-01-14 David Malcolm <dmalcolm@redhat.com> 15477 15478 * tree-diagnostic-path.cc (path_summary::event_range::print): 15479 When testing for UNKNOWN_LOCATION, look through ad-hoc wrappers 15480 using get_pure_location. 15481 154822020-01-15 Jakub Jelinek <jakub@redhat.com> 15483 15484 PR tree-optimization/93262 15485 * tree-ssa-dse.c (maybe_trim_memstar_call): For *_chk builtins, 15486 perform head trimming only if the last argument is constant, 15487 either all ones, or larger or equal to head trim, in the latter 15488 case decrease the last argument by head_trim. 15489 15490 PR tree-optimization/93249 15491 * tree-ssa-dse.c: Include builtins.h and gimple-fold.h. 15492 (maybe_trim_memstar_call): Move head_trim and tail_trim vars to 15493 function body scope, reindent. For BUILTIN_IN_STRNCPY*, don't 15494 perform head trim unless we can prove there are no '\0' chars 15495 from the source among the first head_trim chars. 15496 154972020-01-14 David Malcolm <dmalcolm@redhat.com> 15498 15499 * Makefile.in (ANALYZER_OBJS): Add analyzer/function-set.o. 15500 155012020-01-15 Jakub Jelinek <jakub@redhat.com> 15502 15503 PR target/93009 15504 * config/i386/sse.md 15505 (*<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name>_bcst_1, 15506 *<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name>_bcst_1, 15507 *<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name>_bcst_1, 15508 *<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name>_bcst_1): Use 15509 just a single alternative instead of two, make operands 1 and 2 15510 commutative. 15511 155122020-01-14 Jan Hubicka <hubicka@ucw.cz> 15513 15514 PR lto/91576 15515 * ipa-devirt.c (odr_types_equivalent_p): Compare TREE_ADDRESSABLE and 15516 TYPE_MODE. 15517 155182020-01-14 David Malcolm <dmalcolm@redhat.com> 15519 15520 * Makefile.in (lang_opt_files): Add analyzer.opt. 15521 (ANALYZER_OBJS): New. 15522 (OBJS): Add digraph.o, graphviz.o, ordered-hash-map-tests.o, 15523 tristate.o and ANALYZER_OBJS. 15524 (TEXI_GCCINT_FILES): Add analyzer.texi. 15525 * common.opt (-fanalyzer): New driver option. 15526 * config.in: Regenerate. 15527 * configure: Regenerate. 15528 * configure.ac (--disable-analyzer, ENABLE_ANALYZER): New option. 15529 (gccdepdir): Also create depdir for "analyzer" subdir. 15530 * digraph.cc: New file. 15531 * digraph.h: New file. 15532 * doc/analyzer.texi: New file. 15533 * doc/gccint.texi ("Static Analyzer") New menu item. 15534 (analyzer.texi): Include it. 15535 * doc/invoke.texi ("Static Analyzer Options"): New list and new section. 15536 ("Warning Options"): Add static analysis warnings to the list. 15537 (-Wno-analyzer-double-fclose): New option. 15538 (-Wno-analyzer-double-free): New option. 15539 (-Wno-analyzer-exposure-through-output-file): New option. 15540 (-Wno-analyzer-file-leak): New option. 15541 (-Wno-analyzer-free-of-non-heap): New option. 15542 (-Wno-analyzer-malloc-leak): New option. 15543 (-Wno-analyzer-possible-null-argument): New option. 15544 (-Wno-analyzer-possible-null-dereference): New option. 15545 (-Wno-analyzer-null-argument): New option. 15546 (-Wno-analyzer-null-dereference): New option. 15547 (-Wno-analyzer-stale-setjmp-buffer): New option. 15548 (-Wno-analyzer-tainted-array-index): New option. 15549 (-Wno-analyzer-use-after-free): New option. 15550 (-Wno-analyzer-use-of-pointer-in-stale-stack-frame): New option. 15551 (-Wno-analyzer-use-of-uninitialized-value): New option. 15552 (-Wanalyzer-too-complex): New option. 15553 (-fanalyzer-call-summaries): New warning. 15554 (-fanalyzer-checker=): New warning. 15555 (-fanalyzer-fine-grained): New warning. 15556 (-fno-analyzer-state-merge): New warning. 15557 (-fno-analyzer-state-purge): New warning. 15558 (-fanalyzer-transitivity): New warning. 15559 (-fanalyzer-verbose-edges): New warning. 15560 (-fanalyzer-verbose-state-changes): New warning. 15561 (-fanalyzer-verbosity=): New warning. 15562 (-fdump-analyzer): New warning. 15563 (-fdump-analyzer-callgraph): New warning. 15564 (-fdump-analyzer-exploded-graph): New warning. 15565 (-fdump-analyzer-exploded-nodes): New warning. 15566 (-fdump-analyzer-exploded-nodes-2): New warning. 15567 (-fdump-analyzer-exploded-nodes-3): New warning. 15568 (-fdump-analyzer-supergraph): New warning. 15569 * doc/sourcebuild.texi (dg-require-dot): New. 15570 (dg-check-dot): New. 15571 * gdbinit.in (break-on-saved-diagnostic): New command. 15572 * graphviz.cc: New file. 15573 * graphviz.h: New file. 15574 * ordered-hash-map-tests.cc: New file. 15575 * ordered-hash-map.h: New file. 15576 * passes.def (pass_analyzer): Add before 15577 pass_ipa_whole_program_visibility. 15578 * selftest-run-tests.c (selftest::run_tests): Call 15579 selftest::ordered_hash_map_tests_cc_tests. 15580 * selftest.h (selftest::ordered_hash_map_tests_cc_tests): New 15581 decl. 15582 * shortest-paths.h: New file. 15583 * timevar.def (TV_ANALYZER): New timevar. 15584 (TV_ANALYZER_SUPERGRAPH): Likewise. 15585 (TV_ANALYZER_STATE_PURGE): Likewise. 15586 (TV_ANALYZER_PLAN): Likewise. 15587 (TV_ANALYZER_SCC): Likewise. 15588 (TV_ANALYZER_WORKLIST): Likewise. 15589 (TV_ANALYZER_DUMP): Likewise. 15590 (TV_ANALYZER_DIAGNOSTICS): Likewise. 15591 (TV_ANALYZER_SHORTEST_PATHS): Likewise. 15592 * tree-pass.h (make_pass_analyzer): New decl. 15593 * tristate.cc: New file. 15594 * tristate.h: New file. 15595 155962020-01-14 Uroš Bizjak <ubizjak@gmail.com> 15597 15598 PR target/93254 15599 * config/i386/i386.md (*movsf_internal): Require SSE2 ISA for 15600 alternatives 9 and 10. 15601 156022020-01-14 David Malcolm <dmalcolm@redhat.com> 15603 15604 * attribs.c (excl_hash_traits::empty_zero_p): New static constant. 15605 * gcov.c (function_start_pair_hash::empty_zero_p): Likewise. 15606 * graphite.c (struct sese_scev_hash::empty_zero_p): Likewise. 15607 * hash-map-tests.c (selftest::test_nonzero_empty_key): New selftest. 15608 (selftest::hash_map_tests_c_tests): Call it. 15609 * hash-map-traits.h (simple_hashmap_traits::empty_zero_p): 15610 New static constant, using the value of = H::empty_zero_p. 15611 (unbounded_hashmap_traits::empty_zero_p): Likewise, using the value 15612 from default_hash_traits <Value>. 15613 * hash-map.h (hash_map::empty_zero_p): Likewise, using the value 15614 from Traits. 15615 * hash-set-tests.c (value_hash_traits::empty_zero_p): Likewise. 15616 * hash-table.h (hash_table::alloc_entries): Guard the loop of 15617 calls to mark_empty with !Descriptor::empty_zero_p. 15618 (hash_table::empty_slow): Conditionalize the memset call with a 15619 check that Descriptor::empty_zero_p; otherwise, loop through the 15620 entries calling mark_empty on them. 15621 * hash-traits.h (int_hash::empty_zero_p): New static constant. 15622 (pointer_hash::empty_zero_p): Likewise. 15623 (pair_hash::empty_zero_p): Likewise. 15624 * ipa-devirt.c (default_hash_traits <type_pair>::empty_zero_p): 15625 Likewise. 15626 * ipa-prop.c (ipa_bit_ggc_hash_traits::empty_zero_p): Likewise. 15627 (ipa_vr_ggc_hash_traits::empty_zero_p): Likewise. 15628 * profile.c (location_triplet_hash::empty_zero_p): Likewise. 15629 * sanopt.c (sanopt_tree_triplet_hash::empty_zero_p): Likewise. 15630 (sanopt_tree_couple_hash::empty_zero_p): Likewise. 15631 * tree-hasher.h (int_tree_hasher::empty_zero_p): Likewise. 15632 * tree-ssa-sccvn.c (vn_ssa_aux_hasher::empty_zero_p): Likewise. 15633 * tree-vect-slp.c (bst_traits::empty_zero_p): Likewise. 15634 * tree-vectorizer.h 15635 (default_hash_traits<scalar_cond_masked_key>::empty_zero_p): 15636 Likewise. 15637 156382020-01-14 Kewen Lin <linkw@gcc.gnu.org> 15639 15640 * cfgloopanal.c (average_num_loop_insns): Free bbs when early return, 15641 fix typo on return value. 15642 156432020-01-14 Xiong Hu Luo <luoxhu@linux.ibm.com> 15644 15645 PR ipa/69678 15646 * cgraph.c (symbol_table::create_edge): Init speculative_id and 15647 target_prob. 15648 (cgraph_edge::make_speculative): Add param for setting speculative_id 15649 and target_prob. 15650 (cgraph_edge::speculative_call_info): Update comments and find reference 15651 by speculative_id for multiple indirect targets. 15652 (cgraph_edge::resolve_speculation): Decrease the speculations 15653 for indirect edge, drop it's speculative if not direct target 15654 left. Update comments. 15655 (cgraph_edge::redirect_call_stmt_to_callee): Likewise. 15656 (cgraph_node::dump): Print num_speculative_call_targets. 15657 (cgraph_node::verify_node): Don't report error if speculative 15658 edge not include statement. 15659 (cgraph_edge::num_speculative_call_targets_p): New function. 15660 * cgraph.h (int common_target_id): Remove. 15661 (int common_target_probability): Remove. 15662 (num_speculative_call_targets): New variable. 15663 (make_speculative): Add param for setting speculative_id. 15664 (cgraph_edge::num_speculative_call_targets_p): New declare. 15665 (target_prob): New variable. 15666 (speculative_id): New variable. 15667 * ipa-fnsummary.c (analyze_function_body): Create and duplicate 15668 call summaries for multiple speculative call targets. 15669 * cgraphclones.c (cgraph_node::create_clone): Clone speculative_id. 15670 * ipa-profile.c (struct speculative_call_target): New struct. 15671 (class speculative_call_summary): New class. 15672 (class speculative_call_summaries): New class. 15673 (call_sums): New variable. 15674 (ipa_profile_generate_summary): Generate indirect multiple targets summaries. 15675 (ipa_profile_write_edge_summary): New function. 15676 (ipa_profile_write_summary): Stream out indirect multiple targets summaries. 15677 (ipa_profile_dump_all_summaries): New function. 15678 (ipa_profile_read_edge_summary): New function. 15679 (ipa_profile_read_summary_section): New function. 15680 (ipa_profile_read_summary): Stream in indirect multiple targets summaries. 15681 (ipa_profile): Generate num_speculative_call_targets from 15682 profile summaries. 15683 * ipa-ref.h (speculative_id): New variable. 15684 * ipa-utils.c (ipa_merge_profiles): Update with target_prob. 15685 * lto-cgraph.c (lto_output_edge): Remove indirect common_target_id and 15686 common_target_probability. Stream out speculative_id and 15687 num_speculative_call_targets. 15688 (input_edge): Likewise. 15689 * predict.c (dump_prediction): Remove edges count assert to be 15690 precise. 15691 * symtab.c (symtab_node::create_reference): Init speculative_id. 15692 (symtab_node::clone_references): Clone speculative_id. 15693 (symtab_node::clone_referring): Clone speculative_id. 15694 (symtab_node::clone_reference): Clone speculative_id. 15695 (symtab_node::clear_stmts_in_references): Clear speculative_id. 15696 * tree-inline.c (copy_bb): Duplicate all the speculative edges 15697 if indirect call contains multiple speculative targets. 15698 * value-prof.h (check_ic_target): Remove. 15699 * value-prof.c (gimple_value_profile_transformations): 15700 Use void function gimple_ic_transform. 15701 * value-prof.c (gimple_ic_transform): Handle topn case. 15702 Fix comment typos. Change it to a void function. 15703 157042020-01-13 Andrew Pinski <apinski@marvell.com> 15705 15706 * config/aarch64/aarch64-cores.def (octeontx2): New define. 15707 (octeontx2t98): New define. 15708 (octeontx2t96): New define. 15709 (octeontx2t93): New define. 15710 (octeontx2f95): New define. 15711 (octeontx2f95n): New define. 15712 (octeontx2f95mm): New define. 15713 * config/aarch64/aarch64-tune.md: Regenerate. 15714 * doc/invoke.texi (-mcpu=): Document the new cpu types. 15715 157162020-01-13 Jason Merrill <jason@redhat.com> 15717 15718 PR c++/33799 - destroy return value if local cleanup throws. 15719 * gimplify.c (gimplify_return_expr): Handle COMPOUND_EXPR. 15720 157212020-01-13 Martin Liska <mliska@suse.cz> 15722 15723 * ipa-cp.c (get_max_overall_size): Use newly 15724 renamed param param_ipa_cp_unit_growth. 15725 * params.opt: Remove legacy param name. 15726 157272020-01-13 Martin Sebor <msebor@redhat.com> 15728 15729 PR tree-optimization/93213 15730 * tree-ssa-strlen.c (handle_store): Only allow single-byte nul-over-nul 15731 stores to be eliminated. 15732 157332020-01-13 Martin Liska <mliska@suse.cz> 15734 15735 * opts.c (print_help): Do not print CL_PARAM 15736 and CL_WARNING for CL_OPTIMIZATION. 15737 157382020-01-13 Jonathan Wakely <jwakely@redhat.com> 15739 15740 PR driver/92757 15741 * doc/invoke.texi (Warning Options): Add caveat about some warnings 15742 depending on optimization settings. 15743 157442020-01-13 Jakub Jelinek <jakub@redhat.com> 15745 15746 PR tree-optimization/90838 15747 * tree-ssa-forwprop.c (simplify_count_trailing_zeroes): Use 15748 SCALAR_INT_TYPE_MODE directly in CTZ_DEFINED_VALUE_AT_ZERO macro 15749 argument rather than to initialize temporary for targets that 15750 don't use the mode argument at all. Initialize ctzval to avoid 15751 warning at -O0. 15752 157532020-01-10 Thomas Schwinge <thomas@codesourcery.com> 15754 15755 * tree.h (OMP_CLAUSE_USE_DEVICE_PTR_IF_PRESENT): New definition. 15756 * tree-core.h: Document it. 15757 * gimplify.c (gimplify_omp_workshare): Set it. 15758 * omp-low.c (lower_omp_target): Use it. 15759 * tree-pretty-print.c (dump_omp_clause): Print it. 15760 15761 * omp-low.c (lower_omp_target) <OMP_CLAUSE_USE_DEVICE_PTR etc.>: 15762 Assert that for OpenACC we always have 'GOMP_MAP_USE_DEVICE_PTR'. 15763 157642020-01-10 David Malcolm <dmalcolm@redhat.com> 15765 15766 * Makefile.in (OBJS): Add tree-diagnostic-path.o. 15767 * common.opt (fdiagnostics-path-format=): New option. 15768 (diagnostic_path_format): New enum. 15769 (fdiagnostics-show-path-depths): New option. 15770 * coretypes.h (diagnostic_event_id_t): New forward decl. 15771 * diagnostic-color.c (color_dict): Add "path". 15772 * diagnostic-event-id.h: New file. 15773 * diagnostic-format-json.cc (json_from_expanded_location): Make 15774 non-static. 15775 (json_end_diagnostic): Call context->make_json_for_path if it 15776 exists and the diagnostic has a path. 15777 (diagnostic_output_format_init): Clear context->print_path. 15778 * diagnostic-path.h: New file. 15779 * diagnostic-show-locus.c (colorizer::set_range): Special-case 15780 when printing a run of events in a diagnostic_path so that they 15781 all get the same color. 15782 (layout::m_diagnostic_path_p): New field. 15783 (layout::layout): Initialize it. 15784 (layout::print_any_labels): Don't colorize the label text for an 15785 event in a diagnostic_path. 15786 (gcc_rich_location::add_location_if_nearby): Add 15787 "restrict_to_current_line_spans" and "label" params. Pass the 15788 former to layout.maybe_add_location_range; pass the latter 15789 when calling add_range. 15790 * diagnostic.c: Include "diagnostic-path.h". 15791 (diagnostic_initialize): Initialize context->path_format and 15792 context->show_path_depths. 15793 (diagnostic_show_any_path): New function. 15794 (diagnostic_path::interprocedural_p): New function. 15795 (diagnostic_report_diagnostic): Call diagnostic_show_any_path. 15796 (simple_diagnostic_path::num_events): New function. 15797 (simple_diagnostic_path::get_event): New function. 15798 (simple_diagnostic_path::add_event): New function. 15799 (simple_diagnostic_event::simple_diagnostic_event): New ctor. 15800 (simple_diagnostic_event::~simple_diagnostic_event): New dtor. 15801 (debug): New overload taking a diagnostic_path *. 15802 * diagnostic.def (DK_DIAGNOSTIC_PATH): New. 15803 * diagnostic.h (enum diagnostic_path_format): New enum. 15804 (json::value): New forward decl. 15805 (diagnostic_context::path_format): New field. 15806 (diagnostic_context::show_path_depths): New field. 15807 (diagnostic_context::print_path): New callback field. 15808 (diagnostic_context::make_json_for_path): New callback field. 15809 (diagnostic_show_any_path): New decl. 15810 (json_from_expanded_location): New decl. 15811 * doc/invoke.texi (-fdiagnostics-path-format=): New option. 15812 (-fdiagnostics-show-path-depths): New option. 15813 (-fdiagnostics-color): Add "path" to description of default 15814 GCC_COLORS; describe it. 15815 (-fdiagnostics-format=json): Document how diagnostic paths are 15816 represented in the JSON output format. 15817 * gcc-rich-location.h (gcc_rich_location::add_location_if_nearby): 15818 Add optional params "restrict_to_current_line_spans" and "label". 15819 * opts.c (common_handle_option): Handle 15820 OPT_fdiagnostics_path_format_ and 15821 OPT_fdiagnostics_show_path_depths. 15822 * pretty-print.c: Include "diagnostic-event-id.h". 15823 (pp_format): Implement "%@" format code for printing 15824 diagnostic_event_id_t *. 15825 (selftest::test_pp_format): Add tests for "%@". 15826 * selftest-run-tests.c (selftest::run_tests): Call 15827 selftest::tree_diagnostic_path_cc_tests. 15828 * selftest.h (selftest::tree_diagnostic_path_cc_tests): New decl. 15829 * toplev.c (general_init): Initialize global_dc->path_format and 15830 global_dc->show_path_depths. 15831 * tree-diagnostic-path.cc: New file. 15832 * tree-diagnostic.c (maybe_unwind_expanded_macro_loc): Make 15833 non-static. Drop "diagnostic" param in favor of storing the 15834 original value of "where" and re-using it. 15835 (virt_loc_aware_diagnostic_finalizer): Update for dropped param of 15836 maybe_unwind_expanded_macro_loc. 15837 (tree_diagnostics_defaults): Initialize context->print_path and 15838 context->make_json_for_path. 15839 * tree-diagnostic.h (default_tree_diagnostic_path_printer): New 15840 decl. 15841 (default_tree_make_json_for_path): New decl. 15842 (maybe_unwind_expanded_macro_loc): New decl. 15843 158442020-01-10 Jakub Jelinek <jakub@redhat.com> 15845 15846 PR tree-optimization/93210 15847 * fold-const.h (native_encode_initializer, 15848 can_native_interpret_type_p): Declare. 15849 * fold-const.c (native_encode_string): Fix up handling with off != -1, 15850 simplify. 15851 (native_encode_initializer): New function, moved from dwarf2out.c. 15852 Adjust to native_encode_expr compatible arguments, including dry-run 15853 and partial extraction modes. Don't handle STRING_CST. 15854 (can_native_interpret_type_p): No longer static. 15855 * gimple-fold.c (fold_ctor_reference): For native_encode_expr, verify 15856 offset / BITS_PER_UNIT fits into int and don't call it if 15857 can_native_interpret_type_p fails. If suboff is NULL and for 15858 CONSTRUCTOR fold_{,non}array_ctor_reference returns NULL, retry with 15859 native_encode_initializer. 15860 (fold_const_aggregate_ref_1): Formatting fix. 15861 * dwarf2out.c (native_encode_initializer): Moved to fold-const.c. 15862 (tree_add_const_value_attribute): Adjust caller. 15863 15864 PR tree-optimization/90838 15865 * tree-ssa-forwprop.c (simplify_count_trailing_zeroes): Use 15866 SCALAR_INT_TYPE_MODE instead of TYPE_MODE as operand of 15867 CTZ_DEFINED_VALUE_AT_ZERO. 15868 158692020-01-10 Vladimir Makarov <vmakarov@redhat.com> 15870 15871 PR inline-asm/93027 15872 * lra-constraints.c (match_reload): Permit input operands have the 15873 same mode as output while other input operands have a different 15874 mode. 15875 158762020-01-10 Wilco Dijkstra <wdijkstr@arm.com> 15877 15878 PR tree-optimization/90838 15879 * tree-ssa-forwprop.c (check_ctz_array): Add new function. 15880 (check_ctz_string): Likewise. 15881 (optimize_count_trailing_zeroes): Likewise. 15882 (simplify_count_trailing_zeroes): Likewise. 15883 (pass_forwprop::execute): Try ctz simplification. 15884 * match.pd: Add matching for ctz idioms. 15885 158862020-01-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> 15887 15888 * config/aarch64/aarch64.c (aarch64_invalid_conversion): New function 15889 for target hook. 15890 (aarch64_invalid_unary_op): New function for target hook. 15891 (aarch64_invalid_binary_op): New function for target hook. 15892 158932020-01-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> 15894 15895 * config.gcc: Add arm_bf16.h. 15896 * config/aarch64/aarch64-builtins.c 15897 (aarch64_simd_builtin_std_type): Add BFmode. 15898 (aarch64_init_simd_builtin_types): Define element types for vector 15899 types. 15900 (aarch64_init_bf16_types): New function. 15901 (aarch64_general_init_builtins): Add arm_init_bf16_types function call. 15902 * config/aarch64/aarch64-modes.def: Add BFmode and V4BF, V8BF vector 15903 modes. 15904 * config/aarch64/aarch64-simd-builtin-types.def: Add BF SIMD types. 15905 * config/aarch64/aarch64-simd.md: Add BF vector types to NEON move 15906 patterns. 15907 * config/aarch64/aarch64.h (AARCH64_VALID_SIMD_DREG_MODE): Add V4BF. 15908 (AARCH64_VALID_SIMD_QREG_MODE): Add V8BF. 15909 * config/aarch64/aarch64.c 15910 (aarch64_classify_vector_mode): Add support for BF types. 15911 (aarch64_gimplify_va_arg_expr): Add support for BF types. 15912 (aarch64_vq_mode): Add support for BF types. 15913 (aarch64_simd_container_mode): Add support for BF types. 15914 (aarch64_mangle_type): Add support for BF scalar type. 15915 * config/aarch64/aarch64.md: Add BFmode to movhf pattern. 15916 * config/aarch64/arm_bf16.h: New file. 15917 * config/aarch64/arm_neon.h: Add arm_bf16.h and Bfloat vector types. 15918 * config/aarch64/iterators.md: Add BF types to mode attributes. 15919 (HFBF, GPF_TF_F16_MOV, VDMOV, VQMOV, VQMOV_NO2Em VALL_F16MOV): New. 15920 159212020-01-10 Jason Merrill <jason@redhat.com> 15922 15923 PR c++/93173 - incorrect tree sharing. 15924 * gimplify.c (copy_if_shared): No longer static. 15925 * gimplify.h: Declare it. 15926 159272020-01-10 Richard Sandiford <richard.sandiford@arm.com> 15928 15929 * doc/invoke.texi (-msve-vector-bits=): Document that 15930 -msve-vector-bits=128 now generates VL-specific code for 15931 little-endian targets. 15932 * config/aarch64/aarch64-sve-builtins.cc (register_builtin_types): Use 15933 build_vector_type_for_mode to construct the data vector types. 15934 * config/aarch64/aarch64.c (aarch64_convert_sve_vector_bits): Generate 15935 VL-specific code for -msve-vector-bits=128 on little-endian targets. 15936 (aarch64_simd_container_mode): Always prefer Advanced SIMD modes 15937 for 128-bit vectors. 15938 159392020-01-10 Richard Sandiford <richard.sandiford@arm.com> 15940 15941 * config/aarch64/aarch64.c (aarch64_evpc_sel): Fix gen_vcond_mask 15942 invocation. 15943 159442020-01-10 Richard Sandiford <richard.sandiford@arm.com> 15945 15946 * config/aarch64/aarch64-builtins.c 15947 (aarch64_builtin_vectorized_function): Check for specific vector modes, 15948 rather than checking the number of elements and the element mode. 15949 159502020-01-10 Richard Sandiford <richard.sandiford@arm.com> 15951 15952 * tree-vect-loop.c (vect_create_epilog_for_reduction): Use 15953 get_related_vectype_for_scalar_type rather than build_vector_type 15954 to create the index type for a conditional reduction. 15955 159562020-01-10 Richard Sandiford <richard.sandiford@arm.com> 15957 15958 * tree-vect-loop.c (update_epilogue_loop_vinfo): Update DR_REF 15959 for any type of gather or scatter, including strided accesses. 15960 159612020-01-10 Andre Vieira <andre.simoesdiasvieira@arm.com> 15962 15963 * tree-vectorizer.h (get_dr_vinfo_offset): Add missing function 15964 comment. 15965 159662020-01-10 Andre Vieira <andre.simoesdiasvieira@arm.com> 15967 15968 * tree-vect-data-refs.c (vect_create_addr_base_for_vector_ref): Use 15969 get_dr_vinfo_offset 15970 * tree-vect-loop.c (update_epilogue_loop_vinfo): Remove orig_drs_init 15971 parameter and its use to reset DR_OFFSET's. 15972 (vect_transform_loop): Remove orig_drs_init argument. 15973 * tree-vect-loop-manip.c (vect_update_init_of_dr): Update the offset 15974 member of dr_vec_info rather than the offset of the associated 15975 data_reference's innermost_loop_behavior. 15976 (vect_update_init_of_dr): Pass dr_vec_info instead of data_reference. 15977 (vect_do_peeling): Remove orig_drs_init parameter and its construction. 15978 * tree-vect-stmts.c (check_scan_store): Replace use of DR_OFFSET with 15979 get_dr_vinfo_offset. 15980 (vectorizable_store): Likewise. 15981 (vectorizable_load): Likewise. 15982 159832020-01-10 Richard Biener <rguenther@suse.de> 15984 15985 * gimple-ssa-store-merging 15986 (pass_store_merging::terminate_all_aliasing_chains): Cache alias info. 15987 159882020-01-10 Martin Liska <mliska@suse.cz> 15989 15990 PR ipa/93217 15991 * ipa-inline-analysis.c (offline_size): Make proper parenthesis 15992 encapsulation that was there before r280040. 15993 159942020-01-10 Richard Biener <rguenther@suse.de> 15995 15996 PR middle-end/93199 15997 * tree-eh.c (sink_clobbers): Move clobbers to out-of-IL 15998 sequences to avoid walking them again for secondary opportunities. 15999 (pass_lower_eh_dispatch::execute): Instead actually insert 16000 them here. 16001 160022020-01-10 Richard Biener <rguenther@suse.de> 16003 16004 PR middle-end/93199 16005 * tree-eh.c (redirect_eh_edge_1): Avoid some work if possible. 16006 (cleanup_all_empty_eh): Walk landing pads in reverse order to 16007 avoid quadraticness. 16008 160092020-01-10 Martin Jambor <mjambor@suse.cz> 16010 16011 * params.opt (param_ipa_sra_max_replacements): Mark as Optimization. 16012 * ipa-sra.c (pull_accesses_from_callee): New parameter caller, use it 16013 to get param_ipa_sra_max_replacements. 16014 (param_splitting_across_edge): Pass the caller to 16015 pull_accesses_from_callee. 16016 160172020-01-10 Martin Jambor <mjambor@suse.cz> 16018 16019 * params.opt (param_ipcp_unit_growth): Mark as Optimization. 16020 * ipa-cp.c (max_new_size): Removed. 16021 (orig_overall_size): New variable. 16022 (get_max_overall_size): New function. 16023 (estimate_local_effects): Use it. Adjust dump. 16024 (decide_about_value): Likewise. 16025 (ipcp_propagate_stage): Do not calculate max_new_size, just store 16026 orig_overall_size. Adjust dump. 16027 (ipa_cp_c_finalize): Clear orig_overall_size instead of max_new_size. 16028 160292020-01-10 Martin Jambor <mjambor@suse.cz> 16030 16031 * params.opt (param_ipa_max_agg_items): Mark as Optimization 16032 * ipa-cp.c (merge_agg_lats_step): New parameter max_agg_items, use 16033 instead of param_ipa_max_agg_items. 16034 (merge_aggregate_lattices): Extract param_ipa_max_agg_items from 16035 optimization info for the callee. 16036 160372020-01-09 Kwok Cheung Yeung <kcy@codesourcery.com> 16038 16039 * lto-streamer-in.c (input_function): Remove streamed-in inline debug 16040 markers if debug_inline_points is false. 16041 160422020-01-09 Richard Sandiford <richard.sandiford@arm.com> 16043 16044 * config.gcc (aarch64*-*-*): Add aarch64-sve-builtins-sve2.o to 16045 extra_objs. 16046 * config/aarch64/t-aarch64 (aarch64-sve-builtins.o): Depend on 16047 aarch64-sve-builtins-base.def, aarch64-sve-builtins-sve2.def and 16048 aarch64-sve-builtins-sve2.h. 16049 (aarch64-sve-builtins-sve2.o): New rule. 16050 * config/aarch64/aarch64.h (AARCH64_ISA_SVE2_AES): New macro. 16051 (AARCH64_ISA_SVE2_BITPERM, AARCH64_ISA_SVE2_SHA3): Likewise. 16052 (AARCH64_ISA_SVE2_SM4, TARGET_SVE2_AES, TARGET_SVE2_BITPERM): Likewise. 16053 (TARGET_SVE2_SHA, TARGET_SVE2_SM4): Likewise. 16054 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Handle 16055 TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3 and 16056 TARGET_SVE2_SM4. 16057 * config/aarch64/aarch64-sve.md: Update comments with SVE2 16058 instructions that are handled here. 16059 (@cond_asrd<mode>): Generalize to... 16060 (@cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>): ...this. 16061 (*cond_asrd<mode>_2): Generalize to... 16062 (*cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>_2): ...this. 16063 (*cond_asrd<mode>_z): Generalize to... 16064 (*cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>_z): ...this. 16065 * config/aarch64/aarch64.md (UNSPEC_LDNT1_GATHER): New unspec. 16066 (UNSPEC_STNT1_SCATTER, UNSPEC_WHILEGE, UNSPEC_WHILEGT): Likewise. 16067 (UNSPEC_WHILEHI, UNSPEC_WHILEHS): Likewise. 16068 * config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt<mode>): New 16069 pattern. 16070 (@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>) 16071 (@aarch64_scatter_stnt<mode>): Likewise. 16072 (@aarch64_scatter_stnt_<SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>) 16073 (@aarch64_mul_lane_<mode>): Likewise. 16074 (@aarch64_sve_suqadd<mode>_const): Likewise. 16075 (*<sur>h<addsub><mode>): Generalize to... 16076 (@aarch64_pred_<SVE2_COND_INT_BINARY_REV:sve_int_op><mode>): ...this 16077 new pattern. 16078 (@cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>): New expander. 16079 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_2): New pattern. 16080 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_3): Likewise. 16081 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_any): Likewise. 16082 (*cond_<SVE2_COND_INT_BINARY_NOREV:sve_int_op><mode>_z): Likewise. 16083 (@aarch64_sve_<SVE2_INT_BINARY:sve_int_op><mode>):: Likewise. 16084 (@aarch64_sve_<SVE2_INT_BINARY:sve_int_op>_lane_<mode>): Likewise. 16085 (@aarch64_pred_<SVE2_COND_INT_SHIFT:sve_int_op><mode>): Likewise. 16086 (@cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>): New expander. 16087 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_2): New pattern. 16088 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_3): Likewise. 16089 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_any): Likewise. 16090 (@aarch64_sve_<SVE2_INT_TERNARY:sve_int_op><mode>): Likewise. 16091 (@aarch64_sve_<SVE2_INT_TERNARY_LANE:sve_int_op>_lane_<mode>) 16092 (@aarch64_sve_add_mul_lane_<mode>): Likewise. 16093 (@aarch64_sve_sub_mul_lane_<mode>): Likewise. 16094 (@aarch64_sve2_xar<mode>): Likewise. 16095 (@aarch64_sve2_bcax<mode>): Likewise. 16096 (*aarch64_sve2_eor3<mode>): Rename to... 16097 (@aarch64_sve2_eor3<mode>): ...this. 16098 (@aarch64_sve2_bsl<mode>): New expander. 16099 (@aarch64_sve2_nbsl<mode>): Likewise. 16100 (@aarch64_sve2_bsl1n<mode>): Likewise. 16101 (@aarch64_sve2_bsl2n<mode>): Likewise. 16102 (@aarch64_sve_add_<SHIFTRT:sve_int_op><mode>): Likewise. 16103 (*aarch64_sve2_sra<mode>): Add MOVPRFX support. 16104 (@aarch64_sve_add_<VRSHR_N:sve_int_op><mode>): New pattern. 16105 (@aarch64_sve_<SVE2_INT_SHIFT_INSERT:sve_int_op><mode>): Likewise. 16106 (@aarch64_sve2_<USMAX:su>aba<mode>): New expander. 16107 (*aarch64_sve2_<USMAX:su>aba<mode>): New pattern. 16108 (@aarch64_sve_<SVE2_INT_BINARY_WIDE:sve_int_op><mode>): Likewise. 16109 (<su>mull<bt><Vwide>): Generalize to... 16110 (@aarch64_sve_<SVE2_INT_BINARY_LONG:sve_int_op><mode>): ...this new 16111 pattern. 16112 (@aarch64_sve_<SVE2_INT_BINARY_LONG_lANE:sve_int_op>_lane_<mode>) 16113 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_LONG:sve_int_op><mode>) 16114 (@aarch64_sve_add_<SVE2_INT_ADD_BINARY_LONG:sve_int_op><mode>) 16115 (@aarch64_sve_add_<SVE2_INT_ADD_BINARY_LONG_LANE:sve_int_op>_lane_<mode>) 16116 (@aarch64_sve_qadd_<SVE2_INT_QADD_BINARY_LONG:sve_int_op><mode>) 16117 (@aarch64_sve_qadd_<SVE2_INT_QADD_BINARY_LONG_LANE:sve_int_op>_lane_<mode>) 16118 (@aarch64_sve_sub_<SVE2_INT_SUB_BINARY_LONG:sve_int_op><mode>) 16119 (@aarch64_sve_sub_<SVE2_INT_SUB_BINARY_LONG_LANE:sve_int_op>_lane_<mode>) 16120 (@aarch64_sve_qsub_<SVE2_INT_QSUB_BINARY_LONG:sve_int_op><mode>) 16121 (@aarch64_sve_qsub_<SVE2_INT_QSUB_BINARY_LONG_LANE:sve_int_op>_lane_<mode>) 16122 (@aarch64_sve_<SVE2_FP_TERNARY_LONG:sve_fp_op><mode>): New patterns. 16123 (@aarch64_<SVE2_FP_TERNARY_LONG_LANE:sve_fp_op>_lane_<mode>) 16124 (@aarch64_sve_<SVE2_INT_UNARY_NARROWB:sve_int_op><mode>): Likewise. 16125 (@aarch64_sve_<SVE2_INT_UNARY_NARROWT:sve_int_op><mode>): Likewise. 16126 (@aarch64_sve_<SVE2_INT_BINARY_NARROWB:sve_int_op><mode>): Likewise. 16127 (@aarch64_sve_<SVE2_INT_BINARY_NARROWT:sve_int_op><mode>): Likewise. 16128 (<SHRNB:r>shrnb<mode>): Generalize to... 16129 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_NARROWB:sve_int_op><mode>): ...this 16130 new pattern. 16131 (<SHRNT:r>shrnt<mode>): Generalize to... 16132 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_NARROWT:sve_int_op><mode>): ...this 16133 new pattern. 16134 (@aarch64_pred_<SVE2_INT_BINARY_PAIR:sve_int_op><mode>): New pattern. 16135 (@aarch64_pred_<SVE2_FP_BINARY_PAIR:sve_fp_op><mode>): Likewise. 16136 (@cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>): New expander. 16137 (*cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>_2): New pattern. 16138 (*cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>_z): Likewise. 16139 (@aarch64_sve_<SVE2_INT_CADD:optab><mode>): Likewise. 16140 (@aarch64_sve_<SVE2_INT_CMLA:optab><mode>): Likewise. 16141 (@aarch64_<SVE2_INT_CMLA:optab>_lane_<mode>): Likewise. 16142 (@aarch64_sve_<SVE2_INT_CDOT:optab><mode>): Likewise. 16143 (@aarch64_<SVE2_INT_CDOT:optab>_lane_<mode>): Likewise. 16144 (@aarch64_pred_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): Likewise. 16145 (@cond_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): New expander. 16146 (*cond_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): New pattern. 16147 (@aarch64_sve2_cvtnt<mode>): Likewise. 16148 (@aarch64_pred_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>): Likewise. 16149 (@cond_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>): New expander. 16150 (*cond_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>_any): New pattern. 16151 (@aarch64_sve2_cvtxnt<mode>): Likewise. 16152 (@aarch64_pred_<SVE2_U32_UNARY:sve_int_op><mode>): Likewise. 16153 (@cond_<SVE2_U32_UNARY:sve_int_op><mode>): New expander. 16154 (*cond_<SVE2_U32_UNARY:sve_int_op><mode>): New pattern. 16155 (@aarch64_pred_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): Likewise. 16156 (@cond_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): New expander. 16157 (*cond_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): New pattern. 16158 (@aarch64_sve2_pmul<mode>): Likewise. 16159 (@aarch64_sve_<SVE2_PMULL:optab><mode>): Likewise. 16160 (@aarch64_sve_<SVE2_PMULL_PAIR:optab><mode>): Likewise. 16161 (@aarch64_sve2_tbl2<mode>): Likewise. 16162 (@aarch64_sve2_tbx<mode>): Likewise. 16163 (@aarch64_sve_<SVE2_INT_BITPERM:sve_int_op><mode>): Likewise. 16164 (@aarch64_sve2_histcnt<mode>): Likewise. 16165 (@aarch64_sve2_histseg<mode>): Likewise. 16166 (@aarch64_pred_<SVE2_MATCH:sve_int_op><mode>): Likewise. 16167 (*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_cc): Likewise. 16168 (*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_ptest): Likewise. 16169 (aarch64_sve2_aes<CRYPTO_AES:aes_op>): Likewise. 16170 (aarch64_sve2_aes<CRYPTO_AESMC:aesmc_op>): Likewise. 16171 (*aarch64_sve2_aese_fused, *aarch64_sve2_aesd_fused): Likewise. 16172 (aarch64_sve2_rax1, aarch64_sve2_sm4e, aarch64_sve2_sm4ekey): Likewise. 16173 (<su>mulh<r>s<mode>3): Update after above pattern name changes. 16174 * config/aarch64/iterators.md (VNx16QI_ONLY, VNx4SF_ONLY) 16175 (SVE_STRUCT2, SVE_FULL_BHI, SVE_FULL_HSI, SVE_FULL_HDI) 16176 (SVE2_PMULL_PAIR_I): New mode iterators. 16177 (UNSPEC_ADCLB, UNSPEC_ADCLT, UNSPEC_ADDHNB, UNSPEC_ADDHNT, UNSPEC_BDEP) 16178 (UNSPEC_BEXT, UNSPEC_BGRP, UNSPEC_CADD90, UNSPEC_CADD270, UNSPEC_CDOT) 16179 (UNSPEC_CDOT90, UNSPEC_CDOT180, UNSPEC_CDOT270, UNSPEC_CMLA) 16180 (UNSPEC_CMLA90, UNSPEC_CMLA180, UNSPEC_CMLA270, UNSPEC_COND_FCVTLT) 16181 (UNSPEC_COND_FCVTNT, UNSPEC_COND_FCVTX, UNSPEC_COND_FCVTXNT) 16182 (UNSPEC_COND_FLOGB, UNSPEC_EORBT, UNSPEC_EORTB, UNSPEC_FADDP) 16183 (UNSPEC_FMAXP, UNSPEC_FMAXNMP, UNSPEC_FMLALB, UNSPEC_FMLALT) 16184 (UNSPEC_FMLSLB, UNSPEC_FMLSLT, UNSPEC_FMINP, UNSPEC_FMINNMP) 16185 (UNSPEC_HISTCNT, UNSPEC_HISTSEG, UNSPEC_MATCH, UNSPEC_NMATCH) 16186 (UNSPEC_PMULLB, UNSPEC_PMULLB_PAIR, UNSPEC_PMULLT, UNSPEC_PMULLT_PAIR) 16187 (UNSPEC_RADDHNB, UNSPEC_RADDHNT, UNSPEC_RSUBHNB, UNSPEC_RSUBHNT) 16188 (UNSPEC_SLI, UNSPEC_SRI, UNSPEC_SABDLB, UNSPEC_SABDLT, UNSPEC_SADDLB) 16189 (UNSPEC_SADDLBT, UNSPEC_SADDLT, UNSPEC_SADDWB, UNSPEC_SADDWT) 16190 (UNSPEC_SBCLB, UNSPEC_SBCLT, UNSPEC_SMAXP, UNSPEC_SMINP) 16191 (UNSPEC_SQCADD90, UNSPEC_SQCADD270, UNSPEC_SQDMULLB, UNSPEC_SQDMULLBT) 16192 (UNSPEC_SQDMULLT, UNSPEC_SQRDCMLAH, UNSPEC_SQRDCMLAH90) 16193 (UNSPEC_SQRDCMLAH180, UNSPEC_SQRDCMLAH270, UNSPEC_SQRSHRNB) 16194 (UNSPEC_SQRSHRNT, UNSPEC_SQRSHRUNB, UNSPEC_SQRSHRUNT, UNSPEC_SQSHRNB) 16195 (UNSPEC_SQSHRNT, UNSPEC_SQSHRUNB, UNSPEC_SQSHRUNT, UNSPEC_SQXTNB) 16196 (UNSPEC_SQXTNT, UNSPEC_SQXTUNB, UNSPEC_SQXTUNT, UNSPEC_SSHLLB) 16197 (UNSPEC_SSHLLT, UNSPEC_SSUBLB, UNSPEC_SSUBLBT, UNSPEC_SSUBLT) 16198 (UNSPEC_SSUBLTB, UNSPEC_SSUBWB, UNSPEC_SSUBWT, UNSPEC_SUBHNB) 16199 (UNSPEC_SUBHNT, UNSPEC_TBL2, UNSPEC_UABDLB, UNSPEC_UABDLT) 16200 (UNSPEC_UADDLB, UNSPEC_UADDLT, UNSPEC_UADDWB, UNSPEC_UADDWT) 16201 (UNSPEC_UMAXP, UNSPEC_UMINP, UNSPEC_UQRSHRNB, UNSPEC_UQRSHRNT) 16202 (UNSPEC_UQSHRNB, UNSPEC_UQSHRNT, UNSPEC_UQXTNB, UNSPEC_UQXTNT) 16203 (UNSPEC_USHLLB, UNSPEC_USHLLT, UNSPEC_USUBLB, UNSPEC_USUBLT) 16204 (UNSPEC_USUBWB, UNSPEC_USUBWT): New unspecs. 16205 (UNSPEC_SMULLB, UNSPEC_SMULLT, UNSPEC_UMULLB, UNSPEC_UMULLT) 16206 (UNSPEC_SMULHS, UNSPEC_SMULHRS, UNSPEC_UMULHS, UNSPEC_UMULHRS) 16207 (UNSPEC_RSHRNB, UNSPEC_RSHRNT, UNSPEC_SHRNB, UNSPEC_SHRNT): Move 16208 further down file. 16209 (VNARROW, Ventype): New mode attributes. 16210 (Vewtype): Handle VNx2DI. Fix typo in comment. 16211 (VDOUBLE): New mode attribute. 16212 (sve_lane_con): Handle VNx8HI. 16213 (SVE_INT_UNARY): Include ss_abs and ss_neg for TARGET_SVE2. 16214 (SVE_INT_BINARY): Likewise ss_plus, us_plus, ss_minus and us_minus. 16215 (sve_int_op, sve_int_op_rev): Handle the above codes. 16216 (sve_pred_int_rhs2_operand): Likewise. 16217 (MULLBT, SHRNB, SHRNT): Delete. 16218 (SVE_INT_SHIFT_IMM): New int iterator. 16219 (SVE_WHILE): Add UNSPEC_WHILEGE, UNSPEC_WHILEGT, UNSPEC_WHILEHI 16220 and UNSPEC_WHILEHS for TARGET_SVE2. 16221 (SVE2_U32_UNARY, SVE2_INT_UNARY_NARROWB, SVE2_INT_UNARY_NARROWT) 16222 (SVE2_INT_BINARY, SVE2_INT_BINARY_LANE, SVE2_INT_BINARY_LONG) 16223 (SVE2_INT_BINARY_LONG_LANE, SVE2_INT_BINARY_NARROWB) 16224 (SVE2_INT_BINARY_NARROWT, SVE2_INT_BINARY_PAIR, SVE2_FP_BINARY_PAIR) 16225 (SVE2_INT_BINARY_PAIR_LONG, SVE2_INT_BINARY_WIDE): New int iterators. 16226 (SVE2_INT_SHIFT_IMM_LONG, SVE2_INT_SHIFT_IMM_NARROWB): Likewise. 16227 (SVE2_INT_SHIFT_IMM_NARROWT, SVE2_INT_SHIFT_INSERT, SVE2_INT_CADD) 16228 (SVE2_INT_BITPERM, SVE2_INT_TERNARY, SVE2_INT_TERNARY_LANE): Likewise. 16229 (SVE2_FP_TERNARY_LONG, SVE2_FP_TERNARY_LONG_LANE, SVE2_INT_CMLA) 16230 (SVE2_INT_CDOT, SVE2_INT_ADD_BINARY_LONG, SVE2_INT_QADD_BINARY_LONG) 16231 (SVE2_INT_SUB_BINARY_LONG, SVE2_INT_QSUB_BINARY_LONG): Likewise. 16232 (SVE2_INT_ADD_BINARY_LONG_LANE, SVE2_INT_QADD_BINARY_LONG_LANE) 16233 (SVE2_INT_SUB_BINARY_LONG_LANE, SVE2_INT_QSUB_BINARY_LONG_LANE) 16234 (SVE2_COND_INT_UNARY_FP, SVE2_COND_FP_UNARY_LONG): Likewise. 16235 (SVE2_COND_FP_UNARY_NARROWB, SVE2_COND_INT_BINARY): Likewise. 16236 (SVE2_COND_INT_BINARY_NOREV, SVE2_COND_INT_BINARY_REV): Likewise. 16237 (SVE2_COND_INT_SHIFT, SVE2_MATCH, SVE2_PMULL): Likewise. 16238 (optab): Handle the new unspecs. 16239 (su, r): Remove entries for UNSPEC_SHRNB, UNSPEC_SHRNT, UNSPEC_RSHRNB 16240 and UNSPEC_RSHRNT. 16241 (lr): Handle the new unspecs. 16242 (bt): Delete. 16243 (cmp_op, while_optab_cmp, sve_int_op): Handle the new unspecs. 16244 (sve_int_op_rev, sve_int_add_op, sve_int_qadd_op, sve_int_sub_op) 16245 (sve_int_qsub_op): New int attributes. 16246 (sve_fp_op, rot): Handle the new unspecs. 16247 * config/aarch64/aarch64-sve-builtins.h 16248 (function_resolver::require_matching_pointer_type): Declare. 16249 (function_resolver::resolve_unary): Add an optional boolean argument. 16250 (function_resolver::finish_opt_n_resolution): Add an optional 16251 type_suffix_index argument. 16252 (gimple_folder::redirect_call): Declare. 16253 (gimple_expander::prepare_gather_address_operands): Add an optional 16254 bool parameter. 16255 * config/aarch64/aarch64-sve-builtins.cc: Include 16256 aarch64-sve-builtins-sve2.h. 16257 (TYPES_b_unsigned, TYPES_b_integer, TYPES_bh_integer): New macros. 16258 (TYPES_bs_unsigned, TYPES_hs_signed, TYPES_hs_integer): Likewise. 16259 (TYPES_hd_unsigned, TYPES_hsd_signed): Likewise. 16260 (TYPES_hsd_integer): Use TYPES_hsd_signed. 16261 (TYPES_s_float_hsd_integer, TYPES_s_float_sd_integer): New macros. 16262 (TYPES_s_unsigned): Likewise. 16263 (TYPES_s_integer): Use TYPES_s_unsigned. 16264 (TYPES_sd_signed, TYPES_sd_unsigned): New macros. 16265 (TYPES_sd_integer): Use them. 16266 (TYPES_d_unsigned): New macro. 16267 (TYPES_d_integer): Use it. 16268 (TYPES_d_data, TYPES_cvt_long, TYPES_cvt_narrow_s): New macros. 16269 (TYPES_cvt_narrow): Likewise. 16270 (DEF_SVE_TYPES_ARRAY): Include the new types macros above. 16271 (preds_mx): New variable. 16272 (function_builder::add_overloaded_function): Allow the new feature 16273 set to be more restrictive than the original one. 16274 (function_resolver::infer_pointer_type): Remove qualifiers from 16275 the pointer type before printing it. 16276 (function_resolver::require_matching_pointer_type): New function. 16277 (function_resolver::resolve_sv_displacement): Handle functions 16278 that don't support 32-bit vector indices or svint32_t vector offsets. 16279 (function_resolver::finish_opt_n_resolution): Take the inferred type 16280 as a separate argument. 16281 (function_resolver::resolve_unary): Optionally treat all forms in 16282 the same way as normal merging functions. 16283 (gimple_folder::redirect_call): New function. 16284 (function_expander::prepare_gather_address_operands): Add an argument 16285 that says whether scaled forms are available. If they aren't, 16286 handle scaling of vector indices and don't add the extension and 16287 scaling operands. 16288 (function_expander::map_to_unspecs): If aarch64_sve isn't available, 16289 fall back to using cond_* instead. 16290 * config/aarch64/aarch64-sve-builtins-functions.h (rtx_code_function): 16291 Split out the member variables into... 16292 (rtx_code_function_base): ...this new base class. 16293 (rtx_code_function_rotated): Inherit rtx_code_function_base. 16294 (unspec_based_function): Split out the member variables into... 16295 (unspec_based_function_base): ...this new base class. 16296 (unspec_based_function_rotated): Inherit unspec_based_function_base. 16297 (unspec_based_function_exact_insn): New class. 16298 (unspec_based_add_function, unspec_based_add_lane_function) 16299 (unspec_based_lane_function, unspec_based_pred_function) 16300 (unspec_based_qadd_function, unspec_based_qadd_lane_function) 16301 (unspec_based_qsub_function, unspec_based_qsub_lane_function) 16302 (unspec_based_sub_function, unspec_based_sub_lane_function): New 16303 typedefs. 16304 (unspec_based_fused_function): New class. 16305 (unspec_based_mla_function, unspec_based_mls_function): New typedefs. 16306 (unspec_based_fused_lane_function): New class. 16307 (unspec_based_mla_lane_function, unspec_based_mls_lane_function): New 16308 typedefs. 16309 (CODE_FOR_MODE1): New macro. 16310 (fixed_insn_function): New class. 16311 (while_comparison): Likewise. 16312 * config/aarch64/aarch64-sve-builtins-shapes.h (binary_long_lane) 16313 (binary_long_opt_n, binary_narrowb_opt_n, binary_narrowt_opt_n) 16314 (binary_to_uint, binary_wide, binary_wide_opt_n, compare, compare_ptr) 16315 (load_ext_gather_index_restricted, load_ext_gather_offset_restricted) 16316 (load_gather_sv_restricted, shift_left_imm_long): Declare. 16317 (shift_left_imm_to_uint, shift_right_imm_narrowb): Likewise. 16318 (shift_right_imm_narrowt, shift_right_imm_narrowb_to_uint): Likewise. 16319 (shift_right_imm_narrowt_to_uint, store_scatter_index_restricted) 16320 (store_scatter_offset_restricted, tbl_tuple, ternary_long_lane) 16321 (ternary_long_opt_n, ternary_qq_lane_rotate, ternary_qq_rotate) 16322 (ternary_shift_left_imm, ternary_shift_right_imm, ternary_uint) 16323 (unary_convert_narrowt, unary_long, unary_narrowb, unary_narrowt) 16324 (unary_narrowb_to_uint, unary_narrowt_to_uint, unary_to_int): Likewise. 16325 * config/aarch64/aarch64-sve-builtins-shapes.cc (apply_predication): 16326 Also add an initial argument for unary_convert_narrowt, regardless 16327 of the predication type. 16328 (build_32_64): Allow loads and stores to specify MODE_none. 16329 (build_sv_index64, build_sv_uint_offset): New functions. 16330 (long_type_suffix): New function. 16331 (binary_imm_narrowb_base, binary_imm_narrowt_base): New classes. 16332 (binary_imm_long_base, load_gather_sv_base): Likewise. 16333 (shift_right_imm_narrow_wrapper, ternary_shift_imm_base): Likewise. 16334 (ternary_resize2_opt_n_base, ternary_resize2_lane_base): Likewise. 16335 (unary_narrowb_base, unary_narrowt_base): Likewise. 16336 (binary_long_lane_def, binary_long_lane): New shape. 16337 (binary_long_opt_n_def, binary_long_opt_n): Likewise. 16338 (binary_narrowb_opt_n_def, binary_narrowb_opt_n): Likewise. 16339 (binary_narrowt_opt_n_def, binary_narrowt_opt_n): Likewise. 16340 (binary_to_uint_def, binary_to_uint): Likewise. 16341 (binary_wide_def, binary_wide): Likewise. 16342 (binary_wide_opt_n_def, binary_wide_opt_n): Likewise. 16343 (compare_def, compare): Likewise. 16344 (compare_ptr_def, compare_ptr): Likewise. 16345 (load_ext_gather_index_restricted_def, 16346 load_ext_gather_index_restricted): Likewise. 16347 (load_ext_gather_offset_restricted_def, 16348 load_ext_gather_offset_restricted): Likewise. 16349 (load_gather_sv_def): Inherit from load_gather_sv_base. 16350 (load_gather_sv_restricted_def, load_gather_sv_restricted): New shape. 16351 (shift_left_imm_def, shift_left_imm): Likewise. 16352 (shift_left_imm_long_def, shift_left_imm_long): Likewise. 16353 (shift_left_imm_to_uint_def, shift_left_imm_to_uint): Likewise. 16354 (store_scatter_index_restricted_def, 16355 store_scatter_index_restricted): Likewise. 16356 (store_scatter_offset_restricted_def, 16357 store_scatter_offset_restricted): Likewise. 16358 (tbl_tuple_def, tbl_tuple): Likewise. 16359 (ternary_long_lane_def, ternary_long_lane): Likewise. 16360 (ternary_long_opt_n_def, ternary_long_opt_n): Likewise. 16361 (ternary_qq_lane_def): Inherit from ternary_resize2_lane_base. 16362 (ternary_qq_lane_rotate_def, ternary_qq_lane_rotate): New shape 16363 (ternary_qq_opt_n_def): Inherit from ternary_resize2_opt_n_base. 16364 (ternary_qq_rotate_def, ternary_qq_rotate): New shape. 16365 (ternary_shift_left_imm_def, ternary_shift_left_imm): Likewise. 16366 (ternary_shift_right_imm_def, ternary_shift_right_imm): Likewise. 16367 (ternary_uint_def, ternary_uint): Likewise. 16368 (unary_convert): Fix typo in comment. 16369 (unary_convert_narrowt_def, unary_convert_narrowt): New shape. 16370 (unary_long_def, unary_long): Likewise. 16371 (unary_narrowb_def, unary_narrowb): Likewise. 16372 (unary_narrowt_def, unary_narrowt): Likewise. 16373 (unary_narrowb_to_uint_def, unary_narrowb_to_uint): Likewise. 16374 (unary_narrowt_to_uint_def, unary_narrowt_to_uint): Likewise. 16375 (unary_to_int_def, unary_to_int): Likewise. 16376 * config/aarch64/aarch64-sve-builtins-base.cc (unspec_cmla) 16377 (unspec_fcmla, unspec_cond_fcmla, expand_mla_mls_lane): New functions. 16378 (svasrd_impl): Delete. 16379 (svcadd_impl::expand): Handle integer operations too. 16380 (svcmla_impl::expand, svcmla_lane::expand): Likewise, using the 16381 new functions to derive the unspec numbers. 16382 (svmla_svmls_lane_impl): Replace with... 16383 (svmla_lane_impl, svmls_lane_impl): ...these new classes. Handle 16384 integer operations too. 16385 (svwhile_impl): Rename to... 16386 (svwhilelx_impl): ...this and inherit from while_comparison. 16387 (svasrd): Use unspec_based_function. 16388 (svmla_lane): Use svmla_lane_impl. 16389 (svmls_lane): Use svmls_lane_impl. 16390 (svrecpe, svrsqrte): Handle unsigned integer operations too. 16391 (svwhilele, svwhilelt): Use svwhilelx_impl. 16392 * config/aarch64/aarch64-sve-builtins-sve2.h: New file. 16393 * config/aarch64/aarch64-sve-builtins-sve2.cc: Likewise. 16394 * config/aarch64/aarch64-sve-builtins-sve2.def: Likewise. 16395 * config/aarch64/aarch64-sve-builtins.def: Include 16396 aarch64-sve-builtins-sve2.def. 16397 163982020-01-09 Richard Sandiford <richard.sandiford@arm.com> 16399 16400 * config/aarch64/aarch64-protos.h (aarch64_sve_arith_immediate_p) 16401 (aarch64_sve_sqadd_sqsub_immediate_p): Add a machine_mode argument. 16402 * config/aarch64/aarch64.c (aarch64_sve_arith_immediate_p) 16403 (aarch64_sve_sqadd_sqsub_immediate_p): Likewise. Handle scalar 16404 immediates as well as vector ones. 16405 * config/aarch64/predicates.md (aarch64_sve_arith_immediate) 16406 (aarch64_sve_sub_arith_immediate, aarch64_sve_qadd_immediate) 16407 (aarch64_sve_qsub_immediate): Update calls accordingly. 16408 164092020-01-09 Richard Sandiford <richard.sandiford@arm.com> 16410 16411 * config/aarch64/aarch64-sve2.md: Add banner comments. 16412 (<su>mulh<r>s<mode>3): Move further up file. 16413 (<su>mull<bt><Vwide>, <r>shrnb<mode>, <r>shrnt<mode>) 16414 (*aarch64_sve2_sra<mode>): Move further down file. 16415 * config/aarch64/t-aarch64 (s-check-sve-md): Check aarch64-sve2.md too. 16416 164172020-01-09 Richard Sandiford <richard.sandiford@arm.com> 16418 16419 * config/aarch64/iterators.md (SVE_WHILE): Add UNSPEC_WHILERW 16420 and UNSPEC_WHILEWR. 16421 (while_optab_cmp): Handle them. 16422 * config/aarch64/aarch64-sve.md 16423 (*while_<while_optab_cmp><GPI:mode><PRED_ALL:mode>_ptest): Make public 16424 and add a "@" marker. 16425 * config/aarch64/aarch64-sve2.md (check_<raw_war>_ptrs<mode>): Use it 16426 instead of gen_aarch64_sve2_while_ptest. 16427 (@aarch64_sve2_while<cmp_op><GPI:mode><PRED_ALL:mode>_ptest): Delete. 16428 164292020-01-09 Richard Sandiford <richard.sandiford@arm.com> 16430 16431 * config/aarch64/aarch64.md (UNSPEC_WHILE_LE): Rename to... 16432 (UNSPEC_WHILELE): ...this. 16433 (UNSPEC_WHILE_LO): Rename to... 16434 (UNSPEC_WHILELO): ...this. 16435 (UNSPEC_WHILE_LS): Rename to... 16436 (UNSPEC_WHILELS): ...this. 16437 (UNSPEC_WHILE_LT): Rename to... 16438 (UNSPEC_WHILELT): ...this. 16439 * config/aarch64/iterators.md (SVE_WHILE): Update accordingly. 16440 (cmp_op, while_optab_cmp): Likewise. 16441 * config/aarch64/aarch64.c (aarch64_sve_move_pred_via_while): Likewise. 16442 * config/aarch64/aarch64-sve-builtins-base.cc (svwhilele): Likewise. 16443 (svwhilelt): Likewise. 16444 164452020-01-09 Richard Sandiford <richard.sandiford@arm.com> 16446 16447 * config/aarch64/aarch64-sve-builtins-shapes.h (unary_count): Delete. 16448 (unary_to_uint): Define. 16449 * config/aarch64/aarch64-sve-builtins-shapes.cc (unary_count_def) 16450 (unary_count): Rename to... 16451 (unary_to_uint_def, unary_to_uint): ...this. 16452 * config/aarch64/aarch64-sve-builtins-base.def: Update accordingly. 16453 164542020-01-09 Richard Sandiford <richard.sandiford@arm.com> 16455 16456 * config/aarch64/aarch64-sve-builtins-functions.h 16457 (code_for_mode_function): New class. 16458 (CODE_FOR_MODE0, QUIET_CODE_FOR_MODE0): New macros. 16459 * config/aarch64/aarch64-sve-builtins-base.cc (svcompact_impl) 16460 (svext_impl, svmul_lane_impl, svsplice_impl, svtmad_impl): Delete. 16461 (svcompact, svext, svsplice): Use QUIET_CODE_FOR_MODE0. 16462 (svmul_lane, svtmad): Use CODE_FOR_MODE0. 16463 164642020-01-09 Richard Sandiford <richard.sandiford@arm.com> 16465 16466 * config/aarch64/iterators.md (addsub): New code attribute. 16467 * config/aarch64/aarch64-simd.md (aarch64_<su_optab><optab><mode>): 16468 Re-express as... 16469 (aarch64_<su_optab>q<addsub><mode>): ...this, making the same change 16470 in the asm string and attributes. Fix indentation. 16471 * config/aarch64/aarch64-sve.md (@aarch64_<su_optab><optab><mode>): 16472 Re-express as... 16473 (@aarch64_sve_<optab><mode>): ...this. 16474 * config/aarch64/aarch64-sve-builtins.h 16475 (function_expander::expand_signed_unpred_op): Delete. 16476 * config/aarch64/aarch64-sve-builtins.cc 16477 (function_expander::expand_signed_unpred_op): Likewise. 16478 (function_expander::map_to_rtx_codes): If the optab isn't defined, 16479 try using code_for_aarch64_sve instead. 16480 * config/aarch64/aarch64-sve-builtins-base.cc (svqadd_impl): Delete. 16481 (svqsub_impl): Likewise. 16482 (svqadd, svqsub): Use rtx_code_function instead. 16483 164842020-01-09 Richard Sandiford <richard.sandiford@arm.com> 16485 16486 * config/aarch64/iterators.md (SRHSUB, URHSUB): Delete. 16487 (HADDSUB, sur, addsub): Remove them. 16488 164892020-01-09 Richard Sandiford <richard.sandiford@arm.com> 16490 16491 * tree-nrv.c (pass_return_slot::execute): Handle all internal 16492 functions the same way, rather than singling out those that 16493 aren't mapped directly to optabs. 16494 164952020-01-09 Richard Sandiford <richard.sandiford@arm.com> 16496 16497 * target.def (compatible_vector_types_p): New target hook. 16498 * hooks.h (hook_bool_const_tree_const_tree_true): Declare. 16499 * hooks.c (hook_bool_const_tree_const_tree_true): New function. 16500 * doc/tm.texi.in (TARGET_COMPATIBLE_VECTOR_TYPES_P): New hook. 16501 * doc/tm.texi: Regenerate. 16502 * gimple-expr.c: Include target.h. 16503 (useless_type_conversion_p): Use targetm.compatible_vector_types_p. 16504 * config/aarch64/aarch64.c (aarch64_compatible_vector_types_p): New 16505 function. 16506 (TARGET_COMPATIBLE_VECTOR_TYPES_P): Define. 16507 * config/aarch64/aarch64-sve-builtins.cc (gimple_folder::convert_pred): 16508 Use the original predicate if it already has a suitable type. 16509 165102020-01-09 Martin Jambor <mjambor@suse.cz> 16511 16512 * cgraph.h (cgraph_edge): Make remove, set_call_stmt, make_direct, 16513 resolve_speculation and redirect_call_stmt_to_callee static. Change 16514 return type of set_call_stmt to cgraph_edge *. 16515 * auto-profile.c (afdo_indirect_call): Adjust call to 16516 redirect_call_stmt_to_callee. 16517 * cgraph.c (cgraph_edge::set_call_stmt): Make return cgraph-edge *, 16518 make the this pointer explicit, adjust self-recursive calls and the 16519 call top make_direct. Return the resulting edge. 16520 (cgraph_edge::remove): Make this pointer explicit. 16521 (cgraph_edge::resolve_speculation): Likewise, adjust call to remove. 16522 (cgraph_edge::make_direct): Likewise, adjust call to 16523 resolve_speculation. 16524 (cgraph_edge::redirect_call_stmt_to_callee): Likewise, also adjust 16525 call to set_call_stmt. 16526 (cgraph_update_edges_for_call_stmt_node): Update call to 16527 set_call_stmt and remove. 16528 * cgraphclones.c (cgraph_node::set_call_stmt_including_clones): 16529 Renamed edge to master_edge. Adjusted calls to set_call_stmt. 16530 (cgraph_node::create_edge_including_clones): Moved "first" definition 16531 of edge to the block where it was used. Adjusted calls to 16532 set_call_stmt. 16533 (cgraph_node::remove_symbol_and_inline_clones): Adjust call to 16534 cgraph_edge::remove. 16535 * cgraphunit.c (walk_polymorphic_call_targets): Adjusted calls to 16536 make_direct and redirect_call_stmt_to_callee. 16537 * ipa-fnsummary.c (redirect_to_unreachable): Adjust calls to 16538 resolve_speculation and make_direct. 16539 * ipa-inline-transform.c (inline_transform): Adjust call to 16540 redirect_call_stmt_to_callee. 16541 (check_speculations_1):: Adjust call to resolve_speculation. 16542 * ipa-inline.c (resolve_noninline_speculation): Adjust call to 16543 resolve-speculation. 16544 (inline_small_functions): Adjust call to resolve_speculation. 16545 (ipa_inline): Likewise. 16546 * ipa-prop.c (ipa_make_edge_direct_to_target): Adjust call to 16547 make_direct. 16548 * ipa-visibility.c (function_and_variable_visibility): Make iteration 16549 safe with regards to edge removal, adjust calls to 16550 redirect_call_stmt_to_callee. 16551 * ipa.c (walk_polymorphic_call_targets): Adjust calls to make_direct 16552 and redirect_call_stmt_to_callee. 16553 * multiple_target.c (create_dispatcher_calls): Adjust call to 16554 redirect_call_stmt_to_callee 16555 (redirect_to_specific_clone): Likewise. 16556 * tree-cfgcleanup.c (delete_unreachable_blocks_update_callgraph): 16557 Adjust calls to cgraph_edge::remove. 16558 * tree-inline.c (copy_bb): Adjust call to set_call_stmt. 16559 (redirect_all_calls): Adjust call to redirect_call_stmt_to_callee. 16560 (expand_call_inline): Adjust call to cgraph_edge::remove. 16561 165622020-01-09 Martin Liska <mliska@suse.cz> 16563 16564 * params.opt: Set Optimization for 16565 param_max_speculative_devirt_maydefs. 16566 165672020-01-09 Martin Sebor <msebor@redhat.com> 16568 16569 PR middle-end/93200 16570 PR fortran/92956 16571 * builtins.c (compute_objsize): Avoid handling MEM_REFs of vector type. 16572 165732020-01-09 Martin Liska <mliska@suse.cz> 16574 16575 * auto-profile.c (auto_profile): Use opt_for_fn 16576 for a parameter. 16577 * ipa-cp.c (ipcp_lattice::add_value): Likewise. 16578 (propagate_vals_across_arith_jfunc): Likewise. 16579 (hint_time_bonus): Likewise. 16580 (incorporate_penalties): Likewise. 16581 (good_cloning_opportunity_p): Likewise. 16582 (perform_estimation_of_a_value): Likewise. 16583 (estimate_local_effects): Likewise. 16584 (ipcp_propagate_stage): Likewise. 16585 * ipa-fnsummary.c (decompose_param_expr): Likewise. 16586 (set_switch_stmt_execution_predicate): Likewise. 16587 (analyze_function_body): Likewise. 16588 * ipa-inline-analysis.c (offline_size): Likewise. 16589 * ipa-inline.c (early_inliner): Likewise. 16590 * ipa-prop.c (ipa_analyze_node): Likewise. 16591 (ipcp_transform_function): Likewise. 16592 * ipa-sra.c (process_scan_results): Likewise. 16593 (ipa_sra_summarize_function): Likewise. 16594 * params.opt: Rename ipcp-unit-growth to 16595 ipa-cp-unit-growth. Add Optimization for various 16596 IPA-related parameters. 16597 165982020-01-09 Richard Biener <rguenther@suse.de> 16599 16600 PR middle-end/93054 16601 * gimplify.c (gimplify_expr): Deal with NOP definitions. 16602 166032020-01-09 Richard Biener <rguenther@suse.de> 16604 16605 PR tree-optimization/93040 16606 * gimple-ssa-store-merging.c (find_bswap_or_nop): Raise search limit. 16607 166082020-01-09 Georg-Johann Lay <avr@gjlay.de> 16609 16610 * common/config/avr/avr-common.c (avr_option_optimization_table) 16611 [OPT_LEVELS_1_PLUS]: Set -fsplit-wide-types-early. 16612 166132020-01-09 Martin Liska <mliska@suse.cz> 16614 16615 * cgraphclones.c (symbol_table::materialize_all_clones): 16616 Use cgraph_node::dump_name. 16617 166182020-01-09 Jakub Jelinek <jakub@redhat.com> 16619 16620 PR inline-asm/93202 16621 * config/riscv/riscv.c (riscv_print_operand_reloc): Use 16622 output_operand_lossage instead of gcc_unreachable. 16623 * doc/md.texi (riscv f constraint): Fix typo. 16624 16625 PR target/93141 16626 * config/i386/i386.md (subv<mode>4): Use SWIDWI iterator instead of 16627 SWI. Use <general_hilo_operand> instead of <general_operand>. Use 16628 CONST_SCALAR_INT_P instead of CONST_INT_P. 16629 (*subv<mode>4_1): Rename to ... 16630 (subv<mode>4_1): ... this. 16631 (*subv<dwi>4_doubleword, *addv<dwi>4_doubleword_1): New 16632 define_insn_and_split patterns. 16633 (*subv<mode>4_overflow_1, *addv<mode>4_overflow_2): New define_insn 16634 patterns. 16635 166362020-01-08 David Malcolm <dmalcolm@redhat.com> 16637 16638 * vec.c (class selftest::count_dtor): New class. 16639 (selftest::test_auto_delete_vec): New test. 16640 (selftest::vec_c_tests): Call it. 16641 * vec.h (class auto_delete_vec): New class template. 16642 (auto_delete_vec<T>::~auto_delete_vec): New dtor. 16643 166442020-01-08 David Malcolm <dmalcolm@redhat.com> 16645 16646 * sbitmap.h (auto_sbitmap): Add operator const_sbitmap. 16647 166482020-01-08 Jim Wilson <jimw@sifive.com> 16649 16650 * config/riscv/riscv.c (riscv_legitimize_tls_address): Ifdef out 16651 use of TLS_MODEL_LOCAL_EXEC when not pic. 16652 166532020-01-08 David Malcolm <dmalcolm@redhat.com> 16654 16655 * hash-map-tests.c (selftest::test_map_of_strings_to_int): Fix 16656 memory leak. 16657 166582020-01-08 Jakub Jelinek <jakub@redhat.com> 16659 16660 PR target/93187 16661 * config/i386/i386.md (*stack_protect_set_2_<mode> peephole2, 16662 *stack_protect_set_3 peephole2): Also check that the second 16663 insns source is general_operand. 16664 16665 PR target/93174 16666 * config/i386/i386.md (addcarry<mode>_0): Use nonimmediate_operand 16667 predicate for output operand instead of register_operand. 16668 (addcarry<mode>, addcarry<mode>_1): Likewise. Add alternative with 16669 memory destination and non-memory operands[2]. 16670 166712020-01-08 Martin Liska <mliska@suse.cz> 16672 16673 * cgraph.c (cgraph_node::dump): Use ::dump_name or 16674 ::dump_asm_name instead of (::name or ::asm_name). 16675 * cgraphclones.c (symbol_table::materialize_all_clones): Likewise. 16676 * cgraphunit.c (walk_polymorphic_call_targets): Likewise. 16677 (analyze_functions): Likewise. 16678 (expand_all_functions): Likewise. 16679 * ipa-cp.c (ipcp_cloning_candidate_p): Likewise. 16680 (propagate_bits_across_jump_function): Likewise. 16681 (dump_profile_updates): Likewise. 16682 (ipcp_store_bits_results): Likewise. 16683 (ipcp_store_vr_results): Likewise. 16684 * ipa-devirt.c (dump_targets): Likewise. 16685 * ipa-fnsummary.c (analyze_function_body): Likewise. 16686 * ipa-hsa.c (check_warn_node_versionable): Likewise. 16687 (process_hsa_functions): Likewise. 16688 * ipa-icf.c (sem_item_optimizer::merge_classes): Likewise. 16689 (set_alias_uids): Likewise. 16690 * ipa-inline-transform.c (save_inline_function_body): Likewise. 16691 * ipa-inline.c (recursive_inlining): Likewise. 16692 (inline_to_all_callers_1): Likewise. 16693 (ipa_inline): Likewise. 16694 * ipa-profile.c (ipa_propagate_frequency_1): Likewise. 16695 (ipa_propagate_frequency): Likewise. 16696 * ipa-prop.c (ipa_make_edge_direct_to_target): Likewise. 16697 (remove_described_reference): Likewise. 16698 * ipa-pure-const.c (worse_state): Likewise. 16699 (check_retval_uses): Likewise. 16700 (analyze_function): Likewise. 16701 (propagate_pure_const): Likewise. 16702 (propagate_nothrow): Likewise. 16703 (dump_malloc_lattice): Likewise. 16704 (propagate_malloc): Likewise. 16705 (pass_local_pure_const::execute): Likewise. 16706 * ipa-visibility.c (optimize_weakref): Likewise. 16707 (function_and_variable_visibility): Likewise. 16708 * ipa.c (symbol_table::remove_unreachable_nodes): Likewise. 16709 (ipa_discover_variable_flags): Likewise. 16710 * lto-streamer-out.c (output_function): Likewise. 16711 (output_constructor): Likewise. 16712 * tree-inline.c (copy_bb): Likewise. 16713 * tree-ssa-structalias.c (ipa_pta_execute): Likewise. 16714 * varpool.c (symbol_table::remove_unreferenced_decls): Likewise. 16715 167162020-01-08 Richard Biener <rguenther@suse.de> 16717 16718 PR middle-end/93199 16719 * tree-eh.c (sink_clobbers): Update virtual operands for 16720 the first and last stmt only. Add a dry-run capability. 16721 (pass_lower_eh_dispatch::execute): Perform clobber sinking 16722 after CFG manipulations and in RPO order to catch all 16723 secondary opportunities reliably. 16724 167252020-01-08 Georg-Johann Lay <avr@gjlay.de> 16726 16727 PR target/93182 16728 * doc/invoke.texi (AVR Options) <-nodevicespecs>: Document. 16729 167302019-01-08 Richard Biener <rguenther@suse.de> 16731 16732 PR middle-end/93199 16733 * gimple-fold.c (rewrite_to_defined_overflow): Mark stmt modified. 16734 * tree-ssa-loop-im.c (move_computations_worker): Properly adjust 16735 virtual operand, also updating SSA use. 16736 * gimple-loop-interchange.cc (loop_cand::undo_simple_reduction): 16737 Update stmt after resetting virtual operand. 16738 (tree_loop_interchange::move_code_to_inner_loop): Likewise. 16739 * gimple-iterator.c (gsi_remove): When not removing the stmt 16740 permanently do not delink immediate uses or mark the stmt modified. 16741 167422020-01-08 Martin Liska <mliska@suse.cz> 16743 16744 * ipa-fnsummary.c (dump_ipa_call_summary): Use symtab_node::dump_name. 16745 (ipa_call_context::estimate_size_and_time): Likewise. 16746 (inline_analyze_function): Likewise. 16747 167482020-01-08 Martin Liska <mliska@suse.cz> 16749 16750 * cgraph.c (cgraph_node::dump): Use systematically 16751 dump_asm_name. 16752 167532020-01-08 Georg-Johann Lay <avr@gjlay.de> 16754 16755 Add -nodevicespecs option for avr. 16756 16757 PR target/93182 16758 * config/avr/avr.opt (-nodevicespecs): New driver option. 16759 * config/avr/driver-avr.c (avr_devicespecs_file): Only issue 16760 "-specs=device-specs/..." if that option is not set. 16761 * doc/invoke.texi (AVR Options) <-nodevicespecs>: Document. 16762 167632020-01-08 Georg-Johann Lay <avr@gjlay.de> 16764 16765 Implement 64-bit double functions for avr. 16766 16767 PR target/92055 16768 * config.gcc (tm_defines) [target=avr]: Support --with-libf7, 16769 --with-double-comparison. 16770 * doc/install.texi: Document them. 16771 * config/avr/avr-c.c (avr_cpu_cpp_builtins) 16772 <WITH_LIBF7_LIBGCC, WITH_LIBF7_MATH, WITH_LIBF7_MATH_SYMBOLS> 16773 <WITH_DOUBLE_COMPARISON>: New built-in defines. 16774 * doc/invoke.texi (AVR Built-in Macros): Document them. 16775 * config/avr/avr-protos.h (avr_float_lib_compare_returns_bool): New. 16776 * config/avr/avr.c (avr_float_lib_compare_returns_bool): New function. 16777 * config/avr/avr.h (FLOAT_LIB_COMPARE_RETURNS_BOOL): New macro. 16778 167792020-01-08 Richard Earnshaw <rearnsha@arm.com> 16780 16781 PR target/93188 16782 * config/arm/t-multilib (MULTILIB_MATCHES): Add rules to match 16783 armv7-a{+mp,+sec,+mp+sec} to appropriate armv7 multilib variants 16784 when only building rm-profile multilibs. 16785 167862020-01-08 Feng Xue <fxue@os.amperecomputing.com> 16787 16788 PR ipa/93084 16789 * ipa-cp.c (self_recursively_generated_p): Find matched aggregate 16790 lattice for a value to check. 16791 (propagate_vals_across_arith_jfunc): Add an assertion to ensure 16792 finite propagation in self-recursive scc. 16793 167942020-01-08 Luo Xiong Hu <luoxhu@linux.ibm.com> 16795 16796 * ipa-inline.c (caller_growth_limits): Restore the AND. 16797 167982020-01-07 Andrew Stubbs <ams@codesourcery.com> 16799 16800 * config/gcn/gcn-valu.md (VEC_1REG_INT_ALT): Delete iterator. 16801 (VEC_ALLREG_ALT): New iterator. 16802 (VEC_ALLREG_INT_MODE): New iterator. 16803 (VCMP_MODE): New iterator. 16804 (VCMP_MODE_INT): New iterator. 16805 (vec_cmpu<mode>di): Use VCMP_MODE_INT. 16806 (vec_cmp<u>v64qidi): New define_expand. 16807 (vec_cmp<mode>di_exec): Use VCMP_MODE. 16808 (vec_cmpu<mode>di_exec): New define_expand. 16809 (vec_cmp<u>v64qidi_exec): New define_expand. 16810 (vec_cmp<mode>di_dup): Use VCMP_MODE. 16811 (vec_cmp<mode>di_dup_exec): Use VCMP_MODE. 16812 (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>): Rename ... 16813 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>): ... to this. 16814 (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>_exec): Rename ... 16815 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>_exec): ... to this. 16816 (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>): Rename ... 16817 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>): ... to this. 16818 (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>_exec): Rename ... 16819 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>_exec): ... to 16820 this. 16821 * config/gcn/gcn.c (print_operand): Fix 8 and 16 bit suffixes. 16822 * config/gcn/gcn.md (expander): Add sign_extend and zero_extend. 16823 168242020-01-07 Andrew Stubbs <ams@codesourcery.com> 16825 16826 * config/gcn/constraints.md (DA): Update description and match. 16827 (DB): Likewise. 16828 (Db): New constraint. 16829 * config/gcn/gcn-protos.h (gcn_inline_constant64_p): Add second 16830 parameter. 16831 * config/gcn/gcn.c (gcn_inline_constant64_p): Add 'mixed' parameter. 16832 Implement 'Db' mixed immediate type. 16833 * config/gcn/gcn-valu.md (addcv64si3<exec_vcc>): Rework constraints. 16834 (addcv64si3_dup<exec_vcc>): Delete. 16835 (subcv64si3<exec_vcc>): Rework constraints. 16836 (addv64di3): Rework constraints. 16837 (addv64di3_exec): Rework constraints. 16838 (subv64di3): Rework constraints. 16839 (addv64di3_dup): Delete. 16840 (addv64di3_dup_exec): Delete. 16841 (addv64di3_zext): Rework constraints. 16842 (addv64di3_zext_exec): Rework constraints. 16843 (addv64di3_zext_dup): Rework constraints. 16844 (addv64di3_zext_dup_exec): Rework constraints. 16845 (addv64di3_zext_dup2): Rework constraints. 16846 (addv64di3_zext_dup2_exec): Rework constraints. 16847 (addv64di3_sext_dup2): Rework constraints. 16848 (addv64di3_sext_dup2_exec): Rework constraints. 16849 168502020-01-07 Andre Vieira <andre.simoesdiasvieira@arm.com> 16851 16852 * doc/sourcebuild.texi (arm_little_endian, arm_nothumb): Documented 16853 existing target checks. 16854 168552020-01-07 Richard Biener <rguenther@suse.de> 16856 16857 * doc/install.texi: Bump minimal supported MPC version. 16858 168592020-01-07 Richard Sandiford <richard.sandiford@arm.com> 16860 16861 * langhooks-def.h (lhd_simulate_enum_decl): Declare. 16862 (LANG_HOOKS_SIMULATE_ENUM_DECL): Use it. 16863 * langhooks.c: Include stor-layout.h. 16864 (lhd_simulate_enum_decl): New function. 16865 * config/aarch64/aarch64-sve-builtins.cc (init_builtins): Call 16866 handle_arm_sve_h for the LTO frontend. 16867 (register_vector_type): Cope with null returns from pushdecl. 16868 168692020-01-07 Richard Sandiford <richard.sandiford@arm.com> 16870 16871 * config/aarch64/aarch64-protos.h (aarch64_sve::svbool_type_p) 16872 (aarch64_sve::nvectors_if_data_type): Replace with... 16873 (aarch64_sve::builtin_type_p): ...this. 16874 * config/aarch64/aarch64-sve-builtins.cc: Include attribs.h. 16875 (find_vector_type): Delete. 16876 (add_sve_type_attribute): New function. 16877 (lookup_sve_type_attribute): Likewise. 16878 (register_builtin_types): Add an "SVE type" attribute to each type. 16879 (register_tuple_type): Likewise. 16880 (svbool_type_p, nvectors_if_data_type): Delete. 16881 (mangle_builtin_type): Use lookup_sve_type_attribute. 16882 (builtin_type_p): Likewise. Add an overload that returns the 16883 number of constituent vector and predicate registers. 16884 * config/aarch64/aarch64.c (aarch64_sve_argument_p): Delete. 16885 (aarch64_returns_value_in_sve_regs_p): Use aarch64_sve::builtin_type_p 16886 instead of aarch64_sve_argument_p. 16887 (aarch64_takes_arguments_in_sve_regs_p): Likewise. 16888 (aarch64_pass_by_reference): Likewise. 16889 (aarch64_function_value_1): Likewise. 16890 (aarch64_return_in_memory): Likewise. 16891 (aarch64_layout_arg): Likewise. 16892 168932020-01-07 Jakub Jelinek <jakub@redhat.com> 16894 16895 PR tree-optimization/93156 16896 * tree-ssa-ccp.c (bit_value_binop): For x * x note that the second 16897 least significant bit is always clear. 16898 16899 PR tree-optimization/93118 16900 * match.pd ((x >> c) << c -> x & (-1<<c)): Add nop_convert?. Add new 16901 simplifier with two intermediate conversions. 16902 169032020-01-07 Martin Liska <mliska@suse.cz> 16904 16905 * params.opt: Add Optimization for various parameters. 16906 169072020-01-07 Martin Liska <mliska@suse.cz> 16908 16909 PR ipa/83411 16910 * doc/extend.texi: Explain cloning for target_clone 16911 attribute. 16912 169132020-01-07 Martin Liska <mliska@suse.cz> 16914 16915 PR tree-optimization/92860 16916 * common.opt: Make in Optimization option 16917 as it is affected by -O0, which is an Optimization 16918 option. 16919 * tree-inline.c (tree_inlinable_function_p): 16920 Use opt_for_fn for warn_inline. 16921 (expand_call_inline): Likewise. 16922 169232020-01-07 Martin Liska <mliska@suse.cz> 16924 16925 PR tree-optimization/92860 16926 * common.opt: Make flag_ree as optimization 16927 attribute. 16928 169292020-01-07 Martin Liska <mliska@suse.cz> 16930 16931 PR optimization/92860 16932 * params.opt: Mark param_min_crossjump_insns with Optimization 16933 keyword. 16934 169352020-01-07 Luo Xiong Hu <luoxhu@linux.ibm.com> 16936 16937 * ipa-inline-analysis.c (estimate_growth): Fix typo. 16938 * ipa-inline.c (caller_growth_limits): Use OR instead of AND. 16939 169402020-01-06 Michael Meissner <meissner@linux.ibm.com> 16941 16942 * config/rs6000/rs6000.c (hard_reg_and_mode_to_addr_mask): New 16943 helper function to return the valid addressing formats for a given 16944 hard register and mode. 16945 (rs6000_adjust_vec_address): Call hard_reg_and_mode_to_addr_mask. 16946 16947 * config/rs6000/constraints.md (Q constraint): Update 16948 documentation. 16949 * doc/md.texi (RS/6000 constraints): Update 'Q' cosntraint 16950 documentation. 16951 16952 * config/rs6000/vsx.md (vsx_extract_<mode>_var, VSX_D iterator): 16953 Use 'Q' for doing vector extract from memory. 16954 (vsx_extract_v4sf_var): Use 'Q' for doing vector extract from 16955 memory. 16956 (vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): Use 'Q' for 16957 doing vector extract from memory. 16958 (vsx_extract_<mode>_<VS_scalar>mode_var): Use 'Q' for doing vector 16959 extract from memory. 16960 16961 * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add support 16962 for the offset being 34-bits when -mcpu=future is used. 16963 169642020-01-06 John David Anglin <danglin@gcc.gnu.org> 16965 16966 * config/pa/pa.md: Revert change to use ordered_comparison_operator 16967 instead of cmpib_comparison_operator in cmpib patterns. 16968 * config/pa/predicates.md (cmpib_comparison_operator): Revert removal 16969 of cmpib_comparison_operator. Revise comment. 16970 169712020-01-06 Richard Sandiford <richard.sandiford@arm.com> 16972 16973 * tree-vect-slp.c (vect_build_slp_tree_1): Require all shifts 16974 in an IFN_DIV_POW2 node to be equal. 16975 169762020-01-06 Richard Sandiford <richard.sandiford@arm.com> 16977 16978 * tree-vect-stmts.c (vect_check_load_store_mask): Rename to... 16979 (vect_check_scalar_mask): ...this. 16980 (vectorizable_store, vectorizable_load): Update call accordingly. 16981 (vectorizable_call): Use vect_check_scalar_mask to check the mask 16982 argument in calls to conditional internal functions. 16983 169842020-01-06 Andrew Stubbs <ams@codesourcery.com> 16985 16986 * config/gcn/gcn-valu.md (subv64di3): Use separate alternatives for 16987 '0' matching inputs. 16988 (subv64di3_exec): Likewise. 16989 169902020-01-06 Bryan Stenson <bryan@siliconvortex.com> 16991 16992 * config/mips/mips.c (vr4130_align_insns): Fix typo. 16993 * doc/md.texi (movstr): Likewise. 16994 169952020-01-06 Andrew Stubbs <ams@codesourcery.com> 16996 16997 * config/gcn/gcn-valu.md (vec_extract<mode><scalar_mode>): Add early 16998 clobber. 16999 170002020-01-06 Richard Sandiford <richard.sandiford@arm.com> 17001 17002 * config/aarch64/t-aarch64 ($(srcdir)/config/aarch64/aarch64-tune.md): 17003 Depend on... 17004 (s-aarch64-tune-md): ...this new stamp file. Pipe the new contents 17005 to a temporary file and use move-if-change to update the real 17006 file where necessary. 17007 170082020-01-06 Richard Sandiford <richard.sandiford@arm.com> 17009 17010 * config/aarch64/aarch64-sve.md (@aarch64_sel_dup<mode>): Use Upl 17011 rather than Upa for CPY /M. 17012 170132020-01-06 Andrew Stubbs <ams@codesourcery.com> 17014 17015 * config/gcn/gcn.c (gcn_inline_constant_p): Allow 64 as an inline 17016 immediate. 17017 170182020-01-06 Martin Liska <mliska@suse.cz> 17019 17020 PR tree-optimization/92860 17021 * params.opt: Mark param_max_combine_insns with Optimization 17022 keyword. 17023 170242020-01-05 Jakub Jelinek <jakub@redhat.com> 17025 17026 PR target/93141 17027 * config/i386/i386.md (SWIDWI): New mode iterator. 17028 (DWI, dwi): Add TImode variants. 17029 (addv<mode>4): Use SWIDWI iterator instead of SWI. Use 17030 <general_hilo_operand> instead of <general_operand>. Use 17031 CONST_SCALAR_INT_P instead of CONST_INT_P. 17032 (*addv<mode>4_1): Rename to ... 17033 (addv<mode>4_1): ... this. 17034 (QWI): New mode attribute. 17035 (*addv<dwi>4_doubleword, *addv<dwi>4_doubleword_1): New 17036 define_insn_and_split patterns. 17037 (*addv<mode>4_overflow_1, *addv<mode>4_overflow_2): New define_insn 17038 patterns. 17039 (uaddv<mode>4): Use SWIDWI iterator instead of SWI. Use 17040 <general_hilo_operand> instead of <general_operand>. 17041 (*addcarry<mode>_1): New define_insn. 17042 (*add<dwi>3_doubleword_cc_overflow_1): New define_insn_and_split. 17043 170442020-01-03 Konstantin Kharlamov <Hi-Angel@yandex.ru> 17045 17046 * gdbinit.in (pr, prl, pt, pct, pgg, pgq, pgs, pge, pmz, pdd, pbs, pbm): 17047 Use "call" instead of "set". 17048 170492020-01-03 Martin Jambor <mjambor@suse.cz> 17050 17051 PR ipa/92917 17052 * ipa-cp.c (print_all_lattices): Skip functions without info. 17053 170542020-01-03 Jakub Jelinek <jakub@redhat.com> 17055 17056 PR target/93089 17057 * config/i386/i386-options.c (ix86_simd_clone_adjust): If 17058 TARGET_PREFER_AVX128, use prefer-vector-width=256 for 'c' and 'd' 17059 simd clones. If TARGET_PREFER_AVX256, use prefer-vector-width=512 17060 for 'e' simd clones. 17061 17062 PR target/93089 17063 * config/i386/i386.opt (x_prefer_vector_width_type): Remove TargetSave 17064 entry. 17065 (mprefer-vector-width=): Add Save. 17066 * config/i386/i386-options.c (ix86_target_string): Add PVW argument, print 17067 -mprefer-vector-width= if non-zero. Fix up -mfpmath= comment. 17068 (ix86_debug_options, ix86_function_specific_print): Adjust 17069 ix86_target_string callers. 17070 (ix86_valid_target_attribute_inner_p): Handle prefer-vector-width=. 17071 (ix86_valid_target_attribute_tree): Likewise. 17072 * config/i386/i386-options.h (ix86_target_string): Add PVW argument. 17073 * config/i386/i386-expand.c (ix86_expand_builtin): Adjust 17074 ix86_target_string caller. 17075 17076 PR target/93110 17077 * config/i386/i386.md (abs<mode>2): Use expand_simple_binop instead of 17078 emitting ASHIFTRT, XOR and MINUS by hand. Use gen_int_mode with QImode 17079 instead of gen_int_shift_amount + convert_modes. 17080 17081 PR rtl-optimization/93088 17082 * loop-iv.c (find_single_def_src): Punt after looking through 17083 128 reg copies for regs with single definitions. Move definitions 17084 to first uses. 17085 170862020-01-02 Dennis Zhang <dennis.zhang@arm.com> 17087 17088 * config/arm/arm-c.c (arm_cpu_builtins): Define 17089 __ARM_FEATURE_MATMUL_INT8, __ARM_FEATURE_BF16_VECTOR_ARITHMETIC, 17090 __ARM_FEATURE_BF16_SCALAR_ARITHMETIC, and 17091 __ARM_BF16_FORMAT_ALTERNATIVE when enabled. 17092 * config/arm/arm-cpus.in (armv8_6, i8mm, bf16): New features. 17093 * config/arm/arm-tables.opt: Regenerated. 17094 * config/arm/arm.c (arm_option_reconfigure_globals): Initialize 17095 arm_arch_i8mm and arm_arch_bf16 when enabled. 17096 * config/arm/arm.h (TARGET_I8MM): New macro. 17097 (TARGET_BF16_FP, TARGET_BF16_SIMD): Likewise. 17098 * config/arm/t-aprofile: Add matching rules for -march=armv8.6-a. 17099 * config/arm/t-arm-elf (all_v8_archs): Add armv8.6-a. 17100 * config/arm/t-multilib: Add matching rules for -march=armv8.6-a. 17101 (v8_6_a_simd_variants): New. 17102 (v8_*_a_simd_variants): Add i8mm and bf16. 17103 * doc/invoke.texi (armv8.6-a, i8mm, bf16): Document new options. 17104 171052020-01-02 Jakub Jelinek <jakub@redhat.com> 17106 17107 PR ipa/93087 17108 * predict.c (compute_function_frequency): Don't call 17109 warn_function_cold on functions that already have cold attribute. 17110 171112020-01-01 John David Anglin <danglin@gcc.gnu.org> 17112 17113 PR target/67834 17114 * config/pa/pa.c (pa_elf_select_rtx_section): New. Put references to 17115 COMDAT group function labels in .data.rel.ro.local section. 17116 * config/pa/pa32-linux.h (TARGET_ASM_SELECT_RTX_SECTION): Define. 17117 17118 PR target/93111 17119 * config/pa/pa.md (scc): Use ordered_comparison_operator instead of 17120 comparison_operator in B and S integer comparisons. Likewise, use 17121 ordered_comparison_operator instead of cmpib_comparison_operator in 17122 cmpib patterns. 17123 * config/pa/predicates.md (cmpib_comparison_operator): Remove. 17124 171252020-01-01 Jakub Jelinek <jakub@redhat.com> 17126 17127 Update copyright years. 17128 17129 * gcc.c (process_command): Update copyright notice dates. 17130 * gcov-dump.c (print_version): Ditto. 17131 * gcov.c (print_version): Ditto. 17132 * gcov-tool.c (print_version): Ditto. 17133 * gengtype.c (create_file): Ditto. 17134 * doc/cpp.texi: Bump @copying's copyright year. 17135 * doc/cppinternals.texi: Ditto. 17136 * doc/gcc.texi: Ditto. 17137 * doc/gccint.texi: Ditto. 17138 * doc/gcov.texi: Ditto. 17139 * doc/install.texi: Ditto. 17140 * doc/invoke.texi: Ditto. 17141 171422020-01-01 Jan Hubicka <hubicka@ucw.cz> 17143 17144 * ipa.c (walk_polymorphic_call_targets): Fix updating of overall 17145 summary. 17146 171472020-01-01 Jakub Jelinek <jakub@redhat.com> 17148 17149 PR tree-optimization/93098 17150 * match.pd (popcount): For shift amounts, use integer_onep 17151 or wi::to_widest () == cst instead of tree_to_uhwi () == cst 17152 tests. Make sure that precision is power of two larger than or equal 17153 to 16. Ensure shift is never negative. Use HOST_WIDE_INT_UC macro 17154 instead of ULL suffixed constants. Formatting fixes. 17155 17156Copyright (C) 2020 Free Software Foundation, Inc. 17157 17158Copying and distribution of this file, with or without modification, 17159are permitted in any medium without royalty provided the copyright 17160notice and this notice are preserved. 17161