1 /*
2 * Copyright (C) 2007-2020 Free Software Foundation, Inc.
3 *
4 * This file is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 3, or (at your option) any
7 * later version.
8 *
9 * This file is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * Under Section 7 of GPL version 3, you are granted additional
15 * permissions described in the GCC Runtime Library Exception, version
16 * 3.1, as published by the Free Software Foundation.
17 *
18 * You should have received a copy of the GNU General Public License and
19 * a copy of the GCC Runtime Library Exception along with this program;
20 * see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
21 * <http://www.gnu.org/licenses/>.
22 */
23
24 /* %eax */
25 #define bit_AVX512BF16 (1 << 5)
26
27 /* %ecx */
28 #define bit_SSE3 (1 << 0)
29 #define bit_PCLMUL (1 << 1)
30 #define bit_LZCNT (1 << 5)
31 #define bit_SSSE3 (1 << 9)
32 #define bit_FMA (1 << 12)
33 #define bit_CMPXCHG16B (1 << 13)
34 #define bit_SSE4_1 (1 << 19)
35 #define bit_SSE4_2 (1 << 20)
36 #define bit_MOVBE (1 << 22)
37 #define bit_POPCNT (1 << 23)
38 #define bit_AES (1 << 25)
39 #define bit_XSAVE (1 << 26)
40 #define bit_OSXSAVE (1 << 27)
41 #define bit_AVX (1 << 28)
42 #define bit_F16C (1 << 29)
43 #define bit_RDRND (1 << 30)
44
45 /* %edx */
46 #define bit_CMPXCHG8B (1 << 8)
47 #define bit_CMOV (1 << 15)
48 #define bit_MMX (1 << 23)
49 #define bit_FXSAVE (1 << 24)
50 #define bit_SSE (1 << 25)
51 #define bit_SSE2 (1 << 26)
52
53 /* Extended Features (%eax == 0x80000001) */
54 /* %ecx */
55 #define bit_LAHF_LM (1 << 0)
56 #define bit_ABM (1 << 5)
57 #define bit_SSE4a (1 << 6)
58 #define bit_PRFCHW (1 << 8)
59 #define bit_XOP (1 << 11)
60 #define bit_LWP (1 << 15)
61 #define bit_FMA4 (1 << 16)
62 #define bit_TBM (1 << 21)
63 #define bit_MWAITX (1 << 29)
64
65 /* %edx */
66 #define bit_MMXEXT (1 << 22)
67 #define bit_LM (1 << 29)
68 #define bit_3DNOWP (1 << 30)
69 #define bit_3DNOW (1u << 31)
70
71 /* %ebx */
72 #define bit_CLZERO (1 << 0)
73 #define bit_WBNOINVD (1 << 9)
74
75 /* Extended Features (%eax == 7) */
76 /* %ebx */
77 #define bit_FSGSBASE (1 << 0)
78 #define bit_SGX (1 << 2)
79 #define bit_BMI (1 << 3)
80 #define bit_HLE (1 << 4)
81 #define bit_AVX2 (1 << 5)
82 #define bit_BMI2 (1 << 8)
83 #define bit_RTM (1 << 11)
84 #define bit_MPX (1 << 14)
85 #define bit_AVX512F (1 << 16)
86 #define bit_AVX512DQ (1 << 17)
87 #define bit_RDSEED (1 << 18)
88 #define bit_ADX (1 << 19)
89 #define bit_AVX512IFMA (1 << 21)
90 #define bit_CLFLUSHOPT (1 << 23)
91 #define bit_CLWB (1 << 24)
92 #define bit_AVX512PF (1 << 26)
93 #define bit_AVX512ER (1 << 27)
94 #define bit_AVX512CD (1 << 28)
95 #define bit_SHA (1 << 29)
96 #define bit_AVX512BW (1 << 30)
97 #define bit_AVX512VL (1u << 31)
98
99 /* %ecx */
100 #define bit_PREFETCHWT1 (1 << 0)
101 #define bit_AVX512VBMI (1 << 1)
102 #define bit_PKU (1 << 3)
103 #define bit_OSPKE (1 << 4)
104 #define bit_WAITPKG (1 << 5)
105 #define bit_AVX512VBMI2 (1 << 6)
106 #define bit_SHSTK (1 << 7)
107 #define bit_GFNI (1 << 8)
108 #define bit_VAES (1 << 9)
109 #define bit_AVX512VNNI (1 << 11)
110 #define bit_VPCLMULQDQ (1 << 10)
111 #define bit_AVX512BITALG (1 << 12)
112 #define bit_AVX512VPOPCNTDQ (1 << 14)
113 #define bit_RDPID (1 << 22)
114 #define bit_MOVDIRI (1 << 27)
115 #define bit_MOVDIR64B (1 << 28)
116 #define bit_ENQCMD (1 << 29)
117 #define bit_CLDEMOTE (1 << 25)
118
119 /* %edx */
120 #define bit_AVX5124VNNIW (1 << 2)
121 #define bit_AVX5124FMAPS (1 << 3)
122 #define bit_AVX512VP2INTERSECT (1 << 8)
123 #define bit_IBT (1 << 20)
124 #define bit_PCONFIG (1 << 18)
125 /* XFEATURE_ENABLED_MASK register bits (%eax == 13, %ecx == 0) */
126 #define bit_BNDREGS (1 << 3)
127 #define bit_BNDCSR (1 << 4)
128
129 /* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */
130 #define bit_XSAVEOPT (1 << 0)
131 #define bit_XSAVEC (1 << 1)
132 #define bit_XSAVES (1 << 3)
133
134 /* PT sub leaf (%eax == 14, %ecx == 0) */
135 /* %ebx */
136 #define bit_PTWRITE (1 << 4)
137
138 /* Signatures for different CPU implementations as returned in uses
139 of cpuid with level 0. */
140 #define signature_AMD_ebx 0x68747541
141 #define signature_AMD_ecx 0x444d4163
142 #define signature_AMD_edx 0x69746e65
143
144 #define signature_CENTAUR_ebx 0x746e6543
145 #define signature_CENTAUR_ecx 0x736c7561
146 #define signature_CENTAUR_edx 0x48727561
147
148 #define signature_CYRIX_ebx 0x69727943
149 #define signature_CYRIX_ecx 0x64616574
150 #define signature_CYRIX_edx 0x736e4978
151
152 #define signature_INTEL_ebx 0x756e6547
153 #define signature_INTEL_ecx 0x6c65746e
154 #define signature_INTEL_edx 0x49656e69
155
156 #define signature_TM1_ebx 0x6e617254
157 #define signature_TM1_ecx 0x55504361
158 #define signature_TM1_edx 0x74656d73
159
160 #define signature_TM2_ebx 0x756e6547
161 #define signature_TM2_ecx 0x3638784d
162 #define signature_TM2_edx 0x54656e69
163
164 #define signature_NSC_ebx 0x646f6547
165 #define signature_NSC_ecx 0x43534e20
166 #define signature_NSC_edx 0x79622065
167
168 #define signature_NEXGEN_ebx 0x4778654e
169 #define signature_NEXGEN_ecx 0x6e657669
170 #define signature_NEXGEN_edx 0x72446e65
171
172 #define signature_RISE_ebx 0x65736952
173 #define signature_RISE_ecx 0x65736952
174 #define signature_RISE_edx 0x65736952
175
176 #define signature_SIS_ebx 0x20536953
177 #define signature_SIS_ecx 0x20536953
178 #define signature_SIS_edx 0x20536953
179
180 #define signature_UMC_ebx 0x20434d55
181 #define signature_UMC_ecx 0x20434d55
182 #define signature_UMC_edx 0x20434d55
183
184 #define signature_VIA_ebx 0x20414956
185 #define signature_VIA_ecx 0x20414956
186 #define signature_VIA_edx 0x20414956
187
188 #define signature_VORTEX_ebx 0x74726f56
189 #define signature_VORTEX_ecx 0x436f5320
190 #define signature_VORTEX_edx 0x36387865
191
192 #ifndef __x86_64__
193 /* At least one cpu (Winchip 2) does not set %ebx and %ecx
194 for cpuid leaf 1. Forcibly zero the two registers before
195 calling cpuid as a precaution. */
196 #define __cpuid(level, a, b, c, d) \
197 do { \
198 if (__builtin_constant_p (level) && (level) != 1) \
199 __asm__ ("cpuid\n\t" \
200 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
201 : "0" (level)); \
202 else \
203 __asm__ ("cpuid\n\t" \
204 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
205 : "0" (level), "1" (0), "2" (0)); \
206 } while (0)
207 #else
208 #define __cpuid(level, a, b, c, d) \
209 __asm__ ("cpuid\n\t" \
210 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
211 : "0" (level))
212 #endif
213
214 #define __cpuid_count(level, count, a, b, c, d) \
215 __asm__ ("cpuid\n\t" \
216 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
217 : "0" (level), "2" (count))
218
219
220 /* Return highest supported input value for cpuid instruction. ext can
221 be either 0x0 or 0x80000000 to return highest supported value for
222 basic or extended cpuid information. Function returns 0 if cpuid
223 is not supported or whatever cpuid returns in eax register. If sig
224 pointer is non-null, then first four bytes of the signature
225 (as found in ebx register) are returned in location pointed by sig. */
226
227 static __inline unsigned int
__get_cpuid_max(unsigned int __ext,unsigned int * __sig)228 __get_cpuid_max (unsigned int __ext, unsigned int *__sig)
229 {
230 unsigned int __eax, __ebx, __ecx, __edx;
231
232 #ifndef __x86_64__
233 /* See if we can use cpuid. On AMD64 we always can. */
234 #if __GNUC__ >= 3
235 __asm__ ("pushf{l|d}\n\t"
236 "pushf{l|d}\n\t"
237 "pop{l}\t%0\n\t"
238 "mov{l}\t{%0, %1|%1, %0}\n\t"
239 "xor{l}\t{%2, %0|%0, %2}\n\t"
240 "push{l}\t%0\n\t"
241 "popf{l|d}\n\t"
242 "pushf{l|d}\n\t"
243 "pop{l}\t%0\n\t"
244 "popf{l|d}\n\t"
245 : "=&r" (__eax), "=&r" (__ebx)
246 : "i" (0x00200000));
247 #else
248 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax
249 nor alternatives in i386 code. */
250 __asm__ ("pushfl\n\t"
251 "pushfl\n\t"
252 "popl\t%0\n\t"
253 "movl\t%0, %1\n\t"
254 "xorl\t%2, %0\n\t"
255 "pushl\t%0\n\t"
256 "popfl\n\t"
257 "pushfl\n\t"
258 "popl\t%0\n\t"
259 "popfl\n\t"
260 : "=&r" (__eax), "=&r" (__ebx)
261 : "i" (0x00200000));
262 #endif
263
264 if (!((__eax ^ __ebx) & 0x00200000))
265 return 0;
266 #endif
267
268 /* Host supports cpuid. Return highest supported cpuid input value. */
269 __cpuid (__ext, __eax, __ebx, __ecx, __edx);
270
271 if (__sig)
272 *__sig = __ebx;
273
274 return __eax;
275 }
276
277 /* Return cpuid data for requested cpuid leaf, as found in returned
278 eax, ebx, ecx and edx registers. The function checks if cpuid is
279 supported and returns 1 for valid cpuid information or 0 for
280 unsupported cpuid leaf. All pointers are required to be non-null. */
281
282 static __inline int
__get_cpuid(unsigned int __leaf,unsigned int * __eax,unsigned int * __ebx,unsigned int * __ecx,unsigned int * __edx)283 __get_cpuid (unsigned int __leaf,
284 unsigned int *__eax, unsigned int *__ebx,
285 unsigned int *__ecx, unsigned int *__edx)
286 {
287 unsigned int __ext = __leaf & 0x80000000;
288 unsigned int __maxlevel = __get_cpuid_max (__ext, 0);
289
290 if (__maxlevel == 0 || __maxlevel < __leaf)
291 return 0;
292
293 __cpuid (__leaf, *__eax, *__ebx, *__ecx, *__edx);
294 return 1;
295 }
296
297 /* Same as above, but sub-leaf can be specified. */
298
299 static __inline int
__get_cpuid_count(unsigned int __leaf,unsigned int __subleaf,unsigned int * __eax,unsigned int * __ebx,unsigned int * __ecx,unsigned int * __edx)300 __get_cpuid_count (unsigned int __leaf, unsigned int __subleaf,
301 unsigned int *__eax, unsigned int *__ebx,
302 unsigned int *__ecx, unsigned int *__edx)
303 {
304 unsigned int __ext = __leaf & 0x80000000;
305 unsigned int __maxlevel = __get_cpuid_max (__ext, 0);
306
307 if (__maxlevel == 0 || __maxlevel < __leaf)
308 return 0;
309
310 __cpuid_count (__leaf, __subleaf, *__eax, *__ebx, *__ecx, *__edx);
311 return 1;
312 }
313