1 /* MIPS Simulator definition. 2 Copyright (C) 1997, 1998, 2003, 2007, 2008, 2009, 2010, 2011 3 Free Software Foundation, Inc. 4 Contributed by Cygnus Support. 5 6 This file is part of GDB, the GNU debugger. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21 #ifndef SIM_MAIN_H 22 #define SIM_MAIN_H 23 24 /* This simulator doesn't cache the Current Instruction Address */ 25 /* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */ 26 /* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */ 27 28 #define SIM_HAVE_BIENDIAN 29 30 31 /* hobble some common features for moment */ 32 #define WITH_WATCHPOINTS 1 33 #define WITH_MODULO_MEMORY 1 34 35 36 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ 37 mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR)) 38 39 #include "sim-basics.h" 40 41 typedef address_word sim_cia; 42 43 #include "sim-base.h" 44 #include "bfd.h" 45 46 /* Deprecated macros and types for manipulating 64bit values. Use 47 ../common/sim-bits.h and ../common/sim-endian.h macros instead. */ 48 49 typedef signed64 word64; 50 typedef unsigned64 uword64; 51 52 #define WORD64LO(t) (unsigned int)((t)&0xFFFFFFFF) 53 #define WORD64HI(t) (unsigned int)(((uword64)(t))>>32) 54 #define SET64LO(t) (((uword64)(t))&0xFFFFFFFF) 55 #define SET64HI(t) (((uword64)(t))<<32) 56 #define WORD64(h,l) ((word64)((SET64HI(h)|SET64LO(l)))) 57 #define UWORD64(h,l) (SET64HI(h)|SET64LO(l)) 58 59 /* Check if a value will fit within a halfword: */ 60 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1)) 61 62 63 64 /* Floating-point operations: */ 65 66 #include "sim-fpu.h" 67 #include "cp1.h" 68 69 /* FPU registers must be one of the following types. All other values 70 are reserved (and undefined). */ 71 typedef enum { 72 fmt_single = 0, 73 fmt_double = 1, 74 fmt_word = 4, 75 fmt_long = 5, 76 fmt_ps = 6, 77 /* The following are well outside the normal acceptable format 78 range, and are used in the register status vector. */ 79 fmt_unknown = 0x10000000, 80 fmt_uninterpreted = 0x20000000, 81 fmt_uninterpreted_32 = 0x40000000, 82 fmt_uninterpreted_64 = 0x80000000U, 83 } FP_formats; 84 85 /* For paired word (pw) operations, the opcode representation is fmt_word, 86 but register transfers (StoreFPR, ValueFPR, etc.) are done as fmt_long. */ 87 #define fmt_pw fmt_long 88 89 /* This should be the COC1 value at the start of the preceding 90 instruction: */ 91 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0) 92 93 #ifdef TARGET_ENABLE_FR 94 /* FIXME: this should be enabled for all targets, but needs testing first. */ 95 #define SizeFGR() (((WITH_TARGET_FLOATING_POINT_BITSIZE) == 64) \ 96 ? ((SR & status_FR) ? 64 : 32) \ 97 : (WITH_TARGET_FLOATING_POINT_BITSIZE)) 98 #else 99 #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE) 100 #endif 101 102 103 104 105 106 /* HI/LO register accesses */ 107 108 /* For some MIPS targets, the HI/LO registers have certain timing 109 restrictions in that, for instance, a read of a HI register must be 110 separated by at least three instructions from a preceeding read. 111 112 The struct below is used to record the last access by each of A MT, 113 MF or other OP instruction to a HI/LO register. See mips.igen for 114 more details. */ 115 116 typedef struct _hilo_access { 117 signed64 timestamp; 118 address_word cia; 119 } hilo_access; 120 121 typedef struct _hilo_history { 122 hilo_access mt; 123 hilo_access mf; 124 hilo_access op; 125 } hilo_history; 126 127 128 129 130 /* Integer ALU operations: */ 131 132 #include "sim-alu.h" 133 134 #define ALU32_END(ANS) \ 135 if (ALU32_HAD_OVERFLOW) \ 136 SignalExceptionIntegerOverflow (); \ 137 (ANS) = (signed32) ALU32_OVERFLOW_RESULT 138 139 140 #define ALU64_END(ANS) \ 141 if (ALU64_HAD_OVERFLOW) \ 142 SignalExceptionIntegerOverflow (); \ 143 (ANS) = ALU64_OVERFLOW_RESULT; 144 145 146 147 148 149 /* The following is probably not used for MIPS IV onwards: */ 150 /* Slots for delayed register updates. For the moment we just have a 151 fixed number of slots (rather than a more generic, dynamic 152 system). This keeps the simulator fast. However, we only allow 153 for the register update to be delayed for a single instruction 154 cycle. */ 155 #define PSLOTS (8) /* Maximum number of instruction cycles */ 156 157 typedef struct _pending_write_queue { 158 int in; 159 int out; 160 int total; 161 int slot_delay[PSLOTS]; 162 int slot_size[PSLOTS]; 163 int slot_bit[PSLOTS]; 164 void *slot_dest[PSLOTS]; 165 unsigned64 slot_value[PSLOTS]; 166 } pending_write_queue; 167 168 #ifndef PENDING_TRACE 169 #define PENDING_TRACE 0 170 #endif 171 #define PENDING_IN ((CPU)->pending.in) 172 #define PENDING_OUT ((CPU)->pending.out) 173 #define PENDING_TOTAL ((CPU)->pending.total) 174 #define PENDING_SLOT_SIZE ((CPU)->pending.slot_size) 175 #define PENDING_SLOT_BIT ((CPU)->pending.slot_bit) 176 #define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay) 177 #define PENDING_SLOT_DEST ((CPU)->pending.slot_dest) 178 #define PENDING_SLOT_VALUE ((CPU)->pending.slot_value) 179 180 /* Invalidate the pending write queue, all pending writes are 181 discarded. */ 182 183 #define PENDING_INVALIDATE() \ 184 memset (&(CPU)->pending, 0, sizeof ((CPU)->pending)) 185 186 /* Schedule a write to DEST for N cycles time. For 64 bit 187 destinations, schedule two writes. For floating point registers, 188 the caller should schedule a write to both the dest register and 189 the FPR_STATE register. When BIT is non-negative, only BIT of DEST 190 is updated. */ 191 192 #define PENDING_SCHED(DEST,VAL,DELAY,BIT) \ 193 do { \ 194 if (PENDING_SLOT_DEST[PENDING_IN] != NULL) \ 195 sim_engine_abort (SD, CPU, cia, \ 196 "PENDING_SCHED - buffer overflow\n"); \ 197 if (PENDING_TRACE) \ 198 sim_io_eprintf (SD, "PENDING_SCHED - 0x%lx - dest 0x%lx, val 0x%lx, bit %d, size %d, pending_in %d, pending_out %d, pending_total %d\n", \ 199 (unsigned long) cia, (unsigned long) &(DEST), \ 200 (unsigned long) (VAL), (BIT), (int) sizeof (DEST),\ 201 PENDING_IN, PENDING_OUT, PENDING_TOTAL); \ 202 PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1; \ 203 PENDING_SLOT_DEST[PENDING_IN] = &(DEST); \ 204 PENDING_SLOT_VALUE[PENDING_IN] = (VAL); \ 205 PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST); \ 206 PENDING_SLOT_BIT[PENDING_IN] = (BIT); \ 207 PENDING_IN = (PENDING_IN + 1) % PSLOTS; \ 208 PENDING_TOTAL += 1; \ 209 } while (0) 210 211 #define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1) 212 #define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT) 213 214 #define PENDING_TICK() pending_tick (SD, CPU, cia) 215 216 #define PENDING_FLUSH() abort () /* think about this one */ 217 #define PENDING_FP() abort () /* think about this one */ 218 219 /* For backward compatibility */ 220 #define PENDING_FILL(R,VAL) \ 221 do { \ 222 if ((R) >= FGR_BASE && (R) < FGR_BASE + NR_FGR) \ 223 { \ 224 PENDING_SCHED(FGR[(R) - FGR_BASE], VAL, 1, -1); \ 225 PENDING_SCHED(FPR_STATE[(R) - FGR_BASE], fmt_uninterpreted, 1, -1); \ 226 } \ 227 else \ 228 PENDING_SCHED(GPR[(R)], VAL, 1, -1); \ 229 } while (0) 230 231 232 enum float_operation 233 { 234 FLOP_ADD, FLOP_SUB, FLOP_MUL, FLOP_MADD, 235 FLOP_MSUB, FLOP_MAX=10, FLOP_MIN, FLOP_ABS, 236 FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23 237 }; 238 239 240 /* The internal representation of an MDMX accumulator. 241 Note that 24 and 48 bit accumulator elements are represented in 242 32 or 64 bits. Since the accumulators are 2's complement with 243 overflow suppressed, high-order bits can be ignored in most contexts. */ 244 245 typedef signed32 signed24; 246 typedef signed64 signed48; 247 248 typedef union { 249 signed24 ob[8]; 250 signed48 qh[4]; 251 } MDMX_accumulator; 252 253 254 /* Conventional system arguments. */ 255 #define SIM_STATE sim_cpu *cpu, address_word cia 256 #define SIM_ARGS CPU, cia 257 258 struct _sim_cpu { 259 260 261 /* The following are internal simulator state variables: */ 262 #define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0) 263 #define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA)) 264 address_word dspc; /* delay-slot PC */ 265 #define DSPC ((CPU)->dspc) 266 267 #define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET)) 268 #define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_) 269 270 271 /* State of the simulator */ 272 unsigned int state; 273 unsigned int dsstate; 274 #define STATE ((CPU)->state) 275 #define DSSTATE ((CPU)->dsstate) 276 277 /* Flags in the "state" variable: */ 278 #define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */ 279 #define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */ 280 #define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */ 281 #define simPCOC0 (1 << 17) /* COC[1] from current */ 282 #define simPCOC1 (1 << 18) /* COC[1] from previous */ 283 #define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */ 284 #define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */ 285 #define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */ 286 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */ 287 288 #ifndef ENGINE_ISSUE_PREFIX_HOOK 289 #define ENGINE_ISSUE_PREFIX_HOOK() \ 290 { \ 291 /* Perform any pending writes */ \ 292 PENDING_TICK(); \ 293 /* Set previous flag, depending on current: */ \ 294 if (STATE & simPCOC0) \ 295 STATE |= simPCOC1; \ 296 else \ 297 STATE &= ~simPCOC1; \ 298 /* and update the current value: */ \ 299 if (GETFCC(0)) \ 300 STATE |= simPCOC0; \ 301 else \ 302 STATE &= ~simPCOC0; \ 303 } 304 #endif /* ENGINE_ISSUE_PREFIX_HOOK */ 305 306 307 /* This is nasty, since we have to rely on matching the register 308 numbers used by GDB. Unfortunately, depending on the MIPS target 309 GDB uses different register numbers. We cannot just include the 310 relevant "gdb/tm.h" link, since GDB may not be configured before 311 the sim world, and also the GDB header file requires too much other 312 state. */ 313 314 #ifndef TM_MIPS_H 315 #define LAST_EMBED_REGNUM (96) 316 #define NUM_REGS (LAST_EMBED_REGNUM + 1) 317 318 #define FP0_REGNUM 38 /* Floating point register 0 (single float) */ 319 #define FCRCS_REGNUM 70 /* FP control/status */ 320 #define FCRIR_REGNUM 71 /* FP implementation/revision */ 321 #endif 322 323 324 /* To keep this default simulator simple, and fast, we use a direct 325 vector of registers. The internal simulator engine then uses 326 manifests to access the correct slot. */ 327 328 unsigned_word registers[LAST_EMBED_REGNUM + 1]; 329 330 int register_widths[NUM_REGS]; 331 #define REGISTERS ((CPU)->registers) 332 333 #define GPR (®ISTERS[0]) 334 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL)) 335 336 #define LO (REGISTERS[33]) 337 #define HI (REGISTERS[34]) 338 #define PCIDX 37 339 #define PC (REGISTERS[PCIDX]) 340 #define CAUSE (REGISTERS[36]) 341 #define SRIDX (32) 342 #define SR (REGISTERS[SRIDX]) /* CPU status register */ 343 #define FCR0IDX (71) 344 #define FCR0 (REGISTERS[FCR0IDX]) /* really a 32bit register */ 345 #define FCR31IDX (70) 346 #define FCR31 (REGISTERS[FCR31IDX]) /* really a 32bit register */ 347 #define FCSR (FCR31) 348 #define Debug (REGISTERS[86]) 349 #define DEPC (REGISTERS[87]) 350 #define EPC (REGISTERS[88]) 351 #define ACX (REGISTERS[89]) 352 353 #define AC0LOIDX (33) /* Must be the same register as LO */ 354 #define AC0HIIDX (34) /* Must be the same register as HI */ 355 #define AC1LOIDX (90) 356 #define AC1HIIDX (91) 357 #define AC2LOIDX (92) 358 #define AC2HIIDX (93) 359 #define AC3LOIDX (94) 360 #define AC3HIIDX (95) 361 362 #define DSPLO(N) (REGISTERS[DSPLO_REGNUM[N]]) 363 #define DSPHI(N) (REGISTERS[DSPHI_REGNUM[N]]) 364 365 #define DSPCRIDX (96) /* DSP control register */ 366 #define DSPCR (REGISTERS[DSPCRIDX]) 367 368 #define DSPCR_POS_SHIFT (0) 369 #define DSPCR_POS_MASK (0x3f) 370 #define DSPCR_POS_SMASK (DSPCR_POS_MASK << DSPCR_POS_SHIFT) 371 372 #define DSPCR_SCOUNT_SHIFT (7) 373 #define DSPCR_SCOUNT_MASK (0x3f) 374 #define DSPCR_SCOUNT_SMASK (DSPCR_SCOUNT_MASK << DSPCR_SCOUNT_SHIFT) 375 376 #define DSPCR_CARRY_SHIFT (13) 377 #define DSPCR_CARRY_MASK (1) 378 #define DSPCR_CARRY_SMASK (DSPCR_CARRY_MASK << DSPCR_CARRY_SHIFT) 379 #define DSPCR_CARRY (1 << DSPCR_CARRY_SHIFT) 380 381 #define DSPCR_EFI_SHIFT (14) 382 #define DSPCR_EFI_MASK (1) 383 #define DSPCR_EFI_SMASK (DSPCR_EFI_MASK << DSPCR_EFI_SHIFT) 384 #define DSPCR_EFI (1 << DSPCR_EFI_MASK) 385 386 #define DSPCR_OUFLAG_SHIFT (16) 387 #define DSPCR_OUFLAG_MASK (0xff) 388 #define DSPCR_OUFLAG_SMASK (DSPCR_OUFLAG_MASK << DSPCR_OUFLAG_SHIFT) 389 #define DSPCR_OUFLAG4 (1 << (DSPCR_OUFLAG_SHIFT + 4)) 390 #define DSPCR_OUFLAG5 (1 << (DSPCR_OUFLAG_SHIFT + 5)) 391 #define DSPCR_OUFLAG6 (1 << (DSPCR_OUFLAG_SHIFT + 6)) 392 #define DSPCR_OUFLAG7 (1 << (DSPCR_OUFLAG_SHIFT + 7)) 393 394 #define DSPCR_CCOND_SHIFT (24) 395 #define DSPCR_CCOND_MASK (0xf) 396 #define DSPCR_CCOND_SMASK (DSPCR_CCOND_MASK << DSPCR_CCOND_SHIFT) 397 398 /* All internal state modified by signal_exception() that may need to be 399 rolled back for passing moment-of-exception image back to gdb. */ 400 unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1]; 401 unsigned_word exc_suspend_registers[LAST_EMBED_REGNUM + 1]; 402 int exc_suspended; 403 404 #define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mips_cpu_exception_trigger(SD,CPU,CIA) 405 #define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mips_cpu_exception_suspend(SD,CPU,EXC) 406 #define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mips_cpu_exception_resume(SD,CPU,EXC) 407 408 unsigned_word c0_config_reg; 409 #define C0_CONFIG ((CPU)->c0_config_reg) 410 411 /* The following are pseudonyms for standard registers */ 412 #define ZERO (REGISTERS[0]) 413 #define V0 (REGISTERS[2]) 414 #define A0 (REGISTERS[4]) 415 #define A1 (REGISTERS[5]) 416 #define A2 (REGISTERS[6]) 417 #define A3 (REGISTERS[7]) 418 #define T8IDX 24 419 #define T8 (REGISTERS[T8IDX]) 420 #define SPIDX 29 421 #define SP (REGISTERS[SPIDX]) 422 #define RAIDX 31 423 #define RA (REGISTERS[RAIDX]) 424 425 /* While space is allocated in the main registers arrray for some of 426 the COP0 registers, that space isn't sufficient. Unknown COP0 427 registers overflow into the array below */ 428 429 #define NR_COP0_GPR 32 430 unsigned_word cop0_gpr[NR_COP0_GPR]; 431 #define COP0_GPR ((CPU)->cop0_gpr) 432 #define COP0_BADVADDR (COP0_GPR[8]) 433 434 /* While space is allocated for the floating point registers in the 435 main registers array, they are stored separatly. This is because 436 their size may not necessarily match the size of either the 437 general-purpose or system specific registers. */ 438 #define NR_FGR (32) 439 #define FGR_BASE FP0_REGNUM 440 fp_word fgr[NR_FGR]; 441 #define FGR ((CPU)->fgr) 442 443 /* Keep the current format state for each register: */ 444 FP_formats fpr_state[32]; 445 #define FPR_STATE ((CPU)->fpr_state) 446 447 pending_write_queue pending; 448 449 /* The MDMX accumulator (used only for MDMX ASE). */ 450 MDMX_accumulator acc; 451 #define ACC ((CPU)->acc) 452 453 /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic 454 read-write instructions. It is set when a linked load occurs. It 455 is tested and cleared by the conditional store. It is cleared 456 (during other CPU operations) when a store to the location would 457 no longer be atomic. In particular, it is cleared by exception 458 return instructions. */ 459 int llbit; 460 #define LLBIT ((CPU)->llbit) 461 462 463 /* The HIHISTORY and LOHISTORY timestamps are used to ensure that 464 corruptions caused by using the HI or LO register too close to a 465 following operation is spotted. See mips.igen for more details. */ 466 467 hilo_history hi_history; 468 #define HIHISTORY (&(CPU)->hi_history) 469 hilo_history lo_history; 470 #define LOHISTORY (&(CPU)->lo_history) 471 472 473 sim_cpu_base base; 474 }; 475 476 477 /* MIPS specific simulator watch config */ 478 479 void watch_options_install PARAMS ((SIM_DESC sd)); 480 481 struct swatch { 482 sim_event *pc; 483 sim_event *clock; 484 sim_event *cycles; 485 }; 486 487 488 /* FIXME: At present much of the simulator is still static */ 489 struct sim_state { 490 491 struct swatch watch; 492 493 sim_cpu cpu[MAX_NR_PROCESSORS]; 494 #if (WITH_SMP) 495 #define STATE_CPU(sd,n) (&(sd)->cpu[n]) 496 #else 497 #define STATE_CPU(sd,n) (&(sd)->cpu[0]) 498 #endif 499 500 501 sim_state_base base; 502 }; 503 504 505 506 /* Status information: */ 507 508 /* TODO : these should be the bitmasks for these bits within the 509 status register. At the moment the following are VR4300 510 bit-positions: */ 511 #define status_KSU_mask (0x18) /* mask for KSU bits */ 512 #define status_KSU_shift (3) /* shift for field */ 513 #define ksu_kernel (0x0) 514 #define ksu_supervisor (0x1) 515 #define ksu_user (0x2) 516 #define ksu_unknown (0x3) 517 518 #define SR_KSU ((SR & status_KSU_mask) >> status_KSU_shift) 519 520 #define status_IE (1 << 0) /* Interrupt enable */ 521 #define status_EIE (1 << 16) /* Enable Interrupt Enable */ 522 #define status_EXL (1 << 1) /* Exception level */ 523 #define status_RE (1 << 25) /* Reverse Endian in user mode */ 524 #define status_FR (1 << 26) /* enables MIPS III additional FP registers */ 525 #define status_SR (1 << 20) /* soft reset or NMI */ 526 #define status_BEV (1 << 22) /* Location of general exception vectors */ 527 #define status_TS (1 << 21) /* TLB shutdown has occurred */ 528 #define status_ERL (1 << 2) /* Error level */ 529 #define status_IM7 (1 << 15) /* Timer Interrupt Mask */ 530 #define status_RP (1 << 27) /* Reduced Power mode */ 531 532 /* Specializations for TX39 family */ 533 #define status_IEc (1 << 0) /* Interrupt enable (current) */ 534 #define status_KUc (1 << 1) /* Kernel/User mode */ 535 #define status_IEp (1 << 2) /* Interrupt enable (previous) */ 536 #define status_KUp (1 << 3) /* Kernel/User mode */ 537 #define status_IEo (1 << 4) /* Interrupt enable (old) */ 538 #define status_KUo (1 << 5) /* Kernel/User mode */ 539 #define status_IM_mask (0xff) /* Interrupt mask */ 540 #define status_IM_shift (8) 541 #define status_NMI (1 << 20) /* NMI */ 542 #define status_NMI (1 << 20) /* NMI */ 543 544 /* Status bits used by MIPS32/MIPS64. */ 545 #define status_UX (1 << 5) /* 64-bit user addrs */ 546 #define status_SX (1 << 6) /* 64-bit supervisor addrs */ 547 #define status_KX (1 << 7) /* 64-bit kernel addrs */ 548 #define status_TS (1 << 21) /* TLB shutdown has occurred */ 549 #define status_PX (1 << 23) /* Enable 64 bit operations */ 550 #define status_MX (1 << 24) /* Enable MDMX resources */ 551 #define status_CU0 (1 << 28) /* Coprocessor 0 usable */ 552 #define status_CU1 (1 << 29) /* Coprocessor 1 usable */ 553 #define status_CU2 (1 << 30) /* Coprocessor 2 usable */ 554 #define status_CU3 (1 << 31) /* Coprocessor 3 usable */ 555 /* Bits reserved for implementations: */ 556 #define status_SBX (1 << 16) /* Enable SiByte SB-1 extensions. */ 557 558 #define cause_BD ((unsigned)1 << 31) /* L1 Exception in branch delay slot */ 559 #define cause_BD2 (1 << 30) /* L2 Exception in branch delay slot */ 560 #define cause_CE_mask 0x30000000 /* Coprocessor exception */ 561 #define cause_CE_shift 28 562 #define cause_EXC2_mask 0x00070000 563 #define cause_EXC2_shift 16 564 #define cause_IP7 (1 << 15) /* Interrupt pending */ 565 #define cause_SIOP (1 << 12) /* SIO pending */ 566 #define cause_IP3 (1 << 11) /* Int 0 pending */ 567 #define cause_IP2 (1 << 10) /* Int 1 pending */ 568 569 #define cause_EXC_mask (0x1c) /* Exception code */ 570 #define cause_EXC_shift (2) 571 572 #define cause_SW0 (1 << 8) /* Software interrupt 0 */ 573 #define cause_SW1 (1 << 9) /* Software interrupt 1 */ 574 #define cause_IP_mask (0x3f) /* Interrupt pending field */ 575 #define cause_IP_shift (10) 576 577 #define cause_set_EXC(x) CAUSE = (CAUSE & ~cause_EXC_mask) | ((x << cause_EXC_shift) & cause_EXC_mask) 578 #define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask) 579 580 581 /* NOTE: We keep the following status flags as bit values (1 for true, 582 0 for false). This allows them to be used in binary boolean 583 operations without worrying about what exactly the non-zero true 584 value is. */ 585 586 /* UserMode */ 587 #ifdef SUBTARGET_R3900 588 #define UserMode ((SR & status_KUc) ? 1 : 0) 589 #else 590 #define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0) 591 #endif /* SUBTARGET_R3900 */ 592 593 /* BigEndianMem */ 594 /* Hardware configuration. Affects endianness of LoadMemory and 595 StoreMemory and the endianness of Kernel and Supervisor mode 596 execution. The value is 0 for little-endian; 1 for big-endian. */ 597 #define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) 598 /*(state & simBE) ? 1 : 0)*/ 599 600 /* ReverseEndian */ 601 /* This mode is selected if in User mode with the RE bit being set in 602 SR (Status Register). It reverses the endianness of load and store 603 instructions. */ 604 #define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0) 605 606 /* BigEndianCPU */ 607 /* The endianness for load and store instructions (0=little;1=big). In 608 User mode this endianness may be switched by setting the state_RE 609 bit in the SR register. Thus, BigEndianCPU may be computed as 610 (BigEndianMem EOR ReverseEndian). */ 611 #define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */ 612 613 614 615 /* Exceptions: */ 616 617 /* NOTE: These numbers depend on the processor architecture being 618 simulated: */ 619 enum ExceptionCause { 620 Interrupt = 0, 621 TLBModification = 1, 622 TLBLoad = 2, 623 TLBStore = 3, 624 AddressLoad = 4, 625 AddressStore = 5, 626 InstructionFetch = 6, 627 DataReference = 7, 628 SystemCall = 8, 629 BreakPoint = 9, 630 ReservedInstruction = 10, 631 CoProcessorUnusable = 11, 632 IntegerOverflow = 12, /* Arithmetic overflow (IDT monitor raises SIGFPE) */ 633 Trap = 13, 634 FPE = 15, 635 DebugBreakPoint = 16, /* Impl. dep. in MIPS32/MIPS64. */ 636 MDMX = 22, 637 Watch = 23, 638 MCheck = 24, 639 CacheErr = 30, 640 NMIReset = 31, /* Reserved in MIPS32/MIPS64. */ 641 642 643 /* The following exception code is actually private to the simulator 644 world. It is *NOT* a processor feature, and is used to signal 645 run-time errors in the simulator. */ 646 SimulatorFault = 0xFFFFFFFF 647 }; 648 649 #define TLB_REFILL (0) 650 #define TLB_INVALID (1) 651 652 653 /* The following break instructions are reserved for use by the 654 simulator. The first is used to halt the simulation. The second 655 is used by gdb for break-points. NOTE: Care must be taken, since 656 this value may be used in later revisions of the MIPS ISA. */ 657 #define HALT_INSTRUCTION_MASK (0x03FFFFC0) 658 659 #define HALT_INSTRUCTION (0x03ff000d) 660 #define HALT_INSTRUCTION2 (0x0000ffcd) 661 662 663 #define BREAKPOINT_INSTRUCTION (0x0005000d) 664 #define BREAKPOINT_INSTRUCTION2 (0x0000014d) 665 666 667 668 void interrupt_event (SIM_DESC sd, void *data); 669 670 void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...); 671 #define SignalException(exc,instruction) signal_exception (SD, CPU, cia, (exc), (instruction)) 672 #define SignalExceptionInterrupt(level) signal_exception (SD, CPU, cia, Interrupt, level) 673 #define SignalExceptionInstructionFetch() signal_exception (SD, CPU, cia, InstructionFetch) 674 #define SignalExceptionAddressStore() signal_exception (SD, CPU, cia, AddressStore) 675 #define SignalExceptionAddressLoad() signal_exception (SD, CPU, cia, AddressLoad) 676 #define SignalExceptionDataReference() signal_exception (SD, CPU, cia, DataReference) 677 #define SignalExceptionSimulatorFault(buf) signal_exception (SD, CPU, cia, SimulatorFault, buf) 678 #define SignalExceptionFPE() signal_exception (SD, CPU, cia, FPE) 679 #define SignalExceptionIntegerOverflow() signal_exception (SD, CPU, cia, IntegerOverflow) 680 #define SignalExceptionCoProcessorUnusable(cop) signal_exception (SD, CPU, cia, CoProcessorUnusable) 681 #define SignalExceptionNMIReset() signal_exception (SD, CPU, cia, NMIReset) 682 #define SignalExceptionTLBRefillStore() signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL) 683 #define SignalExceptionTLBRefillLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL) 684 #define SignalExceptionTLBInvalidStore() signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID) 685 #define SignalExceptionTLBInvalidLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID) 686 #define SignalExceptionTLBModification() signal_exception (SD, CPU, cia, TLBModification) 687 #define SignalExceptionMDMX() signal_exception (SD, CPU, cia, MDMX) 688 #define SignalExceptionWatch() signal_exception (SD, CPU, cia, Watch) 689 #define SignalExceptionMCheck() signal_exception (SD, CPU, cia, MCheck) 690 #define SignalExceptionCacheErr() signal_exception (SD, CPU, cia, CacheErr) 691 692 /* Co-processor accesses */ 693 694 /* XXX FIXME: For now, assume that FPU (cp1) is always usable. */ 695 #define COP_Usable(coproc_num) (coproc_num == 1) 696 697 void cop_lw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword)); 698 void cop_ld PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword)); 699 unsigned int cop_sw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg)); 700 uword64 cop_sd PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg)); 701 702 #define COP_LW(coproc_num,coproc_reg,memword) \ 703 cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword) 704 #define COP_LD(coproc_num,coproc_reg,memword) \ 705 cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword) 706 #define COP_SW(coproc_num,coproc_reg) \ 707 cop_sw (SD, CPU, cia, coproc_num, coproc_reg) 708 #define COP_SD(coproc_num,coproc_reg) \ 709 cop_sd (SD, CPU, cia, coproc_num, coproc_reg) 710 711 712 void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction)); 713 #define DecodeCoproc(instruction) \ 714 decode_coproc (SD, CPU, cia, (instruction)) 715 716 int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg); 717 718 719 /* FPR access. */ 720 unsigned64 value_fpr (SIM_STATE, int fpr, FP_formats); 721 #define ValueFPR(FPR,FMT) value_fpr (SIM_ARGS, (FPR), (FMT)) 722 void store_fpr (SIM_STATE, int fpr, FP_formats fmt, unsigned64 value); 723 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SIM_ARGS, (FPR), (FMT), (VALUE)) 724 unsigned64 ps_lower (SIM_STATE, unsigned64 op); 725 #define PSLower(op) ps_lower (SIM_ARGS, op) 726 unsigned64 ps_upper (SIM_STATE, unsigned64 op); 727 #define PSUpper(op) ps_upper (SIM_ARGS, op) 728 unsigned64 pack_ps (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats from); 729 #define PackPS(op1,op2) pack_ps (SIM_ARGS, op1, op2, fmt_single) 730 731 732 /* FCR access. */ 733 unsigned_word value_fcr (SIM_STATE, int fcr); 734 #define ValueFCR(FCR) value_fcr (SIM_ARGS, (FCR)) 735 void store_fcr (SIM_STATE, int fcr, unsigned_word value); 736 #define StoreFCR(FCR,VALUE) store_fcr (SIM_ARGS, (FCR), (VALUE)) 737 void test_fcsr (SIM_STATE); 738 #define TestFCSR() test_fcsr (SIM_ARGS) 739 740 741 /* FPU operations. */ 742 void fp_cmp (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt, int abs, int cond, int cc); 743 #define Compare(op1,op2,fmt,cond,cc) fp_cmp(SIM_ARGS, op1, op2, fmt, 0, cond, cc) 744 unsigned64 fp_abs (SIM_STATE, unsigned64 op, FP_formats fmt); 745 #define AbsoluteValue(op,fmt) fp_abs(SIM_ARGS, op, fmt) 746 unsigned64 fp_neg (SIM_STATE, unsigned64 op, FP_formats fmt); 747 #define Negate(op,fmt) fp_neg(SIM_ARGS, op, fmt) 748 unsigned64 fp_add (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); 749 #define Add(op1,op2,fmt) fp_add(SIM_ARGS, op1, op2, fmt) 750 unsigned64 fp_sub (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); 751 #define Sub(op1,op2,fmt) fp_sub(SIM_ARGS, op1, op2, fmt) 752 unsigned64 fp_mul (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); 753 #define Multiply(op1,op2,fmt) fp_mul(SIM_ARGS, op1, op2, fmt) 754 unsigned64 fp_div (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); 755 #define Divide(op1,op2,fmt) fp_div(SIM_ARGS, op1, op2, fmt) 756 unsigned64 fp_recip (SIM_STATE, unsigned64 op, FP_formats fmt); 757 #define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt) 758 unsigned64 fp_sqrt (SIM_STATE, unsigned64 op, FP_formats fmt); 759 #define SquareRoot(op,fmt) fp_sqrt(SIM_ARGS, op, fmt) 760 unsigned64 fp_rsqrt (SIM_STATE, unsigned64 op, FP_formats fmt); 761 #define RSquareRoot(op,fmt) fp_rsqrt(SIM_ARGS, op, fmt) 762 unsigned64 fp_madd (SIM_STATE, unsigned64 op1, unsigned64 op2, 763 unsigned64 op3, FP_formats fmt); 764 #define MultiplyAdd(op1,op2,op3,fmt) fp_madd(SIM_ARGS, op1, op2, op3, fmt) 765 unsigned64 fp_msub (SIM_STATE, unsigned64 op1, unsigned64 op2, 766 unsigned64 op3, FP_formats fmt); 767 #define MultiplySub(op1,op2,op3,fmt) fp_msub(SIM_ARGS, op1, op2, op3, fmt) 768 unsigned64 fp_nmadd (SIM_STATE, unsigned64 op1, unsigned64 op2, 769 unsigned64 op3, FP_formats fmt); 770 #define NegMultiplyAdd(op1,op2,op3,fmt) fp_nmadd(SIM_ARGS, op1, op2, op3, fmt) 771 unsigned64 fp_nmsub (SIM_STATE, unsigned64 op1, unsigned64 op2, 772 unsigned64 op3, FP_formats fmt); 773 #define NegMultiplySub(op1,op2,op3,fmt) fp_nmsub(SIM_ARGS, op1, op2, op3, fmt) 774 unsigned64 convert (SIM_STATE, int rm, unsigned64 op, FP_formats from, FP_formats to); 775 #define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to) 776 unsigned64 convert_ps (SIM_STATE, int rm, unsigned64 op, FP_formats from, 777 FP_formats to); 778 #define ConvertPS(rm,op,from,to) convert_ps (SIM_ARGS, rm, op, from, to) 779 780 781 /* MIPS-3D ASE operations. */ 782 #define CompareAbs(op1,op2,fmt,cond,cc) \ 783 fp_cmp(SIM_ARGS, op1, op2, fmt, 1, cond, cc) 784 unsigned64 fp_add_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); 785 #define AddR(op1,op2,fmt) fp_add_r(SIM_ARGS, op1, op2, fmt) 786 unsigned64 fp_mul_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); 787 #define MultiplyR(op1,op2,fmt) fp_mul_r(SIM_ARGS, op1, op2, fmt) 788 unsigned64 fp_recip1 (SIM_STATE, unsigned64 op, FP_formats fmt); 789 #define Recip1(op,fmt) fp_recip1(SIM_ARGS, op, fmt) 790 unsigned64 fp_recip2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); 791 #define Recip2(op1,op2,fmt) fp_recip2(SIM_ARGS, op1, op2, fmt) 792 unsigned64 fp_rsqrt1 (SIM_STATE, unsigned64 op, FP_formats fmt); 793 #define RSquareRoot1(op,fmt) fp_rsqrt1(SIM_ARGS, op, fmt) 794 unsigned64 fp_rsqrt2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); 795 #define RSquareRoot2(op1,op2,fmt) fp_rsqrt2(SIM_ARGS, op1, op2, fmt) 796 797 798 /* MDMX access. */ 799 800 typedef unsigned int MX_fmtsel; /* MDMX format select field (5 bits). */ 801 #define ob_fmtsel(sel) (((sel)<<1)|0x0) 802 #define qh_fmtsel(sel) (((sel)<<2)|0x1) 803 804 #define fmt_mdmx fmt_uninterpreted 805 806 #define MX_VECT_AND (0) 807 #define MX_VECT_NOR (1) 808 #define MX_VECT_OR (2) 809 #define MX_VECT_XOR (3) 810 #define MX_VECT_SLL (4) 811 #define MX_VECT_SRL (5) 812 #define MX_VECT_ADD (6) 813 #define MX_VECT_SUB (7) 814 #define MX_VECT_MIN (8) 815 #define MX_VECT_MAX (9) 816 #define MX_VECT_MUL (10) 817 #define MX_VECT_MSGN (11) 818 #define MX_VECT_SRA (12) 819 #define MX_VECT_ABSD (13) /* SB-1 only. */ 820 #define MX_VECT_AVG (14) /* SB-1 only. */ 821 822 unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel); 823 #define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel) 824 #define MX_And(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AND, op1, vt, fmtsel) 825 #define MX_Max(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MAX, op1, vt, fmtsel) 826 #define MX_Min(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MIN, op1, vt, fmtsel) 827 #define MX_Msgn(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MSGN, op1, vt, fmtsel) 828 #define MX_Mul(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MUL, op1, vt, fmtsel) 829 #define MX_Nor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_NOR, op1, vt, fmtsel) 830 #define MX_Or(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_OR, op1, vt, fmtsel) 831 #define MX_ShiftLeftLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SLL, op1, vt, fmtsel) 832 #define MX_ShiftRightArith(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRA, op1, vt, fmtsel) 833 #define MX_ShiftRightLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRL, op1, vt, fmtsel) 834 #define MX_Sub(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SUB, op1, vt, fmtsel) 835 #define MX_Xor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_XOR, op1, vt, fmtsel) 836 #define MX_AbsDiff(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ABSD, op1, vt, fmtsel) 837 #define MX_Avg(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AVG, op1, vt, fmtsel) 838 839 #define MX_C_EQ 0x1 840 #define MX_C_LT 0x4 841 842 void mdmx_cc_op (SIM_STATE, int cond, unsigned64 op1, int vt, MX_fmtsel fmtsel); 843 #define MX_Comp(op1,cond,vt,fmtsel) mdmx_cc_op(SIM_ARGS, cond, op1, vt, fmtsel) 844 845 unsigned64 mdmx_pick_op (SIM_STATE, int tf, unsigned64 op1, int vt, MX_fmtsel fmtsel); 846 #define MX_Pick(tf,op1,vt,fmtsel) mdmx_pick_op(SIM_ARGS, tf, op1, vt, fmtsel) 847 848 #define MX_VECT_ADDA (0) 849 #define MX_VECT_ADDL (1) 850 #define MX_VECT_MULA (2) 851 #define MX_VECT_MULL (3) 852 #define MX_VECT_MULS (4) 853 #define MX_VECT_MULSL (5) 854 #define MX_VECT_SUBA (6) 855 #define MX_VECT_SUBL (7) 856 #define MX_VECT_ABSDA (8) /* SB-1 only. */ 857 858 void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel); 859 #define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel) 860 #define MX_AddL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDL, op1, vt, fmtsel) 861 #define MX_MulA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULA, op1, vt, fmtsel) 862 #define MX_MulL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULL, op1, vt, fmtsel) 863 #define MX_MulS(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULS, op1, vt, fmtsel) 864 #define MX_MulSL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULSL, op1, vt, fmtsel) 865 #define MX_SubA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBA, op1, vt, fmtsel) 866 #define MX_SubL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBL, op1, vt, fmtsel) 867 #define MX_AbsDiffC(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ABSDA, op1, vt, fmtsel) 868 869 #define MX_FMT_OB (0) 870 #define MX_FMT_QH (1) 871 872 /* The following codes chosen to indicate the units of shift. */ 873 #define MX_RAC_L (0) 874 #define MX_RAC_M (1) 875 #define MX_RAC_H (2) 876 877 unsigned64 mdmx_rac_op (SIM_STATE, int, int); 878 #define MX_RAC(op,fmt) mdmx_rac_op(SIM_ARGS, op, fmt) 879 880 void mdmx_wacl (SIM_STATE, int, unsigned64, unsigned64); 881 #define MX_WACL(fmt,vs,vt) mdmx_wacl(SIM_ARGS, fmt, vs, vt) 882 void mdmx_wach (SIM_STATE, int, unsigned64); 883 #define MX_WACH(fmt,vs) mdmx_wach(SIM_ARGS, fmt, vs) 884 885 #define MX_RND_AS (0) 886 #define MX_RND_AU (1) 887 #define MX_RND_ES (2) 888 #define MX_RND_EU (3) 889 #define MX_RND_ZS (4) 890 #define MX_RND_ZU (5) 891 892 unsigned64 mdmx_round_op (SIM_STATE, int, int, MX_fmtsel); 893 #define MX_RNAS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AS, vt, fmt) 894 #define MX_RNAU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AU, vt, fmt) 895 #define MX_RNES(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ES, vt, fmt) 896 #define MX_RNEU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_EU, vt, fmt) 897 #define MX_RZS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZS, vt, fmt) 898 #define MX_RZU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZU, vt, fmt) 899 900 unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64); 901 #define MX_SHFL(shop,op1,op2) mdmx_shuffle(SIM_ARGS, shop, op1, op2) 902 903 904 905 /* Memory accesses */ 906 907 /* The following are generic to all versions of the MIPS architecture 908 to date: */ 909 910 /* Memory Access Types (for CCA): */ 911 #define Uncached (0) 912 #define CachedNoncoherent (1) 913 #define CachedCoherent (2) 914 #define Cached (3) 915 916 #define isINSTRUCTION (1 == 0) /* FALSE */ 917 #define isDATA (1 == 1) /* TRUE */ 918 #define isLOAD (1 == 0) /* FALSE */ 919 #define isSTORE (1 == 1) /* TRUE */ 920 #define isREAL (1 == 0) /* FALSE */ 921 #define isRAW (1 == 1) /* TRUE */ 922 /* The parameter HOST (isTARGET / isHOST) is ignored */ 923 #define isTARGET (1 == 0) /* FALSE */ 924 /* #define isHOST (1 == 1) TRUE */ 925 926 /* The "AccessLength" specifications for Loads and Stores. NOTE: This 927 is the number of bytes minus 1. */ 928 #define AccessLength_BYTE (0) 929 #define AccessLength_HALFWORD (1) 930 #define AccessLength_TRIPLEBYTE (2) 931 #define AccessLength_WORD (3) 932 #define AccessLength_QUINTIBYTE (4) 933 #define AccessLength_SEXTIBYTE (5) 934 #define AccessLength_SEPTIBYTE (6) 935 #define AccessLength_DOUBLEWORD (7) 936 #define AccessLength_QUADWORD (15) 937 938 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \ 939 ? AccessLength_DOUBLEWORD /*7*/ \ 940 : AccessLength_WORD /*3*/) 941 #define PSIZE (WITH_TARGET_ADDRESS_BITSIZE) 942 943 944 INLINE_SIM_MAIN (int) address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw)); 945 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \ 946 address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw) 947 948 INLINE_SIM_MAIN (void) load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD)); 949 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \ 950 load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD) 951 952 INLINE_SIM_MAIN (void) store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr)); 953 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \ 954 store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr) 955 956 INLINE_SIM_MAIN (void) cache_op PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction)); 957 #define CacheOp(op,pAddr,vAddr,instruction) \ 958 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction) 959 960 INLINE_SIM_MAIN (void) sync_operation PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype)); 961 #define SyncOperation(stype) \ 962 sync_operation (SD, CPU, cia, (stype)) 963 964 INLINE_SIM_MAIN (void) prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint)); 965 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) \ 966 prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint) 967 968 void unpredictable_action (sim_cpu *cpu, address_word cia); 969 #define NotWordValue(val) not_word_value (SD_, (val)) 970 #define Unpredictable() unpredictable (SD_) 971 #define UnpredictableResult() /* For now, do nothing. */ 972 973 INLINE_SIM_MAIN (unsigned32) ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr)); 974 #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA)) 975 INLINE_SIM_MAIN (unsigned16) ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr)); 976 #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1)) 977 #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR)) 978 979 void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...)); 980 extern FILE *tracefh; 981 982 extern int DSPLO_REGNUM[4]; 983 extern int DSPHI_REGNUM[4]; 984 985 INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia)); 986 extern SIM_CORE_SIGNAL_FN mips_core_signal; 987 988 char* pr_addr PARAMS ((SIM_ADDR addr)); 989 char* pr_uword64 PARAMS ((uword64 addr)); 990 991 992 #define GPR_CLEAR(N) do { GPR_SET((N),0); } while (0) 993 994 void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc); 995 void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception); 996 void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception); 997 998 #ifdef MIPS_MACH_MULTI 999 extern int mips_mach_multi(SIM_DESC sd); 1000 #define MIPS_MACH(SD) mips_mach_multi(SD) 1001 #else 1002 #define MIPS_MACH(SD) MIPS_MACH_DEFAULT 1003 #endif 1004 1005 /* Macros for determining whether a MIPS IV or MIPS V part is subject 1006 to the hi/lo restrictions described in mips.igen. */ 1007 1008 #define MIPS_MACH_HAS_MT_HILO_HAZARD(SD) \ 1009 (MIPS_MACH (SD) != bfd_mach_mips5500) 1010 1011 #define MIPS_MACH_HAS_MULT_HILO_HAZARD(SD) \ 1012 (MIPS_MACH (SD) != bfd_mach_mips5500) 1013 1014 #define MIPS_MACH_HAS_DIV_HILO_HAZARD(SD) \ 1015 (MIPS_MACH (SD) != bfd_mach_mips5500) 1016 1017 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE) 1018 #include "sim-main.c" 1019 #endif 1020 1021 #endif 1022