1 /* This file is part of the program psim. 2 3 Copyright 1994, 1995, 1996, 1997, 2003 Andrew Cagney 4 5 This program is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 2 of the License, or 8 (at your option) any later version. 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, write to the Free Software 17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 18 19 */ 20 21 /* Additional, and optional expressions. */ 22 #ifdef WITH_ALTIVEC 23 #include "altivec_expression.h" 24 #endif 25 #ifdef WITH_E500 26 #include "e500_expression.h" 27 #endif 28 29 /* 32bit target expressions: 30 31 Each calculation is performed three times using each of the 32 signed64, unsigned64 and long integer types. The macro ALU_END 33 (in _ALU_RESULT_VAL) then selects which of the three alternative 34 results will be used in the final assignment of the target 35 register. As this selection is determined at compile time by 36 fields in the instruction (OE, EA, Rc) the compiler has sufficient 37 information to firstly simplify the selection code into a single 38 case and then back anotate the equations and hence eliminate any 39 resulting dead code. That dead code being the calculations that, 40 as it turned out were not in the end needed. 41 42 64bit arrithemetic is used firstly because it allows the use of 43 gcc's efficient long long operators (typically efficiently output 44 inline) and secondly because the resultant answer will contain in 45 the low 32bits the answer while in the high 32bits is either carry 46 or status information. */ 47 48 /* 64bit target expressions: 49 50 Unfortunatly 128bit arrithemetic isn't that common. Consequently 51 the 32/64 bit trick can not be used. Instead all calculations are 52 required to retain carry/overflow information in separate 53 variables. Even with this restriction it is still possible for the 54 trick of letting the compiler discard the calculation of unneeded 55 values */ 56 57 58 /* Macro's to type cast 32bit constants to 64bits */ 59 #define SIGNED64(val) ((signed64)(signed32)(val)) 60 #define UNSIGNED64(val) ((unsigned64)(unsigned32)(val)) 61 62 63 /* Start a section of ALU code */ 64 65 #define ALU_BEGIN(val) \ 66 { \ 67 natural_word alu_val; \ 68 unsigned64 alu_carry_val; \ 69 signed64 alu_overflow_val; \ 70 ALU_SET(val) 71 72 73 /* assign the result to the target register */ 74 75 #define ALU_END(TARG,CA,OE,Rc) \ 76 { /* select the result to use */ \ 77 signed_word const alu_result = _ALU_RESULT_VAL(CA,OE,Rc); \ 78 /* determine the overflow bit if needed */ \ 79 if (OE) { \ 80 if ((((unsigned64)(alu_overflow_val & BIT64(0))) \ 81 >> 32) \ 82 == (alu_overflow_val & BIT64(32))) \ 83 XER &= (~xer_overflow); \ 84 else \ 85 XER |= (xer_summary_overflow | xer_overflow); \ 86 } \ 87 /* Update the carry bit if needed */ \ 88 if (CA) { \ 89 XER = ((XER & ~xer_carry) \ 90 | SHUFFLED32((alu_carry_val >> 32), 31, xer_carry_bit)); \ 91 /* if (alu_carry_val & BIT64(31)) \ 92 XER |= (xer_carry); \ 93 else \ 94 XER &= (~xer_carry); */ \ 95 } \ 96 TRACE(trace_alu, (" Result = %ld (0x%lx), XER = %ld\n", \ 97 (long)alu_result, (long)alu_result, (long)XER)); \ 98 /* Update the Result Conditions if needed */ \ 99 CR0_COMPARE(alu_result, 0, Rc); \ 100 /* assign targ same */ \ 101 TARG = alu_result; \ 102 }} 103 104 /* select the result from the different options */ 105 106 #define _ALU_RESULT_VAL(CA,OE,Rc) (WITH_TARGET_WORD_BITSIZE == 64 \ 107 ? alu_val \ 108 : (OE \ 109 ? alu_overflow_val \ 110 : (CA \ 111 ? alu_carry_val \ 112 : alu_val))) 113 114 115 /* More basic alu operations */ 116 #if (WITH_TARGET_WORD_BITSIZE == 64) 117 #define ALU_SET(val) \ 118 do { \ 119 alu_val = val; \ 120 alu_carry_val = ((unsigned64)alu_val) >> 32; \ 121 alu_overflow_val = ((signed64)alu_val) >> 32; \ 122 } while (0) 123 #endif 124 #if (WITH_TARGET_WORD_BITSIZE == 32) 125 #define ALU_SET(val) \ 126 do { \ 127 alu_val = val; \ 128 alu_carry_val = (unsigned32)(alu_val); \ 129 alu_overflow_val = (signed32)(alu_val); \ 130 } while (0) 131 #endif 132 133 #if (WITH_TARGET_WORD_BITSIZE == 64) 134 #define ALU_ADD(val) \ 135 do { \ 136 unsigned64 alu_lo = (UNSIGNED64(alu_val) \ 137 + UNSIGNED64(val)); \ 138 signed alu_carry = ((alu_lo & BIT(31)) != 0); \ 139 alu_carry_val = (alu_carry_val \ 140 + UNSIGNED64(EXTRACTED(val, 0, 31)) \ 141 + alu_carry); \ 142 alu_overflow_val = (alu_overflow_val \ 143 + SIGNED64(EXTRACTED(val, 0, 31)) \ 144 + alu_carry); \ 145 alu_val = alu_val + val; \ 146 } while (0) 147 #endif 148 #if (WITH_TARGET_WORD_BITSIZE == 32) 149 #define ALU_ADD(val) \ 150 do { \ 151 alu_val += val; \ 152 alu_carry_val += (unsigned32)(val); \ 153 alu_overflow_val += (signed32)(val); \ 154 } while (0) 155 #endif 156 157 158 #if (WITH_TARGET_WORD_BITSIZE == 64) 159 #define ALU_ADD_CA \ 160 do { \ 161 signed carry = MASKED32(XER, xer_carry_bit, xer_carry_bit) != 0; \ 162 ALU_ADD(carry); \ 163 } while (0) 164 #endif 165 #if (WITH_TARGET_WORD_BITSIZE == 32) 166 #define ALU_ADD_CA \ 167 do { \ 168 signed carry = MASKED32(XER, xer_carry_bit, xer_carry_bit) != 0; \ 169 ALU_ADD(carry); \ 170 } while (0) 171 #endif 172 173 174 #if 0 175 #if (WITH_TARGET_WORD_BITSIZE == 64) 176 #endif 177 #if (WITH_TARGET_WORD_BITSIZE == 32) 178 #define ALU_SUB(val) \ 179 do { \ 180 alu_val -= val; \ 181 alu_carry_val -= (unsigned32)(val); \ 182 alu_overflow_val -= (signed32)(val); \ 183 } while (0) 184 #endif 185 #endif 186 187 #if (WITH_TARGET_WORD_BITSIZE == 64) 188 #endif 189 #if (WITH_TARGET_WORD_BITSIZE == 32) 190 #define ALU_OR(val) \ 191 do { \ 192 alu_val |= val; \ 193 alu_carry_val = (unsigned32)(alu_val); \ 194 alu_overflow_val = (signed32)(alu_val); \ 195 } while (0) 196 #endif 197 198 199 #if (WITH_TARGET_WORD_BITSIZE == 64) 200 #endif 201 #if (WITH_TARGET_WORD_BITSIZE == 32) 202 #define ALU_XOR(val) \ 203 do { \ 204 alu_val ^= val; \ 205 alu_carry_val = (unsigned32)(alu_val); \ 206 alu_overflow_val = (signed32)(alu_val); \ 207 } while (0) 208 #endif 209 210 211 #if 0 212 #if (WITH_TARGET_WORD_BITSIZE == 64) 213 #endif 214 #if (WITH_TARGET_WORD_BITSIZE == 32) 215 #define ALU_NEGATE \ 216 do { \ 217 alu_val = -alu_val; \ 218 alu_carry_val = -alu_carry_val; \ 219 alu_overflow_val = -alu_overflow_val; \ 220 } while(0) 221 #endif 222 #endif 223 224 225 #if (WITH_TARGET_WORD_BITSIZE == 64) 226 #endif 227 #if (WITH_TARGET_WORD_BITSIZE == 32) 228 #define ALU_AND(val) \ 229 do { \ 230 alu_val &= val; \ 231 alu_carry_val = (unsigned32)(alu_val); \ 232 alu_overflow_val = (signed32)(alu_val); \ 233 } while (0) 234 #endif 235 236 237 #if (WITH_TARGET_WORD_BITSIZE == 64) 238 #define ALU_NOT \ 239 do { \ 240 signed64 new_alu_val = ~alu_val; \ 241 ALU_SET(new_alu_val); \ 242 } while (0) 243 #endif 244 #if (WITH_TARGET_WORD_BITSIZE == 32) 245 #define ALU_NOT \ 246 do { \ 247 signed new_alu_val = ~alu_val; \ 248 ALU_SET(new_alu_val); \ 249 } while(0) 250 #endif 251 252 253 /* Macros for updating the condition register */ 254 255 #define CR1_UPDATE(Rc) \ 256 do { \ 257 if (Rc) { \ 258 CR_SET(1, EXTRACTED32(FPSCR, fpscr_fx_bit, fpscr_ox_bit)); \ 259 } \ 260 } while (0) 261 262 263 #define _DO_CR_COMPARE(LHS, RHS) \ 264 (((LHS) < (RHS)) \ 265 ? cr_i_negative \ 266 : (((LHS) > (RHS)) \ 267 ? cr_i_positive \ 268 : cr_i_zero)) 269 270 #define CR_SET(REG, VAL) MBLIT32(CR, REG*4, REG*4+3, VAL) 271 #define CR_FIELD(REG) EXTRACTED32(CR, REG*4, REG*4+3) 272 #define CR_SET_XER_SO(REG, VAL) \ 273 do { \ 274 creg new_bits = ((XER & xer_summary_overflow) \ 275 ? (cr_i_summary_overflow | VAL) \ 276 : VAL); \ 277 CR_SET(REG, new_bits); \ 278 } while(0) 279 280 #define CR_COMPARE(REG, LHS, RHS) \ 281 do { \ 282 creg new_bits = ((XER & xer_summary_overflow) \ 283 ? (cr_i_summary_overflow | _DO_CR_COMPARE(LHS,RHS)) \ 284 : _DO_CR_COMPARE(LHS,RHS)); \ 285 CR_SET(REG, new_bits); \ 286 } while (0) 287 288 #define CR0_COMPARE(LHS, RHS, Rc) \ 289 do { \ 290 if (Rc) { \ 291 CR_COMPARE(0, LHS, RHS); \ 292 TRACE(trace_alu, \ 293 ("CR=0x%08lx, LHS=%ld, RHS=%ld\n", \ 294 (unsigned long)CR, (long)LHS, (long)RHS)); \ 295 } \ 296 } while (0) 297 298 299 300 /* Bring data in from the cold */ 301 302 #define MEM(SIGN, EA, NR_BYTES) \ 303 ((SIGN##_##NR_BYTES) vm_data_map_read_##NR_BYTES(cpu_data_map(processor), EA, \ 304 processor, cia)) \ 305 306 #define STORE(EA, NR_BYTES, VAL) \ 307 do { \ 308 vm_data_map_write_##NR_BYTES(cpu_data_map(processor), EA, VAL, \ 309 processor, cia); \ 310 } while (0) 311 312 313 314 /* some FPSCR update macros. */ 315 316 #define FPSCR_BEGIN \ 317 { \ 318 fpscreg old_fpscr UNUSED = FPSCR 319 320 #define FPSCR_END(Rc) { \ 321 /* always update VX */ \ 322 if ((FPSCR & fpscr_vx_bits)) \ 323 FPSCR |= fpscr_vx; \ 324 else \ 325 FPSCR &= ~fpscr_vx; \ 326 /* always update FEX */ \ 327 if (((FPSCR & fpscr_vx) && (FPSCR & fpscr_ve)) \ 328 || ((FPSCR & fpscr_ox) && (FPSCR & fpscr_oe)) \ 329 || ((FPSCR & fpscr_ux) && (FPSCR & fpscr_ue)) \ 330 || ((FPSCR & fpscr_zx) && (FPSCR & fpscr_ze)) \ 331 || ((FPSCR & fpscr_xx) && (FPSCR & fpscr_xe))) \ 332 FPSCR |= fpscr_fex; \ 333 else \ 334 FPSCR &= ~fpscr_fex; \ 335 CR1_UPDATE(Rc); \ 336 /* interrupt enabled? */ \ 337 if ((MSR & (msr_floating_point_exception_mode_0 \ 338 | msr_floating_point_exception_mode_1)) \ 339 && (FPSCR & fpscr_fex)) \ 340 program_interrupt(processor, cia, \ 341 floating_point_enabled_program_interrupt); \ 342 }} 343 344 #define FPSCR_SET(REG, VAL) MBLIT32(FPSCR, REG*4, REG*4+3, VAL) 345 #define FPSCR_FIELD(REG) EXTRACTED32(FPSCR, REG*4, REG*4+3) 346 347 #define FPSCR_SET_FPCC(VAL) MBLIT32(FPSCR, fpscr_fpcc_bit, fpscr_fpcc_bit+3, VAL) 348 349 /* Handle various exceptions */ 350 351 #define FPSCR_OR_VX(VAL) \ 352 do { \ 353 /* NOTE: VAL != 0 */ \ 354 FPSCR |= (VAL); \ 355 FPSCR |= fpscr_fx; \ 356 } while (0) 357 358 #define FPSCR_SET_OX(COND) \ 359 do { \ 360 if (COND) { \ 361 FPSCR |= fpscr_ox; \ 362 FPSCR |= fpscr_fx; \ 363 } \ 364 else \ 365 FPSCR &= ~fpscr_ox; \ 366 } while (0) 367 368 #define FPSCR_SET_UX(COND) \ 369 do { \ 370 if (COND) { \ 371 FPSCR |= fpscr_ux; \ 372 FPSCR |= fpscr_fx; \ 373 } \ 374 else \ 375 FPSCR &= ~fpscr_ux; \ 376 } while (0) 377 378 #define FPSCR_SET_ZX(COND) \ 379 do { \ 380 if (COND) { \ 381 FPSCR |= fpscr_zx; \ 382 FPSCR |= fpscr_fx; \ 383 } \ 384 else \ 385 FPSCR &= ~fpscr_zx; \ 386 } while (0) 387 388 #define FPSCR_SET_XX(COND) \ 389 do { \ 390 if (COND) { \ 391 FPSCR |= fpscr_xx; \ 392 FPSCR |= fpscr_fx; \ 393 } \ 394 } while (0) 395 396 /* Note: code using SET_FI must also explicitly call SET_XX */ 397 398 #define FPSCR_SET_FR(COND) do { \ 399 if (COND) \ 400 FPSCR |= fpscr_fr; \ 401 else \ 402 FPSCR &= ~fpscr_fr; \ 403 } while (0) 404 405 #define FPSCR_SET_FI(COND) \ 406 do { \ 407 if (COND) { \ 408 FPSCR |= fpscr_fi; \ 409 } \ 410 else \ 411 FPSCR &= ~fpscr_fi; \ 412 } while (0) 413 414 #define FPSCR_SET_FPRF(VAL) \ 415 do { \ 416 FPSCR = (FPSCR & ~fpscr_fprf) | (VAL); \ 417 } while (0) 418