1 /* Copyright (c) 2011 Atmel Corporation 2 All rights reserved. 3 4 Redistribution and use in source and binary forms, with or without 5 modification, are permitted provided that the following conditions are met: 6 7 * Redistributions of source code must retain the above copyright 8 notice, this list of conditions and the following disclaimer. 9 10 * Redistributions in binary form must reproduce the above copyright 11 notice, this list of conditions and the following disclaimer in 12 the documentation and/or other materials provided with the 13 distribution. 14 15 * Neither the name of the copyright holders nor the names of 16 contributors may be used to endorse or promote products derived 17 from this software without specific prior written permission. 18 19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 POSSIBILITY OF SUCH DAMAGE. */ 30 31 /* $Id: iom16hvb.h 2460 2014-12-03 05:39:25Z pitchumani $ */ 32 33 /* avr/iom16hvb.h - definitions for ATmega16HVB */ 34 35 /* This file should only be included from <avr/io.h>, never directly. */ 36 37 #ifndef _AVR_IO_H_ 38 # error "Include <avr/io.h> instead of this file." 39 #endif 40 41 #ifndef _AVR_IOXXX_H_ 42 # define _AVR_IOXXX_H_ "iom16hvb.h" 43 #else 44 # error "Attempt to include more than one <avr/ioXXX.h> file." 45 #endif 46 47 48 #ifndef _AVR_ATmega16HVB_H_ 49 #define _AVR_ATmega16HVB_H_ 1 50 51 52 /* Registers and associated bit numbers. */ 53 54 #define PINA _SFR_IO8(0x00) 55 #define PINA0 0 56 #define PINA1 1 57 #define PINA2 2 58 #define PINA3 3 59 60 #define DDRA _SFR_IO8(0x01) 61 #define DDA0 0 62 #define DDA1 1 63 #define DDA2 2 64 #define DDA3 3 65 66 #define PORTA _SFR_IO8(0x02) 67 #define PORTA0 0 68 #define PORTA1 1 69 #define PORTA2 2 70 #define PORTA3 3 71 72 #define PINB _SFR_IO8(0x03) 73 #define PINB0 0 74 #define PINB1 1 75 #define PINB2 2 76 #define PINB3 3 77 #define PINB4 4 78 #define PINB5 5 79 #define PINB6 6 80 #define PINB7 7 81 82 #define DDRB _SFR_IO8(0x04) 83 #define DDB0 0 84 #define DDB1 1 85 #define DDB2 2 86 #define DDB3 3 87 #define DDB4 4 88 #define DDB5 5 89 #define DDB6 6 90 #define DDB7 7 91 92 #define PORTB _SFR_IO8(0x05) 93 #define PORTB0 0 94 #define PORTB1 1 95 #define PORTB2 2 96 #define PORTB3 3 97 #define PORTB4 4 98 #define PORTB5 5 99 #define PORTB6 6 100 #define PORTB7 7 101 102 #define PINC _SFR_IO8(0x06) 103 #define PINC0 0 104 #define PINC1 1 105 #define PINC2 2 106 #define PINC3 3 107 #define PINC4 4 108 109 #define PORTC _SFR_IO8(0x08) 110 #define PORTC0 0 111 #define PORTC1 1 112 #define PORTC2 2 113 #define PORTC3 3 114 #define PORTC4 4 115 #define PORTC5 5 116 117 #define TIFR0 _SFR_IO8(0x15) 118 #define TOV0 0 119 #define OCF0A 1 120 #define OCF0B 2 121 #define ICF0 3 122 123 #define TIFR1 _SFR_IO8(0x16) 124 #define TOV1 0 125 #define OCF1A 1 126 #define OCF1B 2 127 #define ICF1 3 128 129 #define OSICSR _SFR_IO8(0x17) 130 #define OSIEN 0 131 #define OSIST 1 132 #define OSISEL0 4 133 134 #define PCIFR _SFR_IO8(0x1B) 135 #define PCIF0 0 136 #define PCIF1 1 137 138 #define EIFR _SFR_IO8(0x1C) 139 #define INTF0 0 140 #define INTF1 1 141 #define INTF2 2 142 #define INTF3 3 143 144 #define EIMSK _SFR_IO8(0x1D) 145 #define INT0 0 146 #define INT1 1 147 #define INT2 2 148 #define INT3 3 149 150 #define GPIOR0 _SFR_IO8(0x1E) 151 #define GPIOR00 0 152 #define GPIOR01 1 153 #define GPIOR02 2 154 #define GPIOR03 3 155 #define GPIOR04 4 156 #define GPIOR05 5 157 #define GPIOR06 6 158 #define GPIOR07 7 159 160 #define EECR _SFR_IO8(0x1F) 161 #define EERE 0 162 #define EEPE 1 163 #define EEMPE 2 164 #define EERIE 3 165 #define EEPM0 4 166 #define EEPM1 5 167 168 #define EEDR _SFR_IO8(0x20) 169 #define EEDR0 0 170 #define EEDR1 1 171 #define EEDR2 2 172 #define EEDR3 3 173 #define EEDR4 4 174 #define EEDR5 5 175 #define EEDR6 6 176 #define EEDR7 7 177 178 #define EEAR _SFR_IO16(0x21) 179 180 #define EEARL _SFR_IO8(0x21) 181 #define EEAR0 0 182 #define EEAR1 1 183 #define EEAR2 2 184 #define EEAR3 3 185 #define EEAR4 4 186 #define EEAR5 5 187 #define EEAR6 6 188 #define EEAR7 7 189 190 #define EEARH _SFR_IO8(0x22) 191 #define EEAR8 0 192 #define EEAR9 1 193 194 #define GTCCR _SFR_IO8(0x23) 195 #define PSRSYNC 0 196 #define TSM 7 197 198 #define TCCR0A _SFR_IO8(0x24) 199 #define WGM00 0 200 #define ICS0 3 201 #define ICES0 4 202 #define ICNC0 5 203 #define ICEN0 6 204 #define TCW0 7 205 206 #define TCCR0B _SFR_IO8(0x25) 207 #define CS00 0 208 #define CS01 1 209 #define CS02 2 210 211 #define TCNT0 _SFR_IO16(0x26) 212 213 #define TCNT0L _SFR_IO8(0x26) 214 #define TCNT0L0 0 215 #define TCNT0L1 1 216 #define TCNT0L2 2 217 #define TCNT0L3 3 218 #define TCNT0L4 4 219 #define TCNT0L5 5 220 #define TCNT0L6 6 221 #define TCNT0L7 7 222 223 #define TCNT0H _SFR_IO8(0x27) 224 #define TCNT0H0 0 225 #define TCNT0H1 1 226 #define TCNT0H2 2 227 #define TCNT0H3 3 228 #define TCNT0H4 4 229 #define TCNT0H5 5 230 #define TCNT0H6 6 231 #define TCNT0H7 7 232 233 #define OCR0A _SFR_IO8(0x28) 234 #define OCR0A0 0 235 #define OCR0A1 1 236 #define OCR0A2 2 237 #define OCR0A3 3 238 #define OCR0A4 4 239 #define OCR0A5 5 240 #define OCR0A6 6 241 #define OCR0A7 7 242 243 #define OCR0B _SFR_IO8(0x29) 244 #define OCR0B0 0 245 #define OCR0B1 1 246 #define OCR0B2 2 247 #define OCR0B3 3 248 #define OCR0B4 4 249 #define OCR0B5 5 250 #define OCR0B6 6 251 #define OCR0B7 7 252 253 #define GPIOR1 _SFR_IO8(0x2A) 254 #define GPIOR10 0 255 #define GPIOR11 1 256 #define GPIOR12 2 257 #define GPIOR13 3 258 #define GPIOR14 4 259 #define GPIOR15 5 260 #define GPIOR16 6 261 #define GPIOR17 7 262 263 #define GPIOR2 _SFR_IO8(0x2B) 264 #define GPIOR20 0 265 #define GPIOR21 1 266 #define GPIOR22 2 267 #define GPIOR23 3 268 #define GPIOR24 4 269 #define GPIOR25 5 270 #define GPIOR26 6 271 #define GPIOR27 7 272 273 #define SPCR _SFR_IO8(0x2C) 274 #define SPR0 0 275 #define SPR1 1 276 #define CPHA 2 277 #define CPOL 3 278 #define MSTR 4 279 #define DORD 5 280 #define SPE 6 281 #define SPIE 7 282 283 #define SPSR _SFR_IO8(0x2D) 284 #define SPI2X 0 285 #define WCOL 6 286 #define SPIF 7 287 288 #define SPDR _SFR_IO8(0x2E) 289 #define SPDR0 0 290 #define SPDR1 1 291 #define SPDR2 2 292 #define SPDR3 3 293 #define SPDR4 4 294 #define SPDR5 5 295 #define SPDR6 6 296 #define SPDR7 7 297 298 #define DWDR _SFR_IO8(0x31) 299 300 #define SMCR _SFR_IO8(0x33) 301 #define SE 0 302 #define SM0 1 303 #define SM1 2 304 #define SM2 3 305 306 #define MCUSR _SFR_IO8(0x34) 307 #define PORF 0 308 #define EXTRF 1 309 #define BODRF 2 310 #define WDRF 3 311 #define OCDRF 4 312 313 #define MCUCR _SFR_IO8(0x35) 314 #define IVCE 0 315 #define IVSEL 1 316 #define PUD 4 317 #define CKOE 5 318 319 #define SPMCSR _SFR_IO8(0x37) 320 #define SPMEN 0 321 #define PGERS 1 322 #define PGWRT 2 323 #define LBSET 3 324 #define RWWSRE 4 325 #define SIGRD 5 326 #define RWWSB 6 327 #define SPMIE 7 328 329 #define WDTCSR _SFR_MEM8(0x60) 330 #define WDP0 0 331 #define WDP1 1 332 #define WDP2 2 333 #define WDE 3 334 #define WDCE 4 335 #define WDP3 5 336 #define WDIE 6 337 #define WDIF 7 338 339 #define CLKPR _SFR_MEM8(0x61) 340 #define CLKPS0 0 341 #define CLKPS1 1 342 #define CLKPCE 7 343 344 #define PRR0 _SFR_MEM8(0x64) 345 #define PRVADC 0 346 #define PRTIM0 1 347 #define PRTIM1 2 348 #define PRSPI 3 349 #define PRVRM 5 350 #define PRTWI 6 351 352 #define __AVR_HAVE_PRR0 ((1<<PRVADC)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRSPI)|(1<<PRVRM)|(1<<PRTWI)) 353 #define __AVR_HAVE_PRR0_PRVADC 354 #define __AVR_HAVE_PRR0_PRTIM0 355 #define __AVR_HAVE_PRR0_PRTIM1 356 #define __AVR_HAVE_PRR0_PRSPI 357 #define __AVR_HAVE_PRR0_PRVRM 358 #define __AVR_HAVE_PRR0_PRTWI 359 360 #define FOSCCAL _SFR_MEM8(0x66) 361 #define FCAL0 0 362 #define FCAL1 1 363 #define FCAL2 2 364 #define FCAL3 3 365 #define FCAL4 4 366 #define FCAL5 5 367 #define FCAL6 6 368 #define FCAL7 7 369 370 #define PCICR _SFR_MEM8(0x68) 371 #define PCIE0 0 372 #define PCIE1 1 373 374 #define EICRA _SFR_MEM8(0x69) 375 #define ISC00 0 376 #define ISC01 1 377 #define ISC10 2 378 #define ISC11 3 379 #define ISC20 4 380 #define ISC21 5 381 #define ISC30 6 382 #define ISC31 7 383 384 #define PCMSK0 _SFR_MEM8(0x6B) 385 #define PCINT0 0 386 #define PCINT1 1 387 #define PCINT2 2 388 #define PCINT3 3 389 390 #define PCMSK1 _SFR_MEM8(0x6C) 391 #define PCINT4 0 392 #define PCINT5 1 393 #define PCINT6 2 394 #define PCINT7 3 395 #define PCINT8 4 396 #define PCINT9 5 397 #define PCINT10 6 398 #define PCINT11 7 399 400 #define TIMSK0 _SFR_MEM8(0x6E) 401 #define TOIE0 0 402 #define OCIE0A 1 403 #define OCIE0B 2 404 #define ICIE0 3 405 406 #define TIMSK1 _SFR_MEM8(0x6F) 407 #define TOIE1 0 408 #define OCIE1A 1 409 #define OCIE1B 2 410 #define ICIE1 3 411 412 #define VADC _SFR_MEM16(0x78) 413 414 #define VADCL _SFR_MEM8(0x78) 415 #define VADC0 0 416 #define VADC1 1 417 #define VADC2 2 418 #define VADC3 3 419 #define VADC4 4 420 #define VADC5 5 421 #define VADC6 6 422 #define VADC7 7 423 424 #define VADCH _SFR_MEM8(0x79) 425 #define VADC8 0 426 #define VADC9 1 427 #define VADC10 2 428 #define VADC11 3 429 430 #define VADCSR _SFR_MEM8(0x7A) 431 #define VADCCIE 0 432 #define VADCCIF 1 433 #define VADSC 2 434 #define VADEN 3 435 436 #define VADMUX _SFR_MEM8(0x7C) 437 #define VADMUX0 0 438 #define VADMUX1 1 439 #define VADMUX2 2 440 #define VADMUX3 3 441 442 #define DIDR0 _SFR_MEM8(0x7E) 443 #define PA0DID 0 444 #define PA1DID 1 445 446 #define TCCR1A _SFR_MEM8(0x80) 447 #define WGM10 0 448 #define ICS1 3 449 #define ICES1 4 450 #define ICNC1 5 451 #define ICEN1 6 452 #define TCW1 7 453 454 #define TCCR1B _SFR_MEM8(0x81) 455 #define CS10 0 456 #define CS11 1 457 #define CS12 2 458 459 #define TCNT1 _SFR_MEM16(0x84) 460 461 #define TCNT1L _SFR_MEM8(0x84) 462 #define TCNT1L0 0 463 #define TCNT1L1 1 464 #define TCNT1L2 2 465 #define TCNT1L3 3 466 #define TCNT1L4 4 467 #define TCNT1L5 5 468 #define TCNT1L6 6 469 #define TCNT1L7 7 470 471 #define TCNT1H _SFR_MEM8(0x85) 472 #define TCNT1H0 0 473 #define TCNT1H1 1 474 #define TCNT1H2 2 475 #define TCNT1H3 3 476 #define TCNT1H4 4 477 #define TCNT1H5 5 478 #define TCNT1H6 6 479 #define TCNT1H7 7 480 481 #define OCR1A _SFR_MEM8(0x88) 482 #define OCR1A0 0 483 #define OCR1A1 1 484 #define OCR1A2 2 485 #define OCR1A3 3 486 #define OCR1A4 4 487 #define OCR1A5 5 488 #define OCR1A6 6 489 #define OCR1A7 7 490 491 #define OCR1B _SFR_MEM8(0x89) 492 #define OCR1B0 0 493 #define OCR1B1 1 494 #define OCR1B2 2 495 #define OCR1B3 3 496 #define OCR1B4 4 497 #define OCR1B5 5 498 #define OCR1B6 6 499 #define OCR1B7 7 500 501 #define TWBR _SFR_MEM8(0xB8) 502 #define TWBR0 0 503 #define TWBR1 1 504 #define TWBR2 2 505 #define TWBR3 3 506 #define TWBR4 4 507 #define TWBR5 5 508 #define TWBR6 6 509 #define TWBR7 7 510 511 #define TWSR _SFR_MEM8(0xB9) 512 #define TWPS0 0 513 #define TWPS1 1 514 #define TWS3 3 515 #define TWS4 4 516 #define TWS5 5 517 #define TWS6 6 518 #define TWS7 7 519 520 #define TWAR _SFR_MEM8(0xBA) 521 #define TWGCE 0 522 #define TWA0 1 523 #define TWA1 2 524 #define TWA2 3 525 #define TWA3 4 526 #define TWA4 5 527 #define TWA5 6 528 #define TWA6 7 529 530 #define TWDR _SFR_MEM8(0xBB) 531 #define TWD0 0 532 #define TWD1 1 533 #define TWD2 2 534 #define TWD3 3 535 #define TWD4 4 536 #define TWD5 5 537 #define TWD6 6 538 #define TWD7 7 539 540 #define TWCR _SFR_MEM8(0xBC) 541 #define TWIE 0 542 #define TWEN 2 543 #define TWWC 3 544 #define TWSTO 4 545 #define TWSTA 5 546 #define TWEA 6 547 #define TWINT 7 548 549 #define TWAMR _SFR_MEM8(0xBD) 550 #define TWAM0 1 551 #define TWAM1 2 552 #define TWAM2 3 553 #define TWAM3 4 554 #define TWAM4 5 555 #define TWAM5 6 556 #define TWAM6 7 557 558 #define TWBCSR _SFR_MEM8(0xBE) 559 #define TWBCIP 0 560 #define TWBDT0 1 561 #define TWBDT1 2 562 #define TWBCIE 6 563 #define TWBCIF 7 564 565 #define ROCR _SFR_MEM8(0xC8) 566 #define ROCWIE 0 567 #define ROCWIF 1 568 #define ROCD 4 569 #define ROCS 7 570 571 #define BGCCR _SFR_MEM8(0xD0) 572 #define BGCC0 0 573 #define BGCC1 1 574 #define BGCC2 2 575 #define BGCC3 3 576 #define BGCC4 4 577 #define BGCC5 5 578 579 #define BGCRR _SFR_MEM8(0xD1) 580 #define BGCR0 0 581 #define BGCR1 1 582 #define BGCR2 2 583 #define BGCR3 3 584 #define BGCR4 4 585 #define BGCR5 5 586 #define BGCR6 6 587 #define BGCR7 7 588 589 #define BGCSR _SFR_MEM8(0xD2) 590 #define BGSCDIE 0 591 #define BGSCDIF 1 592 #define BGSCDE 4 593 #define BGD 5 594 595 #define CHGDCSR _SFR_MEM8(0xD4) 596 #define CHGDIE 0 597 #define CHGDIF 1 598 #define CHGDISC0 2 599 #define CHGDISC1 3 600 #define BATTPVL 4 601 602 #define CADAC0 _SFR_MEM8(0xE0) 603 #define CADAC00 0 604 #define CADAC01 1 605 #define CADAC02 2 606 #define CADAC03 3 607 #define CADAC04 4 608 #define CADAC05 5 609 #define CADAC06 6 610 #define CADAC07 7 611 612 #define CADAC1 _SFR_MEM8(0xE1) 613 #define CADAC08 0 614 #define CADAC09 1 615 #define CADAC10 2 616 #define CADAC11 3 617 #define CADAC12 4 618 #define CADAC13 5 619 #define CADAC14 6 620 #define CADAC15 7 621 622 #define CADAC2 _SFR_MEM8(0xE2) 623 #define CADAC16 0 624 #define CADAC17 1 625 #define CADAC18 2 626 #define CADAC19 3 627 #define CADAC20 4 628 #define CADAC21 5 629 #define CADAC22 6 630 #define CADAC23 7 631 632 #define CADAC3 _SFR_MEM8(0xE3) 633 #define CADAC24 0 634 #define CADAC25 1 635 #define CADAC26 2 636 #define CADAC27 3 637 #define CADAC28 4 638 #define CADAC29 5 639 #define CADAC30 6 640 #define CADAC31 7 641 642 #define CADIC _SFR_MEM16(0xE4) 643 644 #define CADICL _SFR_MEM8(0xE4) 645 #define CADICL0 0 646 #define CADICL1 1 647 #define CADICL2 2 648 #define CADICL3 3 649 #define CADICL4 4 650 #define CADICL5 5 651 #define CADICL6 6 652 #define CADICL7 7 653 654 #define CADICH _SFR_MEM8(0xE5) 655 #define CADICH0 0 656 #define CADICH1 1 657 #define CADICH2 2 658 #define CADICH3 3 659 #define CADICH4 4 660 #define CADICH5 5 661 #define CADICH6 6 662 #define CADICH7 7 663 664 #define CADCSRA _SFR_MEM8(0xE6) 665 #define CADSE 0 666 #define CADSI0 1 667 #define CADSI1 2 668 #define CADAS0 3 669 #define CADAS1 4 670 #define CADUB 5 671 #define CADPOL 6 672 #define CADEN 7 673 674 #define CADCSRB _SFR_MEM8(0xE7) 675 #define CADICIF 0 676 #define CADRCIF 1 677 #define CADACIF 2 678 #define CADICIE 4 679 #define CADRCIE 5 680 #define CADACIE 6 681 682 #define CADCSRC _SFR_MEM8(0xE8) 683 #define CADVSE 0 684 685 #define CADRCC _SFR_MEM8(0xE9) 686 #define CADRCC0 0 687 #define CADRCC1 1 688 #define CADRCC2 2 689 #define CADRCC3 3 690 #define CADRCC4 4 691 #define CADRCC5 5 692 #define CADRCC6 6 693 #define CADRCC7 7 694 695 #define CADRDC _SFR_MEM8(0xEA) 696 #define CADRDC0 0 697 #define CADRDC1 1 698 #define CADRDC2 2 699 #define CADRDC3 3 700 #define CADRDC4 4 701 #define CADRDC5 5 702 #define CADRDC6 6 703 #define CADRDC7 7 704 705 #define FCSR _SFR_MEM8(0xF0) 706 #define CFE 0 707 #define DFE 1 708 #define CPS 2 709 #define DUVRD 3 710 711 #define CBCR _SFR_MEM8(0xF1) 712 #define CBE1 0 713 #define CBE2 1 714 #define CBE3 2 715 #define CBE4 3 716 717 #define BPIMSK _SFR_MEM8(0xF2) 718 #define CHCIE 0 719 #define DHCIE 1 720 #define COCIE 2 721 #define DOCIE 3 722 #define SCIE 4 723 724 #define BPIFR _SFR_MEM8(0xF3) 725 #define CHCIF 0 726 #define DHCIF 1 727 #define COCIF 2 728 #define DOCIF 3 729 #define SCIF 4 730 731 #define BPSCD _SFR_MEM8(0xF5) 732 #define SCDL0 0 733 #define SCDL1 1 734 #define SCDL2 2 735 #define SCDL3 3 736 #define SCDL4 4 737 #define SCDL5 5 738 #define SCDL6 6 739 #define SCDL7 7 740 741 #define BPDOCD _SFR_MEM8(0xF6) 742 #define DOCDL0 0 743 #define DOCDL1 1 744 #define DOCDL2 2 745 #define DOCDL3 3 746 #define DOCDL4 4 747 #define DOCDL5 5 748 #define DOCDL6 6 749 #define DOCDL7 7 750 751 #define BPCOCD _SFR_MEM8(0xF7) 752 #define COCDL0 0 753 #define COCDL1 1 754 #define COCDL2 2 755 #define COCDL3 3 756 #define COCDL4 4 757 #define COCDL5 5 758 #define COCDL6 6 759 #define COCDL7 7 760 761 #define BPDHCD _SFR_MEM8(0xF8) 762 #define DHCDL0 0 763 #define DHCDL1 1 764 #define DHCDL2 2 765 #define DHCDL3 3 766 #define DHCDL4 4 767 #define DHCDL5 5 768 #define DHCDL6 6 769 #define DHCDL7 7 770 771 #define BPCHCD _SFR_MEM8(0xF9) 772 #define CHCDL0 0 773 #define CHCDL1 1 774 #define CHCDL2 2 775 #define CHCDL3 3 776 #define CHCDL4 4 777 #define CHCDL5 5 778 #define CHCDL6 6 779 #define CHCDL7 7 780 781 #define BPSCTR _SFR_MEM8(0xFA) 782 #define SCPT0 0 783 #define SCPT1 1 784 #define SCPT2 2 785 #define SCPT3 3 786 #define SCPT4 4 787 #define SCPT5 5 788 #define SCPT6 6 789 790 #define BPOCTR _SFR_MEM8(0xFB) 791 #define OCPT0 0 792 #define OCPT1 1 793 #define OCPT2 2 794 #define OCPT3 3 795 #define OCPT4 4 796 #define OCPT5 5 797 798 #define BPHCTR _SFR_MEM8(0xFC) 799 #define HCPT0 0 800 #define HCPT1 1 801 #define HCPT2 2 802 #define HCPT3 3 803 #define HCPT4 4 804 #define HCPT5 5 805 806 #define BPCR _SFR_MEM8(0xFD) 807 #define CHCD 0 808 #define DHCD 1 809 #define COCD 2 810 #define DOCD 3 811 #define SCD 4 812 #define EPID 5 813 814 #define BPPLR _SFR_MEM8(0xFE) 815 #define BPPL 0 816 #define BPPLE 1 817 818 819 /* Interrupt vectors */ 820 /* Vector 0 is the reset vector */ 821 #define BPINT_vect_num 1 822 #define BPINT_vect _VECTOR(1) /* Battery Protection Interrupt */ 823 #define VREGMON_vect_num 2 824 #define VREGMON_vect _VECTOR(2) /* Voltage regulator monitor interrupt */ 825 #define INT0_vect_num 3 826 #define INT0_vect _VECTOR(3) /* External Interrupt Request 0 */ 827 #define INT1_vect_num 4 828 #define INT1_vect _VECTOR(4) /* External Interrupt Request 1 */ 829 #define INT2_vect_num 5 830 #define INT2_vect _VECTOR(5) /* External Interrupt Request 2 */ 831 #define INT3_vect_num 6 832 #define INT3_vect _VECTOR(6) /* External Interrupt Request 3 */ 833 #define PCINT0_vect_num 7 834 #define PCINT0_vect _VECTOR(7) /* Pin Change Interrupt 0 */ 835 #define PCINT1_vect_num 8 836 #define PCINT1_vect _VECTOR(8) /* Pin Change Interrupt 1 */ 837 #define WDT_vect_num 9 838 #define WDT_vect _VECTOR(9) /* Watchdog Timeout Interrupt */ 839 #define BGSCD_vect_num 10 840 #define BGSCD_vect _VECTOR(10) /* Bandgap Buffer Short Circuit Detected */ 841 #define CHDET_vect_num 11 842 #define CHDET_vect _VECTOR(11) /* Charger Detect */ 843 #define TIMER1_IC_vect_num 12 844 #define TIMER1_IC_vect _VECTOR(12) /* Timer 1 Input capture */ 845 #define TIMER1_COMPA_vect_num 13 846 #define TIMER1_COMPA_vect _VECTOR(13) /* Timer 1 Compare Match A */ 847 #define TIMER1_COMPB_vect_num 14 848 #define TIMER1_COMPB_vect _VECTOR(14) /* Timer 1 Compare Match B */ 849 #define TIMER1_OVF_vect_num 15 850 #define TIMER1_OVF_vect _VECTOR(15) /* Timer 1 overflow */ 851 #define TIMER0_IC_vect_num 16 852 #define TIMER0_IC_vect _VECTOR(16) /* Timer 0 Input Capture */ 853 #define TIMER0_COMPA_vect_num 17 854 #define TIMER0_COMPA_vect _VECTOR(17) /* Timer 0 Comapre Match A */ 855 #define TIMER0_COMPB_vect_num 18 856 #define TIMER0_COMPB_vect _VECTOR(18) /* Timer 0 Compare Match B */ 857 #define TIMER0_OVF_vect_num 19 858 #define TIMER0_OVF_vect _VECTOR(19) /* Timer 0 Overflow */ 859 #define TWIBUSCD_vect_num 20 860 #define TWIBUSCD_vect _VECTOR(20) /* Two-Wire Bus Connect/Disconnect */ 861 #define TWI_vect_num 21 862 #define TWI_vect _VECTOR(21) /* Two-Wire Serial Interface */ 863 #define SPI_STC_vect_num 22 864 #define SPI_STC_vect _VECTOR(22) /* SPI Serial transfer complete */ 865 #define VADC_vect_num 23 866 #define VADC_vect _VECTOR(23) /* Voltage ADC Conversion Complete */ 867 #define CCADC_CONV_vect_num 24 868 #define CCADC_CONV_vect _VECTOR(24) /* Coulomb Counter ADC Conversion Complete */ 869 #define CCADC_REG_CUR_vect_num 25 870 #define CCADC_REG_CUR_vect _VECTOR(25) /* Coloumb Counter ADC Regular Current */ 871 #define CCADC_ACC_vect_num 26 872 #define CCADC_ACC_vect _VECTOR(26) /* Coloumb Counter ADC Accumulator */ 873 #define EE_READY_vect_num 27 874 #define EE_READY_vect _VECTOR(27) /* EEPROM Ready */ 875 #define SPM_vect_num 28 876 #define SPM_vect _VECTOR(28) /* SPM Ready */ 877 878 #define _VECTOR_SIZE 4 /* Size of individual vector. */ 879 #define _VECTORS_SIZE (29 * _VECTOR_SIZE) 880 881 882 /* Constants */ 883 #define SPM_PAGESIZE (128) 884 #define RAMSTART (0x100) 885 #define RAMSIZE (1024) 886 #define RAMEND (RAMSTART + RAMSIZE - 1) 887 #define XRAMSTART (NA) 888 #define XRAMSIZE (NA) 889 #define XRAMEND (RAMEND) 890 #define E2END (0x1FF) 891 #define E2PAGESIZE (4) 892 #define FLASHEND (0x3FFF) 893 894 895 /* Fuses */ 896 #define FUSE_MEMORY_SIZE 2 897 898 /* Low Fuse Byte */ 899 #define FUSE_OSCSEL0 (unsigned char)~_BV(0) /* Oscillator Select */ 900 #define FUSE_OSCSEL1 (unsigned char)~_BV(1) /* Oscillator Select */ 901 #define FUSE_SUT0 (unsigned char)~_BV(2) /* Select start-up time */ 902 #define FUSE_SUT1 (unsigned char)~_BV(3) /* Select start-up time */ 903 #define FUSE_SUT2 (unsigned char)~_BV(4) /* Select start-up time */ 904 #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ 905 #define FUSE_EESAVE (unsigned char)~_BV(6) /* EEPROM memory is preserved through chip erase */ 906 #define FUSE_WDTON (unsigned char)~_BV(7) /* Watchdog Timer Always On */ 907 #define LFUSE_DEFAULT (FUSE_SPIEN & FUSE_OSCSEL0) 908 909 /* High Fuse Byte */ 910 #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ 911 #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ 912 #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ 913 #define FUSE_DWEN (unsigned char)~_BV(3) /* Enable debugWire */ 914 #define FUSE_CKDIV (unsigned char)~_BV(4) /* Clock Divide Register */ 915 #define HFUSE_DEFAULT (FUSE_CKDIV & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) 916 917 918 /* Lock Bits */ 919 #define __LOCK_BITS_EXIST 920 #define __BOOT_LOCK_BITS_0_EXIST 921 #define __BOOT_LOCK_BITS_1_EXIST 922 923 924 /* Signature */ 925 #define SIGNATURE_0 0x1E 926 #define SIGNATURE_1 0x94 927 #define SIGNATURE_2 0x0D 928 929 930 /* Device Pin Definitions */ 931 #define PV2_DDR DDRV 932 #define PV2_PORT PORTV 933 #define PV2_PIN PINV 934 #define PV2_BIT 2 935 936 #define PV1_DDR DDRV 937 #define PV1_PORT PORTV 938 #define PV1_PIN PINV 939 #define PV1_BIT 1 940 941 #define NV_DDR DDRNV 942 #define NV_PORT PORTNV 943 #define NV_PIN PINNV 944 #define NV_BIT NV 945 946 #define VFET_DDR DDRVFET 947 #define VFET_PORT PORTVFET 948 #define VFET_PIN PINVFET 949 #define VFET_BIT VFET 950 951 #define CF1P_DDR DDRCF1P 952 #define CF1P_PORT PORTCF1P 953 #define CF1P_PIN PINCF1P 954 #define CF1P_BIT CF1P 955 956 #define CF1N_DDR DDRCF1N 957 #define CF1N_PORT PORTCF1N 958 #define CF1N_PIN PINCF1N 959 #define CF1N_BIT CF1N 960 961 #define CF2P_DDR DDRCF2P 962 #define CF2P_PORT PORTCF2P 963 #define CF2P_PIN PINCF2P 964 #define CF2P_BIT CF2P 965 966 #define CF2N_DDR DDRCF2N 967 #define CF2N_PORT PORTCF2N 968 #define CF2N_PIN PINCF2N 969 #define CF2N_BIT CF2N 970 971 #define VREG_DDR DDRVREG 972 #define VREG_PORT PORTVREG 973 #define VREG_PIN PINVREG 974 #define VREG_BIT VREG 975 976 #define VREF_DDR DDRVREF 977 #define VREF_PORT PORTVREF 978 #define VREF_PIN PINVREF 979 #define VREF_BIT VREF 980 981 #define VREFGND_DDR DDRVREFGND 982 #define VREFGND_PORT PORTVREFGND 983 #define VREFGND_PIN PINVREFGND 984 #define VREFGND_BIT VREFGND 985 986 #define PI_DDR DDRI 987 #define PI_PORT PORTI 988 #define PI_PIN PINI 989 #define PI_BIT 990 991 #define NI_DDR DDRNI 992 #define NI_PORT PORTNI 993 #define NI_PIN PINNI 994 #define NI_BIT NI 995 996 #define PA0_DDR DDRA 997 #define PA0_PORT PORTA 998 #define PA0_PIN PINA 999 #define PA0_BIT 0 1000 1001 #define PA1_DDR DDRA 1002 #define PA1_PORT PORTA 1003 #define PA1_PIN PINA 1004 #define PA1_BIT 1 1005 1006 #define PA2_DDR DDRA 1007 #define PA2_PORT PORTA 1008 #define PA2_PIN PINA 1009 #define PA2_BIT 2 1010 1011 #define PB0_DDR DDRB 1012 #define PB0_PORT PORTB 1013 #define PB0_PIN PINB 1014 #define PB0_BIT 0 1015 1016 #define PB1_DDR DDRB 1017 #define PB1_PORT PORTB 1018 #define PB1_PIN PINB 1019 #define PB1_BIT 1 1020 1021 #define PB2_DDR DDRB 1022 #define PB2_PORT PORTB 1023 #define PB2_PIN PINB 1024 #define PB2_BIT 2 1025 1026 #define PB3_DDR DDRB 1027 #define PB3_PORT PORTB 1028 #define PB3_PIN PINB 1029 #define PB3_BIT 3 1030 1031 #define PC0_DDR DDRC 1032 #define PC0_PORT PORTC 1033 #define PC0_PIN PINC 1034 #define PC0_BIT 0 1035 1036 #define BATT_DDR DDRBATT 1037 #define BATT_PORT PORTBATT 1038 #define BATT_PIN PINBATT 1039 #define BATT_BIT BATT 1040 1041 #define OC_DDR DDROC 1042 #define OC_PORT PORTOC 1043 #define OC_PIN PINOC 1044 #define OC_BIT OC 1045 1046 1047 #define SLEEP_MODE_IDLE (0x00<<1) 1048 #define SLEEP_MODE_ADC (0x01<<1) 1049 #define SLEEP_MODE_PWR_SAVE (0x03<<1) 1050 #define SLEEP_MODE_PWR_OFF (0x04<<1) 1051 1052 #endif /* _AVR_ATmega16HVB_H_ */ 1053 1054