1 /***************************************************************************** 2 * 3 * Copyright (C) 2014 Atmel Corporation 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * * Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * 17 * * Neither the name of the copyright holders nor the names of 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 ****************************************************************************/ 33 34 35 /* $Id: iom48pa.h 2460 2014-12-03 05:39:25Z pitchumani $ */ 36 37 #ifndef _AVR_ATMEGA48PA_H_INCLUDED 38 #define _AVR_ATMEGA48PA_H_INCLUDED 39 40 41 #ifndef _AVR_IO_H_ 42 # error "Include <avr/io.h> instead of this file." 43 #endif 44 45 #ifndef _AVR_IOXXX_H_ 46 # define _AVR_IOXXX_H_ "iom48pa.h" 47 #else 48 # error "Attempt to include more than one <avr/ioXXX.h> file." 49 #endif 50 51 /* Registers and associated bit numbers */ 52 53 #define PINB _SFR_IO8(0x03) 54 #define PINB7 7 55 #define PINB6 6 56 #define PINB5 5 57 #define PINB4 4 58 #define PINB3 3 59 #define PINB2 2 60 #define PINB1 1 61 #define PINB0 0 62 63 #define DDRB _SFR_IO8(0x04) 64 #define DDRB7 7 65 #define DDRB6 6 66 #define DDRB5 5 67 #define DDRB4 4 68 #define DDRB3 3 69 #define DDRB2 2 70 #define DDRB1 1 71 #define DDRB0 0 72 73 #define PORTB _SFR_IO8(0x05) 74 #define PORTB7 7 75 #define PORTB6 6 76 #define PORTB5 5 77 #define PORTB4 4 78 #define PORTB3 3 79 #define PORTB2 2 80 #define PORTB1 1 81 #define PORTB0 0 82 83 #define PINC _SFR_IO8(0x06) 84 #define PINC6 6 85 #define PINC5 5 86 #define PINC4 4 87 #define PINC3 3 88 #define PINC2 2 89 #define PINC1 1 90 #define PINC0 0 91 92 #define DDRC _SFR_IO8(0x07) 93 #define DDRC6 6 94 #define DDRC5 5 95 #define DDRC4 4 96 #define DDRC3 3 97 #define DDRC2 2 98 #define DDRC1 1 99 #define DDRC0 0 100 101 #define PORTC _SFR_IO8(0x08) 102 #define PORTC6 6 103 #define PORTC5 5 104 #define PORTC4 4 105 #define PORTC3 3 106 #define PORTC2 2 107 #define PORTC1 1 108 #define PORTC0 0 109 110 #define PIND _SFR_IO8(0x09) 111 #define PIND7 7 112 #define PIND6 6 113 #define PIND5 5 114 #define PIND4 4 115 #define PIND3 3 116 #define PIND2 2 117 #define PIND1 1 118 #define PIND0 0 119 120 #define DDRD _SFR_IO8(0x0A) 121 #define DDRD7 7 122 #define DDRD6 6 123 #define DDRD5 5 124 #define DDRD4 4 125 #define DDRD3 3 126 #define DDRD2 2 127 #define DDRD1 1 128 #define DDRD0 0 129 130 #define PORTD _SFR_IO8(0x0B) 131 #define PORTD7 7 132 #define PORTD6 6 133 #define PORTD5 5 134 #define PORTD4 4 135 #define PORTD3 3 136 #define PORTD2 2 137 #define PORTD1 1 138 #define PORTD0 0 139 140 /* Reserved [0x0C..0x14] */ 141 142 #define TIFR0 _SFR_IO8(0x15) 143 #define TOV0 0 144 #define OCF0A 1 145 #define OCF0B 2 146 147 #define TIFR1 _SFR_IO8(0x16) 148 #define TOV1 0 149 #define OCF1A 1 150 #define OCF1B 2 151 #define ICF1 5 152 153 #define TIFR2 _SFR_IO8(0x17) 154 #define TOV2 0 155 #define OCF2A 1 156 #define OCF2B 2 157 158 /* Reserved [0x18..0x1A] */ 159 160 #define PCIFR _SFR_IO8(0x1B) 161 #define PCIF0 0 162 #define PCIF1 1 163 #define PCIF2 2 164 165 #define EIFR _SFR_IO8(0x1C) 166 #define INTF0 0 167 #define INTF1 1 168 169 #define EIMSK _SFR_IO8(0x1D) 170 #define INT0 0 171 #define INT1 1 172 173 #define GPIOR0 _SFR_IO8(0x1E) 174 175 #define EECR _SFR_IO8(0x1F) 176 #define EERE 0 177 #define EEPE 1 178 #define EEMPE 2 179 #define EERIE 3 180 #define EEPM0 4 181 #define EEPM1 5 182 183 #define EEDR _SFR_IO8(0x20) 184 185 #define EEARL _SFR_IO8(0x21) 186 187 /* Reserved [0x22] */ 188 189 #define GTCCR _SFR_IO8(0x23) 190 #define PSRSYNC 0 191 #define TSM 7 192 #define PSRASY 1 193 194 #define TCCR0A _SFR_IO8(0x24) 195 #define WGM00 0 196 #define WGM01 1 197 #define COM0B0 4 198 #define COM0B1 5 199 #define COM0A0 6 200 #define COM0A1 7 201 202 #define TCCR0B _SFR_IO8(0x25) 203 #define CS00 0 204 #define CS01 1 205 #define CS02 2 206 #define WGM02 3 207 #define FOC0B 6 208 #define FOC0A 7 209 210 #define TCNT0 _SFR_IO8(0x26) 211 212 #define OCR0A _SFR_IO8(0x27) 213 214 #define OCR0B _SFR_IO8(0x28) 215 216 /* Reserved [0x29] */ 217 218 #define GPIOR1 _SFR_IO8(0x2A) 219 220 #define GPIOR2 _SFR_IO8(0x2B) 221 222 #define SPCR _SFR_IO8(0x2C) 223 #define SPR0 0 224 #define SPR1 1 225 #define CPHA 2 226 #define CPOL 3 227 #define MSTR 4 228 #define DORD 5 229 #define SPE 6 230 #define SPIE 7 231 232 #define SPSR _SFR_IO8(0x2D) 233 #define SPI2X 0 234 #define WCOL 6 235 #define SPIF 7 236 237 #define SPDR _SFR_IO8(0x2E) 238 239 /* Reserved [0x2F] */ 240 241 #define ACSR _SFR_IO8(0x30) 242 #define ACIS0 0 243 #define ACIS1 1 244 #define ACIC 2 245 #define ACIE 3 246 #define ACI 4 247 #define ACO 5 248 #define ACBG 6 249 #define ACD 7 250 251 /* Reserved [0x31..0x32] */ 252 253 #define SMCR _SFR_IO8(0x33) 254 #define SE 0 255 #define SM0 1 256 #define SM1 2 257 #define SM2 3 258 259 #define MCUSR _SFR_IO8(0x34) 260 #define PORF 0 261 #define EXTRF 1 262 #define BORF 2 263 #define WDRF 3 264 265 #define MCUCR _SFR_IO8(0x35) 266 #define PUD 4 267 #define BODSE 5 268 #define BODS 6 269 270 /* Reserved [0x36] */ 271 272 #define SPMCSR _SFR_IO8(0x37) 273 #define SELFPRGEN 0 274 #define PGERS 1 275 #define PGWRT 2 276 #define BLBSET 3 277 #define RWWSRE 4 278 #define RWWSB 6 279 #define SPMIE 7 280 281 /* Reserved [0x38..0x3C] */ 282 283 /* SP [0x3D..0x3E] */ 284 285 /* SREG [0x3F] */ 286 287 #define WDTCSR _SFR_MEM8(0x60) 288 #define WDE 3 289 #define WDCE 4 290 #define WDP0 0 291 #define WDP1 1 292 #define WDP2 2 293 #define WDP3 5 294 #define WDIE 6 295 #define WDIF 7 296 297 #define CLKPR _SFR_MEM8(0x61) 298 #define CLKPS0 0 299 #define CLKPS1 1 300 #define CLKPS2 2 301 #define CLKPS3 3 302 #define CLKPCE 7 303 304 /* Reserved [0x62..0x63] */ 305 306 #define PRR _SFR_MEM8(0x64) 307 #define PRADC 0 308 #define PRUSART0 1 309 #define PRSPI 2 310 #define PRTIM1 3 311 #define PRTIM0 5 312 #define PRTIM2 6 313 #define PRTWI 7 314 315 #define __AVR_HAVE_PRR ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI)) 316 #define __AVR_HAVE_PRR_PRADC 317 #define __AVR_HAVE_PRR_PRUSART0 318 #define __AVR_HAVE_PRR_PRSPI 319 #define __AVR_HAVE_PRR_PRTIM1 320 #define __AVR_HAVE_PRR_PRTIM0 321 #define __AVR_HAVE_PRR_PRTIM2 322 #define __AVR_HAVE_PRR_PRTWI 323 324 /* Reserved [0x65] */ 325 326 #define OSCCAL _SFR_MEM8(0x66) 327 #define OSCCAL0 0 328 #define OSCCAL1 1 329 #define OSCCAL2 2 330 #define OSCCAL3 3 331 #define OSCCAL4 4 332 #define OSCCAL5 5 333 #define OSCCAL6 6 334 #define OSCCAL7 7 335 336 /* Reserved [0x67] */ 337 338 #define PCICR _SFR_MEM8(0x68) 339 #define PCIE0 0 340 #define PCIE1 1 341 #define PCIE2 2 342 343 #define EICRA _SFR_MEM8(0x69) 344 #define ISC00 0 345 #define ISC01 1 346 #define ISC10 2 347 #define ISC11 3 348 349 /* Reserved [0x6A] */ 350 351 #define PCMSK0 _SFR_MEM8(0x6B) 352 #define PCINT0 0 353 #define PCINT1 1 354 #define PCINT2 2 355 #define PCINT3 3 356 #define PCINT4 4 357 #define PCINT5 5 358 #define PCINT6 6 359 #define PCINT7 7 360 361 #define PCMSK1 _SFR_MEM8(0x6C) 362 #define PCINT8 0 363 #define PCINT9 1 364 #define PCINT10 2 365 #define PCINT11 3 366 #define PCINT12 4 367 #define PCINT13 5 368 #define PCINT14 6 369 370 #define PCMSK2 _SFR_MEM8(0x6D) 371 #define PCINT16 0 372 #define PCINT17 1 373 #define PCINT18 2 374 #define PCINT19 3 375 #define PCINT20 4 376 #define PCINT21 5 377 #define PCINT22 6 378 #define PCINT23 7 379 380 #define TIMSK0 _SFR_MEM8(0x6E) 381 #define TOIE0 0 382 #define OCIE0A 1 383 #define OCIE0B 2 384 385 #define TIMSK1 _SFR_MEM8(0x6F) 386 #define TOIE1 0 387 #define OCIE1A 1 388 #define OCIE1B 2 389 #define ICIE1 5 390 391 #define TIMSK2 _SFR_MEM8(0x70) 392 #define TOIE2 0 393 #define OCIE2A 1 394 #define OCIE2B 2 395 396 /* Reserved [0x71..0x77] */ 397 398 /* Combine ADCL and ADCH */ 399 #ifndef __ASSEMBLER__ 400 #define ADC _SFR_MEM16(0x78) 401 #endif 402 #define ADCW _SFR_MEM16(0x78) 403 404 #define ADCL _SFR_MEM8(0x78) 405 #define ADCH _SFR_MEM8(0x79) 406 407 #define ADCSRA _SFR_MEM8(0x7A) 408 #define ADPS0 0 409 #define ADPS1 1 410 #define ADPS2 2 411 #define ADIE 3 412 #define ADIF 4 413 #define ADATE 5 414 #define ADSC 6 415 #define ADEN 7 416 417 #define ADCSRB _SFR_MEM8(0x7B) 418 #define ADTS0 0 419 #define ADTS1 1 420 #define ADTS2 2 421 #define ACME 6 422 423 #define ADMUX _SFR_MEM8(0x7C) 424 #define MUX0 0 425 #define MUX1 1 426 #define MUX2 2 427 #define MUX3 3 428 #define ADLAR 5 429 #define REFS0 6 430 #define REFS1 7 431 432 /* Reserved [0x7D] */ 433 434 #define DIDR0 _SFR_MEM8(0x7E) 435 #define ADC0D 0 436 #define ADC1D 1 437 #define ADC2D 2 438 #define ADC3D 3 439 #define ADC4D 4 440 #define ADC5D 5 441 442 #define DIDR1 _SFR_MEM8(0x7F) 443 #define AIN0D 0 444 #define AIN1D 1 445 446 #define TCCR1A _SFR_MEM8(0x80) 447 #define WGM10 0 448 #define WGM11 1 449 #define COM1B0 4 450 #define COM1B1 5 451 #define COM1A0 6 452 #define COM1A1 7 453 454 #define TCCR1B _SFR_MEM8(0x81) 455 #define CS10 0 456 #define CS11 1 457 #define CS12 2 458 #define WGM12 3 459 #define WGM13 4 460 #define ICES1 6 461 #define ICNC1 7 462 463 #define TCCR1C _SFR_MEM8(0x82) 464 #define FOC1B 6 465 #define FOC1A 7 466 467 /* Reserved [0x83] */ 468 469 /* Combine TCNT1L and TCNT1H */ 470 #define TCNT1 _SFR_MEM16(0x84) 471 472 #define TCNT1L _SFR_MEM8(0x84) 473 #define TCNT1H _SFR_MEM8(0x85) 474 475 /* Combine ICR1L and ICR1H */ 476 #define ICR1 _SFR_MEM16(0x86) 477 478 #define ICR1L _SFR_MEM8(0x86) 479 #define ICR1H _SFR_MEM8(0x87) 480 481 /* Combine OCR1AL and OCR1AH */ 482 #define OCR1A _SFR_MEM16(0x88) 483 484 #define OCR1AL _SFR_MEM8(0x88) 485 #define OCR1AH _SFR_MEM8(0x89) 486 487 /* Combine OCR1BL and OCR1BH */ 488 #define OCR1B _SFR_MEM16(0x8A) 489 490 #define OCR1BL _SFR_MEM8(0x8A) 491 #define OCR1BH _SFR_MEM8(0x8B) 492 493 /* Reserved [0x8C..0xAF] */ 494 495 #define TCCR2A _SFR_MEM8(0xB0) 496 #define WGM20 0 497 #define WGM21 1 498 #define COM2B0 4 499 #define COM2B1 5 500 #define COM2A0 6 501 #define COM2A1 7 502 503 #define TCCR2B _SFR_MEM8(0xB1) 504 #define CS20 0 505 #define CS21 1 506 #define CS22 2 507 #define WGM22 3 508 #define FOC2B 6 509 #define FOC2A 7 510 511 #define TCNT2 _SFR_MEM8(0xB2) 512 513 #define OCR2A _SFR_MEM8(0xB3) 514 515 #define OCR2B _SFR_MEM8(0xB4) 516 517 /* Reserved [0xB5] */ 518 519 #define ASSR _SFR_MEM8(0xB6) 520 #define TCR2BUB 0 521 #define TCR2AUB 1 522 #define OCR2BUB 2 523 #define OCR2AUB 3 524 #define TCN2UB 4 525 #define AS2 5 526 #define EXCLK 6 527 528 /* Reserved [0xB7] */ 529 530 #define TWBR _SFR_MEM8(0xB8) 531 532 #define TWSR _SFR_MEM8(0xB9) 533 #define TWPS0 0 534 #define TWPS1 1 535 #define TWS3 3 536 #define TWS4 4 537 #define TWS5 5 538 #define TWS6 6 539 #define TWS7 7 540 541 #define TWAR _SFR_MEM8(0xBA) 542 #define TWGCE 0 543 #define TWA0 1 544 #define TWA1 2 545 #define TWA2 3 546 #define TWA3 4 547 #define TWA4 5 548 #define TWA5 6 549 #define TWA6 7 550 551 #define TWDR _SFR_MEM8(0xBB) 552 553 #define TWCR _SFR_MEM8(0xBC) 554 #define TWIE 0 555 #define TWEN 2 556 #define TWWC 3 557 #define TWSTO 4 558 #define TWSTA 5 559 #define TWEA 6 560 #define TWINT 7 561 562 #define TWAMR _SFR_MEM8(0xBD) 563 #define TWAM0 1 564 #define TWAM1 2 565 #define TWAM2 3 566 #define TWAM3 4 567 #define TWAM4 5 568 #define TWAM5 6 569 #define TWAM6 7 570 571 /* Reserved [0xBE..0xBF] */ 572 573 #define UCSR0A _SFR_MEM8(0xC0) 574 #define MPCM0 0 575 #define U2X0 1 576 #define UPE0 2 577 #define DOR0 3 578 #define FE0 4 579 #define UDRE0 5 580 #define TXC0 6 581 #define RXC0 7 582 583 #define UCSR0B _SFR_MEM8(0xC1) 584 #define TXB80 0 585 #define RXB80 1 586 #define UCSZ02 2 587 #define TXEN0 3 588 #define RXEN0 4 589 #define UDRIE0 5 590 #define TXCIE0 6 591 #define RXCIE0 7 592 593 #define UCSR0C _SFR_MEM8(0xC2) 594 #define UCPOL0 0 595 #define UCSZ00 1 596 #define UCSZ01 2 597 #define USBS0 3 598 #define UPM00 4 599 #define UPM01 5 600 #define UMSEL00 6 601 #define UMSEL01 7 602 603 /* Reserved [0xC3] */ 604 605 /* Combine UBRR0L and UBRR0H */ 606 #define UBRR0 _SFR_MEM16(0xC4) 607 608 #define UBRR0L _SFR_MEM8(0xC4) 609 #define UBRR0H _SFR_MEM8(0xC5) 610 611 #define UDR0 _SFR_MEM8(0xC6) 612 613 614 615 /* Interrupt vectors */ 616 /* Vector 0 is the reset vector */ 617 /* External Interrupt Request 0 */ 618 #define INT0_vect _VECTOR(1) 619 #define INT0_vect_num 1 620 621 /* External Interrupt Request 1 */ 622 #define INT1_vect _VECTOR(2) 623 #define INT1_vect_num 2 624 625 /* Pin Change Interrupt Request 0 */ 626 #define PCINT0_vect _VECTOR(3) 627 #define PCINT0_vect_num 3 628 629 /* Pin Change Interrupt Request 0 */ 630 #define PCINT1_vect _VECTOR(4) 631 #define PCINT1_vect_num 4 632 633 /* Pin Change Interrupt Request 1 */ 634 #define PCINT2_vect _VECTOR(5) 635 #define PCINT2_vect_num 5 636 637 /* Watchdog Time-out Interrupt */ 638 #define WDT_vect _VECTOR(6) 639 #define WDT_vect_num 6 640 641 /* Timer/Counter2 Compare Match A */ 642 #define TIMER2_COMPA_vect _VECTOR(7) 643 #define TIMER2_COMPA_vect_num 7 644 645 /* Timer/Counter2 Compare Match A */ 646 #define TIMER2_COMPB_vect _VECTOR(8) 647 #define TIMER2_COMPB_vect_num 8 648 649 /* Timer/Counter2 Overflow */ 650 #define TIMER2_OVF_vect _VECTOR(9) 651 #define TIMER2_OVF_vect_num 9 652 653 /* Timer/Counter1 Capture Event */ 654 #define TIMER1_CAPT_vect _VECTOR(10) 655 #define TIMER1_CAPT_vect_num 10 656 657 /* Timer/Counter1 Compare Match A */ 658 #define TIMER1_COMPA_vect _VECTOR(11) 659 #define TIMER1_COMPA_vect_num 11 660 661 /* Timer/Counter1 Compare Match B */ 662 #define TIMER1_COMPB_vect _VECTOR(12) 663 #define TIMER1_COMPB_vect_num 12 664 665 /* Timer/Counter1 Overflow */ 666 #define TIMER1_OVF_vect _VECTOR(13) 667 #define TIMER1_OVF_vect_num 13 668 669 /* TimerCounter0 Compare Match A */ 670 #define TIMER0_COMPA_vect _VECTOR(14) 671 #define TIMER0_COMPA_vect_num 14 672 673 /* TimerCounter0 Compare Match B */ 674 #define TIMER0_COMPB_vect _VECTOR(15) 675 #define TIMER0_COMPB_vect_num 15 676 677 /* Timer/Couner0 Overflow */ 678 #define TIMER0_OVF_vect _VECTOR(16) 679 #define TIMER0_OVF_vect_num 16 680 681 /* SPI Serial Transfer Complete */ 682 #define SPI_STC_vect _VECTOR(17) 683 #define SPI_STC_vect_num 17 684 685 /* USART Rx Complete */ 686 #define USART_RX_vect _VECTOR(18) 687 #define USART_RX_vect_num 18 688 689 /* USART, Data Register Empty */ 690 #define USART_UDRE_vect _VECTOR(19) 691 #define USART_UDRE_vect_num 19 692 693 /* USART Tx Complete */ 694 #define USART_TX_vect _VECTOR(20) 695 #define USART_TX_vect_num 20 696 697 /* ADC Conversion Complete */ 698 #define ADC_vect _VECTOR(21) 699 #define ADC_vect_num 21 700 701 /* EEPROM Ready */ 702 #define EE_READY_vect _VECTOR(22) 703 #define EE_READY_vect_num 22 704 705 /* Analog Comparator */ 706 #define ANALOG_COMP_vect _VECTOR(23) 707 #define ANALOG_COMP_vect_num 23 708 709 /* Two-wire Serial Interface */ 710 #define TWI_vect _VECTOR(24) 711 #define TWI_vect_num 24 712 713 /* Store Program Memory Read */ 714 #define SPM_Ready_vect _VECTOR(25) 715 #define SPM_Ready_vect_num 25 716 717 #define _VECTORS_SIZE 52 718 719 720 /* Constants */ 721 722 #define SPM_PAGESIZE 64 723 #define FLASHSTART 0x0000 724 #define FLASHEND 0x0FFF 725 #define RAMSTART 0x0100 726 #define RAMSIZE 512 727 #define RAMEND 0x02FF 728 #define E2START 0 729 #define E2SIZE 256 730 #define E2PAGESIZE 4 731 #define E2END 0x00FF 732 #define XRAMEND RAMEND 733 734 735 /* Fuses */ 736 737 #define FUSE_MEMORY_SIZE 3 738 739 /* Low Fuse Byte */ 740 #define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) 741 #define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) 742 #define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) 743 #define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) 744 #define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) 745 #define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) 746 #define FUSE_CKOUT (unsigned char)~_BV(6) 747 #define FUSE_CKDIV8 (unsigned char)~_BV(7) 748 749 /* High Fuse Byte */ 750 #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) 751 #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) 752 #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) 753 #define FUSE_EESAVE (unsigned char)~_BV(3) 754 #define FUSE_WDTON (unsigned char)~_BV(4) 755 #define FUSE_SPIEN (unsigned char)~_BV(5) 756 #define FUSE_DWEN (unsigned char)~_BV(6) 757 #define FUSE_RSTDISBL (unsigned char)~_BV(7) 758 759 /* Extended Fuse Byte */ 760 #define FUSE_SELFPRGEN (unsigned char)~_BV(0) 761 762 763 /* Lock Bits */ 764 #define __LOCK_BITS_EXIST 765 766 767 /* Signature */ 768 #define SIGNATURE_0 0x1E 769 #define SIGNATURE_1 0x92 770 #define SIGNATURE_2 0x0A 771 772 773 774 #define SLEEP_MODE_IDLE (0x00<<1) 775 #define SLEEP_MODE_ADC (0x01<<1) 776 #define SLEEP_MODE_PWR_DOWN (0x02<<1) 777 #define SLEEP_MODE_PWR_SAVE (0x03<<1) 778 #define SLEEP_MODE_STANDBY (0x06<<1) 779 #define SLEEP_MODE_EXT_STANDBY (0x07<<1) 780 781 #endif /* #ifdef _AVR_ATMEGA48PA_H_INCLUDED */ 782 783