1 /* Copyright (c) 2009 Atmel Corporation 2 All rights reserved. 3 4 Redistribution and use in source and binary forms, with or without 5 modification, are permitted provided that the following conditions are met: 6 7 * Redistributions of source code must retain the above copyright 8 notice, this list of conditions and the following disclaimer. 9 10 * Redistributions in binary form must reproduce the above copyright 11 notice, this list of conditions and the following disclaimer in 12 the documentation and/or other materials provided with the 13 distribution. 14 15 * Neither the name of the copyright holders nor the names of 16 contributors may be used to endorse or promote products derived 17 from this software without specific prior written permission. 18 19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 POSSIBILITY OF SUCH DAMAGE. */ 30 31 /* $Id: iotn461a.h 2460 2014-12-03 05:39:25Z pitchumani $ */ 32 33 /* avr/iotn461a.h - definitions for ATtiny461A */ 34 35 /* This file should only be included from <avr/io.h>, never directly. */ 36 37 #ifndef _AVR_IO_H_ 38 # error "Include <avr/io.h> instead of this file." 39 #endif 40 41 #ifndef _AVR_IOXXX_H_ 42 # define _AVR_IOXXX_H_ "iotn461a.h" 43 #else 44 # error "Attempt to include more than one <avr/ioXXX.h> file." 45 #endif 46 47 48 #ifndef _AVR_ATtiny461A_H_ 49 #define _AVR_ATtiny461A_H_ 1 50 51 52 /* Registers and associated bit numbers. */ 53 54 #define TCCR1E _SFR_IO8(0x00) 55 #define OC1OE0 0 56 #define OC1OE1 1 57 #define OC1OE2 2 58 #define OC1OE3 3 59 #define OC1OE4 4 60 #define OC1OE5 5 61 62 #define DIDR0 _SFR_IO8(0x01) 63 #define ADC0D 0 64 #define ADC1D 1 65 #define ADC2D 2 66 #define AREFD 3 67 #define ADC3D 4 68 #define ADC4D 5 69 #define ADC5D 6 70 #define ADC6D 7 71 72 #define DIDR1 _SFR_IO8(0x02) 73 #define ADC7D 4 74 #define ADC8D 5 75 #define ADC9D 6 76 #define ADC10D 7 77 78 #define ADCSRB _SFR_IO8(0x03) 79 #define ADTS0 0 80 #define ADTS1 1 81 #define ADTS2 2 82 #define MUX5 3 83 #define REFS2 4 84 #define IPR 5 85 #define GSEL 6 86 #define BIN 7 87 88 #ifndef __ASSEMBLER__ 89 #define ADC _SFR_IO16(0x04) 90 #endif 91 #define ADCW _SFR_IO16(0x04) 92 93 #define ADCL _SFR_IO8(0x04) 94 #define ADCL0 0 95 #define ADCL1 1 96 #define ADCL2 2 97 #define ADCL3 3 98 #define ADCL4 4 99 #define ADCL5 5 100 #define ADCL6 6 101 #define ADCL7 7 102 103 #define ADCH _SFR_IO8(0x05) 104 #define ADCH0 0 105 #define ADCH1 1 106 #define ADCH2 2 107 #define ADCH3 3 108 #define ADCH4 4 109 #define ADCH5 5 110 #define ADCH6 6 111 #define ADCH7 7 112 113 #define ADCSRA _SFR_IO8(0x06) 114 #define ADPS0 0 115 #define ADPS1 1 116 #define ADPS2 2 117 #define ADIE 3 118 #define ADIF 4 119 #define ADATE 5 120 #define ADSC 6 121 #define ADEN 7 122 123 #define ADMUX _SFR_IO8(0x07) 124 #define MUX0 0 125 #define MUX1 1 126 #define MUX2 2 127 #define MUX3 3 128 #define MUX4 4 129 #define ADLAR 5 130 #define REFS0 6 131 #define REFS1 7 132 133 #define ACSRA _SFR_IO8(0x08) 134 #define ACIS0 0 135 #define ACIS1 1 136 #define ACME 2 137 #define ACIE 3 138 #define ACI 4 139 #define ACO 5 140 #define ACBG 6 141 #define ACD 7 142 143 #define ACSRB _SFR_IO8(0x09) 144 #define ACM0 0 145 #define ACM1 1 146 #define ACM2 2 147 #define HLEV 6 148 #define HSEL 7 149 150 #define GPIOR0 _SFR_IO8(0x0A) 151 #define GPIOR00 0 152 #define GPIOR01 1 153 #define GPIOR02 2 154 #define GPIOR03 3 155 #define GPIOR04 4 156 #define GPIOR05 5 157 #define GPIOR06 6 158 #define GPIOR07 7 159 160 #define GPIOR1 _SFR_IO8(0x0B) 161 #define GPIOR10 0 162 #define GPIOR11 1 163 #define GPIOR12 2 164 #define GPIOR13 3 165 #define GPIOR14 4 166 #define GPIOR15 5 167 #define GPIOR16 6 168 #define GPIOR17 7 169 170 #define GPIOR2 _SFR_IO8(0x0C) 171 #define GPIOR20 0 172 #define GPIOR21 1 173 #define GPIOR22 2 174 #define GPIOR23 3 175 #define GPIOR24 4 176 #define GPIOR25 5 177 #define GPIOR26 6 178 #define GPIOR27 7 179 180 #define USICR _SFR_IO8(0x0D) 181 #define USITC 0 182 #define USICLK 1 183 #define USICS0 2 184 #define USICS1 3 185 #define USIWM0 4 186 #define USIWM1 5 187 #define USIOIE 6 188 #define USISIE 7 189 190 #define USISR _SFR_IO8(0x0E) 191 #define USICNT0 0 192 #define USICNT1 1 193 #define USICNT2 2 194 #define USICNT3 3 195 #define USIDC 4 196 #define USIPF 5 197 #define USIOIF 6 198 #define USISIF 7 199 200 #define USIDR _SFR_IO8(0x0F) 201 #define USIDR0 0 202 #define USIDR1 1 203 #define USIDR2 2 204 #define USIDR3 3 205 #define USIDR4 4 206 #define USIDR5 5 207 #define USIDR6 6 208 #define USIDR7 7 209 210 #define USIBR _SFR_IO8(0x10) 211 #define USIBR0 0 212 #define USIBR1 1 213 #define USIBR2 2 214 #define USIBR3 3 215 #define USIBR4 4 216 #define USIBR5 5 217 #define USIBR6 6 218 #define USIBR7 7 219 220 #define USIPP _SFR_IO8(0x11) 221 #define USIPOS 0 222 223 #define OCR0B _SFR_IO8(0x12) 224 #define OCR0B_0 0 225 #define OCR0B_1 1 226 #define OCR0B_2 2 227 #define OCR0B_3 3 228 #define OCR0B_4 4 229 #define OCR0B_5 5 230 #define OCR0B_6 6 231 #define OCR0B_7 7 232 233 #define OCR0A _SFR_IO8(0x13) 234 #define OCR0A_0 0 235 #define OCR0A_1 1 236 #define OCR0A_2 2 237 #define OCR0A_3 3 238 #define OCR0A_4 4 239 #define OCR0A_5 5 240 #define OCR0A_6 6 241 #define OCR0A_7 7 242 243 #define TCNT0H _SFR_IO8(0x14) 244 #define TCNT0H_0 0 245 #define TCNT0H_1 1 246 #define TCNT0H_2 2 247 #define TCNT0H_3 3 248 #define TCNT0H_4 4 249 #define TCNT0H_5 5 250 #define TCNT0H_6 6 251 #define TCNT0H_7 7 252 253 #define TCCR0A _SFR_IO8(0x15) 254 #define WGM00 0 255 #define ACIC0 3 256 #define ICES0 4 257 #define ICNC0 5 258 #define ICEN0 6 259 #define TCW0 7 260 261 #define PINB _SFR_IO8(0x16) 262 #define PINB0 0 263 #define PINB1 1 264 #define PINB2 2 265 #define PINB3 3 266 #define PINB4 4 267 #define PINB5 5 268 #define PINB6 6 269 #define PINB7 7 270 271 #define DDRB _SFR_IO8(0x17) 272 #define DDB0 0 273 #define DDB1 1 274 #define DDB2 2 275 #define DDB3 3 276 #define DDB4 4 277 #define DDB5 5 278 #define DDB6 6 279 #define DDB7 7 280 281 #define PORTB _SFR_IO8(0x18) 282 #define PORTB0 0 283 #define PORTB1 1 284 #define PORTB2 2 285 #define PORTB3 3 286 #define PORTB4 4 287 #define PORTB5 5 288 #define PORTB6 6 289 #define PORTB7 7 290 291 #define PINA _SFR_IO8(0x19) 292 #define PINA0 0 293 #define PINA1 1 294 #define PINA2 2 295 #define PINA3 3 296 #define PINA4 4 297 #define PINA5 5 298 #define PINA6 6 299 #define PINA7 7 300 301 #define DDRA _SFR_IO8(0x1A) 302 #define DDA0 0 303 #define DDA1 1 304 #define DDA2 2 305 #define DDA3 3 306 #define DDA4 4 307 #define DDA5 5 308 #define DDA6 6 309 #define DDA7 7 310 311 #define PORTA _SFR_IO8(0x1B) 312 #define PORTA0 0 313 #define PORTA1 1 314 #define PORTA2 2 315 #define PORTA3 3 316 #define PORTA4 4 317 #define PORTA5 5 318 #define PORTA6 6 319 #define PORTA7 7 320 321 #define EECR _SFR_IO8(0x1C) 322 #define EERE 0 323 #define EEPE 1 324 #define EEMPE 2 325 #define EERIE 3 326 #define EEPM0 4 327 #define EEPM1 5 328 329 #define EEDR _SFR_IO8(0x1D) 330 #define EEDR0 0 331 #define EEDR1 1 332 #define EEDR2 2 333 #define EEDR3 3 334 #define EEDR4 4 335 #define EEDR5 5 336 #define EEDR6 6 337 #define EEDR7 7 338 339 #define EEAR _SFR_IO16(0x1E) 340 341 #define EEARL _SFR_IO8(0x1E) 342 #define EEAR0 0 343 #define EEAR1 1 344 #define EEAR2 2 345 #define EEAR3 3 346 #define EEAR4 4 347 #define EEAR5 5 348 #define EEAR6 6 349 #define EEAR7 7 350 351 #define EEARH _SFR_IO8(0x1F) 352 #define EEAR8 0 353 354 #define DWDR _SFR_IO8(0x20) 355 #define DWDR0 0 356 #define DWDR1 1 357 #define DWDR2 2 358 #define DWDR3 3 359 #define DWDR4 4 360 #define DWDR5 5 361 #define DWDR6 6 362 #define DWDR7 7 363 364 #define WDTCR _SFR_IO8(0x21) 365 #define WDP0 0 366 #define WDP1 1 367 #define WDP2 2 368 #define WDE 3 369 #define WDCE 4 370 #define WDP3 5 371 #define WDIE 6 372 #define WDIF 7 373 374 #define PCMSK1 _SFR_IO8(0x22) 375 #define PCINT8 0 376 #define PCINT9 1 377 #define PCINT10 2 378 #define PCINT11 3 379 #define PCINT12 4 380 #define PCINT13 5 381 #define PCINT14 6 382 #define PCINT15 7 383 384 #define PCMSK0 _SFR_IO8(0x23) 385 #define PCINT0 0 386 #define PCINT1 1 387 #define PCINT2 2 388 #define PCINT3 3 389 #define PCINT4 4 390 #define PCINT5 5 391 #define PCINT6 6 392 #define PCINT7 7 393 394 #define DT1 _SFR_IO8(0x24) 395 #define DT1L0 0 396 #define DT1L1 1 397 #define DT1L2 2 398 #define DT1L3 3 399 #define DT1H0 4 400 #define DT1H1 5 401 #define DT1H2 6 402 #define DT1H3 7 403 404 #define TC1H _SFR_IO8(0x25) 405 #define TC18 0 406 #define TC19 1 407 408 #define TCCR1D _SFR_IO8(0x26) 409 #define WGM10 0 410 #define WGM11 1 411 #define FPF1 2 412 #define FPAC1 3 413 #define FPES1 4 414 #define FPNC1 5 415 #define FPEN1 6 416 #define FPIE1 7 417 418 #define TCCR1C _SFR_IO8(0x27) 419 #define PWM1D 0 420 #define FOC1D 1 421 #define COM1D0 2 422 #define COM1D1 3 423 #define COM1B0S 4 424 #define COM1B1S 5 425 #define COM1A0S 6 426 #define COM1A1S 7 427 428 #define CLKPR _SFR_IO8(0x28) 429 #define CLKPS0 0 430 #define CLKPS1 1 431 #define CLKPS2 2 432 #define CLKPS3 3 433 #define CLKPCE 7 434 435 #define PLLCSR _SFR_IO8(0x29) 436 #define PLOCK 0 437 #define PLLE 1 438 #define PCKE 2 439 #define LSM 7 440 441 #define OCR1D _SFR_IO8(0x2A) 442 #define OCR1D0 0 443 #define OCR1D1 1 444 #define OCR1D2 2 445 #define OCR1D3 3 446 #define OCR1D4 4 447 #define OCR1D5 5 448 #define OCR1D6 6 449 #define OCR1D7 7 450 451 #define OCR1C _SFR_IO8(0x2B) 452 #define OCR1C0 0 453 #define OCR1C1 1 454 #define OCR1C2 2 455 #define OCR1C3 3 456 #define OCR1C4 4 457 #define OCR1C5 5 458 #define OCR1C6 6 459 #define OCR1C7 7 460 461 #define OCR1B _SFR_IO8(0x2C) 462 #define OCR1B0 0 463 #define OCR1B1 1 464 #define OCR1B2 2 465 #define OCR1B3 3 466 #define OCR1B4 4 467 #define OCR1B5 5 468 #define OCR1B6 6 469 #define OCR1B7 7 470 471 #define OCR1A _SFR_IO8(0x2D) 472 #define OCR1A0 0 473 #define OCR1A1 1 474 #define OCR1A2 2 475 #define OCR1A3 3 476 #define OCR1A4 4 477 #define OCR1A5 5 478 #define OCR1A6 6 479 #define OCR1A7 7 480 481 #define TCNT1 _SFR_IO8(0x2E) 482 #define TC1H_0 0 483 #define TC1H_1 1 484 #define TC1H_2 2 485 #define TC1H_3 3 486 #define TC1H_4 4 487 #define TC1H_5 5 488 #define TC1H_6 6 489 #define TC1H_7 7 490 491 #define TCCR1B _SFR_IO8(0x2F) 492 #define CS10 0 493 #define CS11 1 494 #define CS12 2 495 #define CS13 3 496 #define DTPS10 4 497 #define DTPS11 5 498 #define PSR1 6 499 500 #define TCCR1A _SFR_IO8(0x30) 501 #define PWM1B 0 502 #define PWM1A 1 503 #define FOC1B 2 504 #define FOC1A 3 505 #define COM1B0 4 506 #define COM1B1 5 507 #define COM1A0 6 508 #define COM1A1 7 509 510 #define OSCCAL _SFR_IO8(0x31) 511 #define CAL0 0 512 #define CAL1 1 513 #define CAL2 2 514 #define CAL3 3 515 #define CAL4 4 516 #define CAL5 5 517 #define CAL6 6 518 #define CAL7 7 519 520 #define TCNT0L _SFR_IO8(0x32) 521 #define TCNT0L_0 0 522 #define TCNT0L_1 1 523 #define TCNT0L_2 2 524 #define TCNT0L_3 3 525 #define TCNT0L_4 4 526 #define TCNT0L_5 5 527 #define TCNT0L_6 6 528 #define TCNT0L_7 7 529 530 #define TCCR0B _SFR_IO8(0x33) 531 #define CS00 0 532 #define CS01 1 533 #define CS02 2 534 #define PSR0 3 535 #define TSM 4 536 537 #define MCUSR _SFR_IO8(0x34) 538 #define PORF 0 539 #define EXTRF 1 540 #define BORF 2 541 #define WDRF 3 542 543 #define MCUCR _SFR_IO8(0x35) 544 #define ISC00 0 545 #define ISC01 1 546 #define BODSE 2 547 #define SM0 3 548 #define SM1 4 549 #define SE 5 550 #define PUD 6 551 #define BODS 7 552 553 #define PRR _SFR_IO8(0x36) 554 #define PRADC 0 555 #define PRUSI 1 556 #define PRTIM0 2 557 #define PRTIM1 3 558 559 #define __AVR_HAVE_PRR ((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1)) 560 #define __AVR_HAVE_PRR_PRADC 561 #define __AVR_HAVE_PRR_PRUSI 562 #define __AVR_HAVE_PRR_PRTIM0 563 #define __AVR_HAVE_PRR_PRTIM1 564 565 #define SPMCSR _SFR_IO8(0x37) 566 #define SPMEN 0 567 #define PGERS 1 568 #define PGWRT 2 569 #define RFLB 3 570 #define CTPB 4 571 572 #define TIFR _SFR_IO8(0x38) 573 #define ICF0 0 574 #define TOV0 1 575 #define TOV1 2 576 #define OCF0B 3 577 #define OCF0A 4 578 #define OCF1B 5 579 #define OCF1A 6 580 #define OCF1D 7 581 582 #define TIMSK _SFR_IO8(0x39) 583 #define TICIE0 0 584 #define TOIE0 1 585 #define TOIE1 2 586 #define OCIE0B 3 587 #define OCIE0A 4 588 #define OCIE1B 5 589 #define OCIE1A 6 590 #define OCIE1D 7 591 592 #define GIFR _SFR_IO8(0x3A) 593 #define PCIF 5 594 #define INTF0 6 595 #define INTF1 7 596 597 #define GIMSK _SFR_IO8(0x3B) 598 #define PCIE0 4 599 #define PCIE1 5 600 #define INT0 6 601 #define INT1 7 602 603 604 /* Interrupt vectors */ 605 /* Vector 0 is the reset vector */ 606 #define INT0_vect_num 1 607 #define INT0_vect _VECTOR(1) /* External Interrupt 0 */ 608 #define PCINT_vect_num 2 609 #define PCINT_vect _VECTOR(2) /* Pin Change Interrupt */ 610 #define TIMER1_COMPA_vect_num 3 611 #define TIMER1_COMPA_vect _VECTOR(3) /* Timer/Counter1 Compare Match 1A */ 612 #define TIMER1_COMPB_vect_num 4 613 #define TIMER1_COMPB_vect _VECTOR(4) /* Timer/Counter1 Compare Match 1B */ 614 #define TIMER1_OVF_vect_num 5 615 #define TIMER1_OVF_vect _VECTOR(5) /* Timer/Counter1 Overflow */ 616 #define TIMER0_OVF_vect_num 6 617 #define TIMER0_OVF_vect _VECTOR(6) /* Timer/Counter0 Overflow */ 618 #define USI_START_vect_num 7 619 #define USI_START_vect _VECTOR(7) /* USI Start */ 620 #define USI_OVF_vect_num 8 621 #define USI_OVF_vect _VECTOR(8) /* USI Overflow */ 622 #define EE_RDY_vect_num 9 623 #define EE_RDY_vect _VECTOR(9) /* EEPROM Ready */ 624 #define ANA_COMP_vect_num 10 625 #define ANA_COMP_vect _VECTOR(10) /* Analog Comparator */ 626 #define ADC_vect_num 11 627 #define ADC_vect _VECTOR(11) /* ADC Conversion Complete */ 628 #define WDT_vect_num 12 629 #define WDT_vect _VECTOR(12) /* Watchdog Time-Out */ 630 #define INT1_vect_num 13 631 #define INT1_vect _VECTOR(13) /* External Interrupt 1 */ 632 #define TIMER0_COMPA_vect_num 14 633 #define TIMER0_COMPA_vect _VECTOR(14) /* Timer/Counter0 Compare Match A */ 634 #define TIMER0_COMPB_vect_num 15 635 #define TIMER0_COMPB_vect _VECTOR(15) /* Timer/Counter0 Compare Match B */ 636 #define TIMER0_CAPT_vect_num 16 637 #define TIMER0_CAPT_vect _VECTOR(16) /* ADC Conversion Complete */ 638 #define TIMER1_COMPD_vect_num 17 639 #define TIMER1_COMPD_vect _VECTOR(17) /* Timer/Counter1 Compare Match D */ 640 #define FAULT_PROTECTION_vect_num 18 641 #define FAULT_PROTECTION_vect _VECTOR(18) /* Timer/Counter1 Fault Protection */ 642 643 #define _VECTOR_SIZE 2 /* Size of individual vector. */ 644 #define _VECTORS_SIZE (19 * _VECTOR_SIZE) 645 646 647 /* Constants */ 648 #define SPM_PAGESIZE (64) 649 #define RAMSTART (0x60) 650 #define RAMSIZE (256) 651 #define RAMEND (RAMSTART + RAMSIZE - 1) 652 #define XRAMSTART (NA) 653 #define XRAMSIZE (0) 654 #define XRAMEND (RAMEND) 655 #define E2END (0xFF) 656 #define E2PAGESIZE (4) 657 #define FLASHEND (0xFFF) 658 659 660 /* Fuses */ 661 #define FUSE_MEMORY_SIZE 3 662 663 /* Low Fuse Byte */ 664 #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */ 665 #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */ 666 #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */ 667 #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */ 668 #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ 669 #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ 670 #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */ 671 #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ 672 #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) 673 674 /* High Fuse Byte */ 675 #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ 676 #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ 677 #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ 678 #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */ 679 #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always on */ 680 #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */ 681 #define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ 682 #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */ 683 #define HFUSE_DEFAULT (FUSE_SPIEN) 684 685 /* Extended Fuse Byte */ 686 #define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */ 687 #define EFUSE_DEFAULT (0xFF) 688 689 690 /* Lock Bits */ 691 #define __LOCK_BITS_EXIST 692 693 694 /* Signature */ 695 #define SIGNATURE_0 0x1E 696 #define SIGNATURE_1 0x92 697 #define SIGNATURE_2 0x08 698 699 700 /* Device Pin Definitions */ 701 #define DI_B_DDR DDRMOSI 702 #define DI_B_PORT PORTMOSI 703 #define DI_B_PIN PINMOSI 704 #define DI_B_BIT MOSI 705 706 #define SDA_B_DDR DDRMOSI 707 #define SDA_B_PORT PORTMOSI 708 #define SDA_B_PIN PINMOSI 709 #define SDA_B_BIT MOSI 710 711 #define _OC1A_DDR DDRMOSI 712 #define _OC1A_PORT PORTMOSI 713 #define _OC1A_PIN PINMOSI 714 #define _OC1A_BIT MOSI 715 716 #define PCINT8_DDR DDRMOSI 717 #define PCINT8_PORT PORTMOSI 718 #define PCINT8_PIN PINMOSI 719 #define PCINT8_BIT MOSI 720 721 #define PB0_DDR DDRMOSI 722 #define PB0_PORT PORTMOSI 723 #define PB0_PIN PINMOSI 724 #define PB0_BIT MOSI 725 726 #define DO_B_DDR DDRMISO 727 #define DO_B_PORT PORTMISO 728 #define DO_B_PIN PINMISO 729 #define DO_B_BIT MISO 730 731 #define OC1A_DDR DDRMISO 732 #define OC1A_PORT PORTMISO 733 #define OC1A_PIN PINMISO 734 #define OC1A_BIT MISO 735 736 #define PCINT9_DDR DDRMISO 737 #define PCINT9_PORT PORTMISO 738 #define PCINT9_PIN PINMISO 739 #define PCINT9_BIT MISO 740 741 #define PB1_DDR DDRMISO 742 #define PB1_PORT PORTMISO 743 #define PB1_PIN PINMISO 744 #define PB1_BIT MISO 745 746 #define USCK_B_DDR DDRSCK 747 #define USCK_B_PORT PORTSCK 748 #define USCK_B_PIN PINSCK 749 #define USCK_B_BIT SCK 750 751 #define SCL_B_DDR DDRSCK 752 #define SCL_B_PORT PORTSCK 753 #define SCL_B_PIN PINSCK 754 #define SCL_B_BIT SCK 755 756 #define OC1B_DDR DDRSCK 757 #define OC1B_PORT PORTSCK 758 #define OC1B_PIN PINSCK 759 #define OC1B_BIT SCK 760 761 #define PCINT10_DDR DDRSCK 762 #define PCINT10_PORT PORTSCK 763 #define PCINT10_PIN PINSCK 764 #define PCINT10_BIT SCK 765 766 #define PB2_DDR DDRSCK 767 #define PB2_PORT PORTSCK 768 #define PB2_PIN PINSCK 769 #define PB2_BIT SCK 770 771 #define PCINT11_DDR DDROC1B 772 #define PCINT11_PORT PORTOC1B 773 #define PCINT11_PIN PINOC1B 774 #define PCINT11_BIT OC1B 775 776 #define PB3_DDR DDROC1B 777 #define PB3_PORT PORTOC1B 778 #define PB3_PIN PINOC1B 779 #define PB3_BIT OC1B 780 781 #define PCINT12_DDR DDRADC 782 #define PCINT12_PORT PORTADC 783 #define PCINT12_PIN PINADC 784 #define PCINT12_BIT ADC7 785 786 #define _OC1D_DDR DDRADC 787 #define _OC1D_PORT PORTADC 788 #define _OC1D_PIN PINADC 789 #define _OC1D_BIT ADC7 790 791 #define CLKI_DDR DDRADC 792 #define CLKI_PORT PORTADC 793 #define CLKI_PIN PINADC 794 #define CLKI_BIT ADC7 795 796 #define PB4_DDR DDRADC 797 #define PB4_PORT PORTADC 798 #define PB4_PIN PINADC 799 #define PB4_BIT ADC7 800 801 #define PCINT13_DDR DDRADC 802 #define PCINT13_PORT PORTADC 803 #define PCINT13_PIN PINADC 804 #define PCINT13_BIT ADC8 805 806 #define OC1D_DDR DDRADC 807 #define OC1D_PORT PORTADC 808 #define OC1D_PIN PINADC 809 #define OC1D_BIT ADC8 810 811 #define CKLO_DDR DDRADC 812 #define CKLO_PORT PORTADC 813 #define CKLO_PIN PINADC 814 #define CKLO_BIT ADC8 815 816 #define PB5_DDR DDRADC 817 #define PB5_PORT PORTADC 818 #define PB5_PIN PINADC 819 #define PB5_BIT ADC8 820 821 #define INT0_DDR DDRADC 822 #define INT0_PORT PORTADC 823 #define INT0_PIN PINADC 824 #define INT0_BIT ADC9 825 826 #define T0_DDR DDRADC 827 #define T0_PORT PORTADC 828 #define T0_PIN PINADC 829 #define T0_BIT ADC9 830 831 #define PCINT14_DDR DDRADC 832 #define PCINT14_PORT PORTADC 833 #define PCINT14_PIN PINADC 834 #define PCINT14_BIT ADC9 835 836 #define PB6_DDR DDRADC 837 #define PB6_PORT PORTADC 838 #define PB6_PIN PINADC 839 #define PB6_BIT ADC9 840 841 #define PCINT15_DDR DDRADC1 842 #define PCINT15_PORT PORTADC1 843 #define PCINT15_PIN PINADC1 844 #define PCINT15_BIT ADC10 845 846 #define PB7_DDR DDRADC1 847 #define PB7_PORT PORTADC1 848 #define PB7_PIN PINADC1 849 #define PB7_BIT ADC10 850 851 #define AIN1_DDR DDRADC 852 #define AIN1_PORT PORTADC 853 #define AIN1_PIN PINADC 854 #define AIN1_BIT ADC6 855 856 #define PCINT7_DDR DDRADC 857 #define PCINT7_PORT PORTADC 858 #define PCINT7_PIN PINADC 859 #define PCINT7_BIT ADC6 860 861 #define PA7_DDR DDRADC 862 #define PA7_PORT PORTADC 863 #define PA7_PIN PINADC 864 #define PA7_BIT ADC6 865 866 #define AIN0_DDR DDRADC 867 #define AIN0_PORT PORTADC 868 #define AIN0_PIN PINADC 869 #define AIN0_BIT ADC5 870 871 #define PCINT6_DDR DDRADC 872 #define PCINT6_PORT PORTADC 873 #define PCINT6_PIN PINADC 874 #define PCINT6_BIT ADC5 875 876 #define PA6_DDR DDRADC 877 #define PA6_PORT PORTADC 878 #define PA6_PIN PINADC 879 #define PA6_BIT ADC5 880 881 #define AIN2_DDR DDRADC 882 #define AIN2_PORT PORTADC 883 #define AIN2_PIN PINADC 884 #define AIN2_BIT ADC4 885 886 #define PCINT5_DDR DDRADC 887 #define PCINT5_PORT PORTADC 888 #define PCINT5_PIN PINADC 889 #define PCINT5_BIT ADC4 890 891 #define PA5_DDR DDRADC 892 #define PA5_PORT PORTADC 893 #define PA5_PIN PINADC 894 #define PA5_BIT ADC4 895 896 #define ICP0_DDR DDRADC 897 #define ICP0_PORT PORTADC 898 #define ICP0_PIN PINADC 899 #define ICP0_BIT ADC3 900 901 #define PCINT4_DDR DDRADC 902 #define PCINT4_PORT PORTADC 903 #define PCINT4_PIN PINADC 904 #define PCINT4_BIT ADC3 905 906 #define PA4_DDR DDRADC 907 #define PA4_PORT PORTADC 908 #define PA4_PIN PINADC 909 #define PA4_BIT ADC3 910 911 #define PCINT3_DDR DDRAREF 912 #define PCINT3_PORT PORTAREF 913 #define PCINT3_PIN PINAREF 914 #define PCINT3_BIT AREF 915 916 #define PA3_DDR DDRAREF 917 #define PA3_PORT PORTAREF 918 #define PA3_PIN PINAREF 919 #define PA3_BIT AREF 920 921 #define INT1_DDR DDRADC 922 #define INT1_PORT PORTADC 923 #define INT1_PIN PINADC 924 #define INT1_BIT ADC2 925 926 #define USCK_A_DDR DDRADC 927 #define USCK_A_PORT PORTADC 928 #define USCK_A_PIN PINADC 929 #define USCK_A_BIT ADC2 930 931 #define SCL_A_DDR DDRADC 932 #define SCL_A_PORT PORTADC 933 #define SCL_A_PIN PINADC 934 #define SCL_A_BIT ADC2 935 936 #define PCINT2_DDR DDRADC 937 #define PCINT2_PORT PORTADC 938 #define PCINT2_PIN PINADC 939 #define PCINT2_BIT ADC2 940 941 #define PA2_DDR DDRADC 942 #define PA2_PORT PORTADC 943 #define PA2_PIN PINADC 944 #define PA2_BIT ADC2 945 946 #define DO_A_DDR DDRADC 947 #define DO_A_PORT PORTADC 948 #define DO_A_PIN PINADC 949 #define DO_A_BIT ADC1 950 951 #define PCINT1_DDR DDRADC 952 #define PCINT1_PORT PORTADC 953 #define PCINT1_PIN PINADC 954 #define PCINT1_BIT ADC1 955 956 #define PA1_DDR DDRADC 957 #define PA1_PORT PORTADC 958 #define PA1_PIN PINADC 959 #define PA1_BIT ADC1 960 961 #define DI_A_DDR DDRADC 962 #define DI_A_PORT PORTADC 963 #define DI_A_PIN PINADC 964 #define DI_A_BIT ADC0 965 966 #define SDA_A_DDR DDRADC 967 #define SDA_A_PORT PORTADC 968 #define SDA_A_PIN PINADC 969 #define SDA_A_BIT ADC0 970 971 #define PCINT0_DDR DDRADC 972 #define PCINT0_PORT PORTADC 973 #define PCINT0_PIN PINADC 974 #define PCINT0_BIT ADC0 975 976 #define PA0_DDR DDRADC 977 #define PA0_PORT PORTADC 978 #define PA0_PIN PINADC 979 #define PA0_BIT ADC0 980 981 982 #define SLEEP_MODE_IDLE (0x00<<3) 983 #define SLEEP_MODE_ADC (0x01<<3) 984 #define SLEEP_MODE_PWR_DOWN (0x02<<3) 985 #define SLEEP_MODE_STANDBY (0x03<<3) 986 987 #endif /* _AVR_ATtiny461A_H_ */ 988 989