1 /* Copyright (c) 2009 Atmel Corporation 2 All rights reserved. 3 4 Redistribution and use in source and binary forms, with or without 5 modification, are permitted provided that the following conditions are met: 6 7 * Redistributions of source code must retain the above copyright 8 notice, this list of conditions and the following disclaimer. 9 10 * Redistributions in binary form must reproduce the above copyright 11 notice, this list of conditions and the following disclaimer in 12 the documentation and/or other materials provided with the 13 distribution. 14 15 * Neither the name of the copyright holders nor the names of 16 contributors may be used to endorse or promote products derived 17 from this software without specific prior written permission. 18 19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 POSSIBILITY OF SUCH DAMAGE. */ 30 31 /* $Id: iotn5.h 2460 2014-12-03 05:39:25Z pitchumani $ */ 32 33 /* avr/iotn5.h - definitions for ATtiny5 */ 34 35 /* This file should only be included from <avr/io.h>, never directly. */ 36 37 #ifndef _AVR_IO_H_ 38 # error "Include <avr/io.h> instead of this file." 39 #endif 40 41 #ifndef _AVR_IOXXX_H_ 42 # define _AVR_IOXXX_H_ "iotn5.h" 43 #else 44 # error "Attempt to include more than one <avr/ioXXX.h> file." 45 #endif 46 47 48 #ifndef _AVR_ATtiny5_H_ 49 #define _AVR_ATtiny5_H_ 1 50 51 52 /* Registers and associated bit numbers. */ 53 54 #define PINB _SFR_IO8(0x00) 55 #define PINB0 0 56 #define PINB1 1 57 #define PINB2 2 58 #define PINB3 3 59 60 #define DDRB _SFR_IO8(0x01) 61 #define DDB0 0 62 #define DDB1 1 63 #define DDB2 2 64 #define DDB3 3 65 66 #define PORTB _SFR_IO8(0x02) 67 #define PORTB0 0 68 #define PORTB1 1 69 #define PORTB2 2 70 #define PORTB3 3 71 72 #define PUEB _SFR_IO8(0x03) 73 #define PUEB0 0 74 #define PUEB1 1 75 #define PUEB2 2 76 #define PUEB3 3 77 78 #define PORTCR _SFR_IO8(0x0C) 79 #define BBMB 1 80 81 #define PCMSK _SFR_IO8(0x10) 82 #define PCINT0 0 83 #define PCINT1 1 84 #define PCINT2 2 85 #define PCINT3 3 86 87 #define PCIFR _SFR_IO8(0x11) 88 #define PCIF0 0 89 90 #define PCICR _SFR_IO8(0x12) 91 #define PCIE0 0 92 93 #define EIMSK _SFR_IO8(0x13) 94 #define INT0 0 95 96 #define EIFR _SFR_IO8(0x14) 97 #define INTF0 0 98 99 #define EICRA _SFR_IO8(0x15) 100 #define ISC00 0 101 #define ISC01 1 102 103 #define DIDR0 _SFR_IO8(0x17) 104 #define ADC0D 0 105 #define AIN0D 0 106 #define ADC1D 1 107 #define AIN1D 1 108 #define ADC2D 2 109 #define ADC3D 3 110 111 #define ADCL _SFR_IO8(0x19) 112 #define ADC0 0 113 #define ADC1 1 114 #define ADC2 2 115 #define ADC3 3 116 #define ADC4 4 117 #define ADC5 5 118 #define ADC6 6 119 #define ADC7 7 120 121 #define ADMUX _SFR_IO8(0x1B) 122 #define MUX0 0 123 #define MUX1 1 124 125 #define ADCSRB _SFR_IO8(0x1C) 126 #define ADTS0 0 127 #define ADTS1 1 128 #define ADTS2 2 129 130 #define ADCSRA _SFR_IO8(0x1D) 131 #define ADPS0 0 132 #define ADPS1 1 133 #define ADPS2 2 134 #define ADIE 3 135 #define ADIF 4 136 #define ADATE 5 137 #define ADSC 6 138 #define ADEN 7 139 140 #define ACSR _SFR_IO8(0x1F) 141 #define ACIS0 0 142 #define ACIS1 1 143 #define ACIC 2 144 #define ACIE 3 145 #define ACI 4 146 #define ACO 5 147 #define ACD 7 148 149 #define ICR0 _SFR_IO16(0x22) 150 151 #define ICR0L _SFR_IO8(0x22) 152 #define ICR0_0 0 153 #define ICR0_1 1 154 #define ICR0_2 2 155 #define ICR0_3 3 156 #define ICR0_4 4 157 #define ICR0_5 5 158 #define ICR0_6 6 159 #define ICR0_7 7 160 161 #define ICR0H _SFR_IO8(0x23) 162 #define ICR0_8 0 163 #define ICR0_9 1 164 #define ICR0_10 2 165 #define ICR0_11 3 166 #define ICR0_12 4 167 #define ICR0_13 5 168 #define ICR0_14 6 169 #define ICR0_15 7 170 171 #define OCR0B _SFR_IO16(0x24) 172 173 #define OCR0BL _SFR_IO8(0x24) 174 #define OCR0B0 0 175 #define OCR0B1 1 176 #define OCR0B2 2 177 #define OCR0B3 3 178 #define OCR0B4 4 179 #define OCR0B5 5 180 #define OCR0B6 6 181 #define OCR0B7 7 182 183 #define OCR0BH _SFR_IO8(0x25) 184 #define OCR0B8 0 185 #define OCR0B9 1 186 #define OCR0B10 2 187 #define OCR0B11 3 188 #define OCR0B12 4 189 #define OCR0B13 5 190 #define OCR0B14 6 191 #define OCR0B15 7 192 193 #define OCR0A _SFR_IO16(0x26) 194 195 #define OCR0AL _SFR_IO8(0x26) 196 #define OCR0A0 0 197 #define OCR0A1 1 198 #define OCR0A2 2 199 #define OCR0A3 3 200 #define OCR0A4 4 201 #define OCR0A5 5 202 #define OCR0A6 6 203 #define OCR0A7 7 204 205 #define OCR0AH _SFR_IO8(0x27) 206 #define OCR0A8 0 207 #define OCR0A9 1 208 #define OCR0A10 2 209 #define OCR0A11 3 210 #define OCR0A12 4 211 #define OCR0A13 5 212 #define OCR0A14 6 213 #define OCR0A15 7 214 215 #define TCNT0 _SFR_IO16(0x28) 216 217 #define TCNT0L _SFR_IO8(0x28) 218 #define TCNT0_0 0 219 #define TCNT0_1 1 220 #define TCNT0_2 2 221 #define TCNT0_3 3 222 #define TCNT0_4 4 223 #define TCNT0_5 5 224 #define TCNT0_6 6 225 #define TCNT0_7 7 226 227 #define TCNT0H _SFR_IO8(0x29) 228 #define TCNT0_8 0 229 #define TCNT0_9 1 230 #define TCNT0_10 2 231 #define TCNT0_11 3 232 #define TCNT0_12 4 233 #define TCNT0_13 5 234 #define TCNT0_14 6 235 #define TCNT0_15 7 236 237 #define TIFR0 _SFR_IO8(0x2A) 238 #define TOV0 0 239 #define OCF0A 1 240 #define OCF0B 2 241 #define ICF0 5 242 243 #define TIMSK0 _SFR_IO8(0x2B) 244 #define TOIE0 0 245 #define OCIE0A 1 246 #define OCIE0B 2 247 #define ICIE0 5 248 249 #define TCCR0C _SFR_IO8(0x2C) 250 #define FOC0B 6 251 #define FOC0A 7 252 253 #define TCCR0B _SFR_IO8(0x2D) 254 #define CS00 0 255 #define CS01 1 256 #define CS02 2 257 #define WGM02 3 258 #define WGM03 4 259 #define ICES0 6 260 #define ICNC0 7 261 262 #define TCCR0A _SFR_IO8(0x2E) 263 #define WGM00 0 264 #define WGM01 1 265 #define COM0B0 4 266 #define COM0B1 5 267 #define COM0A0 6 268 #define COM0A1 7 269 270 #define GTCCR _SFR_IO8(0x2F) 271 #define PSR 0 272 #define TSM 7 273 274 #define WDTCSR _SFR_IO8(0x31) 275 #define WDP0 0 276 #define WDP1 1 277 #define WDP2 2 278 #define WDE 3 279 #define WDP3 5 280 #define WDIE 6 281 #define WDIF 7 282 283 #define NVMCSR _SFR_IO8(0x32) 284 #define NVMBSY 7 285 286 #define NVMCMD _SFR_IO8(0x33) 287 #define NVMCMD0 0 288 #define NVMCMD1 1 289 #define NVMCMD2 2 290 #define NVMCMD3 3 291 #define NVMCMD4 4 292 #define NVMCMD5 5 293 294 #define VLMCSR _SFR_IO8(0x34) 295 #define VLM0 0 296 #define VLM1 1 297 #define VLM2 2 298 #define VLMIE 6 299 #define VLMF 7 300 301 #define PRR _SFR_IO8(0x35) 302 #define PRTIM0 0 303 #define PRADC 1 304 305 #define __AVR_HAVE_PRR ((1<<PRTIM0)|(1<<PRADC)) 306 #define __AVR_HAVE_PRR_PRTIM0 307 #define __AVR_HAVE_PRR_PRADC 308 309 #define CLKPSR _SFR_IO8(0x36) 310 #define CLKPS0 0 311 #define CLKPS1 1 312 #define CLKPS2 2 313 #define CLKPS3 3 314 315 #define CLKMSR _SFR_IO8(0x37) 316 #define CLKMS0 0 317 #define CLKMS1 1 318 319 #define OSCCAL _SFR_IO8(0x39) 320 #define CAL0 0 321 #define CAL1 1 322 #define CAL2 2 323 #define CAL3 3 324 #define CAL4 4 325 #define CAL5 5 326 #define CAL6 6 327 #define CAL7 7 328 329 #define SMCR _SFR_IO8(0x3A) 330 #define SE 0 331 #define SM0 1 332 #define SM1 2 333 #define SM2 3 334 335 #define RSTFLR _SFR_IO8(0x3B) 336 #define PORF 0 337 #define EXTRF 1 338 #define WDRF 3 339 340 #define CCP _SFR_IO8(0x3C) 341 #define CCP0 0 342 #define CCP1 1 343 #define CCP2 2 344 #define CCP3 3 345 #define CCP4 4 346 #define CCP5 5 347 #define CCP6 6 348 #define CCP7 7 349 350 351 /* Interrupt vectors */ 352 /* Vector 0 is the reset vector */ 353 #define INT0_vect_num 1 354 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ 355 #define PCINT0_vect_num 2 356 #define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ 357 #define TIM0_CAPT_vect_num 3 358 #define TIM0_CAPT_vect _VECTOR(3) /* Timer/Counter0 Input Capture */ 359 #define TIM0_OVF_vect_num 4 360 #define TIM0_OVF_vect _VECTOR(4) /* Timer/Counter0 Overflow */ 361 #define TIM0_COMPA_vect_num 5 362 #define TIM0_COMPA_vect _VECTOR(5) /* Timer/Counter Compare Match A */ 363 #define TIM0_COMPB_vect_num 6 364 #define TIM0_COMPB_vect _VECTOR(6) /* Timer/Counter Compare Match B */ 365 #define ANA_COMP_vect_num 7 366 #define ANA_COMP_vect _VECTOR(7) /* Analog Comparator */ 367 #define WDT_vect_num 8 368 #define WDT_vect _VECTOR(8) /* Watchdog Time-out */ 369 #define VLM_vect_num 9 370 #define VLM_vect _VECTOR(9) /* Vcc Voltage Level Monitor */ 371 #define ADC_vect_num 10 372 #define ADC_vect _VECTOR(10) /* ADC Conversion Complete */ 373 374 #define _VECTOR_SIZE 2 /* Size of individual vector. */ 375 #define _VECTORS_SIZE (11 * _VECTOR_SIZE) 376 377 378 /* Constants */ 379 #define SPM_PAGESIZE (32) 380 #define RAMSTART (0x40) 381 #define RAMSIZE (32) 382 #define RAMEND (RAMSTART + RAMSIZE - 1) 383 #define XRAMSTART (NA) 384 #define XRAMSIZE (0) 385 #define XRAMEND (RAMEND) 386 #define E2END (0x0) 387 #define E2PAGESIZE (0) 388 #define FLASHEND (0x1FF) 389 390 391 /* Fuses */ 392 #define FUSE_MEMORY_SIZE 0 393 394 395 /* Lock Bits */ 396 #define __LOCK_BITS_EXIST 397 398 399 /* Signature */ 400 #define SIGNATURE_0 0x1E 401 #define SIGNATURE_1 0x90 402 #define SIGNATURE_2 0x09 403 404 405 /* Device Pin Definitions */ 406 #define SPDATA_DDR DDRCINT 407 #define SPDATA_PORT PORTCINT 408 #define SPDATA_PIN PINCINT 409 #define SPDATA_BIT INT0 410 411 #define OC0A_DDR DDRCINT 412 #define OC0A_PORT PORTCINT 413 #define OC0A_PIN PINCINT 414 #define OC0A_BIT INT0 415 416 #define ADC0_DDR DDRCINT 417 #define ADC0_PORT PORTCINT 418 #define ADC0_PIN PINCINT 419 #define ADC0_BIT INT0 420 421 #define AIN0_DDR DDRCINT 422 #define AIN0_PORT PORTCINT 423 #define AIN0_PIN PINCINT 424 #define AIN0_BIT INT0 425 426 #define PB0_DDR DDRCINT 427 #define PB0_PORT PORTCINT 428 #define PB0_PIN PINCINT 429 #define PB0_BIT INT0 430 431 #define SPCLK_DDR DDRCINT 432 #define SPCLK_PORT PORTCINT 433 #define SPCLK_PIN PINCINT 434 #define SPCLK_BIT INT1 435 436 #define CLKI_DDR DDRCINT 437 #define CLKI_PORT PORTCINT 438 #define CLKI_PIN PINCINT 439 #define CLKI_BIT INT1 440 441 #define ICP0_DDR DDRCINT 442 #define ICP0_PORT PORTCINT 443 #define ICP0_PIN PINCINT 444 #define ICP0_BIT INT1 445 446 #define OC0B_DDR DDRCINT 447 #define OC0B_PORT PORTCINT 448 #define OC0B_PIN PINCINT 449 #define OC0B_BIT INT1 450 451 #define ADC1_DDR DDRCINT 452 #define ADC1_PORT PORTCINT 453 #define ADC1_PIN PINCINT 454 #define ADC1_BIT INT1 455 456 #define AIN1_DDR DDRCINT 457 #define AIN1_PORT PORTCINT 458 #define AIN1_PIN PINCINT 459 #define AIN1_BIT INT1 460 461 #define PB1_DDR DDRCINT 462 #define PB1_PORT PORTCINT 463 #define PB1_PIN PINCINT 464 #define PB1_BIT INT1 465 466 #define CLKO_DDR DDRT 467 #define CLKO_PORT PORTT 468 #define CLKO_PIN PINT 469 #define CLKO_BIT T0 470 471 #define PCINT2_DDR DDRT 472 #define PCINT2_PORT PORTT 473 #define PCINT2_PIN PINT 474 #define PCINT2_BIT T0 475 476 #define INT0_DDR DDRT 477 #define INT0_PORT PORTT 478 #define INT0_PIN PINT 479 #define INT0_BIT T0 480 481 #define ADC2_DDR DDRT 482 #define ADC2_PORT PORTT 483 #define ADC2_PIN PINT 484 #define ADC2_BIT T0 485 486 #define PB2_DDR DDRT 487 #define PB2_PORT PORTT 488 #define PB2_PIN PINT 489 #define PB2_BIT T0 490 491 #define PCINT3_DDR DDRRESET 492 #define PCINT3_PORT PORTRESET 493 #define PCINT3_PIN PINRESET 494 #define PCINT3_BIT RESET 495 496 #define ADC3_DDR DDRRESET 497 #define ADC3_PORT PORTRESET 498 #define ADC3_PIN PINRESET 499 #define ADC3_BIT RESET 500 501 #define PB3_DDR DDRRESET 502 #define PB3_PORT PORTRESET 503 #define PB3_PIN PINRESET 504 #define PB3_BIT RESET 505 506 507 #define SLEEP_MODE_IDLE (0x00<<1) 508 #define SLEEP_MODE_ADC (0x01<<1) 509 #define SLEEP_MODE_PWR_DOWN (0x02<<1) 510 #define SLEEP_MODE_STANDBY (0x04<<1) 511 512 #endif /* _AVR_ATtiny5_H_ */ 513 514